Add MaxWidth of 1,000,000 bits

Also base max dshl check on MaxWidth instead of just 31 bits
Resolves #320

2 files changed, 32 insertions, 5 deletions

diff --git a/src/main/scala/firrtl/passes/CheckWidths.scala b/src/main/scala/firrtl/passes/CheckWidths.scala
index 5761986a..ab07e830 100644
--- a/src/main/scala/firrtl/passes/CheckWidths.scala
+++ b/src/main/scala/firrtl/passes/CheckWidths.scala
@@ -10,12 +10,17 @@ import firrtl.Utils._
 
 object CheckWidths extends Pass {
   def name = "Width Check"
+  /** The maximum allowed width for any circuit element */
+  val MaxWidth = 1000000
+  val DshlMaxWidth = ceilLog2(MaxWidth + 1)
   class UninferredWidth (info: Info, mname: String) extends PassException(
     s"$info : [module $mname]  Uninferred width.")
   class WidthTooSmall(info: Info, mname: String, b: BigInt) extends PassException(
     s"$info : [module $mname]  Width too small for constant ${serialize(b)}.")
-  class WidthTooBig(info: Info, mname: String) extends PassException(
-    s"$info : [module $mname]  Width of dshl shift amount cannot be larger than 31 bits.")
+  class WidthTooBig(info: Info, mname: String, b: BigInt) extends PassException(
+    s"$info : [module $mname]  Width $b greater than max allowed width of $MaxWidth bits")
+  class DshlTooBig(info: Info, mname: String) extends PassException(
+    s"$info : [module $mname]  Width of dshl shift amount cannot be larger than $DshlMaxWidth bits.")
   class NegWidthException(info:Info, mname: String) extends PassException(
     s"$info: [module $mname] Width cannot be negative or zero.")
   class BitsWidthException(info: Info, mname: String, hi: BigInt, width: BigInt) extends PassException(
@@ -32,6 +37,8 @@ object CheckWidths extends Pass {
 
     def check_width_w(info: Info, mname: String)(w: Width): Width = {
       w match {
+        case IntWidth(width) if width >= MaxWidth =>
+          errors.append(new WidthTooBig(info, mname, width))
         case w: IntWidth if w.width >= 0 =>
         case _: IntWidth =>
           errors append new NegWidthException(info, mname)
@@ -68,8 +75,8 @@ object CheckWidths extends Pass {
           errors append new HeadWidthException(info, mname, n, bitWidth(a.tpe))
         case DoPrim(Tail, Seq(a), Seq(n), _) if (hasWidth(a.tpe) && bitWidth(a.tpe) <= n) =>
           errors append new TailWidthException(info, mname, n, bitWidth(a.tpe))
-        case DoPrim(Dshl, Seq(a, b), _, _) if (hasWidth(a.tpe) && bitWidth(b.tpe) >= BigInt(32)) =>
-          errors append new WidthTooBig(info, mname)
+        case DoPrim(Dshl, Seq(a, b), _, _) if (hasWidth(a.tpe) && bitWidth(b.tpe) >= DshlMaxWidth) =>
+          errors append new DshlTooBig(info, mname)
         case _ =>
       }
       //e map check_width_t(info, mname) map check_width_e(info, mname)
diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala
index 9b0ee139..770c2785 100644
--- a/src/test/scala/firrtlTests/WidthSpec.scala
+++ b/src/test/scala/firrtlTests/WidthSpec.scala
@@ -58,7 +58,7 @@ class WidthSpec extends FirrtlFlatSpec {
     val check = Seq( "output z : SInt<5>")
     executeTest(input, check, passes)
   }
-  "Dshl by 32 bits" should "result in an error" in {
+  "Dshl by 20 bits" should "result in an error" in {
     val passes = Seq(
       ToWorkingIR,
       CheckHighForm,
@@ -74,6 +74,26 @@ class WidthSpec extends FirrtlFlatSpec {
         |    input y: UInt<32>
         |    output z: UInt
         |    z <= dshl(x, y)""".stripMargin
+    // Throws both DshlTooBig and WidthTooBig
+    // TODO check message
+    intercept[PassExceptions] {
+      executeTest(input, Nil, passes)
+    }
+  }
+  "Width >= MaxWidth" should "result in an error" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      InferWidths,
+      CheckWidths)
+    val input =
+     s"""circuit Unit :
+        |  module Unit :
+        |    input x: UInt<${CheckWidths.MaxWidth}>
+      """.stripMargin
     intercept[CheckWidths.WidthTooBig] {
       executeTest(input, Nil, passes)
     }