Add check for muxing between clocks (#360)

Also run CheckTypes after ExpandWhens
Fixes #330

4 files changed, 30 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index eb873232..c29ce01a 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -64,6 +64,7 @@ class HighFirrtlToMiddleFirrtl extends CoreTransform {
     passes.CheckInitialization,
     passes.ResolveKinds,
     passes.InferTypes,
+    passes.CheckTypes,
     passes.ResolveGenders,
     passes.InferWidths,
     passes.CheckWidths)
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 0d16ef00..769f68a9 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -250,6 +250,8 @@ object CheckTypes extends Pass {
     s"$info: [module $mname]  Must mux between passive types.")
   class MuxCondUInt(info: Info, mname: String) extends PassException(
     s"$info: [module $mname]  A mux condition must be of type UInt.")
+  class MuxClock(info: Info, mname: String) extends PassException(
+    s"$info: [module $mname]  Firrtl does not support muxing clocks.")
   class ValidIfPassiveTypes(info: Info, mname: String) extends PassException(
     s"$info: [module $mname]  Must validif a passive type.")
   class ValidIfCondUInt(info: Info, mname: String) extends PassException(
@@ -371,6 +373,8 @@ object CheckTypes extends Pass {
             case _: UIntType =>
             case _ => errors append new MuxCondUInt(info, mname)
           }
+          if ((e.tval.tpe == ClockType) || (e.fval.tpe == ClockType))
+            errors.append(new MuxClock(info, mname))
         case (e: ValidIf) =>
           if (!passive(e.tpe))
             errors append new ValidIfPassiveTypes(info, mname)
diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala
index 90db3524..a2c880c3 100644
--- a/src/test/scala/firrtlTests/FirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/FirrtlSpec.scala
@@ -109,6 +109,14 @@ trait BackendCompilationUtilities {
 trait FirrtlRunners extends BackendCompilationUtilities {
   def parse(str: String) = Parser.parse(str.split("\n").toIterator, IgnoreInfo)
   lazy val cppHarness = new File(s"/top.cpp")
+  /** Compiles input Firrtl to Verilog */
+  def compileToVerilog(input: String, annotations: AnnotationMap = AnnotationMap(Seq.empty)): String = {
+    val circuit = Parser.parse(input.split("\n").toIterator)
+    val compiler = new VerilogCompiler
+    val writer = new java.io.StringWriter
+    compiler.compile(CircuitState(circuit, HighForm, Some(annotations)), writer)
+    writer.toString
+  }
   /** Compile a Firrtl file
     *
     * @param prefix is the name of the Firrtl file without path or file extension
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index e2f8f729..cb07448f 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -304,4 +304,21 @@ class UnitTests extends FirrtlFlatSpec {
     }
 
   }
+
+  "Conditional conection of clocks" should "throw an exception" in {
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    input clock1 : Clock
+        |    input clock2 : Clock
+        |    input sel : UInt<1>
+        |    output clock3 : Clock
+        |    clock3 <= clock1
+        |    when sel :
+        |      clock3 <= clock2
+        |""".stripMargin
+    intercept[PassExceptions] { // Both MuxClock and InvalidConnect are thrown
+      compileToVerilog(input)
+    }
+  }
 }