diff options
| author | Adam Izraelevitz | 2016-12-05 09:29:40 -0800 |
|---|---|---|
| committer | GitHub | 2016-12-05 09:29:40 -0800 |
| commit | ad36788b79f8b63be59d9612134889aef874c286 (patch) | |
| tree | a8e305c6265b44a51ad960f4a757f28462ddb76b /src | |
| parent | a4da2e07469374dcafd1b2b50293ed875340832f (diff) | |
Bugfix: expand whens not voiding memories (#380)
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/ExpandWhens.scala | 3 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/ExpandWhensSpec.scala | 52 |
2 files changed, 51 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala index 52c7e6ee..4d02e192 100644 --- a/src/main/scala/firrtl/passes/ExpandWhens.scala +++ b/src/main/scala/firrtl/passes/ExpandWhens.scala @@ -78,6 +78,9 @@ object ExpandWhens extends Pass { case w: DefWire => netlist ++= (getFemaleRefs(w.name, w.tpe, BIGENDER) map (ref => we(ref) -> WVoid)) w + case w: DefMemory => + netlist ++= (getFemaleRefs(w.name, MemPortUtils.memType(w), MALE) map (ref => we(ref) -> WVoid)) + w case r: DefRegister => netlist ++= (getFemaleRefs(r.name, r.tpe, BIGENDER) map (ref => we(ref) -> ref)) r diff --git a/src/test/scala/firrtlTests/ExpandWhensSpec.scala b/src/test/scala/firrtlTests/ExpandWhensSpec.scala index 6d1a74c0..a7824087 100644 --- a/src/test/scala/firrtlTests/ExpandWhensSpec.scala +++ b/src/test/scala/firrtlTests/ExpandWhensSpec.scala @@ -11,14 +11,17 @@ import firrtl.ir._ import firrtl.Parser.IgnoreInfo class ExpandWhensSpec extends FirrtlFlatSpec { - private def executeTest(input: String, notExpected: String, passes: Seq[Pass]) = { + private def executeTest(input: String, check: String, passes: Seq[Pass], expected: Boolean) = { val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { (c: Circuit, p: Pass) => p.run(c) } val lines = c.serialize.split("\n") map normalized + println(c.serialize) - lines foreach { l => - l.contains(notExpected) should be (false) + if(expected) { + c.serialize.contains(check) should be (true) + } else { + lines foreach { l => l.contains(check) should be (false) } } } "Expand Whens" should "not emit INVALID" in { @@ -48,7 +51,48 @@ class ExpandWhensSpec extends FirrtlFlatSpec { | a is invalid | a.b <= UInt<64>("h04000000000000000")""".stripMargin val check = "INVALID" - executeTest(input, check, passes) + executeTest(input, check, passes, false) + } + "Expand Whens" should "void unwritten memory fields" in { + val passes = Seq( + ToWorkingIR, + CheckHighForm, + ResolveKinds, + InferTypes, + CheckTypes, + Uniquify, + ResolveKinds, + InferTypes, + ResolveGenders, + CheckGenders, + InferWidths, + CheckWidths, + PullMuxes, + ExpandConnects, + RemoveAccesses, + ExpandWhens) + val input = + """|circuit Tester : + | module Tester : + | input clk : Clock + | mem memory: + | data-type => UInt<32> + | depth => 32 + | reader => r0 + | writer => w0 + | read-latency => 0 + | write-latency => 1 + | read-under-write => undefined + | memory.r0.addr <= UInt<1>(1) + | memory.r0.en <= UInt<1>(1) + | memory.r0.clk <= clk + | memory.w0.addr <= UInt<1>(1) + | memory.w0.data <= UInt<1>(1) + | memory.w0.en <= UInt<1>(1) + | memory.w0.clk <= clk + | """.stripMargin + val check = "VOID" + executeTest(input, check, passes, true) } } |
