Fix CHIRRTL bugs (#355)

* handle uninferred ports gracefully in RemoveCHIRRTL

memory port directions are not inferred during CInferMDir if not being used, so handle them properly in RemoveCHIRRTL

* fix CInferTypes

5 files changed, 21 insertions, 4 deletions

diff --git a/src/main/scala/firrtl/passes/InferTypes.scala b/src/main/scala/firrtl/passes/InferTypes.scala
index 372d2942..0e503115 100644
--- a/src/main/scala/firrtl/passes/InferTypes.scala
+++ b/src/main/scala/firrtl/passes/InferTypes.scala
@@ -90,7 +90,7 @@ object CInferTypes extends Pass {
          case (e: SubIndex) => e copy (tpe = sub_type(e.expr.tpe))
          case (e: SubAccess) => e copy (tpe = sub_type(e.expr.tpe))
          case (e: DoPrim) => PrimOps.set_primop_type(e)
-         case (e: Mux) => e copy (tpe = mux_type(e.tval,e.tval))
+         case (e: Mux) => e copy (tpe = mux_type(e.tval, e.fval))
          case (e: ValidIf) => e copy (tpe = e.value.tpe)
          case e @ (_: UIntLiteral | _: SIntLiteral) => e
       }
@@ -103,8 +103,9 @@ object CInferTypes extends Pass {
         types(sx.name) = sx.tpe
         sx
       case sx: DefNode =>
-        types(sx.name) = sx.value.tpe
-        sx
+        val sxx = (sx map infer_types_e(types)).asInstanceOf[DefNode]
+        types(sxx.name) = sxx.value.tpe
+        sxx
       case sx: DefMemory =>
         types(sx.name) = MemPortUtils.memType(sx)
         sx
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
index abd45f75..aae4ca80 100644
--- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
+++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
@@ -52,6 +52,7 @@ object RemoveCHIRRTL extends Pass {
           case MRead => p.readers += MPort(sx.name, sx.exps(1))
           case MWrite => p.writers += MPort(sx.name, sx.exps(1))
           case MReadWrite => p.readwriters += MPort(sx.name, sx.exps(1))
+          case MInfer => // direction may not be inferred if it's not being used
         }
         mports(sx.mem) = p
       case _ =>
@@ -119,6 +120,7 @@ object RemoveCHIRRTL extends Pass {
               raddrs(e.name) = SubField(SubField(Reference(sx.mem, ut), sx.name, ut), "en", ut)
             case _ => ens += "en"
           }
+        case MInfer => // do nothing if it's not being used
       }
       Block(
         (addrs map (x => Connect(sx.info, SubField(SubField(Reference(sx.mem, ut), sx.name, ut), x, ut), sx.exps.head))) ++
diff --git a/src/test/resources/features/EmptyChirrtlMem.fir b/src/test/resources/features/EmptyChirrtlMem.fir
new file mode 100644
index 00000000..036d3830
--- /dev/null
+++ b/src/test/resources/features/EmptyChirrtlMem.fir
@@ -0,0 +1,5 @@
+circuit Queue :
+  module Queue :
+    input clock : Clock
+    cmem ram : UInt<1>[2]
+    infer mport T_107 = ram[UInt(0)], clock
diff --git a/src/test/resources/features/NodeType.fir b/src/test/resources/features/NodeType.fir
new file mode 100644
index 00000000..fe48871b
--- /dev/null
+++ b/src/test/resources/features/NodeType.fir
@@ -0,0 +1,8 @@
+circuit NodeType :
+  module NodeType :
+    input clock : Clock
+
+    cmem rf : UInt<64>[31]
+    node rf_wdata = mux(UInt(0), UInt(0), UInt(0))
+    infer mport port = rf[UInt(0)], clock
+    port <- rf_wdata
diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala
index 05c53cce..3b360de6 100644
--- a/src/test/scala/firrtlTests/ChirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala
@@ -71,4 +71,5 @@ class ChirrtlSpec extends FirrtlFlatSpec {
 }
 
 class ChirrtlMemsExecutionTest extends ExecutionTest("ChirrtlMems", "/features")
-
+class EmptyChirrtlMemCompilationTest extends CompilationTest("EmptyChirrtlMem", "/features")
+class NodeTypeCompilationTest extends CompilationTest("NodeType", "/features")