diff options
| author | azidar | 2016-11-03 10:43:18 -0700 |
|---|---|---|
| committer | azidar | 2016-11-03 10:43:18 -0700 |
| commit | ce1a91981e7fab75c8b41363b9ffcaedfcbef2e9 (patch) | |
| tree | e6c235f1433b35d4b9a025d86baf816656609e6a /src | |
| parent | 097cd70a1f44a4181297e4e6dadaec03f4c92636 (diff) | |
Added Legalize to MiddleToLowFirrtl
Makes low firrtl more like a netlist, should probably update spec
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index f42d11ba..446df6d0 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -127,7 +127,8 @@ class MiddleFirrtlToLowFirrtl extends Transform with SimpleRun { passes.InferTypes, passes.ResolveGenders, passes.InferWidths, - passes.ConvertFixedToSInt) + passes.ConvertFixedToSInt, + passes.Legalize) def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = run(circuit, passSeq) } |
