fix bug. remove spurious connect that reassigns node (#358)

1 files changed, 0 insertions, 1 deletions

diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
index 3aa63942..0bb1a617 100644
--- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
+++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
@@ -94,7 +94,6 @@ object VerilogMemDelays extends Pass {
               val condn = namespace newName s"${LowerTypes.loweredName(e)}_en"
               val condx = WRef(condn, BoolType, NodeKind, FEMALE)
               Seq(DefNode(NoInfo, condn, cond),
-                  Connect(NoInfo, condx, cond),
                   Connect(NoInfo, exx, Mux(condx, ex, exx, e.tpe)))
             })
           )