From 938f1e7317984f40e59bb7744d95124ab7350c1c Mon Sep 17 00:00:00 2001
From: Scott Beamer
Date: Tue, 1 Nov 2016 13:11:10 -0700
Subject: fix bug. remove spurious connect that reassigns node (#358)

---
 src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
index 3aa63942..0bb1a617 100644
--- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
+++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
@@ -94,7 +94,6 @@ object VerilogMemDelays extends Pass {
               val condn = namespace newName s"${LowerTypes.loweredName(e)}_en"
               val condx = WRef(condn, BoolType, NodeKind, FEMALE)
               Seq(DefNode(NoInfo, condn, cond),
-                  Connect(NoInfo, condx, cond),
                   Connect(NoInfo, exx, Mux(condx, ex, exx, e.tpe)))
             })
           )
-- 
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