Clk2clock - rename the implicit "clk" module input "clock" (#387)

* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.

26 files changed, 254 insertions, 254 deletions

diff --git a/src/test/resources/blackboxes/MultiExtModuleTester.fir b/src/test/resources/blackboxes/MultiExtModuleTester.fir
index fa8effdf..82ac172f 100644
--- a/src/test/resources/blackboxes/MultiExtModuleTester.fir
+++ b/src/test/resources/blackboxes/MultiExtModuleTester.fir
@@ -9,7 +9,7 @@ circuit MultiExtModuleTester :
     output bar : UInt<16>
 
   module MultiExtModuleTester :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     inst dut1 of SimpleExtModule
@@ -22,16 +22,16 @@ circuit MultiExtModuleTester :
 
     when not(reset) :
       when neq(dut1.bar, UInt(1234)) :
-        printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-        stop(clk, not(reset), 1)
+        printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+        stop(clock, not(reset), 1)
       else :
         when neq(dut2.bar, UInt(5678)) :
-          printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-          stop(clk, not(reset), 1)
+          printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+          stop(clock, not(reset), 1)
         else :
           when neq(dut3.bar, UInt(101)) :
-            printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-            stop(clk, not(reset), 1)
+            printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+            stop(clock, not(reset), 1)
           else :
-            stop(clk, not(reset), 0)
+            stop(clock, not(reset), 0)
 
diff --git a/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir b/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir
index eb9ba13f..3167cded 100644
--- a/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir
+++ b/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir
@@ -21,7 +21,7 @@ circuit ParameterizedExtModuleTester :
     parameter TYP = 'bit [1:0]'
 
   module ParameterizedExtModuleTester  :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     inst dut1 of ParameterizedExtModule_1
@@ -32,12 +32,12 @@ circuit ParameterizedExtModuleTester :
 
     when not(reset) :
       when neq(dut1.bar, UInt(1003)) :
-        printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-        stop(clk, not(reset), 1)
+        printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+        stop(clock, not(reset), 1)
       else :
         when neq(dut2.bar, UInt(1008)) :
-          printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-          stop(clk, not(reset), 1)
+          printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+          stop(clock, not(reset), 1)
         else :
-          stop(clk, not(reset), 0)
+          stop(clock, not(reset), 0)
 
diff --git a/src/test/resources/blackboxes/RenamedExtModuleTester.fir b/src/test/resources/blackboxes/RenamedExtModuleTester.fir
index 9e807813..37338c9f 100644
--- a/src/test/resources/blackboxes/RenamedExtModuleTester.fir
+++ b/src/test/resources/blackboxes/RenamedExtModuleTester.fir
@@ -7,7 +7,7 @@ circuit RenamedExtModuleTester :
     defname = SimpleExtModule
 
   module RenamedExtModuleTester :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     inst dut of ThisIsJustTheFirrtlName
@@ -16,8 +16,8 @@ circuit RenamedExtModuleTester :
 
     when not(reset) :
       when neq(dut.bar, UInt(1234)) :
-        printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-        stop(clk, not(reset), 1)
+        printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+        stop(clock, not(reset), 1)
       else :
-        stop(clk, not(reset), 0)
+        stop(clock, not(reset), 0)
 
diff --git a/src/test/resources/blackboxes/SimpleExtModuleTester.fir b/src/test/resources/blackboxes/SimpleExtModuleTester.fir
index 264ce5fa..7118ec9f 100644
--- a/src/test/resources/blackboxes/SimpleExtModuleTester.fir
+++ b/src/test/resources/blackboxes/SimpleExtModuleTester.fir
@@ -5,7 +5,7 @@ circuit SimpleExtModuleTester :
     output bar : UInt<16>
 
   module SimpleExtModuleTester :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     inst dut of SimpleExtModule
@@ -14,8 +14,8 @@ circuit SimpleExtModuleTester :
 
     when not(reset) :
       when neq(dut.bar, UInt(1234)) :
-        printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-        stop(clk, not(reset), 1)
+        printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+        stop(clock, not(reset), 1)
       else :
-        stop(clk, not(reset), 0)
+        stop(clock, not(reset), 0)
 
diff --git a/src/test/resources/features/ChirrtlMems.fir b/src/test/resources/features/ChirrtlMems.fir
index 6cc9f122..c51e3b78 100644
--- a/src/test/resources/features/ChirrtlMems.fir
+++ b/src/test/resources/features/ChirrtlMems.fir
@@ -1,22 +1,22 @@
 ; See LICENSE for license details.
 circuit ChirrtlMems :
   module ChirrtlMems :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     cmem ram : UInt<32>[16]
-    node newClock = clk
+    node newClock = clock
 
     wire wen : UInt<1>
     wen <= not(reset) ; Don't const prop me!
 
-    reg raddr : UInt<4>, clk with : (reset => (reset, UInt(0)))
+    reg raddr : UInt<4>, clock with : (reset => (reset, UInt(0)))
     raddr <= add(raddr, UInt(1))
     infer mport r = ram[raddr], newClock
 
     when wen :
-      node newerClock = clk
-      reg waddr : UInt<4>, clk with : (reset => (reset, UInt(0)))
+      node newerClock = clock
+      reg waddr : UInt<4>, clock with : (reset => (reset, UInt(0)))
       waddr <= add(waddr, UInt(1))
       infer mport w = ram[waddr], newerClock
       w <= waddr
@@ -27,8 +27,8 @@ circuit ChirrtlMems :
     when not(reset) :
       when gt(waddr, UInt(1)) :
         when neq(r, raddr) :
-          printf(clk, UInt(1), "Assertion failed! r =/= raddr\n")
-          stop(clk, UInt(1), 1) ; Failure!
+          printf(clock, UInt(1), "Assertion failed! r =/= raddr\n")
+          stop(clock, UInt(1), 1) ; Failure!
       when eq(raddr, UInt(15)) :
-        stop(clk, UInt(1), 0) ; Success!
+        stop(clock, UInt(1), 0) ; Success!
     
diff --git a/src/test/resources/features/CustomTransform.fir b/src/test/resources/features/CustomTransform.fir
index 61bd6ad2..de00f261 100644
--- a/src/test/resources/features/CustomTransform.fir
+++ b/src/test/resources/features/CustomTransform.fir
@@ -2,21 +2,21 @@
 circuit CustomTransform :
   ; Replaced in custom transform by an implementation
   extmodule Delay :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
     input a : UInt<32>
     input en : UInt<1>
     output b : UInt<32>
 
   module CustomTransform :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
-    reg cycle : UInt<32>, clk with : (reset => (reset, UInt<32>(0)))
+    reg cycle : UInt<32>, clock with : (reset => (reset, UInt<32>(0)))
     cycle <= tail(add(cycle, UInt<32>(1)), 1)
 
     inst delay of Delay
-    delay.clk <= clk
+    delay.clock <= clock
     delay.reset <= reset
     delay.a <= UInt(0)
     delay.en <= UInt(0)
@@ -26,9 +26,9 @@ circuit CustomTransform :
       delay.a <= UInt("hdeadbeef")
     when eq(cycle, UInt(1)) :
       when neq(delay.b, UInt("hdeadbeef")) :
-        printf(clk, UInt(1), "Assertion failed!\n")
-        stop(clk, UInt(1), 1)
+        printf(clock, UInt(1), "Assertion failed!\n")
+        stop(clock, UInt(1), 1)
     when eq(cycle, UInt(2)) :
-      printf(clk, UInt(1), "Success!\n")
-      stop(clk, UInt(1), 0)
+      printf(clock, UInt(1), "Success!\n")
+      stop(clock, UInt(1), 0)
 
diff --git a/src/test/resources/features/NestedSubAccessTester.fir b/src/test/resources/features/NestedSubAccessTester.fir
index c40da6a0..84b4cfbe 100644
--- a/src/test/resources/features/NestedSubAccessTester.fir
+++ b/src/test/resources/features/NestedSubAccessTester.fir
@@ -12,7 +12,7 @@ circuit NestedSubAccessTester :
     out <= vec[foo[index]]
 
   module NestedSubAccessTester :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     inst dut of NestedSubAccess
@@ -22,9 +22,9 @@ circuit NestedSubAccessTester :
     dut.foo[2] <= UInt(1)
 
     when neq(dut.out, UInt(4)) :
-      printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-      stop(clk, not(reset), 1)
+      printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+      stop(clock, not(reset), 1)
     else :
-      stop(clk, not(reset), 0)
+      stop(clock, not(reset), 0)
 
 
diff --git a/src/test/resources/features/Printf.fir b/src/test/resources/features/Printf.fir
index a19e2493..5e065b9c 100644
--- a/src/test/resources/features/Printf.fir
+++ b/src/test/resources/features/Printf.fir
@@ -1,17 +1,17 @@
 ; See LICENSE for license details.
 circuit Printf : 
   module Printf : 
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
-    reg count : UInt<10>, clk with :
+    reg count : UInt<10>, clock with :
       reset => (reset, UInt<6>(0))
-    reg const : UInt<32> clk with :
+    reg const : UInt<32> clock with :
       reset => (reset, UInt(123456))
 
     node notReset = not(reset)
     count <= add(count, UInt(1))
-    printf(clk, notReset, "\tcount = %d 0x%x b%b\\\'%d%%\'\n", count, count, count, const)
+    printf(clock, notReset, "\tcount = %d 0x%x b%b\\\'%d%%\'\n", count, count, count, const)
 
     when eq(count, UInt(255)) :
-      stop(clk, UInt(1), 0)
+      stop(clock, UInt(1), 0)
diff --git a/src/test/resources/features/ZeroPortMem.fir b/src/test/resources/features/ZeroPortMem.fir
index 7e509ecf..96327f5c 100644
--- a/src/test/resources/features/ZeroPortMem.fir
+++ b/src/test/resources/features/ZeroPortMem.fir
@@ -1,7 +1,7 @@
 ; See LICENSE for license details.
 circuit ZeroPortMem :
   module ZeroPortMem :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     mem mymem :
@@ -16,8 +16,8 @@ circuit ZeroPortMem :
 
     when not(reset) :
       when eq(foo, UInt<32>("hdeadbeef")) :
-        stop(clk, UInt(1), 0) ; Success !
+        stop(clock, UInt(1), 0) ; Success !
       else :
-        printf(clk, UInt(1), "Assertion failed!\n")
-        stop(clk, UInt(1), 1) ; Failure!
+        printf(clock, UInt(1), "Assertion failed!\n")
+        stop(clock, UInt(1), 1) ; Failure!
 
diff --git a/src/test/resources/passes/ExpandWhens/ExpandWhens.fir b/src/test/resources/passes/ExpandWhens/ExpandWhens.fir
index 7d4c4cbb..291cf1b4 100644
--- a/src/test/resources/passes/ExpandWhens/ExpandWhens.fir
+++ b/src/test/resources/passes/ExpandWhens/ExpandWhens.fir
@@ -1,12 +1,12 @@
 ; See LICENSE for license details.
 circuit ExpandWhens :
   module ExpandWhens :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     node done = UInt(6)
 
-    reg x : UInt<16>, clk with :
+    reg x : UInt<16>, clock with :
       reset => (reset, UInt(0))
     x <= x
 
@@ -30,18 +30,18 @@ circuit ExpandWhens :
         when lt(x, UInt(5)) :
           x <= UInt(5)
 
-    reg count : UInt<16>, clk with :
+    reg count : UInt<16>, clock with :
       reset => (reset, UInt(0))
     when neq(count, done) :
       count <= add(count, UInt(1))
 
-    printf(clk, UInt(1), "count = %d, x = %d\n", count, x)
+    printf(clock, UInt(1), "count = %d, x = %d\n", count, x)
 
     when not(reset) :
       when neq(x, count) : 
-        printf(clk, UInt(1), "Assertion failed! x =/= count!\n")
-        stop(clk, UInt(1), 1)
+        printf(clock, UInt(1), "Assertion failed! x =/= count!\n")
+        stop(clock, UInt(1), 1)
       when eq(x, done) :
-        stop(clk, UInt(1), 0)
+        stop(clock, UInt(1), 0)
 
      
diff --git a/src/test/resources/passes/Legalize/Legalize.fir b/src/test/resources/passes/Legalize/Legalize.fir
index 8d8ac8bd..716dff83 100644
--- a/src/test/resources/passes/Legalize/Legalize.fir
+++ b/src/test/resources/passes/Legalize/Legalize.fir
@@ -1,18 +1,18 @@
 ; See LICENSE for license details.
 circuit Legalize :
   module Legalize :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     ; Count till done
     node done = UInt(6)
-    reg count : UInt<16>, clk with :
+    reg count : UInt<16>, clock with :
       reset => (reset, UInt(0))
     when neq(count, done) :
       count <= add(count, UInt(1))
     when not(reset) :
       when eq(count, done) :
-        stop(clk, UInt(1), 0)
+        stop(clock, UInt(1), 0)
 
     ; Begin Test
     ; Check assignment to smaller width
@@ -20,22 +20,22 @@ circuit Legalize :
     wire y : UInt<16>
     y <- x
     when neq(y, UInt("hbeef")) :
-      printf(clk, UInt(1), "Assertion failed!\n y != beef\n")
-      stop(clk, UInt(1), 1)
+      printf(clock, UInt(1), "Assertion failed!\n y != beef\n")
+      stop(clock, UInt(1), 1)
 
     ; Check bit select of literal
     node b = bits(UInt("hd0"), 7, 5)
     node b2 = bits(UInt("h9"), 3, 3)
     when neq(b, UInt(6)) :
-      printf(clk, UInt(1), "Assertion failed!\n b != 6\n")
-      stop(clk, UInt(1), 1)
+      printf(clock, UInt(1), "Assertion failed!\n b != 6\n")
+      stop(clock, UInt(1), 1)
     when neq(b2, UInt(1)) :
-      printf(clk, UInt(1), "Assertion failed!\n b2 != 1\n")
-      stop(clk, UInt(1), 1)
+      printf(clock, UInt(1), "Assertion failed!\n b2 != 1\n")
+      stop(clock, UInt(1), 1)
 
     ; Check padding of literal
     node bar = pad(SInt(-1), 16)
     node bar_15 = bits(bar, 15, 15)
     when neq(bar_15, UInt(1)) :
-      printf(clk, UInt(1), "Assertion failed!\n bar_15 != 0\n")
-      stop(clk, UInt(1), 1)
+      printf(clock, UInt(1), "Assertion failed!\n bar_15 != 0\n")
+      stop(clock, UInt(1), 1)
diff --git a/src/test/resources/top.cpp b/src/test/resources/top.cpp
index c117126d..08ad42fa 100644
--- a/src/test/resources/top.cpp
+++ b/src/test/resources/top.cpp
@@ -46,10 +46,10 @@ int main(int argc, char** argv) {
       top->reset = 0;   // Deassert reset
     }
     if ((main_time % 10) == 1) {
-      top->clk = 1;       // Toggle clock
+      top->clock = 1;       // Toggle clock
     }
     if ((main_time % 10) == 6) {
-      top->clk = 0;
+      top->clock = 0;
     }
     top->eval();               // Evaluate model
 #if VM_TRACE
@@ -70,10 +70,10 @@ int main(int argc, char** argv) {
   vluint64_t end_time = main_time + 100;
   while (main_time < end_time) {
     if ((main_time % 10) == 1) {
-      top->clk = 1;       // Toggle clock
+      top->clock = 1;       // Toggle clock
     }
     if ((main_time % 10) == 6) {
-      top->clk = 0;
+      top->clock = 0;
     }
     top->eval();               // Evaluate model
 #if VM_TRACE
diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala
index c3df4232..2eba9b96 100644
--- a/src/test/scala/firrtlTests/AttachSpec.scala
+++ b/src/test/scala/firrtlTests/AttachSpec.scala
@@ -210,7 +210,7 @@ class AttachAnalogSpec extends FirrtlFlatSpec {
     val input =
       """circuit Unit :
         |  module Unit :
-        |    input clk: Clock
+        |    input clock: Clock
         |    mem m: 
         |      data-type => Analog<2>
         |      depth => 4
diff --git a/src/test/scala/firrtlTests/CInferMDirSpec.scala b/src/test/scala/firrtlTests/CInferMDirSpec.scala
index 1385b29d..3721543b 100644
--- a/src/test/scala/firrtlTests/CInferMDirSpec.scala
+++ b/src/test/scala/firrtlTests/CInferMDirSpec.scala
@@ -48,7 +48,7 @@ class CInferMDir extends LowTransformSpec {
     val input = """
 circuit foo :
   module foo :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
     output io : {flip wen : UInt<1>, flip in : UInt<1>, flip counter : UInt<2>, ren: UInt<1>[4], out : UInt<1>[4]}
 
@@ -56,7 +56,7 @@ circuit foo :
     cmem indices : UInt<2>[4]
     node T_0 = add(io.counter, UInt<1>("h01"))
     node temp = tail(T_0, 1)
-    infer mport index = indices[temp], clk
+    infer mport index = indices[temp], clock
     io.out[0] <= UInt<1>("h0")
     io.out[1] <= UInt<1>("h0")
     io.out[2] <= UInt<1>("h0")
@@ -65,7 +65,7 @@ circuit foo :
       io.out[index] <= io.in
     else :
       when io.wen :
-        infer mport bar = indices[temp], clk
+        infer mport bar = indices[temp], clock
         bar <= io.in
 """.stripMargin
 
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index 7b0f76a7..2fe5baf5 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -166,7 +166,7 @@ class CheckSpec extends FlatSpec with Matchers {
           |    input jtag : {TCK : Clock}
           | 
           |  module TheRealTop : 
-          |    input clk : Clock
+          |    input clock : Clock
           |    input reset : UInt<1>
           |    output io : {flip jtag : {TCK : Clock}}
           |    
diff --git a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
index 3d8c9825..2bbe46c8 100644
--- a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
@@ -61,7 +61,7 @@ class ChirrtlMemSpec extends LowTransformSpec {
     val input = """
 circuit foo :
   module foo :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
     output io : {flip wen : UInt<1>, flip in : UInt<1>, flip counter : UInt<2>, out : UInt<1>}
 
@@ -69,9 +69,9 @@ circuit foo :
     smem mem : UInt<1>[4]
     node T_0 = add(io.counter, UInt<1>("h01"))
     node temp = tail(T_0, 1)
-    read mport bar = mem[temp], clk
+    read mport bar = mem[temp], clock
     when io.wen :
-      write mport T_1 = mem[io.counter], clk
+      write mport T_1 = mem[io.counter], clock
       T_1 <= io.in
     io.out <= bar
 """.stripMargin
@@ -87,18 +87,18 @@ circuit foo :
     val input = """
 circuit foo :
   module foo :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
     output io : {flip ren: UInt<1>, flip wen : UInt<1>, flip in : UInt<1>, flip counter : UInt<2>, out : UInt<1>}
 
     io is invalid
     cmem mem : UInt<1>[4]
-    reg counter : UInt<1>, clk with : (reset => (reset, UInt<1>("h0")))
-    read mport bar = mem[counter], clk
+    reg counter : UInt<1>, clock with : (reset => (reset, UInt<1>("h0")))
+    read mport bar = mem[counter], clock
     when io.ren:
       counter <= add(counter, UInt<1>("h1"))
     when io.wen :
-      write mport T_1 = mem[io.counter], clk
+      write mport T_1 = mem[io.counter], clock
       T_1 <= io.in
     io.out <= bar
 """.stripMargin
diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala
index 3b360de6..0ae112f0 100644
--- a/src/test/scala/firrtlTests/ChirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala
@@ -35,9 +35,9 @@ class ChirrtlSpec extends FirrtlFlatSpec {
     val input =
      """circuit Unit :
        |  module Unit :
-       |    input clk : Clock
+       |    input clock : Clock
        |    smem ram : UInt<32>[128]
-       |    node newClock = clk
+       |    node newClock = clock
        |    infer mport x = ram[UInt(2)], newClock
        |    x <= UInt(3)
        |    when UInt(1) :
@@ -53,9 +53,9 @@ class ChirrtlSpec extends FirrtlFlatSpec {
     val input =
      """circuit Unit :
        |  module Unit :
-       |    input clk : Clock
+       |    input clock : Clock
        |    smem ram : UInt<32>[128]
-       |    node newClock = clk
+       |    node newClock = clock
        |    infer mport x = ram[UInt(2)], newClock
        |    x <= UInt(3)
        |    when UInt(1) :
diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala
index 4a3faf6b..3a20082f 100644
--- a/src/test/scala/firrtlTests/CustomTransformSpec.scala
+++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala
@@ -15,13 +15,13 @@ class CustomTransformSpec extends FirrtlFlatSpec {
     val delayModuleString = """
       |circuit Delay :
       |  module Delay :
-      |    input clk : Clock
+      |    input clock : Clock
       |    input reset : UInt<1>
       |    input a : UInt<32>
       |    input en : UInt<1>
       |    output b : UInt<32>
       |
-      |    reg r : UInt<32>, clk
+      |    reg r : UInt<32>, clock
       |    r <= r
       |    when en :
       |      r <= a
diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
index b92feacd..a5eea147 100644
--- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala
+++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
@@ -55,7 +55,7 @@ class InferReadWriteSpec extends SimpleTransformSpec {
     val input = """
 circuit sram6t :
   module sram6t :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
     output io : {flip en : UInt<1>, flip wen : UInt<1>, flip waddr : UInt<8>, flip wdata : UInt<32>, flip raddr : UInt<8>, rdata : UInt<32>}
 
@@ -67,11 +67,11 @@ circuit sram6t :
     T_2 is invalid
     when T_1 :
       T_2 <= io.raddr
-    read mport T_3 = mem[T_2], clk
+    read mport T_3 = mem[T_2], clock
     io.rdata <= T_3
     node T_4 = and(io.en, io.wen)
     when T_4 :
-      write mport T_5 = mem[io.waddr], clk
+      write mport T_5 = mem[io.waddr], clock
       T_5 <= io.wdata
 """.stripMargin
 
diff --git a/src/test/scala/firrtlTests/LowerTypesSpec.scala b/src/test/scala/firrtlTests/LowerTypesSpec.scala
index b48bcd16..89461f12 100644
--- a/src/test/scala/firrtlTests/LowerTypesSpec.scala
+++ b/src/test/scala/firrtlTests/LowerTypesSpec.scala
@@ -66,16 +66,16 @@ class LowerTypesSpec extends FirrtlFlatSpec {
     val input =
       """circuit Test :
         |  module Test :
-        |    input clk : Clock
+        |    input clock : Clock
         |    input reset : UInt<1>
-        |    reg w : UInt<1>, clk
-        |    reg x : {a : UInt<1>, b : UInt<1>}, clk
-        |    reg y : UInt<1>[4], clk
-        |    reg z : { c : { d : UInt<1>, e : UInt<1>}, f : UInt<1>[2] }[2], clk
+        |    reg w : UInt<1>, clock
+        |    reg x : {a : UInt<1>, b : UInt<1>}, clock
+        |    reg y : UInt<1>[4], clock
+        |    reg z : { c : { d : UInt<1>, e : UInt<1>}, f : UInt<1>[2] }[2], clock
       """.stripMargin
     val expected = Seq("w", "x_a", "x_b", "y_0", "y_1", "y_2", "y_3", "z_0_c_d",
       "z_0_c_e", "z_0_f_0", "z_0_f_1", "z_1_c_d", "z_1_c_e", "z_1_f_0",
-      "z_1_f_1") map (x => s"reg $x : UInt<1>, clk with :") map normalized
+      "z_1_f_1") map (x => s"reg $x : UInt<1>, clock with :") map normalized
 
     executeTest(input, expected)
   }
@@ -84,34 +84,34 @@ class LowerTypesSpec extends FirrtlFlatSpec {
     val input =
      """circuit Test :
        |  module Test :
-       |    input clk : Clock
+       |    input clock : Clock
        |    input reset : UInt<1>
        |    input init : { a : UInt<1>, b : UInt<1>}[2]
-       |    reg x : { a : UInt<1>, b : UInt<1>}[2], clk with :
+       |    reg x : { a : UInt<1>, b : UInt<1>}[2], clock with :
        |      reset => (reset, init)
      """.stripMargin
     val expected = Seq(
-      "reg x_0_a : UInt<1>, clk with :", "reset => (reset, init_0_a)",
-      "reg x_0_b : UInt<1>, clk with :", "reset => (reset, init_0_b)",
-      "reg x_1_a : UInt<1>, clk with :", "reset => (reset, init_1_a)",
-      "reg x_1_b : UInt<1>, clk with :", "reset => (reset, init_1_b)"
+      "reg x_0_a : UInt<1>, clock with :", "reset => (reset, init_0_a)",
+      "reg x_0_b : UInt<1>, clock with :", "reset => (reset, init_0_b)",
+      "reg x_1_a : UInt<1>, clock with :", "reset => (reset, init_1_a)",
+      "reg x_1_b : UInt<1>, clock with :", "reset => (reset, init_1_b)"
     ) map normalized
 
     executeTest(input, expected)
   }
 
-  it should "lower DefRegister expressions: clk, reset, and init" in {
+  it should "lower DefRegister expressions: clock, reset, and init" in {
     val input =
       """circuit Test :
         |  module Test :
-        |    input clk : Clock[2]
+        |    input clock : Clock[2]
         |    input reset : { a : UInt<1>, b : UInt<1>}
         |    input init : { a : UInt<4>, b : { c : UInt<4>, d : UInt<4>}[2]}[4]
-        |    reg foo : UInt<4>, clk[1], with :
+        |    reg foo : UInt<4>, clock[1], with :
         |      reset => (reset.a, init[3].b[1].d)
       """.stripMargin
     val expected = Seq(
-      "reg foo : UInt<4>, clk_1 with :",
+      "reg foo : UInt<4>, clock_1 with :",
       "reset => (reset_a, init_3_b_1_d)"
     ) map normalized
 
@@ -145,7 +145,7 @@ class LowerTypesSpec extends FirrtlFlatSpec {
     val input =
      """circuit Test :
        |  module Test :
-       |    input clk : Clock
+       |    input clock : Clock
        |    mem m :
        |      data-type => { a : UInt<8>, b : UInt<8>}[2]
        |      depth => 32
@@ -153,13 +153,13 @@ class LowerTypesSpec extends FirrtlFlatSpec {
        |      write-latency => 1
        |      reader => read
        |      writer => write
-       |    m.read.clk <= clk
+       |    m.read.clk <= clock
        |    m.read.en <= UInt<1>(1)
        |    m.read.addr is invalid
        |    node x = m.read.data
        |    node y = m.read.data[0].b
        |
-       |    m.write.clk <= clk
+       |    m.write.clk <= clock
        |    m.write.en <= UInt<1>(0)
        |    m.write.mask is invalid
        |    m.write.addr is invalid
@@ -173,8 +173,8 @@ class LowerTypesSpec extends FirrtlFlatSpec {
      """.stripMargin
     val expected = Seq(
       "mem m_0_a :", "mem m_0_b :", "mem m_1_a :", "mem m_1_b :",
-      "m_0_a.read.clk <= clk", "m_0_b.read.clk <= clk",
-      "m_1_a.read.clk <= clk", "m_1_b.read.clk <= clk",
+      "m_0_a.read.clk <= clock", "m_0_b.read.clk <= clock",
+      "m_1_a.read.clk <= clock", "m_1_b.read.clk <= clock",
       "m_0_a.read.addr is invalid", "m_0_b.read.addr is invalid",
       "m_1_a.read.addr is invalid", "m_1_b.read.addr is invalid",
       "node x_0_a = m_0_a.read.data", "node x_0_b = m_0_b.read.data",
diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
index 2cde085a..b851f176 100644
--- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala
+++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
@@ -27,7 +27,7 @@ class ReplSeqMemSpec extends SimpleTransformSpec {
     val input = """
 circuit Top : 
   module Top : 
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
     input head_ptr : UInt<5>
     input tail_ptr : UInt<5>
@@ -40,15 +40,15 @@ circuit Top :
 
     smem entries_info : {takens : UInt<2>, history : UInt<14>, info : UInt<14>}[24]
     when io.backend.allocate.valid :
-      write mport W = entries_info[tail_ptr], clk
+      write mport W = entries_info[tail_ptr], clock
       W <- io.backend.allocate.bits.info
 
-    read mport R = entries_info[head_ptr], clk
+    read mport R = entries_info[head_ptr], clock
     io.commit_entry.bits.info <- R
 
     smem entries_info2 : {takens : UInt<2>, history : UInt<14>, info : UInt<14>}[24]
     when io2.backend.allocate.valid :
-      write mport W1 = entries_info2[tail_ptr], clk
+      write mport W1 = entries_info2[tail_ptr], clock
       when wmask.takens :
         W1.takens <- io.backend.allocate.bits.info.takens
       when wmask.history :
@@ -56,7 +56,7 @@ circuit Top :
       when wmask.info :
         W1.info <- io.backend.allocate.bits.info.history
       
-    read mport R1 = entries_info2[head_ptr], clk
+    read mport R1 = entries_info2[head_ptr], clock
     io2.commit_entry.bits.info <- R1
 """.stripMargin
     val confLoc = "ReplSeqMemTests.confTEMP"
@@ -72,15 +72,15 @@ circuit Top :
     val input = """
 circuit Top :
   module Top :
-    input clk : Clock
+    input clock : Clock
     input hsel : UInt<1>
 
-    reg p_valid : UInt<1>, clk
-    reg p_address : UInt<5>, clk
+    reg p_valid : UInt<1>, clock
+    reg p_address : UInt<5>, clock
     smem mem : UInt<8>[8][32] 
     when hsel : 
       when p_valid : 
-        write mport T_155 = mem[p_address], clk
+        write mport T_155 = mem[p_address], clock
 """.stripMargin
     val confLoc = "ReplSeqMemTests.confTEMP"
     val aMap = AnnotationMap(Seq(ReplSeqMemAnnotation("-c:Top:-o:"+confLoc)))
diff --git a/src/test/scala/firrtlTests/UniquifySpec.scala b/src/test/scala/firrtlTests/UniquifySpec.scala
index b43efbe5..14c0f652 100644
--- a/src/test/scala/firrtlTests/UniquifySpec.scala
+++ b/src/test/scala/firrtlTests/UniquifySpec.scala
@@ -52,15 +52,15 @@ class UniquifySpec extends FirrtlFlatSpec {
     val input =
       """circuit Test :
         |  module Test :
-        |    input clk : Clock
-        |    reg a : { b : UInt<1>, c : { d : UInt<2>, e : UInt<3>}[2], c_1_e : UInt<4>}[2], clk
-        |    reg a_0_c_ : UInt<5>, clk
-        |    reg a__0 : UInt<6>, clk
+        |    input clock : Clock
+        |    reg a : { b : UInt<1>, c : { d : UInt<2>, e : UInt<3>}[2], c_1_e : UInt<4>}[2], clock
+        |    reg a_0_c_ : UInt<5>, clock
+        |    reg a__0 : UInt<6>, clock
       """.stripMargin
     val expected = Seq(
-      "reg a__ : { b : UInt<1>, c_ : { d : UInt<2>, e : UInt<3>}[2], c_1_e : UInt<4>}[2], clk with :",
-      "reg a_0_c_ : UInt<5>, clk with :",
-      "reg a__0 : UInt<6>, clk with :") map normalized
+      "reg a__ : { b : UInt<1>, c_ : { d : UInt<2>, e : UInt<3>}[2], c_1_e : UInt<4>}[2], clock with :",
+      "reg a_0_c_ : UInt<5>, clock with :",
+      "reg a__0 : UInt<6>, clock with :") map normalized
 
     executeTest(input, expected)
   }
@@ -69,8 +69,8 @@ class UniquifySpec extends FirrtlFlatSpec {
     val input =
       """circuit Test :
         |  module Test :
-        |    input clk : Clock
-        |    reg x : { b : UInt<1>, c : { d : UInt<2>, e : UInt<3>}[2], c_1_e : UInt<4>}[2], clk
+        |    input clock : Clock
+        |    reg x : { b : UInt<1>, c : { d : UInt<2>, e : UInt<3>}[2], c_1_e : UInt<4>}[2], clock
         |    node a = x
         |    node a_0_c_ = a[0].b
         |    node a__0  = a[1].c[0].d
@@ -81,21 +81,21 @@ class UniquifySpec extends FirrtlFlatSpec {
   }
 
 
-  it should "rename DefRegister expressions: clk, reset, and init" in {
+  it should "rename DefRegister expressions: clock, reset, and init" in {
     val input =
       """circuit Test :
         |  module Test :
-        |    input clk : Clock[2]
-        |    input clk_0 : Clock
+        |    input clock : Clock[2]
+        |    input clock_0 : Clock
         |    input reset : { a : UInt<1>, b : UInt<1>}
         |    input reset_a : UInt<1>
         |    input init : { a : UInt<4>, b : { c : UInt<4>, d : UInt<4>}[2], b_1_c : UInt<4>}[4]
         |    input init_0_a : UInt<4>
-        |    reg foo : UInt<4>, clk[1], with :
+        |    reg foo : UInt<4>, clock[1], with :
         |      reset => (reset.a, init[3].b[1].d)
       """.stripMargin
     val expected = Seq(
-      "reg foo : UInt<4>, clk_[1] with :",
+      "reg foo : UInt<4>, clock_[1] with :",
       "reset => (reset_.a, init_[3].b_[1].d)"
     ) map normalized
 
@@ -187,7 +187,7 @@ class UniquifySpec extends FirrtlFlatSpec {
     val input =
       """circuit Test :
         |  module Test :
-        |    input clk : Clock
+        |    input clock : Clock
         |    mem mem :
         |      data-type => { a : UInt<8>, b : UInt<8>[2]}[2]
         |      depth => 32
@@ -199,12 +199,12 @@ class UniquifySpec extends FirrtlFlatSpec {
         |
         |    mem.read.addr is invalid
         |    mem.read.en <= UInt(1)
-        |    mem.read.clk <= clk
+        |    mem.read.clk <= clock
         |    mem.write.data is invalid
         |    mem.write.mask is invalid
         |    mem.write.addr is invalid
         |    mem.write.en <= UInt(0)
-        |    mem.write.clk <= clk
+        |    mem.write.clk <= clock
       """.stripMargin
     val expected = Seq(
       "mem mem_ :",
@@ -218,7 +218,7 @@ class UniquifySpec extends FirrtlFlatSpec {
     val input =
       """circuit Test :
         |  module Test :
-        |    input clk : Clock
+        |    input clock : Clock
         |    mem mem :
         |      data-type => { a : UInt<8>, b : UInt<8>[2], b_0 : UInt<8> }
         |      depth => 32
@@ -230,12 +230,12 @@ class UniquifySpec extends FirrtlFlatSpec {
         |
         |    mem.read.addr is invalid
         |    mem.read.en <= UInt(1)
-        |    mem.read.clk <= clk
+        |    mem.read.clk <= clock
         |    mem.write.data is invalid
         |    mem.write.mask is invalid
         |    mem.write.addr is invalid
         |    mem.write.en <= UInt(0)
-        |    mem.write.clk <= clk
+        |    mem.write.clk <= clock
       """.stripMargin
     val expected = Seq(
       "data-type => { a : UInt<8>, b_ : UInt<8>[2], b_0 : UInt<8>}",
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index cb07448f..ec328818 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -71,10 +71,10 @@ class UnitTests extends FirrtlFlatSpec {
     val input =
      """circuit Unit :
        |  module Unit :
-       |    input clk : Clock
+       |    input clock : Clock
        |    input reset : UInt<1>
        |    wire x : { valid : UInt<1> }
-       |    reg y : { valid : UInt<1>, bits : UInt<3> }, clk with :
+       |    reg y : { valid : UInt<1>, bits : UInt<3> }, clock with :
        |      reset => (reset, x)""".stripMargin
     intercept[CheckTypes.InvalidRegInit] {
       passes.foldLeft(parse(input)) {
@@ -202,13 +202,13 @@ class UnitTests extends FirrtlFlatSpec {
     val input =
       """circuit AssignViaDeref : 
          |  module AssignViaDeref : 
-         |    input clk : Clock
+         |    input clock : Clock
          |    input reset : UInt<1>
          |    output io : {a : UInt<8>, sel : UInt<1>}
          |
          |    io is invalid
-         |    reg table : {a : UInt<8>}[2], clk
-         |    reg otherTable : {a : UInt<8>}[2], clk
+         |    reg table : {a : UInt<8>}[2], clock
+         |    reg otherTable : {a : UInt<8>}[2], clock
          |    otherTable[table[UInt<1>("h01")].a].a <= UInt<1>("h00")""".stripMargin
      //TODO(azidar): I realize this is brittle, but unfortunately there
      //  isn't a better way to test this pass
diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala
index e8143741..e84cbf47 100644
--- a/src/test/scala/firrtlTests/WiringTests.scala
+++ b/src/test/scala/firrtlTests/WiringTests.scala
@@ -39,78 +39,78 @@ class WiringTests extends FirrtlFlatSpec {
     val input =
       """circuit Top :
         |  module Top :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst a of A
-        |    a.clk <= clk
+        |    a.clock <= clock
         |  module A :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst b of B
-        |    b.clk <= clk
+        |    b.clock <= clock
         |    inst x of X
-        |    x.clk <= clk
+        |    x.clock <= clock
         |    inst d of D
-        |    d.clk <= clk
+        |    d.clock <= clock
         |  module B :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst c of C
-        |    c.clk <= clk
+        |    c.clock <= clock
         |    inst d of D
-        |    d.clk <= clk
+        |    d.clock <= clock
         |  module C :
-        |    input clk: Clock
-        |    reg r: UInt<5>, clk
+        |    input clock: Clock
+        |    reg r: UInt<5>, clock
         |  module D :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst x1 of X
-        |    x1.clk <= clk
+        |    x1.clock <= clock
         |    inst x2 of X
-        |    x2.clk <= clk
+        |    x2.clock <= clock
         |  extmodule X :
-        |    input clk: Clock
+        |    input clock: Clock
         |""".stripMargin
     val check =
       """circuit Top :
         |  module Top :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst a of A
-        |    a.clk <= clk
+        |    a.clock <= clock
         |  module A :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst b of B
-        |    b.clk <= clk
+        |    b.clock <= clock
         |    inst x of X
-        |    x.clk <= clk
+        |    x.clock <= clock
         |    inst d of D
-        |    d.clk <= clk
+        |    d.clock <= clock
         |    wire r: UInt<5>
         |    r <= b.r
         |    x.pin <= r
         |    d.r <= r
         |  module B :
-        |    input clk: Clock
+        |    input clock: Clock
         |    output r: UInt<5>
         |    inst c of C
-        |    c.clk <= clk
+        |    c.clock <= clock
         |    inst d of D
-        |    d.clk <= clk
+        |    d.clock <= clock
         |    r <= c.r_0
         |    d.r <= r
         |  module C :
-        |    input clk: Clock
+        |    input clock: Clock
         |    output r_0: UInt<5>
-        |    reg r: UInt<5>, clk
+        |    reg r: UInt<5>, clock
         |    r_0 <= r
         |  module D :
-        |    input clk: Clock
+        |    input clock: Clock
         |    input r: UInt<5>
         |    inst x1 of X
-        |    x1.clk <= clk
+        |    x1.clock <= clock
         |    inst x2 of X
-        |    x2.clk <= clk
+        |    x2.clock <= clock
         |    x1.pin <= r
         |    x2.pin <= r
         |  extmodule X :
-        |    input clk: Clock
+        |    input clock: Clock
         |    input pin: UInt<5>
         |""".stripMargin
     val c = passes.foldLeft(parse(input)) {
@@ -127,33 +127,33 @@ class WiringTests extends FirrtlFlatSpec {
     val input =
       """circuit Top :
         |  module Top :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst a of A
-        |    a.clk <= clk
+        |    a.clock <= clock
         |  module A :
-        |    input clk: Clock
-        |    reg r : {x: UInt<5>}, clk
+        |    input clock: Clock
+        |    reg r : {x: UInt<5>}, clock
         |    inst x of X
-        |    x.clk <= clk
+        |    x.clock <= clock
         |  extmodule X :
-        |    input clk: Clock
+        |    input clock: Clock
         |""".stripMargin
     val check =
       """circuit Top :
         |  module Top :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst a of A
-        |    a.clk <= clk
+        |    a.clock <= clock
         |  module A :
-        |    input clk: Clock
-        |    reg r: {x: UInt<5>}, clk
+        |    input clock: Clock
+        |    reg r: {x: UInt<5>}, clock
         |    inst x of X
-        |    x.clk <= clk
+        |    x.clock <= clock
         |    wire r_x: UInt<5>
         |    r_x <= r.x
         |    x.pin <= r_x
         |  extmodule X :
-        |    input clk: Clock
+        |    input clock: Clock
         |    input pin: UInt<5>
         |""".stripMargin
     val c = passes.foldLeft(parse(input)) {
@@ -163,37 +163,37 @@ class WiringTests extends FirrtlFlatSpec {
     val retC = wiringPass.run(c)
     (parse(retC.serialize).serialize) should be (parse(check).serialize)
   }
-  "Wiring from clk to X" should "work" in {
+  "Wiring from clock to X" should "work" in {
     val sinks = Set("X")
-    val sas = WiringInfo("A", "clk", sinks, "pin", "A")
+    val sas = WiringInfo("A", "clock", sinks, "pin", "A")
     val input =
       """circuit Top :
         |  module Top :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst a of A
-        |    a.clk <= clk
+        |    a.clock <= clock
         |  module A :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst x of X
-        |    x.clk <= clk
+        |    x.clock <= clock
         |  extmodule X :
-        |    input clk: Clock
+        |    input clock: Clock
         |""".stripMargin
     val check =
       """circuit Top :
         |  module Top :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst a of A
-        |    a.clk <= clk
+        |    a.clock <= clock
         |  module A :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst x of X
-        |    x.clk <= clk
-        |    wire clk_0: Clock
-        |    clk_0 <= clk
-        |    x.pin <= clk_0
+        |    x.clock <= clock
+        |    wire clock_0: Clock
+        |    clock_0 <= clock
+        |    x.pin <= clock_0
         |  extmodule X :
-        |    input clk: Clock
+        |    input clock: Clock
         |    input pin: Clock
         |""".stripMargin
     val c = passes.foldLeft(parse(input)) {
@@ -205,21 +205,21 @@ class WiringTests extends FirrtlFlatSpec {
   }
   "Two sources" should "fail" in {
     val sinks = Set("X")
-    val sas = WiringInfo("A", "clk", sinks, "pin", "Top")
+    val sas = WiringInfo("A", "clock", sinks, "pin", "Top")
     val input =
       """circuit Top :
         |  module Top :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst a1 of A
-        |    a1.clk <= clk
+        |    a1.clock <= clock
         |    inst a2 of A
-        |    a2.clk <= clk
+        |    a2.clock <= clock
         |  module A :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst x of X
-        |    x.clk <= clk
+        |    x.clock <= clock
         |  extmodule X :
-        |    input clk: Clock
+        |    input clock: Clock
         |""".stripMargin
     intercept[WiringException] {
       val c = passes.foldLeft(parse(input)) {
@@ -229,41 +229,41 @@ class WiringTests extends FirrtlFlatSpec {
       val retC = wiringPass.run(c)
     }
   }
-  "Wiring from A.clk to X, with 2 A's, and A as top" should "work" in {
+  "Wiring from A.clock to X, with 2 A's, and A as top" should "work" in {
     val sinks = Set("X")
-    val sas = WiringInfo("A", "clk", sinks, "pin", "A")
+    val sas = WiringInfo("A", "clock", sinks, "pin", "A")
     val input =
       """circuit Top :
         |  module Top :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst a1 of A
-        |    a1.clk <= clk
+        |    a1.clock <= clock
         |    inst a2 of A
-        |    a2.clk <= clk
+        |    a2.clock <= clock
         |  module A :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst x of X
-        |    x.clk <= clk
+        |    x.clock <= clock
         |  extmodule X :
-        |    input clk: Clock
+        |    input clock: Clock
         |""".stripMargin
     val check =
       """circuit Top :
         |  module Top :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst a1 of A
-        |    a1.clk <= clk
+        |    a1.clock <= clock
         |    inst a2 of A
-        |    a2.clk <= clk
+        |    a2.clock <= clock
         |  module A :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst x of X
-        |    x.clk <= clk
-        |    wire clk_0: Clock
-        |    clk_0 <= clk
-        |    x.pin <= clk_0
+        |    x.clock <= clock
+        |    wire clock_0: Clock
+        |    clock_0 <= clock
+        |    x.pin <= clock_0
         |  extmodule X :
-        |    input clk: Clock
+        |    input clock: Clock
         |    input pin: Clock
         |""".stripMargin
     val c = passes.foldLeft(parse(input)) {
@@ -273,25 +273,25 @@ class WiringTests extends FirrtlFlatSpec {
     val retC = wiringPass.run(c)
     (parse(retC.serialize).serialize) should be (parse(check).serialize)
   }
-  "Wiring from A.clk to X, with 2 A's, and A as top, but Top instantiates X" should "error" in {
+  "Wiring from A.clock to X, with 2 A's, and A as top, but Top instantiates X" should "error" in {
     val sinks = Set("X")
-    val sas = WiringInfo("A", "clk", sinks, "pin", "A")
+    val sas = WiringInfo("A", "clock", sinks, "pin", "A")
     val input =
       """circuit Top :
         |  module Top :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst a1 of A
-        |    a1.clk <= clk
+        |    a1.clock <= clock
         |    inst a2 of A
-        |    a2.clk <= clk
+        |    a2.clock <= clock
         |    inst x of X
-        |    x.clk <= clk
+        |    x.clock <= clock
         |  module A :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst x of X
-        |    x.clk <= clk
+        |    x.clock <= clock
         |  extmodule X :
-        |    input clk: Clock
+        |    input clock: Clock
         |""".stripMargin
     intercept[WiringException] {
       val c = passes.foldLeft(parse(input)) {
@@ -307,35 +307,35 @@ class WiringTests extends FirrtlFlatSpec {
     val input =
       """circuit Top :
         |  module Top :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst a of A
-        |    a.clk <= clk
+        |    a.clock <= clock
         |  module A :
-        |    input clk: Clock
-        |    reg r: UInt<2>[5], clk
+        |    input clock: Clock
+        |    reg r: UInt<2>[5], clock
         |    node a = UInt(5)
         |    inst x of X
-        |    x.clk <= clk
+        |    x.clock <= clock
         |  extmodule X :
-        |    input clk: Clock
+        |    input clock: Clock
         |""".stripMargin
     val check =
       """circuit Top :
         |  module Top :
-        |    input clk: Clock
+        |    input clock: Clock
         |    inst a of A
-        |    a.clk <= clk
+        |    a.clock <= clock
         |  module A :
-        |    input clk: Clock
-        |    reg r: UInt<2>[5], clk
+        |    input clock: Clock
+        |    reg r: UInt<2>[5], clock
         |    node a = UInt(5)
         |    inst x of X
-        |    x.clk <= clk
+        |    x.clock <= clock
         |    wire r_a: UInt<2>
         |    r_a <= r[a]
         |    x.pin <= r_a
         |  extmodule X :
-        |    input clk: Clock
+        |    input clock: Clock
         |    input pin: UInt<2>
         |""".stripMargin
     val c = passes.foldLeft(parse(input)) {
diff --git a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
index 9b35a19a..2750ee71 100644
--- a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
@@ -264,7 +264,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       """
         |circuit Unit :
         |  module Unit :
-        |    input clk : Clock
+        |    input clock : Clock
         |    input reset : UInt<1>
         |    input io_in : Fixed<6><<0>>
         |    output io_out : Fixed<6><<0>>
@@ -277,7 +277,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       """
         |circuit Unit :
         |  module Unit :
-        |    input clk : Clock
+        |    input clock : Clock
         |    input reset : UInt<1>
         |    input io_in : SInt<6>
         |    output io_out : SInt<6>
diff --git a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
index 6bd06f10..4910cb5e 100644
--- a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
@@ -167,7 +167,7 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       """
         |circuit Unit :
         |  module Unit :
-        |    input clk : Clock
+        |    input clock : Clock
         |    input reset : UInt<1>
         |    input io_in : Fixed<6><<0>>
         |    output io_out : Fixed