Add RawString ExtModule parameter support

While unsafe, this supports Verilog parameter types.
Tests now require Verilator 3.884+ to pass.

6 files changed, 31 insertions, 7 deletions

diff --git a/src/main/antlr4/FIRRTL.g4 b/src/main/antlr4/FIRRTL.g4
index f4d9d3f8..70716c94 100644
--- a/src/main/antlr4/FIRRTL.g4
+++ b/src/main/antlr4/FIRRTL.g4
@@ -97,6 +97,7 @@ parameter
   : 'parameter' id '=' IntLit NEWLINE
   | 'parameter' id '=' StringLit NEWLINE
   | 'parameter' id '=' DoubleLit NEWLINE
+  | 'parameter' id '=' RawString NEWLINE
   ;
 
 moduleBlock
@@ -321,7 +322,16 @@ HexDigit
   ;
 
 StringLit
-  : '"' ('\\"'|.)*? '"'
+  : '"' UnquotedString? '"'
+  ;
+
+RawString
+  : '\'' UnquotedString? '\''
+  ;
+
+fragment
+UnquotedString
+  : ('\\"'|~[\r\n])+?
   ;
 
 FileInfo
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index e3a146e2..5a4420c6 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -89,6 +89,7 @@ class VerilogEmitter extends Emitter {
     case StringParam(name, value) =>
       val strx = "\"" + VerilogStringLitHandler.escape(value) + "\""
       s".${name}($strx)"
+    case RawStringParam(name, value) => s".$name($value)"
   }
   def emit(x: Any)(implicit w: Writer) { emit(x, 0) }
   def emit(x: Any, top: Int)(implicit w: Writer) {
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index 03be0c4e..5e07668a 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -119,10 +119,11 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
 
   private def visitParameter[FirrtlNode](ctx: FIRRTLParser.ParameterContext): Param = {
     val name = ctx.id.getText
-    (ctx.IntLit, ctx.StringLit, ctx.DoubleLit) match {
-      case (int, null, null) => IntParam(name, string2BigInt(int.getText))
-      case (null, str, null) => StringParam(name, visitStringLit(str))
-      case (null, null, dbl) => DoubleParam(name, dbl.getText.toDouble)
+    (ctx.IntLit, ctx.StringLit, ctx.DoubleLit, ctx.RawString) match {
+      case (int, null, null, null) => IntParam(name, string2BigInt(int.getText))
+      case (null, str, null, null) => StringParam(name, visitStringLit(str))
+      case (null, null, dbl, null) => DoubleParam(name, dbl.getText.toDouble)
+      case (null, null, null, raw) => RawStringParam(name, raw.getText.tail.init) // Remove "\'"s
       case _ => throw new Exception(s"Internal error: Visiting impossible parameter ${ctx.getText}")
     }
   }
diff --git a/src/main/scala/firrtl/ir/IR.scala b/src/main/scala/firrtl/ir/IR.scala
index b9b31427..236a7884 100644
--- a/src/main/scala/firrtl/ir/IR.scala
+++ b/src/main/scala/firrtl/ir/IR.scala
@@ -457,6 +457,13 @@ case class DoubleParam(name: String, value: Double) extends Param {
 case class StringParam(name: String, value: StringLit) extends Param {
   override def serialize: String = super.serialize + value.serialize
 }
+/** Raw String Parameter
+  * Useful for Verilog type parameters
+  * @note Firrtl doesn't guarantee anything about this String being legal in any backend
+  */
+case class RawStringParam(name: String, value: String) extends Param {
+  override def serialize: String = super.serialize + s"'$value'"
+}
 
 /** Base class for modules */
 abstract class DefModule extends FirrtlNode with IsDeclaration {
diff --git a/src/test/resources/blackboxes/ParameterizedExtModule.v b/src/test/resources/blackboxes/ParameterizedExtModule.v
index ee6e3ec3..ae5d94be 100644
--- a/src/test/resources/blackboxes/ParameterizedExtModule.v
+++ b/src/test/resources/blackboxes/ParameterizedExtModule.v
@@ -6,10 +6,13 @@ module ParameterizedExtModule(
   parameter VALUE = 0;
   parameter STRING = "one";
   parameter REAL = 1.0;
+  parameter type TYP = bit;
   wire [15:0] fizz;
   wire [15:0] buzz;
-  assign bar = foo + VALUE + fizz + buzz;
+  wire TYP tpe;
+  assign bar = foo + VALUE + fizz + buzz + tpe;
   assign fizz = (STRING == "two")? 2 : (STRING == "one")? 1 : 0;
   assign buzz = (REAL > 2.5E50)? 2 : (REAL < 0.0)? 1 : 0;
+  assign tpe = 2; // Will give 0 if bit, 2 for any larger width
 endmodule
 
diff --git a/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir b/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir
index 29769e84..e360e4cf 100644
--- a/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir
+++ b/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir
@@ -7,6 +7,7 @@ circuit ParameterizedExtModuleTester :
     parameter VALUE = 1
     parameter STRING = "one"
     parameter REAL = -1.7
+    parameter TYP = 'bit'
 
   extmodule ParameterizedExtModule_2 :
     input foo : UInt<16>
@@ -16,6 +17,7 @@ circuit ParameterizedExtModuleTester :
     parameter VALUE = 2
     parameter STRING = "two"
     parameter REAL = 2.6E50
+    parameter TYP = 'bit [1:0]'
 
   module ParameterizedExtModuleTester  :
     input clk : Clock
@@ -32,7 +34,7 @@ circuit ParameterizedExtModuleTester :
         printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
         stop(clk, not(reset), 1)
       else :
-        when neq(dut2.bar, UInt(1006)) :
+        when neq(dut2.bar, UInt(1008)) :
           printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
           stop(clk, not(reset), 1)
         else :