Fix wrong omitting same clocked nondirect children (#374)

* Fix wrong omitting same clocked nondirect children

* Minor style fixes

2 files changed, 36 insertions, 3 deletions

diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
index c79b6d1a..04e99d99 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
@@ -48,12 +48,14 @@ object ClockListUtils {
       case Module(i, n, ports, b) => ports.collectFirst { case p if p.name == "clock" => me + sep + "clock" }
       case ExtModule(i, n, ports, dn, p) => None
     }
-    // Return new origins with children removed, if they match my clock
+    // Return new origins with direct children removed, if they match my clock
     clockOpt match {
       case Some(clock) =>
         val myOrigin = getOrigin(connects, clock).serialize
         childrenOrigins.foldLeft(Map(me -> myOrigin)) { case (o, (childInstance, childOrigin)) =>
-          if(childOrigin == myOrigin) o else o + (childInstance -> childOrigin)
+          val childrenInstances = lin.children.map { case (instance, _) => me + sep + instance }
+          // If direct child shares my origin, omit it
+          if(childOrigin == myOrigin && childrenInstances.contains(childInstance)) o else o + (childInstance -> childOrigin)
         }
       case None => childrenOrigins
     }
diff --git a/src/test/scala/firrtlTests/ClockListTests.scala b/src/test/scala/firrtlTests/ClockListTests.scala
index 534aab89..ddad7235 100644
--- a/src/test/scala/firrtlTests/ClockListTests.scala
+++ b/src/test/scala/firrtlTests/ClockListTests.scala
@@ -82,6 +82,37 @@ class ClockListTests extends FirrtlFlatSpec {
     }
     val writer = new StringWriter()
     val retC = new ClockList("HTop", writer).run(c)
-    (writer.toString()) should be (check)
+    (writer.toString) should be (check)
+  }
+  "A->B->C, and A.clock == C.clock" should "still emit C.clock origin" in {
+    val input =
+      """circuit A :
+        |  module A :
+        |    input clock: Clock
+        |    input clkB: Clock
+        |    inst b of B
+        |    b.clock <= clkB
+        |    b.clkC <= clock
+        |  module B :
+        |    input clock: Clock
+        |    input clkC: Clock
+        |    inst c of C
+        |    c.clock <= clkC
+        |  module C :
+        |    input clock: Clock
+        |    reg r: UInt<5>, clock
+        |""".stripMargin
+    val check = 
+  """Sourcelist: List(clock, clkB) 
+    |Good Origin of clock is clock
+    |Good Origin of b.clock is clkB
+    |Good Origin of b$c.clock is clock
+    |""".stripMargin
+    val c = passes.foldLeft(parse(input)) {
+      (c: Circuit, p: Pass) => p.run(c)
+    }
+    val writer = new StringWriter()
+    val retC = new ClockList("A", writer).run(c)
+    (writer.toString) should be (check)
   }
 }