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AgeCommit message (Expand)Author
2016-12-13Add MaxWidth of 1,000,000 bitsjackkoenig
2016-12-08Copy (explicitly) test resource to targetdir. (#392)Jim Lawson
2016-12-08Clk2clock - rename the implicit "clk" module input "clock" (#387)Jim Lawson
2016-12-06Fixes for Annotation serialized/deserialize (#390)Chick Markley
2016-12-05Add check for muxing between clocks (#360)Jack Koenig
2016-12-05Bugfix: expand whens not voiding memories (#380)Adam Izraelevitz
2016-11-30Bugfix: Dedup aggressively (ignore comments) (#375)Adam Izraelevitz
2016-11-23Stringified annotations (#367)Adam Izraelevitz
2016-11-21Bugfix: exponential runtime of pull muxes (#379)Adam Izraelevitz
2016-11-21Rewrote inline xform to fix quadratic perf. bug (#377)Adam Izraelevitz
2016-11-15Fixed multi wiring (#368)Adam Izraelevitz
2016-11-14Fix wrong omitting same clocked nondirect children (#374)Adam Izraelevitz
2016-11-09Bugfix: removed recursive removal in infer widthsazidar
2016-11-07Clock List Transform (#365)Adam Izraelevitz
2016-11-07Fix annotations (#366)Adam Izraelevitz
2016-11-07make default dir be current directory (#361)Chick Markley
2016-11-07Added underscore to GEN, now its _GEN (#362)Adam Izraelevitz
2016-11-05Fix CHIRRTL bugs (#355)Donggyu
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
2016-11-04Add a pass to deduplicate modulesazidar
2016-11-04Refactor Compilers and Transformsjackkoenig
2016-11-01Fix Match Error in Check Types on Partial Connect (#359)Jack Koenig
2016-10-31Fixed Verilog emission of andr, orr, and xorr (#357)Adam Izraelevitz
2016-10-30Cleanup fixed point tests (#339)Jack Koenig
2016-10-30Keep package name + directory structure consistent (#354)Colin Schmidt
2016-10-27Wiring (#348)Adam Izraelevitz
2016-10-26Add RawString ExtModule parameter supportjackkoenig
2016-10-26Add Support for Parameterized ExtModules and Name Overridejackkoenig
2016-10-26Add ExtModule Testsjackkoenig
2016-10-26Improve integration test API and add support for Verilog resourcesjackkoenig
2016-10-18Create a simple system for executions and command line parameters (#337)Chick Markley
2016-10-17Reorganized memory blackboxing (#336)Adam Izraelevitz
2016-10-17Add fixed point type (#322)Adam Izraelevitz
2016-10-07Add test for Firrtl mems with no ports (#327)Jack Koenig
2016-09-26add CInferMDirSpecDonggyu Kim
2016-09-26Added max width check to dshl shift amount (#318)Adam Izraelevitz
2016-09-25Spec features added: AnalogType and Attach (#295)Adam Izraelevitz
2016-09-22Fixed width inference for add, sub (#312)Adam Izraelevitz
2016-09-21Fix clock connections in InferReadWrite (#310)Donggyu
2016-09-21refactor AnnotateMemMacrosDonggyu Kim
2016-09-21refactor InferReadWriteDonggyu Kim
2016-09-14Added Rob.fir for regression testing (#258)Donggyu
2016-09-14fix enable signal inferecne for smems' read ports (#289)Donggyu
2016-09-14Fixed infinite loop for finding connect origin in ReplSeqMem (#300)Angie Wang
2016-09-12Add LegalizeSpec for testing Verilog Legalization passJack
2016-09-12Added test to check invalid bug was fixedazidar
2016-09-12Bug fix -- remove all empty expressions after ReplSeqMem passes (#294)Angie Wang
2016-09-08Remove brittle ReplSeqMemTestjackkoenig
2016-09-08remove Utils.{AND, OR, NOT, EQV}Donggyu Kim
2016-09-08clean up ExpandWhensDonggyu Kim
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