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authorjackkoenig2016-12-13 14:45:57 -0800
committerJack Koenig2016-12-13 15:26:08 -0800
commit1ea7b6d686a276537f3feb5a40cbe8453ba10ac8 (patch)
tree347529b878c7270a1dfa462c1a52d2b40398a944 /src/test
parentb555af18772f3fe43751adb2ddebf128c05035a0 (diff)
Add MaxWidth of 1,000,000 bits
Also base max dshl check on MaxWidth instead of just 31 bits Resolves #320
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/WidthSpec.scala22
1 files changed, 21 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala
index 9b0ee139..770c2785 100644
--- a/src/test/scala/firrtlTests/WidthSpec.scala
+++ b/src/test/scala/firrtlTests/WidthSpec.scala
@@ -58,7 +58,7 @@ class WidthSpec extends FirrtlFlatSpec {
val check = Seq( "output z : SInt<5>")
executeTest(input, check, passes)
}
- "Dshl by 32 bits" should "result in an error" in {
+ "Dshl by 20 bits" should "result in an error" in {
val passes = Seq(
ToWorkingIR,
CheckHighForm,
@@ -74,6 +74,26 @@ class WidthSpec extends FirrtlFlatSpec {
| input y: UInt<32>
| output z: UInt
| z <= dshl(x, y)""".stripMargin
+ // Throws both DshlTooBig and WidthTooBig
+ // TODO check message
+ intercept[PassExceptions] {
+ executeTest(input, Nil, passes)
+ }
+ }
+ "Width >= MaxWidth" should "result in an error" in {
+ val passes = Seq(
+ ToWorkingIR,
+ CheckHighForm,
+ ResolveKinds,
+ InferTypes,
+ CheckTypes,
+ InferWidths,
+ CheckWidths)
+ val input =
+ s"""circuit Unit :
+ | module Unit :
+ | input x: UInt<${CheckWidths.MaxWidth}>
+ """.stripMargin
intercept[CheckWidths.WidthTooBig] {
executeTest(input, Nil, passes)
}