diff options
| author | Donggyu Kim | 2016-09-16 01:02:39 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-09-21 13:17:02 -0700 |
| commit | 56f1014669638de90fa1c58007aaf4c16b9876ef (patch) | |
| tree | e902a48cb61f44b715a215a02cf9aa6b9a68a235 /src/test | |
| parent | 350ffd7bbc1b014b9d9b256da4181c59bf0419e3 (diff) | |
refactor InferReadWrite
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/InferReadWriteSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala index 7e3383b2..3af018bd 100644 --- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala +++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala @@ -38,7 +38,7 @@ class InferReadWriteSpec extends SimpleTransformSpec { val name = "Check Infer ReadWrite Ports" def findReadWrite(s: Statement): Boolean = s match { case s: DefMemory if s.readLatency > 0 && s.readwriters.size == 1 => - s.name == "mem" && s.readwriters.head == "rw_0" + s.name == "mem" && s.readwriters.head == "rw" case s: Block => s.stmts exists findReadWrite case _ => false |