Stringified annotations (#367)

Restricts annotations to be string-based (and thus less typesafe)
Makes annotations more easily serializable and interact with Chisel

18 files changed, 76 insertions, 45 deletions

diff --git a/src/test/resources/annotations/SampleAnnotations.anno b/src/test/resources/annotations/SampleAnnotations.anno
new file mode 100644
index 00000000..8fa9f44f
--- /dev/null
+++ b/src/test/resources/annotations/SampleAnnotations.anno
@@ -0,0 +1,30 @@
+- transformClass: firrtl.passes.InlineInstances
+  targetString: ModC
+  value: ModC.this params 16 32
+- transformClass: firrtl.passes.InlineInstances
+  targetString: ModC.io.out
+  value: ModuleC(16,32) width < 32
+- transformClass: firrtl.passes.InlineInstances
+  targetString: ModA
+  value: ModA.this
+- transformClass: firrtl.passes.InlineInstances
+  targetString: ModA.io.out
+  value: inside ModA.io.out params 64,64
+- transformClass: firrtl.passes.InlineInstances
+  targetString: ModC_1
+  value: ModC.this params 42 77
+- transformClass: firrtl.passes.InlineInstances
+  targetString: ModC_1.io.out
+  value: ModuleC(42,77) width < 77
+- transformClass: firrtl.passes.InlineInstances
+  targetString: ModB.io.out
+  value: inside ModB.io.out params 32,48
+- transformClass: firrtl.passes.InlineInstances
+  targetString: TopOfDiamond
+  value: |-
+    TopOfDiamond
+    With
+    Some new lines
+- transformClass: firrtl.passes.InlineInstances
+  targetString: ModB.io.in
+  value: TopOfDiamond.moduleB.io.in
diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala
index a0a935a9..9ffbbd85 100644
--- a/src/test/scala/firrtlTests/AnnotationTests.scala
+++ b/src/test/scala/firrtlTests/AnnotationTests.scala
@@ -9,7 +9,7 @@ import org.scalatest.Matchers
 import org.scalatest.junit.JUnitRunner
 
 import firrtl.ir.Circuit
-import firrtl.Parser
+import firrtl.{Parser, AnnotationMap}
 import firrtl.{
    CircuitState,
    ResolveAndCheck,
@@ -20,22 +20,13 @@ import firrtl.{
    VerilogCompiler,
    Transform
 }
-import firrtl.Annotations.{
+import firrtl.annotations.{
    Named,
    CircuitName,
    ModuleName,
    ComponentName,
    AnnotationException,
-   Annotation,
-   Strict,
-   Rigid,
-   Firm,
-   Loose,
-   Sticky,
-   Insistent,
-   Fickle,
-   Unstable,
-   AnnotationMap
+   Annotation
 }
 
 /**
@@ -79,12 +70,8 @@ class AnnotationTests extends AnnotationSpec with Matchers {
   val cName = ComponentName("c", mName)
 
   "Loose and Sticky annotation on a node" should "pass through" in {
-    case class TestAnnotation(target: Named) extends Annotation with Loose with Sticky {
-      def duplicate(to: Named) = this.copy(target=to)
-      def transform = classOf[Transform]
-    }
     val w = new StringWriter()
-    val ta = TestAnnotation(cName)
+    val ta = Annotation(cName, classOf[Transform], "")
     execute(w, getAMap(ta), input, ta)
   }
 }
diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala
index d9912ae2..c3df4232 100644
--- a/src/test/scala/firrtlTests/AttachSpec.scala
+++ b/src/test/scala/firrtlTests/AttachSpec.scala
@@ -6,7 +6,7 @@ import java.io._
 import org.scalatest._
 import org.scalatest.prop._
 import firrtl._
-import firrtl.Annotations._
+import firrtl.annotations._
 import firrtl.ir.Circuit
 import firrtl.passes._
 import firrtl.Parser.IgnoreInfo
diff --git a/src/test/scala/firrtlTests/CInferMDirSpec.scala b/src/test/scala/firrtlTests/CInferMDirSpec.scala
index d3c104f5..1385b29d 100644
--- a/src/test/scala/firrtlTests/CInferMDirSpec.scala
+++ b/src/test/scala/firrtlTests/CInferMDirSpec.scala
@@ -6,7 +6,7 @@ import firrtl._
 import firrtl.ir._
 import firrtl.passes._
 import firrtl.Mappers._
-import Annotations._
+import annotations._
 
 class CInferMDir extends LowTransformSpec {
   object CInferMDirCheckPass extends Pass {
diff --git a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
index 2166e9cf..3d8c9825 100644
--- a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
@@ -6,7 +6,7 @@ import firrtl._
 import firrtl.ir._
 import firrtl.passes._
 import firrtl.Mappers._
-import Annotations._
+import annotations._
 
 class ChirrtlMemSpec extends LowTransformSpec {
   object MemEnableCheckPass extends Pass {
diff --git a/src/test/scala/firrtlTests/ClockListTests.scala b/src/test/scala/firrtlTests/ClockListTests.scala
index ddad7235..9069c145 100644
--- a/src/test/scala/firrtlTests/ClockListTests.scala
+++ b/src/test/scala/firrtlTests/ClockListTests.scala
@@ -7,7 +7,7 @@ import firrtl._
 import firrtl.ir.Circuit
 import firrtl.passes._
 import firrtl.Parser.IgnoreInfo
-import Annotations._
+import annotations._
 import clocklist._
 
 class ClockListTests extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/DriverSpec.scala b/src/test/scala/firrtlTests/DriverSpec.scala
index 3ff7bed3..f0b5e403 100644
--- a/src/test/scala/firrtlTests/DriverSpec.scala
+++ b/src/test/scala/firrtlTests/DriverSpec.scala
@@ -4,7 +4,12 @@ package firrtlTests
 
 import java.io.File
 
-import firrtl.passes.memlib.{InferReadWriteAnnotation, ReplSeqMemAnnotation}
+import firrtl.annotations.Annotation
+import org.scalatest.{Matchers, FreeSpec}
+
+import firrtl._
+import firrtl.passes.InlineInstances
+import firrtl.passes.memlib.{ReplSeqMem, InferReadWrite}
 import org.scalatest.{Matchers, FreeSpec}
 
 import firrtl._
@@ -92,7 +97,7 @@ class DriverSpec extends FreeSpec with Matchers {
         val firrtlOptions = optionsManager.firrtlOptions
         firrtlOptions.annotations.length should be (3)
         firrtlOptions.annotations.foreach { annotation =>
-          annotation shouldBe a [passes.InlineAnnotation]
+          annotation.transform shouldBe classOf[InlineInstances]
         }
       }
       "infer-rw annotation" in {
@@ -105,7 +110,7 @@ class DriverSpec extends FreeSpec with Matchers {
         val firrtlOptions = optionsManager.firrtlOptions
         firrtlOptions.annotations.length should be (1)
         firrtlOptions.annotations.foreach { annotation =>
-          annotation shouldBe a [InferReadWriteAnnotation]
+          annotation.transform shouldBe classOf[InferReadWrite]
         }
       }
       "repl-seq-mem annotation" in {
@@ -116,15 +121,28 @@ class DriverSpec extends FreeSpec with Matchers {
         ) should be (true)
 
         val firrtlOptions = optionsManager.firrtlOptions
-
         firrtlOptions.annotations.length should be (1)
         firrtlOptions.annotations.foreach { annotation =>
-          annotation shouldBe a [ReplSeqMemAnnotation]
+          annotation.transform shouldBe classOf[ReplSeqMem]
         }
       }
     }
   }
 
+  "Annotations can be read from a file" in {
+    val optionsManager = new ExecutionOptionsManager("test") with HasFirrtlOptions {
+      commonOptions = commonOptions.copy(topName = "a.fir")
+      firrtlOptions = firrtlOptions.copy(
+        annotationFileNameOverride = "src/test/resources/annotations/SampleAnnotations"
+      )
+    }
+    optionsManager.firrtlOptions.annotations.length should be (0)
+    Driver.loadAnnotations(optionsManager)
+    optionsManager.firrtlOptions.annotations.length should be (9)
+
+    optionsManager.firrtlOptions.annotations.head.transformClass should be ("firrtl.passes.InlineInstances")
+  }
+
   val input =
     """
       |circuit Dummy :
diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala
index c46ecdb7..90db3524 100644
--- a/src/test/scala/firrtlTests/FirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/FirrtlSpec.scala
@@ -12,7 +12,7 @@ import scala.io.Source
 
 import firrtl._
 import firrtl.Parser.IgnoreInfo
-import firrtl.Annotations.AnnotationMap
+import firrtl.annotations
 
 // This trait is borrowed from Chisel3, ideally this code should only exist in one location
 trait BackendCompilationUtilities {
diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
index cc840981..b92feacd 100644
--- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala
+++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
@@ -6,7 +6,7 @@ import firrtl._
 import firrtl.ir._
 import firrtl.passes._
 import firrtl.Mappers._
-import Annotations._
+import annotations._
 
 class InferReadWriteSpec extends SimpleTransformSpec {
   class InferReadWriteCheckException extends PassException(
diff --git a/src/test/scala/firrtlTests/InlineInstancesTests.scala b/src/test/scala/firrtlTests/InlineInstancesTests.scala
index 92ed1195..a3e2b38d 100644
--- a/src/test/scala/firrtlTests/InlineInstancesTests.scala
+++ b/src/test/scala/firrtlTests/InlineInstancesTests.scala
@@ -9,15 +9,14 @@ import org.scalatest.Matchers
 import org.scalatest.junit.JUnitRunner
 
 import firrtl.ir.Circuit
-import firrtl.Parser
+import firrtl.{Parser, AnnotationMap}
 import firrtl.passes.PassExceptions
-import firrtl.Annotations.{
+import firrtl.annotations.{
    Named,
    CircuitName,
    ModuleName,
    ComponentName,
-   Annotation,
-   AnnotationMap
+   Annotation
 }
 import firrtl.passes.{InlineInstances, InlineAnnotation}
 
diff --git a/src/test/scala/firrtlTests/MultiThreadingSpec.scala b/src/test/scala/firrtlTests/MultiThreadingSpec.scala
index b2934314..169aa6b2 100644
--- a/src/test/scala/firrtlTests/MultiThreadingSpec.scala
+++ b/src/test/scala/firrtlTests/MultiThreadingSpec.scala
@@ -2,7 +2,7 @@
 
 package firrtlTests
 
-import firrtl.{ChirrtlForm, CircuitState, Compiler, Annotations}
+import firrtl.{ChirrtlForm, CircuitState, Compiler, annotations}
 
 import scala.concurrent.{Future, Await, ExecutionContext}
 import scala.concurrent.duration.Duration
diff --git a/src/test/scala/firrtlTests/PassTests.scala b/src/test/scala/firrtlTests/PassTests.scala
index 444be732..7fa67153 100644
--- a/src/test/scala/firrtlTests/PassTests.scala
+++ b/src/test/scala/firrtlTests/PassTests.scala
@@ -11,6 +11,7 @@ import firrtl.Parser.IgnoreInfo
 import firrtl.passes.{Pass, PassExceptions, RemoveEmpty}
 import firrtl.{
    Transform,
+   AnnotationMap,
    PassBasedTransform,
    CircuitState,
    CircuitForm,
@@ -28,7 +29,6 @@ import firrtl.{
    Compiler,
    Parser
 }
-import firrtl.Annotations.AnnotationMap
 
 
 // An example methodology for testing Firrtl Passes
diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
index c4ce6975..2cde085a 100644
--- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala
+++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
@@ -5,7 +5,7 @@ package firrtlTests
 import firrtl._
 import firrtl.passes._
 import firrtl.passes.memlib._
-import Annotations._
+import annotations._
 
 class ReplSeqMemSpec extends SimpleTransformSpec {
   def transforms = Seq(
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
index 2a1723f3..39592269 100644
--- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala
+++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
@@ -6,7 +6,7 @@ import java.io._
 import org.scalatest._
 import org.scalatest.prop._
 import firrtl._
-import firrtl.Annotations._
+import firrtl.annotations._
 import firrtl.ir.Circuit
 import firrtl.passes._
 import firrtl.Parser.IgnoreInfo
diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala
index b5116f90..e8143741 100644
--- a/src/test/scala/firrtlTests/WiringTests.scala
+++ b/src/test/scala/firrtlTests/WiringTests.scala
@@ -9,7 +9,7 @@ import firrtl._
 import firrtl.ir.Circuit
 import firrtl.passes._
 import firrtl.Parser.IgnoreInfo
-import Annotations._
+import annotations._
 import wiring.WiringUtils._
 import wiring._
 
diff --git a/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala b/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala
index 4a87290d..0c30b59e 100644
--- a/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala
@@ -4,8 +4,7 @@ package firrtlTests.fixed
 
 import java.io.StringWriter
 
-import firrtl.Annotations.AnnotationMap
-import firrtl.{CircuitState, ChirrtlForm, LowFirrtlCompiler, Parser}
+import firrtl.{CircuitState, ChirrtlForm, LowFirrtlCompiler, Parser, AnnotationMap}
 import firrtl.Parser.IgnoreInfo
 import firrtlTests.FirrtlFlatSpec
 
diff --git a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
index f5105059..6bd06f10 100644
--- a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
@@ -3,7 +3,6 @@
 package firrtlTests
 package fixed
 
-import firrtl.Annotations.AnnotationMap
 import firrtl._
 import firrtl.ir.Circuit
 import firrtl.passes._
diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala
index bea352ef..1bcd711c 100644
--- a/src/test/scala/firrtlTests/transforms/DedupTests.scala
+++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala
@@ -10,15 +10,14 @@ import org.scalatest.Matchers
 import org.scalatest.junit.JUnitRunner
 
 import firrtl.ir.Circuit
-import firrtl.Parser
+import firrtl.{Parser, AnnotationMap}
 import firrtl.passes.PassExceptions
-import firrtl.Annotations.{
+import firrtl.annotations.{
    Named,
    CircuitName,
-   Annotation,
-   AnnotationMap
+   Annotation
 }
-import firrtl.transforms.{DedupModules, DedupAnnotation}
+import firrtl.transforms.DedupModules
 
 
 /**