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authorAdam Izraelevitz2016-11-21 13:30:11 -0800
committerGitHub2016-11-21 13:30:11 -0800
commit9a967a27aa8bb51f4b62969d2889f9a9caa48e31 (patch)
treedad7370c71df7ce8d4628f70b4079296bfee4d99 /src/test
parentaad8e09f355f4804d29361d75f54ce4a5c2d5c52 (diff)
Bugfix: exponential runtime of pull muxes (#379)
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/UnitTests.scala19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index 1e181141..e2f8f729 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -22,6 +22,25 @@ class UnitTests extends FirrtlFlatSpec {
}
}
+ "Pull muxes" should "not be exponential in runtime" in {
+ val passes = Seq(
+ ToWorkingIR,
+ CheckHighForm,
+ ResolveKinds,
+ InferTypes,
+ CheckTypes,
+ PullMuxes)
+ val input =
+ """circuit Unit :
+ | module Unit :
+ | input _2: UInt<1>
+ | output x: UInt<32>
+ | x <= cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat(_2, cat( _2, cat(_2, cat(_2, cat(_2, _2)))))))))))))))))))))))))))))))""".stripMargin
+ passes.foldLeft(parse(input)) {
+ (c: Circuit, p: Pass) => p.run(c)
+ }
+ }
+
"Connecting bundles of different types" should "throw an exception" in {
val passes = Seq(
ToWorkingIR,