Bug fix -- remove all empty expressions after ReplSeqMem passes (#294)

* Bug fix -- remove all empty expressions after ReplSeqMem passes

* Added test to make sure ReplSeqMem can handle BundleType SMem (EmptyExpression leakage)

1 files changed, 47 insertions, 2 deletions

diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
index 252ec58f..4f729578 100644
--- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala
+++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
@@ -16,10 +16,55 @@ class ReplSeqMemSpec extends SimpleTransformSpec {
     new passes.ReplSeqMem(TransID(-2)),
     new MiddleFirrtlToLowFirrtl(),
     (new Transform with SimpleRun {
-     def execute(c: ir.Circuit, a: AnnotationMap) = run(c, passSeq) }),
+     def execute(c: ir.Circuit, a: AnnotationMap) = run(c, passSeq) } ),
     new EmitFirrtl(writer)
   )
 
+  "ReplSeqMem" should "generate blackbox wrappers" in {
+    val input = """
+circuit Top : 
+  module Top : 
+    input clk : Clock
+    input reset : UInt<1>
+    input head_ptr : UInt<5>
+    input tail_ptr : UInt<5>
+    input wmask : {takens : UInt<2>, history : UInt<14>, info : UInt<14>}
+    output io : {backend : {flip allocate : {valid : UInt<1>, bits : {info : {takens : UInt<2>, history : UInt<14>, info : UInt<14>}}}}, commit_entry : {valid : UInt<1>, bits : {info : {takens : UInt<2>, history : UInt<14>, info : UInt<14>}}}}
+    output io2 : {backend : {flip allocate : {valid : UInt<1>, bits : {info : {takens : UInt<2>, history : UInt<14>, info : UInt<14>}}}}, commit_entry : {valid : UInt<1>, bits : {info : {takens : UInt<2>, history : UInt<14>, info : UInt<14>}}}}
+
+    io is invalid
+    io2 is invalid
+
+    smem entries_info : {takens : UInt<2>, history : UInt<14>, info : UInt<14>}[24]
+    when io.backend.allocate.valid :
+      write mport W = entries_info[tail_ptr], clk
+      W <- io.backend.allocate.bits.info
+
+    read mport R = entries_info[head_ptr], clk
+    io.commit_entry.bits.info <- R
+
+    smem entries_info2 : {takens : UInt<2>, history : UInt<14>, info : UInt<14>}[24]
+    when io2.backend.allocate.valid :
+      write mport W1 = entries_info2[tail_ptr], clk
+      when wmask.takens :
+        W1.takens <- io.backend.allocate.bits.info.takens
+      when wmask.history :
+        W1.history <- io.backend.allocate.bits.info.history
+      when wmask.info :
+        W1.info <- io.backend.allocate.bits.info.history
+      
+    read mport R1 = entries_info2[head_ptr], clk
+    io2.commit_entry.bits.info <- R1
+""".stripMargin
+    val confLoc = "ReplSeqMemTests.confTEMP"
+    val aMap = AnnotationMap(Seq(ReplSeqMemAnnotation("-c:Top:-o:"+confLoc, TransID(-2))))
+    val writer = new java.io.StringWriter
+    compile(parse(input), aMap, writer)
+    // Check correctness of firrtl
+    parse(writer.toString)
+    (new java.io.File(confLoc)).delete()
+  }
+
   "ReplSeqMem Utility -- getConnectOrigin" should 
       "determine connect origin across nodes/PrimOps even if ConstProp isn't performed" in {
     def checkConnectOrigin(hurdle: String, origin: String) = {
@@ -61,7 +106,7 @@ circuit Top :
       "bits(a, 0, 0)" -> "a"
     )
 
-    tests.foreach{ case(hurdle, origin) => checkConnectOrigin(hurdle, origin) }
+    tests foreach { case(hurdle, origin) => checkConnectOrigin(hurdle, origin) }
 
   }
 }