Add RawString ExtModule parameter support

While unsafe, this supports Verilog parameter types.
Tests now require Verilator 3.884+ to pass.

2 files changed, 7 insertions, 2 deletions

diff --git a/src/test/resources/blackboxes/ParameterizedExtModule.v b/src/test/resources/blackboxes/ParameterizedExtModule.v
index ee6e3ec3..ae5d94be 100644
--- a/src/test/resources/blackboxes/ParameterizedExtModule.v
+++ b/src/test/resources/blackboxes/ParameterizedExtModule.v
@@ -6,10 +6,13 @@ module ParameterizedExtModule(
   parameter VALUE = 0;
   parameter STRING = "one";
   parameter REAL = 1.0;
+  parameter type TYP = bit;
   wire [15:0] fizz;
   wire [15:0] buzz;
-  assign bar = foo + VALUE + fizz + buzz;
+  wire TYP tpe;
+  assign bar = foo + VALUE + fizz + buzz + tpe;
   assign fizz = (STRING == "two")? 2 : (STRING == "one")? 1 : 0;
   assign buzz = (REAL > 2.5E50)? 2 : (REAL < 0.0)? 1 : 0;
+  assign tpe = 2; // Will give 0 if bit, 2 for any larger width
 endmodule
 
diff --git a/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir b/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir
index 29769e84..e360e4cf 100644
--- a/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir
+++ b/src/test/resources/blackboxes/ParameterizedExtModuleTester.fir
@@ -7,6 +7,7 @@ circuit ParameterizedExtModuleTester :
     parameter VALUE = 1
     parameter STRING = "one"
     parameter REAL = -1.7
+    parameter TYP = 'bit'
 
   extmodule ParameterizedExtModule_2 :
     input foo : UInt<16>
@@ -16,6 +17,7 @@ circuit ParameterizedExtModuleTester :
     parameter VALUE = 2
     parameter STRING = "two"
     parameter REAL = 2.6E50
+    parameter TYP = 'bit [1:0]'
 
   module ParameterizedExtModuleTester  :
     input clk : Clock
@@ -32,7 +34,7 @@ circuit ParameterizedExtModuleTester :
         printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
         stop(clk, not(reset), 1)
       else :
-        when neq(dut2.bar, UInt(1006)) :
+        when neq(dut2.bar, UInt(1008)) :
           printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
           stop(clk, not(reset), 1)
         else :