Fix CHIRRTL bugs (#355)

* handle uninferred ports gracefully in RemoveCHIRRTL

memory port directions are not inferred during CInferMDir if not being used, so handle them properly in RemoveCHIRRTL

* fix CInferTypes

3 files changed, 15 insertions, 1 deletions

diff --git a/src/test/resources/features/EmptyChirrtlMem.fir b/src/test/resources/features/EmptyChirrtlMem.fir
new file mode 100644
index 00000000..036d3830
--- /dev/null
+++ b/src/test/resources/features/EmptyChirrtlMem.fir
@@ -0,0 +1,5 @@
+circuit Queue :
+  module Queue :
+    input clock : Clock
+    cmem ram : UInt<1>[2]
+    infer mport T_107 = ram[UInt(0)], clock
diff --git a/src/test/resources/features/NodeType.fir b/src/test/resources/features/NodeType.fir
new file mode 100644
index 00000000..fe48871b
--- /dev/null
+++ b/src/test/resources/features/NodeType.fir
@@ -0,0 +1,8 @@
+circuit NodeType :
+  module NodeType :
+    input clock : Clock
+
+    cmem rf : UInt<64>[31]
+    node rf_wdata = mux(UInt(0), UInt(0), UInt(0))
+    infer mport port = rf[UInt(0)], clock
+    port <- rf_wdata
diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala
index 05c53cce..3b360de6 100644
--- a/src/test/scala/firrtlTests/ChirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala
@@ -71,4 +71,5 @@ class ChirrtlSpec extends FirrtlFlatSpec {
 }
 
 class ChirrtlMemsExecutionTest extends ExecutionTest("ChirrtlMems", "/features")
-
+class EmptyChirrtlMemCompilationTest extends CompilationTest("EmptyChirrtlMem", "/features")
+class NodeTypeCompilationTest extends CompilationTest("NodeType", "/features")