diff options
| author | Donggyu Kim | 2016-09-16 01:59:38 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-09-21 13:17:39 -0700 |
| commit | e91fab5e9bc168492b682c2bdca86caeb67d06a1 (patch) | |
| tree | 29b0f7def0972d155bdc8e67ec30f7660ca122e5 /src/test | |
| parent | 56f1014669638de90fa1c58007aaf4c16b9876ef (diff) | |
refactor AnnotateMemMacros
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/ReplSeqMemTests.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala index 7219b1ce..8aeafc9e 100644 --- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala +++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala @@ -107,7 +107,7 @@ circuit Top : val circuit = InferTypes.run(ToWorkingIR.run(parse(input))) val m = circuit.modules.head.asInstanceOf[ir.Module] val connects = AnalysisUtils.getConnects(m) - val calculatedOrigin = AnalysisUtils.getConnectOrigin(connects,"f").serialize + val calculatedOrigin = AnalysisUtils.getConnectOrigin(connects)("f").serialize require(calculatedOrigin == origin, s"getConnectOrigin returns incorrect origin $calculatedOrigin !") } |
