From e91fab5e9bc168492b682c2bdca86caeb67d06a1 Mon Sep 17 00:00:00 2001
From: Donggyu Kim
Date: Fri, 16 Sep 2016 01:59:38 -0700
Subject: refactor AnnotateMemMacros

---
 src/test/scala/firrtlTests/ReplSeqMemTests.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
index 7219b1ce..8aeafc9e 100644
--- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala
+++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
@@ -107,7 +107,7 @@ circuit Top :
       val circuit = InferTypes.run(ToWorkingIR.run(parse(input)))
       val m = circuit.modules.head.asInstanceOf[ir.Module]
       val connects = AnalysisUtils.getConnects(m)
-      val calculatedOrigin = AnalysisUtils.getConnectOrigin(connects,"f").serialize 
+      val calculatedOrigin = AnalysisUtils.getConnectOrigin(connects)("f").serialize 
       require(calculatedOrigin == origin, s"getConnectOrigin returns incorrect origin $calculatedOrigin !")
     }
 
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