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AgeCommit message (Expand)Author
2017-03-09make sure infer-rw works for exclusive when statements (#481)Donggyu
2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
2017-03-06Zero width (#402)Adam Izraelevitz
2017-03-06Fix mistake when rebasingAdam Izraelevitz
2017-03-06After merge, fixed added transformsAdam Izraelevitz
2017-03-06Added more stylized debugging styleAdam Izraelevitz
2017-03-06Addresses #459. Rewords transform annotations API.Adam Izraelevitz
2017-03-06Add ability to emit 1 file per module (#443)Jack Koenig
2017-03-03Bugfix: InlineInstances must prefix instancesAdam Izraelevitz
2017-03-01Allow nested digit fields in subfield expressionsJack Koenig
2017-03-01Fix bug in Lexer rule for DoubleLit and add testsJack Koenig
2017-02-26Align types and names of ports in emitted Verilog (#463)Jack Koenig
2017-02-23Add support for bundle fields to start with digits (#462)Jack Koenig
2017-02-21Implementation of nodedupe mem (#447)Colin Schmidt
2017-02-14Add support for Analog types in partial connect (#435)Jack Koenig
2017-02-14Fixes #441, ConvertFixedToSInt not recursing expsAdam Izraelevitz
2017-02-12Changed fixed-point cat semantics to return uint (#436)Adam Izraelevitz
2017-02-07Rework Attach to work on arbitrary Analog hierarchies (#415)Jack Koenig
2017-02-01Fix anno in backend (#428)Chick Markley
2017-02-01Fetch resource files as resources. (#399)Jim Lawson
2017-01-31Replace createTempDirectory with createTestDirectory (#427)Jack Koenig
2017-01-31Blackboxhelper (#418)Chick Markley
2017-01-29Keep firrtl's simulation environment in sync with chisel's. (#425)Jim Lawson
2017-01-27Fix signed types (#422)Angie Wang
2017-01-27Move BackendCompilationUtilities into a util package for use by chisel3. (#400)Jim Lawson
2017-01-23Add FixedType to uniqueify match statement.Paul Rigge
2017-01-20Remove merging of source locators during module deduplicationJack
2017-01-19Merge branch 'master' into addmiddlefirrtlcompilerJim Lawson
2017-01-19Verilog rem fix (#404)grebe
2017-01-19Merge branch 'master' into addmiddlefirrtlcompilerJim Lawson
2016-12-15Delete annotationsTestFile after test (#405)Leonard Truong
2016-12-14Merge branch 'master' into addmiddlefirrtlcompilerJim Lawson
2016-12-14Remove scalpels.Jim Lawson
2016-12-14Add support for top-level use of MiddleFirrtlCompiler.Jim Lawson
2016-12-14Added NoDedup annotation and test (#397)Adam Izraelevitz
2016-12-13Add MaxWidth of 1,000,000 bitsjackkoenig
2016-12-08Copy (explicitly) test resource to targetdir. (#392)Jim Lawson
2016-12-08Clk2clock - rename the implicit "clk" module input "clock" (#387)Jim Lawson
2016-12-06Fixes for Annotation serialized/deserialize (#390)Chick Markley
2016-12-05Add check for muxing between clocks (#360)Jack Koenig
2016-12-05Bugfix: expand whens not voiding memories (#380)Adam Izraelevitz
2016-11-30Bugfix: Dedup aggressively (ignore comments) (#375)Adam Izraelevitz
2016-11-23Stringified annotations (#367)Adam Izraelevitz
2016-11-21Bugfix: exponential runtime of pull muxes (#379)Adam Izraelevitz
2016-11-21Rewrote inline xform to fix quadratic perf. bug (#377)Adam Izraelevitz
2016-11-15Fixed multi wiring (#368)Adam Izraelevitz
2016-11-14Fix wrong omitting same clocked nondirect children (#374)Adam Izraelevitz
2016-11-09Bugfix: removed recursive removal in infer widthsazidar
2016-11-07Clock List Transform (#365)Adam Izraelevitz
2016-11-07Fix annotations (#366)Adam Izraelevitz
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