Blackboxhelper (#418)

* First pass at implementing a annotation based mechanism to move black box verilator files into the target directory

* A little bit of style cleanup

* A little bit of style cleanup

* Fix the driver, wasn't appending targetDir properly
Add some docs

* test had wrong value now that targetdir is added to annnos

* Now saves a list of all black box verilog files moved into target directory.
Then creates a file black_box_verilog_files.f that contains this list with -v prepended to each line

* Made black box source helper be low to low form
Added it to the verilog compiler transforms
Added a test to make sure it got there

* targetDir annotation is targeted to a CircuitName("All")

2 files changed, 101 insertions, 1 deletions

diff --git a/src/test/scala/firrtlTests/DriverSpec.scala b/src/test/scala/firrtlTests/DriverSpec.scala
index ff888e2e..5bed2a2b 100644
--- a/src/test/scala/firrtlTests/DriverSpec.scala
+++ b/src/test/scala/firrtlTests/DriverSpec.scala
@@ -136,7 +136,7 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities
     copyResourceToFile("/annotations/SampleAnnotations.anno", annotationsTestFile)
     optionsManager.firrtlOptions.annotations.length should be (0)
     Driver.loadAnnotations(optionsManager)
-    optionsManager.firrtlOptions.annotations.length should be (9)
+    optionsManager.firrtlOptions.annotations.length should be (10) // 9 from circuit plus 1 for targetDir
 
     optionsManager.firrtlOptions.annotations.head.transformClass should be ("firrtl.passes.InlineInstances")
     annotationsTestFile.delete()
diff --git a/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala b/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala
new file mode 100644
index 00000000..b037accf
--- /dev/null
+++ b/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala
@@ -0,0 +1,100 @@
+// See LICENSE for license details.
+
+package firrtlTests.transforms
+
+import java.io.StringWriter
+
+import firrtl.annotations.{Annotation, CircuitName, ModuleName}
+import firrtl.transforms._
+import firrtl.{AnnotationMap, FIRRTLException, Transform, VerilogCompiler}
+import firrtlTests.{HighTransformSpec, LowTransformSpec}
+import org.scalacheck.Test.Failed
+import org.scalatest.{FreeSpec, Matchers, Succeeded}
+
+
+/**
+ * Tests inline instances transformation
+ */
+class BlacklBoxSourceHelperSpec extends FreeSpec with Matchers {
+  "BlackBoxSourceAnnotations" - {
+    val modName = ModuleName("dog", CircuitName("fox"))
+    val resource = "file://somefile.v"
+
+    "should parse and unparse" in {
+
+      val serialized = BlackBoxResource(resource).serialize
+      BlackBoxSource.parse(serialized) match {
+        case Some(BlackBoxResource(id)) =>
+          id should be (resource)
+          Succeeded
+        case _ => Failed
+      }
+    }
+    "should fail on unsupported kinds" in {
+      intercept[FIRRTLException] {
+        BlackBoxSourceAnnotation(modName, "bad value")
+      }
+      BlackBoxSourceAnnotation(modName, BlackBoxResource(resource).serialize).isInstanceOf[Annotation] should be(true)
+    }
+  }
+}
+
+class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
+   def transform: Transform = new BlackBoxSourceHelper
+
+  private val moduleName = ModuleName("Top", CircuitName("Top"))
+  private val input = """
+                        |circuit Top :
+                        |
+                        |  extmodule AdderExtModule :
+                        |    input foo : UInt<16>
+                        |    output bar : UInt<16>
+                        |
+                        |    defname = BBFAdd
+                        |
+                        |  module Top :
+                        |   input x : UInt<16>
+                        |   output y : UInt<16>
+                        |
+                        |   inst a1 of AdderExtModule
+                        |   a1.foo <= x
+                        |   y <= a1.bar
+                      """.stripMargin
+  private val output = """
+                        |circuit Top :
+                        |
+                        |  extmodule AdderExtModule :
+                        |    input foo : UInt<16>
+                        |    output bar : UInt<16>
+                        |
+                        |    defname = BBFAdd
+                        |
+                        |  module Top :
+                        |   input x : UInt<16>
+                        |   output y : UInt<16>
+                        |
+                        |   inst a1 of AdderExtModule
+                        |   y <= a1.bar
+                        |   a1.foo <= x
+                      """.stripMargin
+
+  "annotated external modules" should "appear in output directory" in {
+
+    val writer = new StringWriter()
+    val aMap = AnnotationMap(Seq(
+      Annotation(moduleName, classOf[BlackBoxSourceHelper], BlackBoxTargetDir("test_run_dir").serialize),
+      Annotation(moduleName, classOf[BlackBoxSourceHelper], BlackBoxResource("/blackboxes/AdderExtModule.v").serialize)
+    ))
+
+    execute(writer, aMap, input, output)
+
+    new java.io.File("test_run_dir/AdderExtModule.v").exists should be (true)
+    new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.FileListName}").exists should be (true)
+  }
+
+  "verilog compiler" should "have BlackBoxSourceHelper transform" in {
+    val verilogCompiler = new VerilogCompiler
+    verilogCompiler.transforms.map { x => x.getClass } should contain (classOf[BlackBoxSourceHelper])
+  }
+}
+