Add support for Analog types in partial connect (#435)

Also add support for width inference

1 files changed, 48 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala
index 32dc00a0..5eed33bd 100644
--- a/src/test/scala/firrtlTests/AttachSpec.scala
+++ b/src/test/scala/firrtlTests/AttachSpec.scala
@@ -144,6 +144,29 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
     executeTest(input, check, compiler)
   }
 
+  it should "work in partial connect" in {
+    val compiler = new VerilogCompiler
+    val input =
+      """circuit Attaching :
+         |  module Attaching :
+         |    input foo : { b : UInt<3>, a : Analog<3> }
+         |    output bar : { b : UInt<3>, a : Analog<3> }
+         |    bar <- foo""".stripMargin
+    // Omitting `ifdef SYNTHESIS and `elseif verilator since it's tested above
+    val check =
+      """module Attaching(
+        |  input  [2:0] foo_b,
+        |  inout  [2:0] foo_a,
+        |  output  [2:0] bar_b,
+        |  inout  [2:0] bar_a
+        |);
+        |  assign bar_b = foo_b;
+        |  alias bar_a = foo_a;
+        |endmodule
+        |""".stripMargin.split("\n") map normalized
+    executeTest(input, check, compiler)
+  }
+
   it should "preserve attach order" in {
     val compiler = new VerilogCompiler
     val input =
@@ -190,6 +213,31 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
         |""".stripMargin.split("\n") map normalized
     executeTest(input2, check2, compiler)
   }
+
+  it should "infer widths" in {
+    val compiler = new VerilogCompiler
+    val input =
+     """circuit Attaching :
+        |  module Attaching :
+        |    input an: Analog
+        |    inst a of A
+        |    attach (an, a.an1)
+        |  module A:
+        |    input an1: Analog<3>""".stripMargin
+    val check =
+     """module Attaching(
+       |  inout  [2:0] an
+       |);
+       |  A a (
+       |    .an1(an)
+       |  );
+       |endmodule
+       |module A(
+       |  inout  [2:0] an1
+       |);
+       |endmodule""".stripMargin.split("\n") map normalized
+    executeTest(input, check, compiler)
+  }
 }
 
 class AttachAnalogSpec extends FirrtlFlatSpec {