Merge branch 'master' into addmiddlefirrtlcompiler

1 files changed, 31 insertions, 1 deletions

diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala
index a17e6ae1..b23e9127 100644
--- a/src/test/scala/firrtlTests/transforms/DedupTests.scala
+++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala
@@ -15,9 +15,10 @@ import firrtl.passes.PassExceptions
 import firrtl.annotations.{
    Named,
    CircuitName,
+   ModuleName,
    Annotation
 }
-import firrtl.transforms.DedupModules
+import firrtl.transforms.{DedupModules, NoDedupAnnotation}
 
 
 /**
@@ -127,6 +128,35 @@ class DedupModuleTests extends HighTransformSpec {
       val aMap = new AnnotationMap(Nil)
       execute(writer, aMap, input, check)
    }
+   "The module B, but not A, with comments" should "be deduped if not annotated" in {
+      val input =
+         """circuit Top :
+           |  module Top :
+           |    inst a1 of A
+           |    inst a2 of A_
+           |  module A : @[yy 2:2]
+           |    output x: UInt<1> @[yy 2:2]
+           |    x <= UInt(1)
+           |  module A_ : @[xx 1:1]
+           |    output x: UInt<1> @[xx 1:1]
+           |    x <= UInt(1)
+           """.stripMargin
+      val check =
+         """circuit Top :
+           |  module Top :
+           |    inst a1 of A
+           |    inst a2 of A_
+           |  module A : @[yy 2:2]
+           |    output x: UInt<1> @[yy 2:2]
+           |    x <= UInt(1)
+           |  module A_ : @[xx 1:1]
+           |    output x: UInt<1> @[xx 1:1]
+           |    x <= UInt(1)
+           """.stripMargin
+      val writer = new StringWriter()
+      val aMap = new AnnotationMap(Seq(NoDedupAnnotation(ModuleName("A", CircuitName("Top")))))
+      execute(writer, aMap, input, check)
+   }
 }
 
 // Execution driven tests for inlining modules