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AgeCommit message (Expand)Author
2017-03-14Added lesson2Adam Izraelevitz
2017-03-10Changed custom transform option and help textAdam Izraelevitz
2017-03-10Added comments and section in READMEAdam Izraelevitz
2017-03-10Added tutorial passAdam Izraelevitz
2017-03-10Added custom transform commandline optionAdam Izraelevitz
2017-03-10Added Circuit mappersAdam Izraelevitz
2017-03-09make sure infer-rw works for exclusive when statements (#481)Donggyu
2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
2017-03-06Zero width (#402)Adam Izraelevitz
2017-03-06Fix mistake when rebasingAdam Izraelevitz
2017-03-06After merge, fixed added transformsAdam Izraelevitz
2017-03-06Added more stylized debugging styleAdam Izraelevitz
2017-03-06Addresses #459. Rewords transform annotations API.Adam Izraelevitz
2017-03-06Added pass name to debug loggerAdam Izraelevitz
2017-03-06Add ability to emit 1 file per module (#443)Jack Koenig
2017-03-03Bugfix: InlineInstances must prefix instancesAdam Izraelevitz
2017-03-01Allow nested digit fields in subfield expressionsJack Koenig
2017-03-01Fix bug in Lexer rule for DoubleLit and add testsJack Koenig
2017-02-28Fix validation print for log-level (#394)Colin Schmidt
2017-02-27castrhs shouldn't assume rhs is uint (#467)Angie Wang
2017-02-27Add chisel2 isVCSAvailable, isCommandAvailable to FileUtils. (#439)Jim Lawson
2017-02-26Align types and names of ports in emitted Verilog (#463)Jack Koenig
2017-02-23move more general utils out of memutils, mov WIR helpers to WIR.scala and upd...Angie
2017-02-23messed up clocktype matchAngie
2017-02-23fix bug in blackboxsourcehelper apply -- pointed to wrong transformAngie
2017-02-23added more helpersAngie
2017-02-23Add support for bundle fields to start with digits (#462)Jack Koenig
2017-02-23Fix warning from Cadence IncisiveScott Johnson
2017-02-22[stevo]: Adams fixStevo Bailey
2017-02-21Implementation of nodedupe mem (#447)Colin Schmidt
2017-02-14Add support for Analog types in partial connect (#435)Jack Koenig
2017-02-14Fixes #441, ConvertFixedToSInt not recursing expsAdam Izraelevitz
2017-02-14Add println/throwInternalError to EmitterAdam Izraelevitz
2017-02-13Emit memories larger than 512 MB with a sparse annotation (#438)Colin Schmidt
2017-02-12Changed fixed-point cat semantics to return uint (#436)Adam Izraelevitz
2017-02-07Rework Attach to work on arbitrary Analog hierarchies (#415)Jack Koenig
2017-02-07Return a new circuit object after execution (#433)Colin Schmidt
2017-02-06Fix stack overflow from massive MaxWidth chains during width inference (#407)Jack Koenig
2017-02-01Fix anno in backend (#428)Chick Markley
2017-02-01Fetch resource files as resources. (#399)Jim Lawson
2017-01-31Replace createTempDirectory with createTestDirectory (#427)Jack Koenig
2017-01-31Blackboxhelper (#418)Chick Markley
2017-01-29Keep firrtl's simulation environment in sync with chisel's. (#425)Jim Lawson
2017-01-27Fix signed types (#422)Angie Wang
2017-01-27Move BackendCompilationUtilities into a util package for use by chisel3. (#400)Jim Lawson
2017-01-23Add FixedType to uniqueify match statement.Paul Rigge
2017-01-22use new annotations correctly for wiring (#416)Colin Schmidt
2017-01-20Remove merging of source locators during module deduplicationJack
2017-01-20Add MultiInfo. Speedup Info concatenation. Fixes #391Jack
2017-01-20Merge branch 'master' into scaladocrootJim Lawson
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