diff options
| author | Stevo Bailey | 2017-02-22 17:04:40 -0800 |
|---|---|---|
| committer | Adam Izraelevitz | 2017-02-22 17:17:45 -0800 |
| commit | 5cbf5ea3723376bde20167793d5454104c524867 (patch) | |
| tree | 7cffc3343845a49e60eb7803ed6e2a1a44937f53 /src | |
| parent | 7b4ab673ef1b5716f8bbe689faaf474c60a0d2fd (diff) | |
[stevo]: Adams fix
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 4 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/ConvertFixedToSInt.scala | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 5201942a..1a4b24cd 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -67,7 +67,8 @@ class HighFirrtlToMiddleFirrtl extends CoreTransform { passes.CheckTypes, passes.ResolveGenders, passes.InferWidths, - passes.CheckWidths) + passes.CheckWidths, + passes.ConvertFixedToSInt) } /** Expands all aggregate types into many ground-typed components. Must @@ -84,7 +85,6 @@ class MiddleFirrtlToLowFirrtl extends CoreTransform { passes.InferTypes, passes.ResolveGenders, passes.InferWidths, - passes.ConvertFixedToSInt, passes.Legalize) } diff --git a/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala b/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala index 3ddfb124..823fb7fb 100644 --- a/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala +++ b/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala @@ -31,7 +31,7 @@ object ConvertFixedToSInt extends Pass { def toSIntType(t: Type): Type = t match { case FixedType(IntWidth(w), IntWidth(p)) => SIntType(IntWidth(w)) case FixedType(w, p) => error("Shouldn't be here") - case _ => t + case _ => t map toSIntType } def run(c: Circuit): Circuit = { val moduleTypes = mutable.HashMap[String,Type]() |