diff options
| author | Angie | 2017-02-22 17:50:23 -0800 |
|---|---|---|
| committer | Adam Izraelevitz | 2017-02-23 14:55:00 -0800 |
| commit | 1d652352b752502dd6d130aeb85981df214d7021 (patch) | |
| tree | 069870e1d36b1f5316c2c0d2ef18ddfb3c774453 /src | |
| parent | 7f771d36ea80bb51e5bef6e985e4fb0b600e199e (diff) | |
messed up clocktype match
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/MemUtils.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemUtils.scala b/src/main/scala/firrtl/passes/memlib/MemUtils.scala index 75378824..c7eb4539 100644 --- a/src/main/scala/firrtl/passes/memlib/MemUtils.scala +++ b/src/main/scala/firrtl/passes/memlib/MemUtils.scala @@ -94,7 +94,7 @@ object castRhs { lhst match { case _: SIntType => DoPrim(AsSInt, Seq(rhs), Seq.empty, lhst) case FixedType(_, IntWidth(p)) => DoPrim(AsFixedPoint, Seq(rhs), Seq(p), lhst) - case _: ClockType => DoPrim(AsClock, Seq(rhs), Seq.empty, lhst) + case ClockType => DoPrim(AsClock, Seq(rhs), Seq.empty, lhst) case _: UIntType => rhs } } |