From 1d652352b752502dd6d130aeb85981df214d7021 Mon Sep 17 00:00:00 2001
From: Angie
Date: Wed, 22 Feb 2017 17:50:23 -0800
Subject: messed up clocktype match

---
 src/main/scala/firrtl/passes/memlib/MemUtils.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/passes/memlib/MemUtils.scala b/src/main/scala/firrtl/passes/memlib/MemUtils.scala
index 75378824..c7eb4539 100644
--- a/src/main/scala/firrtl/passes/memlib/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemUtils.scala
@@ -94,7 +94,7 @@ object castRhs {
     lhst match {
       case _: SIntType => DoPrim(AsSInt, Seq(rhs), Seq.empty, lhst)
       case FixedType(_, IntWidth(p)) => DoPrim(AsFixedPoint, Seq(rhs), Seq(p), lhst)
-      case _: ClockType => DoPrim(AsClock, Seq(rhs), Seq.empty, lhst)
+      case ClockType => DoPrim(AsClock, Seq(rhs), Seq.empty, lhst)
       case _: UIntType => rhs
     }  
   }
-- 
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