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-rw-r--r--src/main/scala/firrtl/passes/memlib/MemUtils.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemUtils.scala b/src/main/scala/firrtl/passes/memlib/MemUtils.scala
index 75378824..c7eb4539 100644
--- a/src/main/scala/firrtl/passes/memlib/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemUtils.scala
@@ -94,7 +94,7 @@ object castRhs {
lhst match {
case _: SIntType => DoPrim(AsSInt, Seq(rhs), Seq.empty, lhst)
case FixedType(_, IntWidth(p)) => DoPrim(AsFixedPoint, Seq(rhs), Seq(p), lhst)
- case _: ClockType => DoPrim(AsClock, Seq(rhs), Seq.empty, lhst)
+ case ClockType => DoPrim(AsClock, Seq(rhs), Seq.empty, lhst)
case _: UIntType => rhs
}
}