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authorAdam Izraelevitz2017-02-12 23:33:20 -0800
committerGitHub2017-02-12 23:33:20 -0800
commit7b2a3bc74d5fd0303c0056b4cb785fb34d7806bc (patch)
treede0e881ad213a0ff71a81cf41a3bbb997c4a246c /src
parent2f4ae9b4164cf415600de970b3ac5a1b9760efa5 (diff)
Changed fixed-point cat semantics to return uint (#436)
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/PrimOps.scala4
-rw-r--r--src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala4
2 files changed, 3 insertions, 5 deletions
diff --git a/src/main/scala/firrtl/PrimOps.scala b/src/main/scala/firrtl/PrimOps.scala
index b28cd000..fa523e12 100644
--- a/src/main/scala/firrtl/PrimOps.scala
+++ b/src/main/scala/firrtl/PrimOps.scala
@@ -314,9 +314,7 @@ object PrimOps extends LazyLogging {
case _ => UnknownType
}
case Cat => (t1, t2) match {
- case (_: UIntType | _: SIntType, _: UIntType | _: SIntType) => UIntType(PLUS(w1, w2))
- case (_: FixedType, _: UIntType| _: SIntType) => FixedType(PLUS(w1, w2), PLUS(p1, w2))
- case (_: UIntType | _: SIntType, _: FixedType) => FixedType(PLUS(w1, w2), p1)
+ case (_: UIntType | _: SIntType | _: FixedType, _: UIntType | _: SIntType | _: FixedType) => UIntType(PLUS(w1, w2))
case (t1, t2) => UnknownType
}
case Bits => t1 match {
diff --git a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
index d567a6da..44fa1d29 100644
--- a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
@@ -206,7 +206,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
| input a : Fixed<10><<2>>
| input b : Fixed<7><<3>>
| input c : UInt<2>
- | output cat : Fixed
+ | output cat : UInt
| output head : UInt
| output tail : UInt
| output bits : UInt
@@ -220,7 +220,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
| input a : Fixed<10><<2>>
| input b : Fixed<7><<3>>
| input c : UInt<2>
- | output cat : Fixed<12><<4>>
+ | output cat : UInt<12>
| output head : UInt<3>
| output tail : UInt<7>
| output bits : UInt<4>