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authorScott Johnson2017-02-21 18:50:48 -0800
committerAdam Izraelevitz2017-02-23 14:02:04 -0800
commit4811d49cbccfd42fccabc8fc37179d709c6f7e9d (patch)
treebe2495138744a74a1a6bb069b74a468cf634284c /src
parent5cbf5ea3723376bde20167793d5454104c524867 (diff)
Fix warning from Cadence Incisive
The fix for PR #305 caused a new compile warning from Cadence Incisive: always @(*) begin end | ncelab: *W,STARMT (../TestHarness.MyConfig.v,196147|9): This @* expands to empty list, will never wake up. This change satisfies all of: VCS, Incisive, Questa, Vivado, Verilator.
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/Emitter.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 9e78cbb3..151ad9e4 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -527,7 +527,7 @@ class VerilogEmitter extends Emitter with PassBased {
}
emit(Seq(");"))
- if (declares.isEmpty && assigns.isEmpty) emit(Seq(tab, "always @(*) begin end"))
+ if (declares.isEmpty && assigns.isEmpty) emit(Seq(tab, "initial begin end"))
for (x <- declares) emit(Seq(tab, x))
for (x <- instdeclares) emit(Seq(tab, x))
for (x <- assigns) emit(Seq(tab, x))