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Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 9e78cbb3..151ad9e4 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -527,7 +527,7 @@ class VerilogEmitter extends Emitter with PassBased { } emit(Seq(");")) - if (declares.isEmpty && assigns.isEmpty) emit(Seq(tab, "always @(*) begin end")) + if (declares.isEmpty && assigns.isEmpty) emit(Seq(tab, "initial begin end")) for (x <- declares) emit(Seq(tab, x)) for (x <- instdeclares) emit(Seq(tab, x)) for (x <- assigns) emit(Seq(tab, x)) |