Fix signed types (#422)

* type conversions between sint/fixed and uint added at memory interfaces for replseqmem

* turns out asFixed requires bp as constant in PrimOps (really should be documented)

* fixed legalizeconnects to handle FixedPt

* added tests for replseqmem failure with signed types

3 files changed, 66 insertions, 3 deletions

diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 87458a2b..0e91c642 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -210,7 +210,7 @@ object Legalize extends Pass {
       val expr = t match {
         case UIntType(_) => bits
         case SIntType(_) => DoPrim(AsSInt, Seq(bits), Seq(), SIntType(IntWidth(w)))
-        //case FixedType(width, point) => FixedType(width, point)
+        case FixedType(_, IntWidth(p)) => DoPrim(AsFixedPoint, Seq(bits), Seq(p), t)
       }
       Connect(c.info, c.loc, expr)
     }
diff --git a/src/main/scala/firrtl/passes/memlib/MemUtils.scala b/src/main/scala/firrtl/passes/memlib/MemUtils.scala
index ffe3bbcd..0962015e 100644
--- a/src/main/scala/firrtl/passes/memlib/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemUtils.scala
@@ -31,7 +31,7 @@ object toBits {
       hiercat(WSubIndex(e, i, t.tpe, UNKNOWNGENDER))))
     case t: BundleType => seqCat(t.fields map (f =>
       hiercat(WSubField(e, f.name, f.tpe, UNKNOWNGENDER))))
-    case t: GroundType => e
+    case t: GroundType => DoPrim(AsUInt, Seq(e), Seq.empty, UnknownType)
     case t => error("Unknown type encountered in toBits!")
   }
 }
@@ -89,6 +89,16 @@ object bitWidth {
   }
 }
 
+object castRhs {
+  def apply(lhst: Type, rhs: Expression) = {
+    lhst match {
+      case _: SIntType => DoPrim(AsSInt, Seq(rhs), Seq.empty, lhst)
+      case FixedType(_, IntWidth(p)) => DoPrim(AsFixedPoint, Seq(rhs), Seq(p), lhst)
+      case _: UIntType => rhs
+    }  
+  }
+}
+
 object fromBits {
   def apply(lhs: Expression, rhs: Expression): Statement = {
     val fbits = lhs match {
@@ -103,7 +113,8 @@ object fromBits {
                             offset: BigInt): (BigInt, Seq[Statement]) = {
     val intWidth = bitWidth(lhst)
     val sel = DoPrim(PrimOps.Bits, Seq(rhs), Seq(offset + intWidth - 1, offset), UnknownType)
-    (offset + intWidth, Seq(Connect(NoInfo, lhs, sel)))
+    val rhsConnect = castRhs(lhst, sel)
+    (offset + intWidth, Seq(Connect(NoInfo, lhs, rhsConnect)))
   }
   private def getPart(lhs: Expression,
                       lhst: Type,
diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
index b851f176..fc3bfe8e 100644
--- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala
+++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
@@ -91,6 +91,58 @@ circuit Top :
     (new java.io.File(confLoc)).delete()
   }
 
+  "ReplSeqMem" should "not fail with FixedPoint types " in {
+    val input = """
+circuit CustomMemory : 
+  module CustomMemory : 
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip rClk : Clock, flip rAddr : UInt<3>, dO : Fixed<16><<8>>, flip wClk : Clock, flip wAddr : UInt<3>, flip wEn : UInt<1>, flip dI : Fixed<16><<8>>}
+    
+    io is invalid
+    smem mem : Fixed<16><<8>>[7] 
+    read mport _T_17 = mem[io.rAddr], clock
+    io.dO <= _T_17 
+    when io.wEn : 
+      write mport _T_18 = mem[io.wAddr], clock
+      _T_18 <= io.dI
+      skip 
+""".stripMargin
+    val confLoc = "ReplSeqMemTests.confTEMP"
+    val aMap = AnnotationMap(Seq(ReplSeqMemAnnotation("-c:CustomMemory:-o:"+confLoc)))
+    val writer = new java.io.StringWriter
+    compile(CircuitState(parse(input), ChirrtlForm, Some(aMap)), writer)
+    // Check correctness of firrtl
+    parse(writer.toString)
+    (new java.io.File(confLoc)).delete()
+  }
+
+  "ReplSeqMem" should "not fail with Signed types " in {
+    val input = """
+circuit CustomMemory : 
+  module CustomMemory : 
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip rClk : Clock, flip rAddr : UInt<3>, dO : SInt<16>, flip wClk : Clock, flip wAddr : UInt<3>, flip wEn : UInt<1>, flip dI : SInt<16>}
+    
+    io is invalid
+    smem mem : SInt<16>[7] 
+    read mport _T_17 = mem[io.rAddr], clock
+    io.dO <= _T_17 
+    when io.wEn : 
+      write mport _T_18 = mem[io.wAddr], clock
+      _T_18 <= io.dI
+      skip 
+""".stripMargin
+    val confLoc = "ReplSeqMemTests.confTEMP"
+    val aMap = AnnotationMap(Seq(ReplSeqMemAnnotation("-c:CustomMemory:-o:"+confLoc)))
+    val writer = new java.io.StringWriter
+    compile(CircuitState(parse(input), ChirrtlForm, Some(aMap)), writer)
+    // Check correctness of firrtl
+    parse(writer.toString)
+    (new java.io.File(confLoc)).delete()
+  }
+
   "ReplSeqMem Utility -- getConnectOrigin" should 
       "determine connect origin across nodes/PrimOps even if ConstProp isn't performed" in {
     def checkConnectOrigin(hurdle: String, origin: String) = {