Bugfix: InlineInstances must prefix instances

2 files changed, 41 insertions, 1 deletions

diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index 002343ac..93ec6cea 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -137,7 +137,7 @@ class InlineInstances extends Transform {
           }
           val stmts = toInline.ports.map(p => DefWire(p.info, p.name, p.tpe)) :+ toInline.body
           onStmt(prefix + instName + inlineDelim, moduleName)(Block(stmts))
-        } else s
+        } else WDefInstance(info, prefix + instName, moduleName, instTpe)
       case sx => sx map appendRefPrefix(prefix, currentModule) map onStmt(prefix, currentModule) map appendNamePrefix(prefix)
     }
 
diff --git a/src/test/scala/firrtlTests/InlineInstancesTests.scala b/src/test/scala/firrtlTests/InlineInstancesTests.scala
index a3e2b38d..89862145 100644
--- a/src/test/scala/firrtlTests/InlineInstancesTests.scala
+++ b/src/test/scala/firrtlTests/InlineInstancesTests.scala
@@ -170,6 +170,46 @@ class InlineInstancesTests extends LowTransformSpec {
       execute(writer, aMap, input, check)
    }
 
+   "Non-inlined instances" should "still prepend prefix" in {
+      val input =
+         """circuit Top :
+           |  module Top :
+           |    input a : UInt<32>
+           |    output b : UInt<32>
+           |    inst i of A
+           |    i.a <= a
+           |    b <= i.b
+           |  module A :
+           |    input a : UInt<32>
+           |    output b : UInt<32>
+           |    inst i of B
+           |    i.a <= a
+           |    b <= i.b
+           |  module B :
+           |    input a : UInt<32>
+           |    output b : UInt<32>
+           |    b <= a""".stripMargin
+      val check =
+         """circuit Top :
+           |  module Top :
+           |    input a : UInt<32>
+           |    output b : UInt<32>
+           |    wire i$a : UInt<32>
+           |    wire i$b : UInt<32>
+           |    inst i$i of B
+           |    i$b <= i$i.b
+           |    i$i.a <= i$a
+           |    b <= i$b
+           |    i$a <= a
+           |  module B :
+           |    input a : UInt<32>
+           |    output b : UInt<32>
+           |    b <= a""".stripMargin
+      val writer = new StringWriter()
+      val aMap = new AnnotationMap(Seq(InlineAnnotation(ModuleName("A", CircuitName("Top")))))
+      execute(writer, aMap, input, check)
+   }
+
    // ---- Errors ----
    // 1) ext module
    "External module" should "not be inlined" in {