| Age | Commit message (Collapse) | Author |
|---|
|
Fix init accessor
|
|
StandardVerilogCompiler
|
|
Make Link.fir reference relative path
|
|
particular directory structure.
|
|
|
|
|
|
|
|
|
|
|
|
catching of initialization of accessors. Missing use case of accessing an accessor. Still need to update tests to pass
|
|
|
|
|
|
|
|
enable with muxing the index with poison bits
|
|
is unneeded
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Code like
add(UInt<1>(1), SInt<1>(1))
was resulting in Verilog like
$signed(1'h1) + $signed(1'sh1)
which is incorrect: it computes -2, not 0. The fix is to zero-extend the
unsigned operand, e.g.
$signed({1'b0,1'h1}) + $signed(1'sh1)
|
|
conditional assignment
|
|
Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt
|
|
|
|
|
|
|
|
|
|
now be small examples, categorized by either passes, errors, or features.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Updated tests to match. #29.
|
|
Updated tests to match.
|
|
|
|
|
|
|
|
|
|
extract, not >>
|
|
|
|
|
