diff options
| author | azidar | 2015-08-18 16:39:07 -0700 |
|---|---|---|
| committer | azidar | 2015-08-18 16:39:07 -0700 |
| commit | 51411657aee01568519811659afd0316b6db346f (patch) | |
| tree | 119aa67e1a4f8cd7032c899068a86f930054a5e7 | |
| parent | f64e4868fdb72cc592226250f02a021fd38b40f5 (diff) | |
Updated shr test so it is an expected pass
| -rw-r--r-- | test/passes/expand-whens/scoped-reg.fir | 1 | ||||
| -rw-r--r-- | test/passes/infer-widths/shr.fir (renamed from test/passes/infer-widths/shl.fir) | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir index b052df5d..a1f28cc7 100644 --- a/test/passes/expand-whens/scoped-reg.fir +++ b/test/passes/expand-whens/scoped-reg.fir @@ -1,5 +1,4 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * circuit top : module top : input clk : Clock diff --git a/test/passes/infer-widths/shl.fir b/test/passes/infer-widths/shr.fir index 080b4a31..c0a6e358 100644 --- a/test/passes/infer-widths/shl.fir +++ b/test/passes/infer-widths/shr.fir @@ -1,5 +1,4 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * ;CHECK: Infer Widths ; CHECK: Finished Infer Widths |