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authorazidar2015-09-01 13:04:21 -0700
committerazidar2015-09-01 13:04:21 -0700
commitd8bf7de8c3b7c3e37716fcbc7afc617213c1561b (patch)
tree7b9dd09e78ed8231ad2ac2279dd97d15efa6c2ec
parent80a70c300d693d0eb06bc1a455d83bd2e6e4f10e (diff)
Added a conditional readport example, with new idea of representing a read enable with muxing the index with poison bits
-rw-r--r--test/features/CondRead.fir25
1 files changed, 25 insertions, 0 deletions
diff --git a/test/features/CondRead.fir b/test/features/CondRead.fir
new file mode 100644
index 00000000..8961715e
--- /dev/null
+++ b/test/features/CondRead.fir
@@ -0,0 +1,25 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; XFAIL: *
+circuit CondRead :
+ module CondRead :
+ input pred : UInt<1>
+ input index : UInt<6>
+ input clk : Clock
+ output out : UInt<20>
+
+ smem mem : UInt<20>[128],clk
+
+ poison xxx : UInt<20>
+ wire data : UInt<20>
+ data := xxx
+ when pred :
+ read accessor readport = mem[index]
+ data := readport
+
+ out := data
+
+
+; CHECK: poison index_0 : UInt<6>
+; CHECK: read accessor readport = mem[mux(pred,index,index_0)]
+; CHECK: Done!
+