Fixed bug in split expression that leaked connect statements out of a conditional assignment

4 files changed, 42 insertions, 5 deletions

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index b54069e4..8a03fb10 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2183,8 +2183,7 @@ public defmethod short-name (b:SplitExp) -> String : "split-expressions"
 defn full-name (e:Expression) -> Symbol|False :
    match(e) :
       (e:WRef) : name(e)
-      (e:WSubfield) : false
-      (e) : error("Non-supported expression.")
+      (e) : false
 
 defn split-exp (c:Circuit) :
    defn split-exp-s (s:Stmt,v:Vector<Stmt>,sh:HashTable<Symbol,Int>) -> False :
@@ -2211,8 +2210,14 @@ defn split-exp (c:Circuit) :
          (s:Begin) : 
             do(f,s)
          (s:Conditionally) : 
-            add(v,map(split-exp-e{_,full-name(loc(conseq(s) as Connect)),info(s)},s))
-            do(f,s)
+            ;Predicate
+            val pred* = map(split-exp-e{_,full-name(pred(s)),info(s)},pred(s))
+
+            ;Connect
+            val c = conseq(s) as Connect
+            val exp* = map(split-exp-e{_,full-name(loc(c)),info(c)},exp(c))
+            val conseq* = Connect(info(c),loc(c),exp*)
+            add(v,Conditionally(info(s),pred*,conseq*,alt(s)))
          (s:Connect) : 
             val exp* = map(split-exp-e{_,full-name(loc(s)),info(s)},exp(s))
             add(v,Connect(info(s),loc(s),exp*))
diff --git a/test/errors/init/Output.fir b/test/errors/init/Output.fir
new file mode 100644
index 00000000..f28d1e0b
--- /dev/null
+++ b/test/errors/init/Output.fir
@@ -0,0 +1,10 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Reference y is not fully initialized.
+
+circuit Top : 
+  module Top : 
+    input clk : Clock
+    wire y : UInt<1>
+
+    when UInt(0) : 
+      y := UInt(1)
diff --git a/test/passes/split-exp/primop.fir b/test/passes/split-exp/primop.fir
index 3b120217..b2f0af82 100644
--- a/test/passes/split-exp/primop.fir
+++ b/test/passes/split-exp/primop.fir
@@ -4,7 +4,6 @@
 circuit Top :
    module Top :
       output out : UInt<1>
-      output out2 : UInt<1>
 
       wire m : UInt<1>[3]
       m[0] := UInt(0)
diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir
new file mode 100644
index 00000000..ddf6a155
--- /dev/null
+++ b/test/passes/split-exp/split-in-when.fir
@@ -0,0 +1,23 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Split Expressions
+circuit Top :
+   module Top :
+      input p : UInt<1>
+      input clk : Clock
+      input a : UInt<10>
+      input b : UInt<10>
+      input c : UInt<10>
+      
+      reg out : UInt<10>,clk,p
+
+      when bit(subw(a,c),3) : out := mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b))
+
+;CHECK: node T = subw(a, c)
+;CHECK: node out_1 = eqv(UInt("h0"), UInt("hd"))
+;CHECK: node out_3 = addw(b, c)
+;CHECK: node out_2 = addw(a, out_3)
+;CHECK: node out_4 = subw(c, b)
+;CHECK: when bit(T, 3) : out := mux(out_1, out_2, out_4)   
+
+;CHECK: Finished Split Expressions