Removed IntWidth, now only use LongWidth. Now do width inference for Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt

10 files changed, 73 insertions, 79 deletions

diff --git a/src/main/stanza/bigint2.stanza b/src/main/stanza/bigint2.stanza
index ebd01652..64c587ee 100644
--- a/src/main/stanza/bigint2.stanza
+++ b/src/main/stanza/bigint2.stanza
@@ -88,9 +88,10 @@ defmethod set (b:BigInt, index:Int, bit:Int) -> False :
    d(b)[word-index] = ((bit & 1) << bit-index) | d(b)[word-index]
    
 public defmethod to-string (b:BigInt) : to-hex(b)
+   ;string-join([to-hex(b) "'" num-bits(b)])
 
 public defmethod print (o:OutputStream, b:BigInt) :
-  print(o, to-string(b))
+   print(o, to-string(b))
 
 public defn BigIntZero (num-bits:Int) -> BigInt :
    val num-words = (num-bits + word-size - 1) / word-size
diff --git a/src/main/stanza/custom-passes.stanza b/src/main/stanza/custom-passes.stanza
index 44eb6b5e..ed71784d 100644
--- a/src/main/stanza/custom-passes.stanza
+++ b/src/main/stanza/custom-passes.stanza
@@ -45,7 +45,7 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Sym
    val when-bits = Vector<Ref>()
    val inst-bits = Vector<Ref>()
    val sym = HashTable<Symbol,Int>(symbol-hash)
-   val w1 = IntWidth(1)
+   val w1 = LongWidth(1)
    val t1 = UIntType(w1)
    val u1 = UIntValue(BigIntLit("h1"),w1)
    defn when-coverage (s:Stmt) -> Stmt :
@@ -70,13 +70,13 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Sym
 
    val w-ls = to-list $ when-bits
    if length(w-ls) != 0 :
-      val reg-ref = Ref(reg-name,UIntType(IntWidth(length(w-ls))))
+      val reg-ref = Ref(reg-name,UIntType(LongWidth(length(w-ls))))
       ;add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref)) TODO add clock and reset
       for (x in w-ls, i in 0 to false) do :
          add{logic,_} $ DefWire(FileInfo(),name(x),type(x))
          add{logic,_} $ Connect(FileInfo(),x,DoPrim(BIT-SELECT-OP,list(reg-ref),list(i),UIntType(w1)))
       add{logic,_} $ Connect(FileInfo(),reg-ref,concat-all(w-ls))
-      add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(BigIntLit("h0"),IntWidth(length(w-ls))))
+      add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(BigIntLit("h0"),LongWidth(length(w-ls))))
 
    val i-ls = to-list $ inst-bits
    if length(i-ls) != 0 :
@@ -161,7 +161,7 @@ public defn when-coverage (port-name:String, reg-name:String, c:Circuit) :
 ;   val when-bits = Vector<Ref>()
 ;   val inst-bits = Vector<Ref>()
 ;   val sym = HashTable<Symbol,Int>(symbol-hash)
-;   val w1 = IntWidth(1)
+;   val w1 = LongWidth(1)
 ;   val t1 = UIntType(w1)
 ;   val u1 = UIntValue(to-long $ 1,w1)
 ;   defn insert-temporal-asserts (s:Stmt) -> Stmt :
@@ -186,9 +186,9 @@ public defn when-coverage (port-name:String, reg-name:String, c:Circuit) :
 ;
 ;   val w-ls = to-list $ when-bits
 ;   if length(w-ls) != 0 :
-;      val reg-ref = Ref(reg-name,UIntType(IntWidth(length(w-ls))))
+;      val reg-ref = Ref(reg-name,UIntType(LongWidth(length(w-ls))))
 ;      add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref))
-;      add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(to-long $ 0,IntWidth(length(w-ls))))
+;      add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(to-long $ 0,LongWidth(length(w-ls))))
 ;      for (x in w-ls, i in 0 to false) do :
 ;         add{logic,_} $ DefWire(FileInfo(),name(x),type(x))
 ;         add{logic,_} $ Connect(FileInfo(),x,DoPrim(BIT-SELECT-OP,list(reg-ref),list(i),UIntType(w1)))
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index 72535242..fd3dfc2a 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -252,8 +252,8 @@ public defn check-high-form (c:Circuit) -> Circuit :
 
    defn check-high-form-w (info:FileInfo,w:Width,unknown-ok?:True|False) -> Width :
       match(w) :
-         (w:IntWidth) : 
-            if width(w) <= 0 : add(errors,NegWidth(info))
+         (w:LongWidth) : 
+            if width(w) <= to-long(0) : add(errors,NegWidth(info))
             w
          (w:UnknownWidth) : 
             if unknown-ok? == false : add(errors,IllegalUnknownWidth(info))
@@ -907,8 +907,6 @@ public defn check-width (c:Circuit) -> Circuit :
    defn check-width-m (m:Module) -> False :
       defn check-width-w (info:FileInfo,w:Width) -> Width :
          match(w) :
-            (w:IntWidth) : 
-               if width(w) <= 0 : add(errors,NegWidth(info))
             (w:LongWidth) :
                if width(w) <= to-long(0) : add(errors,NegWidth(info))
             (w) : 
@@ -917,11 +915,15 @@ public defn check-width (c:Circuit) -> Circuit :
 
       defn check-width-e (info:FileInfo,e:Expression) -> Expression :
          match(map(check-width-e{info,_},e)) :
-            (e:UIntValue|SIntValue) : 
+            (e:UIntValue) : 
                match(width(e)) :
-                  (w:IntWidth) : 
-                     if num-bits(value(e)) > width(w) : 
+                  (w:LongWidth) : 
+                     if max(to-long(1),to-long(num-bits(value(e)) - 1)) > width(w) : 
                         add(errors,WidthTooSmall(info,to-string(value(e))))
+                  (w) : add(errors,UninferredWidth(info))
+               check-width-w(info,width(e))
+            (e:SIntValue) : 
+               match(width(e)) :
                   (w:LongWidth) : 
                      if to-long(num-bits(value(e))) > width(w) : 
                         add(errors,WidthTooSmall(info,to-string(value(e))))
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index de9b6cb3..b0db73b2 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -29,8 +29,7 @@ public val RDWR = new AccDirection
 
 public definterface Width
 public defstruct UnknownWidth <: Width
-public defstruct IntWidth <: Width :
-   width: Int
+public defn LongWidth (width:Int) : LongWidth(to-long(width))
 public defstruct LongWidth <: Width :
    width: Long
 
diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index b34af613..3b1dbf76 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -65,7 +65,6 @@ defn flo-op-name (op:PrimOp, args:List<Expression>) -> String :
 
 defn sane-width (wd:Width) -> Int|Long :
   match(wd) :
-    (w:IntWidth) : max(1, width(w))
     (w:LongWidth) : max(to-long(1), width(w))
     (w)          : error(string-join(["Unknown width: " w]))
 
@@ -173,7 +172,7 @@ defn emit-s (s:Stmt, flokinds:HashTable<Symbol,FloKind>, top:Symbol,sh:HashTable
       (s:DefNode) :
          emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top)
       (s:Begin) : do(emit-s{_, flokinds, top,sh}, body(s))
-      (s:Connect) : emit-connect(s,UIntValue(BigIntLit("1"),IntWidth(1)))
+      (s:Connect) : emit-connect(s,UIntValue(BigIntLit("1"),LongWidth(1)))
       (s:Conditionally) : emit-connect(conseq(s) as Connect,pred(s))
       (s) : s 
 
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index adffc62d..d3d9c379 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -5,6 +5,7 @@ defpackage firrtl/parser :
    import stz/parser
    import firrtl/lexer
    import bigint2
+   import firrtl/ir-utils
 
 ;======= Convenience Functions ========
 defn first-info? (form) -> FileInfo|False :
@@ -227,7 +228,7 @@ defsyntax firrtl :
       accdir = (rdwr) : RDWR
 
    defrule width :
-      width = (?x:#int) : IntWidth(x)
+      width = (?x:#int) : LongWidth(x)
       width = (?) : UnknownWidth()
 
    ;Main Statement Productions
@@ -285,8 +286,19 @@ defsyntax firrtl :
             (t:UIntType) : 
                if (v as Int) < 0 : 
                   FPE(form, "UIntValue cannot be negative.")
-               UIntValue(BigIntLit(v as Int), width(t))
-            (t:SIntType) : SIntValue(BigIntLit(v as Int), width(t))
+               match(width(t)) :
+                  (w:LongWidth) : 
+                     UIntValue(BigIntLit(v as Int,to-int(width(w))),w)
+                  (w) : 
+                     val num-bits = req-num-bits(v as Int)
+                     UIntValue(BigIntLit(v as Int,num-bits), LongWidth(max(1,num-bits - 1)))
+            (t:SIntType) :
+               match(width(t)) :
+                  (w:LongWidth) : 
+                     SIntValue(BigIntLit(v as Int,to-int(width(w))),w)
+                  (w) : 
+                     val num-bits = req-num-bits(v as Int)
+                     SIntValue(BigIntLit(v as Int,num-bits), LongWidth(num-bits))
 
       expterm = (?op:#sym(?es:#exp ... ?ints:#int ... ?rest ...)) :
          if not empty?(rest) :
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 3e375e81..0c3140ed 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -160,7 +160,6 @@ defmethod print (o:OutputStream, w:Width) :
    print{o, _} $
    match(w) :
       (w:UnknownWidth) : "?"
-      (w:IntWidth) : width(w)
       (w:LongWidth) : width(w)
 
 defmethod print (o:OutputStream, op:PrimOp) :
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 5c09b034..b54069e4 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -545,7 +545,7 @@ defn to-working-ir (c:Circuit) :
 ;
 ;      var ports! = ports(m)
 ;      if not contains?(explicit-reset,name(m)) :
-;         ports! = append(ports(m),list(Port(FileInfo(),`reset,INPUT,UIntType(IntWidth(1)))))
+;         ports! = append(ports(m),list(Port(FileInfo(),`reset,INPUT,UIntType(LongWidth(1)))))
 ;      match(m) :
 ;         (m:InModule) : 
 ;            val body! = route-reset(body(m))
@@ -1242,8 +1242,8 @@ public defmethod short-name (b:ExpandWhens) -> String : "expand-whens"
 
 ; ======== Expression Computation Library ===========
 
-val zero = UIntValue(BigIntLit(0),IntWidth(1))
-val one = UIntValue(BigIntLit(1),IntWidth(1))
+val zero = UIntValue(BigIntLit(0),LongWidth(1))
+val one = UIntValue(BigIntLit(1),LongWidth(1))
 
 defmethod equal? (e1:Expression,e2:Expression) -> True|False :
    match(e1,e2) :
@@ -1274,19 +1274,19 @@ defn AND (e1:Expression,e2:Expression) -> Expression :
    else if e1 == zero or e2 == zero : zero
    else if e1 == one : e2
    else if e2 == one : e1
-   else : DoPrim(BIT-AND-OP,list(e1,e2),list(),UIntType(IntWidth(1)))
+   else : DoPrim(BIT-AND-OP,list(e1,e2),list(),UIntType(LongWidth(1)))
 
 defn OR (e1:Expression,e2:Expression) -> Expression :
    if e1 == e2 : e1
    else if e1 == one or e2 == one : one
    else if e1 == zero : e2
    else if e2 == zero : e1
-   else : DoPrim(BIT-OR-OP,list(e1,e2),list(),UIntType(IntWidth(1)))
+   else : DoPrim(BIT-OR-OP,list(e1,e2),list(),UIntType(LongWidth(1)))
 
 defn NOT (e1:Expression) -> Expression :
    if e1 == one : zero
    else if e1 == zero : one
-   else : DoPrim(EQUIV-OP,list(e1,zero),list(),UIntType(IntWidth(1)))
+   else : DoPrim(EQUIV-OP,list(e1,zero),list(),UIntType(LongWidth(1)))
 
 defn children (e:Expression) -> List<Expression> :
    val es = Vector<Expression>()
@@ -1395,7 +1395,7 @@ defn to-exp (sv:SymbolicValue) -> Expression|False :
          DoPrim(MUX-OP,
                 list(pred(sv),to-exp(conseq(sv)) as Expression,to-exp(alt(sv)) as Expression),
                 list(),
-                UIntType(IntWidth(1)))
+                UIntType(LongWidth(1)))
       (sv:SVExp) : exp(sv)
       (sv:SVNul) : false
 defn reduce-or (l:List<True|False>) -> True|False :
@@ -1794,9 +1794,6 @@ defmethod equal? (w1:Width,w2:Width) -> True|False :
                for w in args(w1) do :
                   if not contains?(args(w2),w) : ret(false)
                ret(true)
-      (w1:IntWidth,w2:IntWidth) : width(w1) == width(w2)
-      (w1:LongWidth,w2:IntWidth) : width(w1) == to-long $ width(w2)
-      (w1:IntWidth,w2:LongWidth) : to-long(width(w1)) == width(w2)
       (w1:LongWidth,w2:LongWidth) : width(w1) == width(w2)
       (w1:PlusWidth,w2:PlusWidth) : 
          (arg1(w1) == arg1(w2) and arg2(w1) == arg2(w2)) or (arg1(w1) == arg2(w2) and arg2(w1) == arg1(w2))
@@ -1833,21 +1830,14 @@ defn solve-constraints (l:List<WGeq>) -> HashTable<Symbol,Width> :
             MaxWidth(unique(v))
          (w:PlusWidth) : 
             match(arg1(w),arg2(w)) :
-               (w1:IntWidth,w2:IntWidth) : IntWidth(width(w1) + width(w2))
-               (w1:LongWidth,w2:IntWidth) : LongWidth(plus(width(w1),to-long $ width(w2)))
-               (w1:IntWidth,w2:LongWidth) : LongWidth(plus(to-long $ width(w1), width(w2)))
                (w1:LongWidth,w2:LongWidth) : LongWidth(plus(width(w1),width(w2)))
                (w1,w2) : w
          (w:MinusWidth) : 
             match(arg1(w),arg2(w)) :
-               (w1:IntWidth,w2:IntWidth) : IntWidth(width(w1) - width(w2))
-               (w1:LongWidth,w2:IntWidth) : LongWidth(minus(width(w1),to-long $ width(w2)))
-               (w1:IntWidth,w2:LongWidth) : LongWidth(minus(to-long $ width(w1), width(w2)))
                (w1:LongWidth,w2:LongWidth) : LongWidth(minus(width(w1),width(w2)))
                (w1,w2) : w
          (w:ExpWidth) : 
             match(arg1(w)) :
-               (w1:IntWidth) : LongWidth(pow(to-long(2),to-long(width(w1))) - to-long(1))
                (w1:LongWidth) : LongWidth(pow(to-long(2),width(w1)) - to-long(1))
                (w1) : w
          (w) : w
@@ -1953,7 +1943,7 @@ public defn width! (t:Type) -> Width :
    match(t) :
       (t:UIntType) : width(t)
       (t:SIntType) : width(t)
-      (t:ClockType) : IntWidth(1)
+      (t:ClockType) : LongWidth(1)
       (t) : error("No width!")
 public defn width! (e:Expression) -> Width : width!(type(e))
 
@@ -1978,8 +1968,8 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
             Connect(info(s),l,e)
          (s:Conditionally) : 
             val p = gen-constraints(pred(s))
-            add(v,WGeq(width!(type(p)),IntWidth(1)))
-            add(v,WGeq(IntWidth(1),width!(type(p))))
+            add(v,WGeq(width!(type(p)),LongWidth(1)))
+            add(v,WGeq(LongWidth(1),width!(type(p))))
             map(gen-constraints-s,Conditionally(info(s),p,conseq(s),alt(s)))
          (s) : s
 
@@ -1993,14 +1983,14 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
             match(width(e)) :
                (w:UnknownWidth) : 
                   val w* = VarWidth(firrtl-gensym(`w,width-name-hash))
-                  add(v,WGeq(w*,IntWidth(num-bits(value(e)))))
+                  add(v,WGeq(w*,LongWidth(max(1,num-bits(value(e)) - 1))))
                   UIntValue(value(e),w*)
                (w) : e
          (e:SIntValue) : 
             match(width(e)) :
                (w:UnknownWidth) : 
                   val w* = VarWidth(firrtl-gensym(`w,width-name-hash))
-                  add(v,WGeq(w*,IntWidth(1 + num-bits(value(e)))))
+                  add(v,WGeq(w*,LongWidth(num-bits(value(e)))))
                   SIntValue(value(e),w*)
                (w) : e
          (e) : e
@@ -2058,7 +2048,6 @@ defn reduce-var-widths (c:Circuit,h:HashTable<Symbol,Width>) -> Circuit :
             (w:PlusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{plus(_,_)})
             (w:MinusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{minus(_,_)})
             (w:ExpWidth) : apply(to-long(2),solve(arg1(w)),{minus(pow(_,_),to-long(1))})
-            (w:IntWidth) : to-long(width(w))
             (w:LongWidth) : width(w)
             (w) : 
                println(w)
@@ -2066,9 +2055,7 @@ defn reduce-var-widths (c:Circuit,h:HashTable<Symbol,Width>) -> Circuit :
    
       val s = solve(w)
       match(s) :
-         (s:Long) : 
-            if s > to-long(2147483647) : LongWidth(s)
-            else : IntWidth(to-int $ to-string $ s)
+         (s:Long) : LongWidth(s)
          (s) : w
 
    defn reduce-var-widths-w (w:Width) -> Width :
@@ -2348,7 +2335,6 @@ public defmethod name (b:Pad) -> String : "Pad Widths"
 ;------------ Helper Functions --------------
 defn int-width! (t:Type) -> Long :
    match(width!(t)) :
-      (w:IntWidth) : to-long(width(w))
       (w:LongWidth) : width(w)
       (w) : error("Non-int width")
 
diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza
index c0be85a4..c1a1bfd4 100644
--- a/src/main/stanza/primop.stanza
+++ b/src/main/stanza/primop.stanza
@@ -71,53 +71,53 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type :
 
    println-all-debug(["Looking at " op(e) " with inputs " args(e)])
    val w* = switch {op(e) == _} :
-      ADD-OP : PlusWidth(get-max(0,1),IntWidth(1))
-      SUB-OP : PlusWidth(get-max(0,1),IntWidth(1))
+      ADD-OP : PlusWidth(get-max(0,1),LongWidth(1))
+      SUB-OP : PlusWidth(get-max(0,1),LongWidth(1))
       MUL-OP : PlusWidth(get-max(0,1),get-max(0,1))
       DIV-OP : 
          match(type(args(e)[0]),type(args(e)[1])) :
-            (t0:UIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1))
-            (t0:SIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1))
+            (t0:UIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),LongWidth(1))
+            (t0:SIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),LongWidth(1))
             (t0,t1) : width!(args(e)[0])
       MOD-OP : 
          match(type(args(e)[0]),type(args(e)[1])) :
-            (t0:SIntType,t1:UIntType) : PlusWidth(width!(args(e)[1]),IntWidth(1))
+            (t0:SIntType,t1:UIntType) : PlusWidth(width!(args(e)[1]),LongWidth(1))
             (t0,t1) : width!(args(e)[1])
       QUO-OP : 
          match(type(args(e)[0]),type(args(e)[1])) :
-            (t0:UIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1))
-            (t0:SIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1))
+            (t0:UIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),LongWidth(1))
+            (t0:SIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),LongWidth(1))
             (t0,t1) : width!(args(e)[0])
       REM-OP : 
          match(type(args(e)[0]),type(args(e)[1])) :
-            (t0:SIntType,t1:UIntType) : PlusWidth(width!(args(e)[1]),IntWidth(1))
+            (t0:SIntType,t1:UIntType) : PlusWidth(width!(args(e)[1]),LongWidth(1))
             (t0,t1) : width!(args(e)[1])
       ADD-WRAP-OP : get-max(0,1)
       SUB-WRAP-OP : get-max(0,1)
-      LESS-OP : IntWidth(1)
-      LESS-EQ-OP : IntWidth(1)
-      GREATER-OP : IntWidth(1)
-      GREATER-EQ-OP : IntWidth(1)
-      EQUAL-OP : IntWidth(1)
-      NEQUAL-OP : IntWidth(1)
-      EQUIV-OP : IntWidth(1)
-      NEQUIV-OP : IntWidth(1)
+      LESS-OP : LongWidth(1)
+      LESS-EQ-OP : LongWidth(1)
+      GREATER-OP : LongWidth(1)
+      GREATER-EQ-OP : LongWidth(1)
+      EQUAL-OP : LongWidth(1)
+      NEQUAL-OP : LongWidth(1)
+      EQUIV-OP : LongWidth(1)
+      NEQUIV-OP : LongWidth(1)
       MUX-OP : 
-         add(v,WGeq(IntWidth(1),width!(args(e)[0])))
-         add(v,WGeq(width!(args(e)[0]),IntWidth(1)))
+         add(v,WGeq(LongWidth(1),width!(args(e)[0])))
+         add(v,WGeq(width!(args(e)[0]),LongWidth(1)))
          get-max(1,2)
-      PAD-OP : IntWidth(consts(e)[0])
+      PAD-OP : LongWidth(consts(e)[0])
       AS-UINT-OP : width!(args(e)[0])
       AS-SINT-OP : width!(args(e)[0])
-      SHIFT-LEFT-OP : PlusWidth(width!(args(e)[0]),IntWidth(consts(e)[0]))
-      SHIFT-RIGHT-OP : MinusWidth(width!(args(e)[0]),IntWidth(consts(e)[0]))
+      SHIFT-LEFT-OP : PlusWidth(width!(args(e)[0]),LongWidth(consts(e)[0]))
+      SHIFT-RIGHT-OP : MinusWidth(width!(args(e)[0]),LongWidth(consts(e)[0]))
       DYN-SHIFT-LEFT-OP : PlusWidth(width!(args(e)[0]),ExpWidth(width!(args(e)[1])))
       DYN-SHIFT-RIGHT-OP : width!(args(e)[0])
       CONVERT-OP : 
          match(type(args(e)[0])) :
-            (t0:UIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1))
+            (t0:UIntType) : PlusWidth(width!(args(e)[0]),LongWidth(1))
             (t0:SIntType) : width!(args(e)[0])
-      NEG-OP : PlusWidth(width!(args(e)[0]),IntWidth(1))
+      NEG-OP : PlusWidth(width!(args(e)[0]),LongWidth(1))
       BIT-NOT-OP : width!(args(e)[0])
       BIT-AND-OP : get-max(0,1)
       BIT-OR-OP :  get-max(0,1)
@@ -126,8 +126,8 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type :
       BIT-OR-REDUCE-OP  : all-max()
       BIT-XOR-REDUCE-OP : all-max()
       CONCAT-OP : PlusWidth(width!(args(e)[0]),width!(args(e)[1]))
-      BIT-SELECT-OP  : IntWidth(1)
-      BITS-SELECT-OP : IntWidth(consts(e)[0] - consts(e)[1] + 1)
+      BIT-SELECT-OP  : LongWidth(1)
+      BITS-SELECT-OP : LongWidth(consts(e)[0] - consts(e)[1] + 1)
 
    match(type(e)) :
       (t:UIntType) : UIntType(w*)
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 053b78e7..1223026e 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -16,7 +16,6 @@ public defmethod short-name (b:Verilog) -> String : "To Verilog"
 
 defn width! (w:Width) -> Long :
    match(w) : 
-      (w:IntWidth) : to-long(width(w))
       (w:LongWidth) : width(w)
       (w) : error("Non-supported width type.")
 
@@ -28,9 +27,6 @@ defn width! (t:Type) -> Long :
 
 defn emit (w:Width) -> String :
    match(w) : 
-      (w:IntWidth) : 
-         if width(w) >= 1 : string-join $ ["[" width(w) - 1 ":0]"] ;TODO check if need to special case 0 or 1 width wires
-         else : ""
       (w:LongWidth) : 
          if width(w) >= to-long(1) : string-join $ ["[" width(w) - to-long(1) ":0]"] ;TODO check if need to special case 0 or 1 width wires
          else : ""
@@ -41,7 +37,7 @@ defn get-width (t:Type) -> String :
    match(t) :
       (t:UIntType) : emit(width(t))
       (t:SIntType) : emit(width(t))
-      (t:ClockType) : emit(IntWidth(1))
+      (t:ClockType) : emit(LongWidth(1))
       (t) : error("Non-supported type.")
 
 defn remove-subfield (e:Expression) -> Expression :