Fixed so its length is greater than what it connects to. Changed shr to be extract, not >>

8 files changed, 31 insertions, 21 deletions

diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index e8c5cb45..9d1cd536 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -126,9 +126,9 @@ defn emit (e:Expression) -> String :
                if type(e) typeof SIntType : [emit-as-type(args(e)[0],type(e)) " >>> " emit(args(e)[1])]
                else : [emit-as-type(args(e)[0],type(e)) " >> " emit(args(e)[1])]
             SHIFT-LEFT-OP : [emit-as-type(args(e)[0],type(e)) " << " consts(e)[0]]
-            SHIFT-RIGHT-OP : 
-               if type(e) typeof SIntType : [emit-as-type(args(e)[0],type(e)) " >>> " consts(e)[0]]
-               else : [emit-as-type(args(e)[0],type(e)) " >> " consts(e)[0]]
+            SHIFT-RIGHT-OP : [emit-as-type(args(e)[0],type(e)) "[" width!(type(args(e)[0])) - to-long(1) ":" consts(e)[0] "]"]
+               ;if type(e) typeof SIntType : [emit-as-type(args(e)[0],type(e)) " >>> " consts(e)[0]]
+               ;else : [emit-as-type(args(e)[0],type(e)) " >> " consts(e)[0]]
             NEG-OP : ["-{" emit-as-type(args(e)[0],type(e)) "}"]
             CONVERT-OP : 
                match(type(args(e)[0])) :
@@ -190,6 +190,7 @@ defn emit-module (m:InModule) :
 
    val sh = get-sym-hash(m)
    val rand-value = "$rand" ;"0"
+   defn rand-string (w:Long) -> String : string-join(["{" ((w + to-long(31)) / to-long(32)) "{" rand-value "}};"])
 
    for x in vdecs do :
       val sym = key(x)
@@ -209,12 +210,13 @@ defn emit-module (m:InModule) :
             else :
                add(my-clk-update,[sym " <= " emit(cons[sym]) ";"])
             updates[get-name(clock(s))] = my-clk-update
-            add(inits,[sym " = {" width!(type(s)) "{" rand-value "}};"])
+            val w = width!(type(s))
+            add(inits,[sym " = " rand-string(w)])
          (s:DefMemory) :
             val vtype = type(s) as VectorType
             add(regs,["reg  " get-width(type(vtype)) " " sym " [0:" size(vtype) - 1 "];"])
             add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"])
-            add(inits,["  " sym "[initvar] = {" width!(type(vtype)) "{" rand-value "}};"])
+            add(inits,["  " sym "[initvar] = " rand-string(width!(type(vtype))) ])
          (s:DefNode) :
             add(wires,["wire " get-width(type(value(s))) " " sym ";"])
             add(assigns,["assign " sym " = " emit(value(s)) ";"])
@@ -235,7 +237,8 @@ defn emit-module (m:InModule) :
                      ; to make it sequential, register the index for an additional cycle
                      val index* = Ref(firrtl-gensym(name(index(s) as Ref),sh),type(index(s)))
                      add(regs,[ "reg  " get-width(type(index*)) " " name(index*) ";"]) 
-                     add(inits,[name(index*) " = {" width!(type(index*)) "{" rand-value "}};"])
+                     val w = width!(type(index*))
+                     add(inits,[name(index*) " = " rand-string(w)])
                      val my-clk-update = get?(updates,get-name(clock(mem-declaration)),Vector<Streamable>())
                      add(my-clk-update,[name(index*) " <= " emit(index(s)) ";"])
                      updates[get-name(clock(mem-declaration))] = my-clk-update
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index 70a52088..9bbdb11c 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -24,10 +24,10 @@ circuit top :
       ; CHECK: wire b{{[_$]+}}y : UInt<32>
       ; CHECK: b{{[_$]+}}x := a{{[_$]+}}0{{[_$]+}}x
       ; CHECK: node i_1 = i
-      ; CHECK: when eqv(i_1, UInt("h00000001")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x      
+      ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x      
       ; CHECK: node i_2 = i
-      ; CHECK: when eqv(i_2, UInt("h00000000")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y      
-      ; CHECK: when eqv(i_2, UInt("h00000001")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y      
+      ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y      
+      ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y      
       j := b.x
       b.y := UInt(1)
       
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
index f7b14c0f..21bbbc52 100644
--- a/test/passes/expand-whens/bundle-init.fir
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -19,8 +19,8 @@ circuit top :
 
 ; CHECK: r$x := mux(reset, w$x, a)
 ; CHECK: r$y := mux(reset, w$y, b)
-; CHECK: a := UInt("h00000001")
-; CHECK: b := UInt("h00000002")
+; CHECK: a := UInt("h1")
+; CHECK: b := UInt("h2")
 ; CHECK: w$x := b
 ; CHECK: w$y := a
       
diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir
index f8076a3e..2403816a 100644
--- a/test/passes/expand-whens/reg-dwc.fir
+++ b/test/passes/expand-whens/reg-dwc.fir
@@ -15,8 +15,8 @@ circuit top :
 ; CHECK:   module top :
 ; CHECK:     wire p : UInt
 ; CHECK:     reg r : UInt
-; CHECK:     p := UInt("h00000001")
-; CHECK:     when p : r := UInt("h00000002")
+; CHECK:     p := UInt("h1")
+; CHECK:     when p : r := UInt("h2")
 
 ; CHECK: Finished Expand Whens
 
diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir
index 0defc432..a32985b6 100644
--- a/test/passes/expand-whens/reg-dwoc.fir
+++ b/test/passes/expand-whens/reg-dwoc.fir
@@ -16,8 +16,8 @@ circuit top :
 ; CHECK:   module top :
 ; CHECK:     wire p : UInt
 ; CHECK:     reg r : UInt, clk, reset
-; CHECK:     p := UInt("h00000001")
-; CHECK:     when p : r := mux(reset, UInt("h00000001"), UInt("h00000002"))
+; CHECK:     p := UInt("h1")
+; CHECK:     when p : r := mux(reset, UInt("h1"), UInt("h2"))
 
 ; CHECK: Finished Expand Whens
 
diff --git a/test/passes/expand-whens/wacc-wdc.fir b/test/passes/expand-whens/wacc-wdc.fir
index 127e10ed..001f2f25 100644
--- a/test/passes/expand-whens/wacc-wdc.fir
+++ b/test/passes/expand-whens/wacc-wdc.fir
@@ -15,9 +15,9 @@ circuit top :
 ; CHECK:   module top :
 ; CHECK:     wire p : UInt
 ; CHECK:     cmem m : UInt<4>[10], clk
-; CHECK:     write accessor a = m[UInt("h00000003")]
-; CHECK:     p := UInt("h00000001")
-; CHECK:     when p : a := UInt("h00000002")
+; CHECK:     write accessor a = m[UInt("h3")]
+; CHECK:     p := UInt("h1")
+; CHECK:     when p : a := UInt("h2")
 
 ; CHECK: Finished Expand Whens
 
diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir
index f3bfa522..98e48c0c 100644
--- a/test/passes/infer-types/bundle.fir
+++ b/test/passes/infer-types/bundle.fir
@@ -20,10 +20,10 @@ circuit top :
       a[8] := UInt(1)
       a[9] := UInt(1)
       node b = a[2]           ;CHECK: node b = a@<t:UInt<3>[10]@<t:UInt>>[2]@<t:UInt>
-      read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h00000003")]
+      read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h3")]
 ; CHECK: Finished Infer Types
 ; CHECK: Resolve Genders 
-; CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h00000003")]   
+; CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h3")]   
 ; CHECK: Finished Resolve Genders 
 
 
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index 45c88a43..94f481f7 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p ct 2>&1 | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Types
 circuit top :
@@ -9,6 +9,12 @@ circuit top :
       wire d : SInt<8>
       wire e : UInt<1>
 
+      a := UInt(1)
+      b := UInt(1)
+      c := SInt(1)
+      d := SInt(1)
+      e := UInt(1)
+
       node vadd = add(a, c)    ;CHECK: node vadd = add(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wadd = add(a, b) ;CHECK: node wadd = add(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xadd = add(a, d) ;CHECK: node xadd = add(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
@@ -139,6 +145,7 @@ circuit top :
       node wshr = shr(a, 10) ;CHECK: node wshr = shr(a@<t:UInt>, 10)@<t:UInt>
       node zshr = shr(c, 10) ;CHECK: node zshr = shr(c@<t:SInt>, 10)@<t:SInt>
    
+
       node vcvt = cvt(a)   ;CHECK: node vcvt = cvt(a@<t:UInt>)@<t:SInt>
       node wcvt = cvt(a) ;CHECK: node wcvt = cvt(a@<t:UInt>)@<t:SInt>
       node zcvt = cvt(c) ;CHECK: node zcvt = cvt(c@<t:SInt>)@<t:SInt>