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| author | azidar | 2015-08-24 11:47:47 -0700 |
|---|---|---|
| committer | azidar | 2015-08-24 11:47:47 -0700 |
| commit | 6cd96b6315c32bbf6c4ace28197ff1d4be86a129 (patch) | |
| tree | 495655134143e14f655d7d9f1164ae72833c8aa1 | |
| parent | b2be9c1bec800422581e208b22be9dffd6d0d5f1 (diff) | |
Temporarily deprecated the flo backend until I fix it
| -rw-r--r-- | src/main/stanza/firrtl-test-main.stanza | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza index 77365d12..cc60f0cc 100644 --- a/src/main/stanza/firrtl-test-main.stanza +++ b/src/main/stanza/firrtl-test-main.stanza @@ -129,7 +129,8 @@ defn main () : run-passes(circuit*,get-passes(to-list(pass-names))) else : switch {_ == compiler} : - "flo" : run-passes(circuit*,StandardFlo(with-output)) + "flo" : error("Flo backend not currently supported.") + ; run-passes(circuit*,StandardFlo(with-output)) "verilog" : run-passes(circuit*,StandardVerilog(with-output)) "verilute" : run-passes(circuit*,InstrumentedVerilog(with-output,to-list $ pass-args)) else : error("Invalid compiler flag") |