diff options
| author | azidar | 2015-08-26 15:02:26 -0700 |
|---|---|---|
| committer | azidar | 2015-08-26 15:07:53 -0700 |
| commit | a9b33b97892abaea65f5ffda50f2b170122ce335 (patch) | |
| tree | bb7e079d69766943a9343ea9ca7c60d8d5a14e88 | |
| parent | 3d0ed2091a4b0028593a4d9dcb293303d03546e1 (diff) | |
Added regression test
| -rw-r--r-- | .gitignore | 3 | ||||
| -rw-r--r-- | Makefile | 6 | ||||
| -rw-r--r-- | regress/rocket.fir | 32895 |
3 files changed, 32903 insertions, 1 deletions
@@ -7,6 +7,9 @@ */*.swp */*/*.swp */*/*/*.swp +*/*.flo +*/*.v +*/*.out */*/*.flo */*/*.v */*/*.out @@ -3,6 +3,7 @@ root_dir ?= $(PWD) test_dir ?= $(root_dir)/test +regress_dir ?= $(root_dir)/regress firrtl_dir ?= $(root_dir)/src/main/stanza all-noise: @@ -30,6 +31,9 @@ build-fast: check: cd $(test_dir) && lit -v . --path=$(root_dir)/utils/bin/ +regress: + cd $(regress_dir) && firrtl -i rocket.fir -o rocket.v -X verilog + passes: cd $(test_dir)/passes && lit -v . --path=$(root_dir)/utils/bin/ @@ -62,4 +66,4 @@ done: build check fail: say "fail" -.PHONY: all install build-deploy build check clean fail succeed +.PHONY: all install build-deploy build check clean fail succeed regress diff --git a/regress/rocket.fir b/regress/rocket.fir new file mode 100644 index 00000000..242ca041 --- /dev/null +++ b/regress/rocket.fir @@ -0,0 +1,32895 @@ +circuit Top : + module HTIF : + output scr : {flip rdata : UInt<64>[64], wen : UInt<1>, waddr : UInt<6>, wdata : UInt<64>} + output mem_1 : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input cpu : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}[1] + output host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>} + input clock : Clock + input reset : UInt<1> + + scr.wdata := UInt<1>("h00") + scr.waddr := UInt<1>("h00") + scr.wen := UInt<1>("h00") + mem_1.grant.ready := UInt<1>("h00") + mem_1.acquire.bits.union := UInt<1>("h00") + mem_1.acquire.bits.a_type := UInt<1>("h00") + mem_1.acquire.bits.is_builtin_type := UInt<1>("h00") + mem_1.acquire.bits.data := UInt<1>("h00") + mem_1.acquire.bits.addr_beat := UInt<1>("h00") + mem_1.acquire.bits.client_xact_id := UInt<1>("h00") + mem_1.acquire.bits.addr_block := UInt<1>("h00") + mem_1.acquire.valid := UInt<1>("h00") + cpu[0].ipi_rep.bits := UInt<1>("h00") + cpu[0].ipi_rep.valid := UInt<1>("h00") + cpu[0].ipi_req.ready := UInt<1>("h00") + cpu[0].pcr_rep.ready := UInt<1>("h00") + cpu[0].pcr_req.bits.data := UInt<1>("h00") + cpu[0].pcr_req.bits.addr := UInt<1>("h00") + cpu[0].pcr_req.bits.rw := UInt<1>("h00") + cpu[0].pcr_req.valid := UInt<1>("h00") + cpu[0].id := UInt<1>("h00") + cpu[0].reset := UInt<1>("h00") + host.debug_stats_pcr := UInt<1>("h00") + host.out.bits := UInt<1>("h00") + host.out.valid := UInt<1>("h00") + host.in.ready := UInt<1>("h00") + host.clk_edge := UInt<1>("h00") + host.clk := UInt<1>("h00") + host.debug_stats_pcr := cpu[0].debug_stats_pcr + reg rx_count : UInt<15>, clock, reset + onreset rx_count := UInt<15>("h00") + reg rx_shifter : UInt<64>, clock, reset + node T_804 = bits(rx_shifter, 63, 16) + node rx_shifter_in = cat(host.in.bits, T_804) + node next_cmd = bits(rx_shifter_in, 3, 0) + reg cmd : UInt<?>, clock, reset + reg size : UInt<?>, clock, reset + reg pos : UInt<?>, clock, reset + reg seqno : UInt<?>, clock, reset + reg addr : UInt<?>, clock, reset + node T_817 = and(host.in.valid, host.in.ready) + when T_817 : + rx_shifter := rx_shifter_in + node T_819 = addw(rx_count, UInt<1>("h01")) + rx_count := T_819 + node T_821 = eq(rx_count, UInt<2>("h03")) + when T_821 : + cmd := next_cmd + node T_822 = bits(rx_shifter_in, 15, 4) + size := T_822 + node T_823 = bits(rx_shifter_in, 15, 7) + pos := T_823 + node T_824 = bits(rx_shifter_in, 23, 16) + seqno := T_824 + node T_825 = bits(rx_shifter_in, 63, 24) + addr := T_825 + skip + skip + node rx_word_count = shr(rx_count, 2) + node T_827 = bits(rx_count, 1, 0) + node T_828 = not(T_827) + node T_830 = eq(T_828, UInt<1>("h00")) + node rx_word_done = and(host.in.valid, T_830) + cmem packet_ram : UInt<64>[8], clock + node T_835 = and(rx_word_done, host.in.ready) + when T_835 : + node T_836 = bits(rx_word_count, 2, 0) + node T_838 = subw(T_836, UInt<1>("h01")) + infer accessor T_839 = packet_ram[T_838] + T_839 := rx_shifter_in + skip + node pcr_addr = bits(addr, 11, 0) + node pcr_coreid = bits(addr, 21, 20) + infer accessor pcr_wdata = packet_ram[UInt<1>("h00")] + node T_851 = bits(size, 2, 0) + node T_853 = neq(T_851, UInt<1>("h00")) + node T_854 = bits(addr, 2, 0) + node T_856 = neq(T_854, UInt<1>("h00")) + node bad_mem_packet = or(T_853, T_856) + node T_858 = eq(cmd, UInt<1>("h00")) + node T_859 = eq(cmd, UInt<1>("h01")) + node T_860 = or(T_858, T_859) + node T_861 = eq(cmd, UInt<2>("h02")) + node T_862 = eq(cmd, UInt<2>("h03")) + node T_863 = or(T_861, T_862) + node T_865 = neq(size, UInt<1>("h01")) + node T_867 = mux(T_863, T_865, UInt<1>("h01")) + node nack = mux(T_860, bad_mem_packet, T_867) + reg tx_count : UInt<15>, clock, reset + onreset tx_count := UInt<15>("h00") + node tx_subword_count = bits(tx_count, 1, 0) + node tx_word_count = bits(tx_count, 14, 2) + node T_873 = bits(tx_word_count, 2, 0) + node packet_ram_raddr = subw(T_873, UInt<1>("h01")) + node T_876 = and(host.out.valid, host.out.ready) + when T_876 : + node T_878 = addw(tx_count, UInt<1>("h01")) + tx_count := T_878 + skip + node T_880 = eq(rx_word_count, UInt<1>("h00")) + node T_881 = neq(next_cmd, UInt<1>("h01")) + node T_882 = neq(next_cmd, UInt<2>("h03")) + node T_883 = and(T_881, T_882) + node T_884 = eq(rx_word_count, size) + node T_885 = bits(rx_word_count, 2, 0) + node T_887 = eq(T_885, UInt<1>("h00")) + node T_888 = or(T_884, T_887) + node T_889 = mux(T_880, T_883, T_888) + node rx_done = and(rx_word_done, T_889) + node T_892 = eq(nack, UInt<1>("h00")) + node T_893 = eq(cmd, UInt<1>("h00")) + node T_894 = eq(cmd, UInt<2>("h02")) + node T_895 = or(T_893, T_894) + node T_896 = eq(cmd, UInt<2>("h03")) + node T_897 = or(T_895, T_896) + node T_898 = and(T_892, T_897) + node tx_size = mux(T_898, size, UInt<1>("h00")) + node T_901 = not(tx_subword_count) + node T_903 = eq(T_901, UInt<1>("h00")) + node T_904 = and(host.out.ready, T_903) + node T_905 = eq(tx_word_count, tx_size) + node T_907 = gt(tx_word_count, UInt<1>("h00")) + node T_908 = not(packet_ram_raddr) + node T_910 = eq(T_908, UInt<1>("h00")) + node T_911 = and(T_907, T_910) + node T_912 = or(T_905, T_911) + node tx_done = and(T_904, T_912) + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + node T_924 = eq(state, UInt<3>("h04")) + node T_925 = and(T_924, mem_1.acquire.ready) + node T_926 = eq(state, UInt<3>("h05")) + node T_927 = and(T_926, mem_1.grant.valid) + node T_928 = or(T_925, T_927) + reg cnt : UInt<2>, clock, reset + onreset cnt := UInt<2>("h00") + when T_928 : + node T_932 = eq(cnt, UInt<2>("h03")) + node T_934 = and(UInt<1>("h00"), T_932) + node T_937 = addw(cnt, UInt<1>("h01")) + node T_938 = mux(T_934, UInt<1>("h00"), T_937) + cnt := T_938 + skip + node cnt_done = and(T_928, T_932) + node T_941 = eq(rx_word_count, UInt<1>("h00")) + node rx_cmd = mux(T_941, next_cmd, cmd) + node T_943 = eq(state, UInt<1>("h00")) + node T_944 = and(T_943, rx_done) + when T_944 : + node T_945 = eq(rx_cmd, UInt<1>("h00")) + node T_946 = eq(rx_cmd, UInt<1>("h01")) + node T_947 = eq(rx_cmd, UInt<2>("h02")) + node T_948 = eq(rx_cmd, UInt<2>("h03")) + node T_949 = or(T_947, T_948) + node T_950 = mux(T_949, UInt<1>("h01"), UInt<3>("h07")) + node T_951 = mux(T_946, UInt<3>("h04"), T_950) + node T_952 = mux(T_945, UInt<2>("h03"), T_951) + state := T_952 + skip + node T_953 = eq(state, UInt<3>("h04")) + when T_953 : + when cnt_done : + state := UInt<3>("h06") + skip + skip + node T_954 = eq(state, UInt<2>("h03")) + when T_954 : + when mem_1.acquire.ready : + state := UInt<3>("h05") + skip + skip + node T_955 = eq(state, UInt<3>("h06")) + node T_956 = and(T_955, mem_1.grant.valid) + when T_956 : + node T_957 = eq(cmd, UInt<1>("h00")) + node T_959 = eq(pos, UInt<1>("h01")) + node T_960 = or(T_957, T_959) + node T_961 = mux(T_960, UInt<3>("h07"), UInt<1>("h00")) + state := T_961 + node T_963 = subw(pos, UInt<1>("h01")) + pos := T_963 + node T_965 = addw(addr, UInt<4>("h08")) + addr := T_965 + skip + node T_966 = eq(state, UInt<3>("h05")) + node T_967 = and(T_966, cnt_done) + when T_967 : + node T_968 = eq(cmd, UInt<1>("h00")) + node T_970 = eq(pos, UInt<1>("h01")) + node T_971 = or(T_968, T_970) + node T_972 = mux(T_971, UInt<3>("h07"), UInt<1>("h00")) + state := T_972 + node T_974 = subw(pos, UInt<1>("h01")) + pos := T_974 + node T_976 = addw(addr, UInt<4>("h08")) + addr := T_976 + skip + node T_977 = eq(state, UInt<3>("h07")) + node T_978 = and(T_977, tx_done) + when T_978 : + node T_979 = eq(tx_word_count, tx_size) + when T_979 : + rx_count := UInt<1>("h00") + tx_count := UInt<1>("h00") + skip + node T_982 = eq(cmd, UInt<1>("h00")) + node T_984 = neq(pos, UInt<1>("h00")) + node T_985 = and(T_982, T_984) + node T_986 = mux(T_985, UInt<2>("h03"), UInt<1>("h00")) + state := T_986 + skip + node T_988 = eq(state, UInt<3>("h05")) + node T_989 = and(T_988, mem_1.grant.valid) + when T_989 : + node T_990 = cat(mem_1.grant.bits.addr_beat, UInt<1>("h00")) + infer accessor T_991 = packet_ram[T_990] + node T_992 = bits(mem_1.grant.bits.data, 63, 0) + T_991 := T_992 + skip + node T_993 = cat(cnt, UInt<1>("h00")) + infer accessor T_994 = packet_ram[T_993] + node T_996 = eq(state, UInt<3>("h05")) + node T_997 = and(T_996, mem_1.grant.valid) + when T_997 : + node T_998 = cat(mem_1.grant.bits.addr_beat, UInt<1>("h01")) + infer accessor T_999 = packet_ram[T_998] + node T_1000 = bits(mem_1.grant.bits.data, 127, 64) + T_999 := T_1000 + skip + node T_1001 = cat(cnt, UInt<1>("h01")) + infer accessor T_1002 = packet_ram[T_1001] + node mem_req_data = cat(T_1002, T_994) + node init_addr = shr(addr, 3) + node T_1005 = eq(state, UInt<2>("h03")) + node T_1006 = eq(state, UInt<3>("h04")) + node T_1007 = or(T_1005, T_1006) + mem_1.acquire.valid := T_1007 + node T_1008 = eq(cmd, UInt<1>("h01")) + node T_1045 = asUInt(asSInt(UInt<16>("h0ffff"))) + node T_1046 = cat(T_1045, UInt<1>("h01")) + wire T_1078 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} + T_1078.union := UInt<1>("h00") + T_1078.a_type := UInt<1>("h00") + T_1078.is_builtin_type := UInt<1>("h00") + T_1078.data := UInt<1>("h00") + T_1078.addr_beat := UInt<1>("h00") + T_1078.client_xact_id := UInt<1>("h00") + T_1078.addr_block := UInt<1>("h00") + T_1078.is_builtin_type := UInt<1>("h01") + T_1078.a_type := UInt<3>("h03") + T_1078.client_xact_id := UInt<1>("h00") + T_1078.addr_block := init_addr + T_1078.addr_beat := cnt + T_1078.data := mem_req_data + T_1078.union := T_1046 + node T_1120 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1121 = cat(UInt<3>("h07"), T_1120) + wire T_1155 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} + T_1155.union := UInt<1>("h00") + T_1155.a_type := UInt<1>("h00") + T_1155.is_builtin_type := UInt<1>("h00") + T_1155.data := UInt<1>("h00") + T_1155.addr_beat := UInt<1>("h00") + T_1155.client_xact_id := UInt<1>("h00") + T_1155.addr_block := UInt<1>("h00") + T_1155.is_builtin_type := UInt<1>("h01") + T_1155.a_type := UInt<3>("h01") + T_1155.client_xact_id := UInt<1>("h00") + T_1155.addr_block := init_addr + T_1155.addr_beat := UInt<1>("h00") + T_1155.data := UInt<1>("h00") + T_1155.union := T_1121 + wire T_1224 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} + T_1224 <> T_1155 + when T_1008 : + T_1224 <> T_1078 + skip + mem_1.acquire.bits <> T_1224 + mem_1.grant.ready := UInt<1>("h01") + reg rtc : UInt<64>, clock, reset + onreset rtc := UInt<64>("h00") + reg T_1259 : UInt<7>, clock, reset + onreset T_1259 := UInt<7>("h00") + node rtc_tick = eq(T_1259, UInt<7>("h063")) + node T_1263 = and(UInt<1>("h01"), rtc_tick) + node T_1266 = addw(T_1259, UInt<1>("h01")) + node T_1267 = mux(T_1263, UInt<1>("h00"), T_1266) + T_1259 := T_1267 + when rtc_tick : + node T_1269 = addw(rtc, UInt<1>("h01")) + rtc := T_1269 + skip + reg pcrReadData : UInt<64>, clock, reset + reg T_1273 : UInt<1>, clock, reset + onreset T_1273 := UInt<1>("h01") + reg T_1275 : UInt<1>, clock, reset + onreset T_1275 := UInt<1>("h00") + node T_1277 = eq(pcr_coreid, UInt<1>("h00")) + node T_1278 = eq(state, UInt<1>("h01")) + node T_1279 = and(T_1278, T_1277) + node T_1281 = neq(pcr_addr, UInt<11>("h0782")) + node T_1282 = and(T_1279, T_1281) + cpu[0].pcr_req.valid := T_1282 + node T_1283 = eq(cmd, UInt<2>("h03")) + cpu[0].pcr_req.bits.rw := T_1283 + cpu[0].pcr_req.bits.addr := pcr_addr + cpu[0].pcr_req.bits.data := pcr_wdata + cpu[0].reset := T_1273 + reg T_1285 : UInt<1>, clock, reset + onreset T_1285 := UInt<1>("h00") + reg T_1287 : UInt<1>, clock, reset + onreset T_1287 := UInt<1>("h00") + when rtc_tick : + T_1285 := UInt<1>("h00") + skip + when cpu[0].pcr_rep.valid : + T_1287 := UInt<1>("h00") + skip + when T_1287 : + cpu[0].pcr_req.valid := UInt<1>("h00") + skip + node T_1291 = neq(state, UInt<1>("h01")) + node T_1292 = neq(state, UInt<2>("h02")) + node T_1293 = and(T_1291, T_1292) + node T_1295 = eq(T_1285, UInt<1>("h00")) + node T_1296 = and(T_1293, T_1295) + node T_1298 = eq(T_1287, UInt<1>("h00")) + node T_1299 = and(T_1296, T_1298) + when T_1299 : + cpu[0].pcr_req.valid := UInt<1>("h01") + cpu[0].pcr_req.bits.rw := UInt<1>("h01") + cpu[0].pcr_req.bits.addr := UInt<11>("h0782") + cpu[0].pcr_req.bits.data := rtc + T_1285 := cpu[0].pcr_req.ready + T_1287 := cpu[0].pcr_req.ready + skip + when cpu[0].ipi_rep.ready : + T_1275 := UInt<1>("h00") + skip + cpu[0].ipi_rep.valid := T_1275 + cpu[0].ipi_req.ready := UInt<1>("h01") + node T_1306 = eq(cpu[0].ipi_req.bits, UInt<1>("h00")) + node T_1307 = and(cpu[0].ipi_req.valid, T_1306) + when T_1307 : + T_1275 := UInt<1>("h01") + skip + node T_1309 = eq(state, UInt<1>("h01")) + node T_1310 = and(cpu[0].pcr_req.ready, cpu[0].pcr_req.valid) + node T_1311 = and(T_1309, T_1310) + when T_1311 : + state := UInt<2>("h02") + skip + node T_1312 = eq(state, UInt<1>("h01")) + node T_1313 = and(T_1312, T_1277) + node T_1315 = eq(pcr_addr, UInt<11>("h0782")) + node T_1316 = and(T_1313, T_1315) + when T_1316 : + node T_1317 = eq(cmd, UInt<2>("h03")) + when T_1317 : + node T_1318 = bit(pcr_wdata, 0) + T_1273 := T_1318 + skip + pcrReadData := T_1273 + state := UInt<3>("h07") + skip + cpu[0].pcr_rep.ready := UInt<1>("h01") + node T_1320 = eq(state, UInt<2>("h02")) + node T_1321 = and(T_1320, cpu[0].pcr_rep.valid) + when T_1321 : + pcrReadData := cpu[0].pcr_rep.bits + state := UInt<3>("h07") + skip + node scr_addr = bits(addr, 5, 0) + wire scr_rdata : UInt<64>[64] + scr_rdata[0] := UInt<1>("h00") + scr_rdata[1] := UInt<1>("h00") + scr_rdata[2] := UInt<1>("h00") + scr_rdata[3] := UInt<1>("h00") + scr_rdata[4] := UInt<1>("h00") + scr_rdata[5] := UInt<1>("h00") + scr_rdata[6] := UInt<1>("h00") + scr_rdata[7] := UInt<1>("h00") + scr_rdata[8] := UInt<1>("h00") + scr_rdata[9] := UInt<1>("h00") + scr_rdata[10] := UInt<1>("h00") + scr_rdata[11] := UInt<1>("h00") + scr_rdata[12] := UInt<1>("h00") + scr_rdata[13] := UInt<1>("h00") + scr_rdata[14] := UInt<1>("h00") + scr_rdata[15] := UInt<1>("h00") + scr_rdata[16] := UInt<1>("h00") + scr_rdata[17] := UInt<1>("h00") + scr_rdata[18] := UInt<1>("h00") + scr_rdata[19] := UInt<1>("h00") + scr_rdata[20] := UInt<1>("h00") + scr_rdata[21] := UInt<1>("h00") + scr_rdata[22] := UInt<1>("h00") + scr_rdata[23] := UInt<1>("h00") + scr_rdata[24] := UInt<1>("h00") + scr_rdata[25] := UInt<1>("h00") + scr_rdata[26] := UInt<1>("h00") + scr_rdata[27] := UInt<1>("h00") + scr_rdata[28] := UInt<1>("h00") + scr_rdata[29] := UInt<1>("h00") + scr_rdata[30] := UInt<1>("h00") + scr_rdata[31] := UInt<1>("h00") + scr_rdata[32] := UInt<1>("h00") + scr_rdata[33] := UInt<1>("h00") + scr_rdata[34] := UInt<1>("h00") + scr_rdata[35] := UInt<1>("h00") + scr_rdata[36] := UInt<1>("h00") + scr_rdata[37] := UInt<1>("h00") + scr_rdata[38] := UInt<1>("h00") + scr_rdata[39] := UInt<1>("h00") + scr_rdata[40] := UInt<1>("h00") + scr_rdata[41] := UInt<1>("h00") + scr_rdata[42] := UInt<1>("h00") + scr_rdata[43] := UInt<1>("h00") + scr_rdata[44] := UInt<1>("h00") + scr_rdata[45] := UInt<1>("h00") + scr_rdata[46] := UInt<1>("h00") + scr_rdata[47] := UInt<1>("h00") + scr_rdata[48] := UInt<1>("h00") + scr_rdata[49] := UInt<1>("h00") + scr_rdata[50] := UInt<1>("h00") + scr_rdata[51] := UInt<1>("h00") + scr_rdata[52] := UInt<1>("h00") + scr_rdata[53] := UInt<1>("h00") + scr_rdata[54] := UInt<1>("h00") + scr_rdata[55] := UInt<1>("h00") + scr_rdata[56] := UInt<1>("h00") + scr_rdata[57] := UInt<1>("h00") + scr_rdata[58] := UInt<1>("h00") + scr_rdata[59] := UInt<1>("h00") + scr_rdata[60] := UInt<1>("h00") + scr_rdata[61] := UInt<1>("h00") + scr_rdata[62] := UInt<1>("h00") + scr_rdata[63] := UInt<1>("h00") + scr_rdata[0] := scr.rdata[0] + scr_rdata[1] := scr.rdata[1] + scr_rdata[2] := scr.rdata[2] + scr_rdata[3] := scr.rdata[3] + scr_rdata[4] := scr.rdata[4] + scr_rdata[5] := scr.rdata[5] + scr_rdata[6] := scr.rdata[6] + scr_rdata[7] := scr.rdata[7] + scr_rdata[8] := scr.rdata[8] + scr_rdata[9] := scr.rdata[9] + scr_rdata[10] := scr.rdata[10] + scr_rdata[11] := scr.rdata[11] + scr_rdata[12] := scr.rdata[12] + scr_rdata[13] := scr.rdata[13] + scr_rdata[14] := scr.rdata[14] + scr_rdata[15] := scr.rdata[15] + scr_rdata[16] := scr.rdata[16] + scr_rdata[17] := scr.rdata[17] + scr_rdata[18] := scr.rdata[18] + scr_rdata[19] := scr.rdata[19] + scr_rdata[20] := scr.rdata[20] + scr_rdata[21] := scr.rdata[21] + scr_rdata[22] := scr.rdata[22] + scr_rdata[23] := scr.rdata[23] + scr_rdata[24] := scr.rdata[24] + scr_rdata[25] := scr.rdata[25] + scr_rdata[26] := scr.rdata[26] + scr_rdata[27] := scr.rdata[27] + scr_rdata[28] := scr.rdata[28] + scr_rdata[29] := scr.rdata[29] + scr_rdata[30] := scr.rdata[30] + scr_rdata[31] := scr.rdata[31] + scr_rdata[32] := scr.rdata[32] + scr_rdata[33] := scr.rdata[33] + scr_rdata[34] := scr.rdata[34] + scr_rdata[35] := scr.rdata[35] + scr_rdata[36] := scr.rdata[36] + scr_rdata[37] := scr.rdata[37] + scr_rdata[38] := scr.rdata[38] + scr_rdata[39] := scr.rdata[39] + scr_rdata[40] := scr.rdata[40] + scr_rdata[41] := scr.rdata[41] + scr_rdata[42] := scr.rdata[42] + scr_rdata[43] := scr.rdata[43] + scr_rdata[44] := scr.rdata[44] + scr_rdata[45] := scr.rdata[45] + scr_rdata[46] := scr.rdata[46] + scr_rdata[47] := scr.rdata[47] + scr_rdata[48] := scr.rdata[48] + scr_rdata[49] := scr.rdata[49] + scr_rdata[50] := scr.rdata[50] + scr_rdata[51] := scr.rdata[51] + scr_rdata[52] := scr.rdata[52] + scr_rdata[53] := scr.rdata[53] + scr_rdata[54] := scr.rdata[54] + scr_rdata[55] := scr.rdata[55] + scr_rdata[56] := scr.rdata[56] + scr_rdata[57] := scr.rdata[57] + scr_rdata[58] := scr.rdata[58] + scr_rdata[59] := scr.rdata[59] + scr_rdata[60] := scr.rdata[60] + scr_rdata[61] := scr.rdata[61] + scr_rdata[62] := scr.rdata[62] + scr_rdata[63] := scr.rdata[63] + scr_rdata[0] := UInt<1>("h01") + scr_rdata[1] := UInt<13>("h01000") + scr.wen := UInt<1>("h00") + scr.wdata := pcr_wdata + scr.waddr := scr_addr + node T_1526 = eq(state, UInt<1>("h01")) + node T_1527 = not(pcr_coreid) + node T_1529 = eq(T_1527, UInt<1>("h00")) + node T_1530 = and(T_1526, T_1529) + when T_1530 : + node T_1531 = eq(cmd, UInt<2>("h03")) + scr.wen := T_1531 + infer accessor T_1532 = scr_rdata[scr_addr] + pcrReadData := T_1532 + state := UInt<3>("h07") + skip + node tx_cmd = mux(nack, UInt<3>("h05"), UInt<3>("h04")) + node tx_cmd_ext = cat(UInt<1>("h00"), tx_cmd) + node T_1536 = cat(addr, seqno) + node T_1537 = cat(tx_size, tx_cmd_ext) + node tx_header = cat(T_1536, T_1537) + node T_1540 = eq(tx_word_count, UInt<1>("h00")) + node T_1541 = eq(cmd, UInt<2>("h02")) + node T_1542 = eq(cmd, UInt<2>("h03")) + node T_1543 = or(T_1541, T_1542) + infer accessor T_1544 = packet_ram[packet_ram_raddr] + node T_1545 = mux(T_1543, pcrReadData, T_1544) + node tx_data = mux(T_1540, tx_header, T_1545) + node T_1547 = eq(state, UInt<1>("h00")) + host.in.ready := T_1547 + node T_1548 = eq(state, UInt<3>("h07")) + host.out.valid := T_1548 + node T_1549 = bits(tx_count, 1, 0) + node T_1551 = cat(T_1549, UInt<4>("h00")) + node T_1552 = dshr(tx_data, T_1551) + host.out.bits := T_1552 + + module ClientTileLinkIOWrapper : + output out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + input in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input clock : Clock + input reset : UInt<1> + + out.release.bits.voluntary := UInt<1>("h00") + out.release.bits.r_type := UInt<1>("h00") + out.release.bits.data := UInt<1>("h00") + out.release.bits.addr_beat := UInt<1>("h00") + out.release.bits.client_xact_id := UInt<1>("h00") + out.release.bits.addr_block := UInt<1>("h00") + out.release.valid := UInt<1>("h00") + out.probe.ready := UInt<1>("h00") + out.grant.ready := UInt<1>("h00") + out.acquire.bits.union := UInt<1>("h00") + out.acquire.bits.a_type := UInt<1>("h00") + out.acquire.bits.is_builtin_type := UInt<1>("h00") + out.acquire.bits.data := UInt<1>("h00") + out.acquire.bits.addr_beat := UInt<1>("h00") + out.acquire.bits.client_xact_id := UInt<1>("h00") + out.acquire.bits.addr_block := UInt<1>("h00") + out.acquire.valid := UInt<1>("h00") + in.grant.bits.g_type := UInt<1>("h00") + in.grant.bits.is_builtin_type := UInt<1>("h00") + in.grant.bits.manager_xact_id := UInt<1>("h00") + in.grant.bits.client_xact_id := UInt<1>("h00") + in.grant.bits.data := UInt<1>("h00") + in.grant.bits.addr_beat := UInt<1>("h00") + in.grant.valid := UInt<1>("h00") + in.acquire.ready := UInt<1>("h00") + out.acquire <> in.acquire + in.grant <> out.grant + out.probe.ready := UInt<1>("h01") + out.release.valid := UInt<1>("h00") + + module FinishQueue : + output count : UInt<2> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.dst := UInt<1>("h00") + deq.bits.fin.manager_xact_id := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem T_463 : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}[2], clock + reg T_465 : UInt<1>, clock, reset + onreset T_465 := UInt<1>("h00") + reg T_467 : UInt<1>, clock, reset + onreset T_467 := UInt<1>("h00") + reg T_469 : UInt<1>, clock, reset + onreset T_469 := UInt<1>("h00") + node T_470 = eq(T_465, T_467) + node T_472 = eq(T_469, UInt<1>("h00")) + node T_473 = and(T_470, T_472) + node T_474 = and(T_470, T_469) + node T_476 = and(UInt<1>("h00"), T_473) + node T_477 = and(T_476, deq.ready) + node T_478 = and(enq.ready, enq.valid) + node T_480 = eq(T_477, UInt<1>("h00")) + node T_481 = and(T_478, T_480) + node T_482 = and(deq.ready, deq.valid) + node T_484 = eq(T_477, UInt<1>("h00")) + node T_485 = and(T_482, T_484) + when T_481 : + infer accessor T_486 = T_463[T_465] + T_486 <> enq.bits + node T_537 = eq(T_465, UInt<1>("h01")) + node T_539 = and(UInt<1>("h00"), T_537) + node T_542 = addw(T_465, UInt<1>("h01")) + node T_543 = mux(T_539, UInt<1>("h00"), T_542) + T_465 := T_543 + skip + when T_485 : + node T_545 = eq(T_467, UInt<1>("h01")) + node T_547 = and(UInt<1>("h00"), T_545) + node T_550 = addw(T_467, UInt<1>("h01")) + node T_551 = mux(T_547, UInt<1>("h00"), T_550) + T_467 := T_551 + skip + node T_552 = neq(T_481, T_485) + when T_552 : + T_469 := T_481 + skip + node T_554 = eq(T_473, UInt<1>("h00")) + node T_556 = and(UInt<1>("h00"), enq.valid) + node T_557 = or(T_554, T_556) + deq.valid := T_557 + node T_559 = eq(T_474, UInt<1>("h00")) + node T_561 = and(UInt<1>("h00"), deq.ready) + node T_562 = or(T_559, T_561) + enq.ready := T_562 + infer accessor T_563 = T_463[T_467] + wire T_663 : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>} + T_663 <> T_563 + when T_476 : + T_663 <> enq.bits + skip + deq.bits <> T_663 + node T_713 = subw(T_465, T_467) + node T_714 = and(T_469, T_470) + node T_715 = cat(T_714, T_713) + count := T_715 + + module FinishUnit : + output ready : UInt<1> + output finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} + output refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} + input grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input clock : Clock + input reset : UInt<1> + + ready := UInt<1>("h00") + finish.bits.payload.manager_xact_id := UInt<1>("h00") + finish.bits.header.dst := UInt<1>("h00") + finish.bits.header.src := UInt<1>("h00") + finish.valid := UInt<1>("h00") + refill.bits.g_type := UInt<1>("h00") + refill.bits.is_builtin_type := UInt<1>("h00") + refill.bits.manager_xact_id := UInt<1>("h00") + refill.bits.client_xact_id := UInt<1>("h00") + refill.bits.data := UInt<1>("h00") + refill.bits.addr_beat := UInt<1>("h00") + refill.valid := UInt<1>("h00") + grant.ready := UInt<1>("h00") + node T_441 = and(grant.ready, grant.valid) + wire T_446 : UInt<3>[1] + T_446[0] := UInt<3>("h05") + node T_449 = eq(T_446[0], grant.bits.payload.g_type) + node T_451 = or(UInt<1>("h00"), T_449) + wire T_453 : UInt<1>[2] + T_453[0] := UInt<1>("h00") + T_453[1] := UInt<1>("h01") + node T_457 = eq(T_453[0], grant.bits.payload.g_type) + node T_458 = eq(T_453[1], grant.bits.payload.g_type) + node T_460 = or(UInt<1>("h00"), T_457) + node T_461 = or(T_460, T_458) + node T_462 = mux(grant.bits.payload.is_builtin_type, T_451, T_461) + node T_463 = and(UInt<1>("h01"), T_462) + node T_464 = and(T_441, T_463) + reg T_466 : UInt<2>, clock, reset + onreset T_466 := UInt<2>("h00") + when T_464 : + node T_468 = eq(T_466, UInt<2>("h03")) + node T_470 = and(UInt<1>("h00"), T_468) + node T_473 = addw(T_466, UInt<1>("h01")) + node T_474 = mux(T_470, UInt<1>("h00"), T_473) + T_466 := T_474 + skip + node T_475 = and(T_464, T_468) + node T_476 = mux(T_463, T_466, UInt<1>("h00")) + node T_477 = mux(T_463, T_475, T_441) + inst T_634 of FinishQueue + T_634.deq.ready := UInt<1>("h00") + T_634.enq.bits.dst := UInt<1>("h00") + T_634.enq.bits.fin.manager_xact_id := UInt<1>("h00") + T_634.enq.valid := UInt<1>("h00") + T_634.reset := UInt<1>("h00") + T_634.clock := clock + T_634.reset := reset + node T_533 = and(grant.ready, grant.valid) + node T_536 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_538 = eq(grant.bits.payload.g_type, UInt<3>("h00")) + node T_539 = and(grant.bits.payload.is_builtin_type, T_538) + node T_541 = eq(T_539, UInt<1>("h00")) + node T_542 = and(T_536, T_541) + node T_543 = and(T_533, T_542) + wire T_547 : UInt<3>[1] + T_547[0] := UInt<3>("h05") + node T_550 = eq(T_547[0], grant.bits.payload.g_type) + node T_552 = or(UInt<1>("h00"), T_550) + wire T_554 : UInt<1>[2] + T_554[0] := UInt<1>("h00") + T_554[1] := UInt<1>("h01") + node T_558 = eq(T_554[0], grant.bits.payload.g_type) + node T_559 = eq(T_554[1], grant.bits.payload.g_type) + node T_561 = or(UInt<1>("h00"), T_558) + node T_562 = or(T_561, T_559) + node T_563 = mux(grant.bits.payload.is_builtin_type, T_552, T_562) + node T_564 = and(UInt<1>("h01"), T_563) + node T_566 = eq(T_564, UInt<1>("h00")) + node T_567 = or(T_566, T_477) + node T_568 = and(T_543, T_567) + T_634.enq.valid := T_568 + wire T_594 : {manager_xact_id : UInt<4>} + T_594.manager_xact_id := UInt<1>("h00") + T_594.manager_xact_id := grant.bits.payload.manager_xact_id + T_634.enq.bits.fin <> T_594 + T_634.enq.bits.dst := grant.bits.header.src + finish.bits.header.src := UInt<1>("h00") + finish.bits.header.dst := T_634.deq.bits.dst + finish.bits.payload <> T_634.deq.bits.fin + finish.valid := T_634.deq.valid + T_634.deq.ready := finish.ready + refill.valid := grant.valid + refill.bits <> grant.bits.payload + node T_623 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_625 = eq(grant.bits.payload.g_type, UInt<3>("h00")) + node T_626 = and(grant.bits.payload.is_builtin_type, T_625) + node T_628 = eq(T_626, UInt<1>("h00")) + node T_629 = and(T_623, T_628) + node T_631 = eq(T_629, UInt<1>("h00")) + node T_632 = or(T_634.enq.ready, T_631) + node T_633 = and(T_632, refill.ready) + grant.ready := T_633 + ready := T_634.enq.ready + + module ClientTileLinkNetworkPort : + output network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} + input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + input clock : Clock + input reset : UInt<1> + + network.release.bits.payload.voluntary := UInt<1>("h00") + network.release.bits.payload.r_type := UInt<1>("h00") + network.release.bits.payload.data := UInt<1>("h00") + network.release.bits.payload.addr_beat := UInt<1>("h00") + network.release.bits.payload.client_xact_id := UInt<1>("h00") + network.release.bits.payload.addr_block := UInt<1>("h00") + network.release.bits.header.dst := UInt<1>("h00") + network.release.bits.header.src := UInt<1>("h00") + network.release.valid := UInt<1>("h00") + network.probe.ready := UInt<1>("h00") + network.finish.bits.payload.manager_xact_id := UInt<1>("h00") + network.finish.bits.header.dst := UInt<1>("h00") + network.finish.bits.header.src := UInt<1>("h00") + network.finish.valid := UInt<1>("h00") + network.grant.ready := UInt<1>("h00") + network.acquire.bits.payload.union := UInt<1>("h00") + network.acquire.bits.payload.a_type := UInt<1>("h00") + network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + network.acquire.bits.payload.data := UInt<1>("h00") + network.acquire.bits.payload.addr_beat := UInt<1>("h00") + network.acquire.bits.payload.client_xact_id := UInt<1>("h00") + network.acquire.bits.payload.addr_block := UInt<1>("h00") + network.acquire.bits.header.dst := UInt<1>("h00") + network.acquire.bits.header.src := UInt<1>("h00") + network.acquire.valid := UInt<1>("h00") + client.release.ready := UInt<1>("h00") + client.probe.bits.p_type := UInt<1>("h00") + client.probe.bits.addr_block := UInt<1>("h00") + client.probe.valid := UInt<1>("h00") + client.grant.bits.g_type := UInt<1>("h00") + client.grant.bits.is_builtin_type := UInt<1>("h00") + client.grant.bits.manager_xact_id := UInt<1>("h00") + client.grant.bits.client_xact_id := UInt<1>("h00") + client.grant.bits.data := UInt<1>("h00") + client.grant.bits.addr_beat := UInt<1>("h00") + client.grant.valid := UInt<1>("h00") + client.acquire.ready := UInt<1>("h00") + inst finisher of FinishUnit + finisher.finish.ready := UInt<1>("h00") + finisher.refill.ready := UInt<1>("h00") + finisher.grant.bits.payload.g_type := UInt<1>("h00") + finisher.grant.bits.payload.is_builtin_type := UInt<1>("h00") + finisher.grant.bits.payload.manager_xact_id := UInt<1>("h00") + finisher.grant.bits.payload.client_xact_id := UInt<1>("h00") + finisher.grant.bits.payload.data := UInt<1>("h00") + finisher.grant.bits.payload.addr_beat := UInt<1>("h00") + finisher.grant.bits.header.dst := UInt<1>("h00") + finisher.grant.bits.header.src := UInt<1>("h00") + finisher.grant.valid := UInt<1>("h00") + finisher.reset := UInt<1>("h00") + finisher.clock := clock + finisher.reset := reset + finisher.grant <> network.grant + network.finish <> finisher.finish + wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} + acq_with_header.bits.payload.union := UInt<1>("h00") + acq_with_header.bits.payload.a_type := UInt<1>("h00") + acq_with_header.bits.payload.is_builtin_type := UInt<1>("h00") + acq_with_header.bits.payload.data := UInt<1>("h00") + acq_with_header.bits.payload.addr_beat := UInt<1>("h00") + acq_with_header.bits.payload.client_xact_id := UInt<1>("h00") + acq_with_header.bits.payload.addr_block := UInt<1>("h00") + acq_with_header.bits.header.dst := UInt<1>("h00") + acq_with_header.bits.header.src := UInt<1>("h00") + acq_with_header.valid := UInt<1>("h00") + acq_with_header.ready := UInt<1>("h00") + acq_with_header.bits.payload <> client.acquire.bits + acq_with_header.bits.header.src := UInt<1>("h00") + acq_with_header.bits.header.dst := UInt<1>("h00") + acq_with_header.valid := client.acquire.valid + client.acquire.ready := acq_with_header.ready + wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + rel_with_header.bits.payload.voluntary := UInt<1>("h00") + rel_with_header.bits.payload.r_type := UInt<1>("h00") + rel_with_header.bits.payload.data := UInt<1>("h00") + rel_with_header.bits.payload.addr_beat := UInt<1>("h00") + rel_with_header.bits.payload.client_xact_id := UInt<1>("h00") + rel_with_header.bits.payload.addr_block := UInt<1>("h00") + rel_with_header.bits.header.dst := UInt<1>("h00") + rel_with_header.bits.header.src := UInt<1>("h00") + rel_with_header.valid := UInt<1>("h00") + rel_with_header.ready := UInt<1>("h00") + rel_with_header.bits.payload <> client.release.bits + rel_with_header.bits.header.src := UInt<1>("h00") + rel_with_header.bits.header.dst := UInt<1>("h00") + rel_with_header.valid := client.release.valid + client.release.ready := rel_with_header.ready + wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} + prb_without_header.bits.p_type := UInt<1>("h00") + prb_without_header.bits.addr_block := UInt<1>("h00") + prb_without_header.valid := UInt<1>("h00") + prb_without_header.ready := UInt<1>("h00") + prb_without_header.valid := network.probe.valid + prb_without_header.bits <> network.probe.bits.payload + network.probe.ready := prb_without_header.ready + network.acquire.bits <> acq_with_header.bits + node T_2345 = and(acq_with_header.valid, finisher.ready) + network.acquire.valid := T_2345 + node T_2346 = and(network.acquire.ready, finisher.ready) + acq_with_header.ready := T_2346 + network.release <> rel_with_header + client.probe <> prb_without_header + client.grant <> finisher.refill + + module Queue : + output count : UInt<2> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.payload.union := UInt<1>("h00") + deq.bits.payload.a_type := UInt<1>("h00") + deq.bits.payload.is_builtin_type := UInt<1>("h00") + deq.bits.payload.data := UInt<1>("h00") + deq.bits.payload.addr_beat := UInt<1>("h00") + deq.bits.payload.client_xact_id := UInt<1>("h00") + deq.bits.payload.addr_block := UInt<1>("h00") + deq.bits.header.dst := UInt<1>("h00") + deq.bits.header.src := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}[2], clock + reg T_331 : UInt<1>, clock, reset + onreset T_331 := UInt<1>("h00") + reg T_333 : UInt<1>, clock, reset + onreset T_333 := UInt<1>("h00") + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(T_331, T_333) + node T_338 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_338) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_344 = and(enq.ready, enq.valid) + node T_346 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_344, T_346) + node T_348 = and(deq.ready, deq.valid) + node T_350 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_348, T_350) + when do_enq : + infer accessor T_352 = ram[T_331] + T_352 <> enq.bits + node T_388 = eq(T_331, UInt<1>("h01")) + node T_390 = and(UInt<1>("h00"), T_388) + node T_393 = addw(T_331, UInt<1>("h01")) + node T_394 = mux(T_390, UInt<1>("h00"), T_393) + T_331 := T_394 + skip + when do_deq : + node T_396 = eq(T_333, UInt<1>("h01")) + node T_398 = and(UInt<1>("h00"), T_396) + node T_401 = addw(T_333, UInt<1>("h01")) + node T_402 = mux(T_398, UInt<1>("h00"), T_401) + T_333 := T_402 + skip + node T_403 = neq(do_enq, do_deq) + when T_403 : + maybe_full := do_enq + skip + node T_405 = eq(empty, UInt<1>("h00")) + node T_407 = and(UInt<1>("h00"), enq.valid) + node T_408 = or(T_405, T_407) + deq.valid := T_408 + node T_410 = eq(full, UInt<1>("h00")) + node T_412 = and(UInt<1>("h00"), deq.ready) + node T_413 = or(T_410, T_412) + enq.ready := T_413 + infer accessor T_414 = ram[T_333] + wire T_484 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} + T_484 <> T_414 + when maybe_flow : + T_484 <> enq.bits + skip + deq.bits <> T_484 + node ptr_diff = subw(T_331, T_333) + node T_520 = and(maybe_full, ptr_match) + node T_521 = cat(T_520, ptr_diff) + count := T_521 + + module Queue_2 : + output count : UInt<2> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.payload.p_type := UInt<1>("h00") + deq.bits.payload.addr_block := UInt<1>("h00") + deq.bits.header.dst := UInt<1>("h00") + deq.bits.header.src := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}[2], clock + reg T_286 : UInt<1>, clock, reset + onreset T_286 := UInt<1>("h00") + reg T_288 : UInt<1>, clock, reset + onreset T_288 := UInt<1>("h00") + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(T_286, T_288) + node T_293 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_293) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_299 = and(enq.ready, enq.valid) + node T_301 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_299, T_301) + node T_303 = and(deq.ready, deq.valid) + node T_305 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_303, T_305) + when do_enq : + infer accessor T_307 = ram[T_286] + T_307 <> enq.bits + node T_338 = eq(T_286, UInt<1>("h01")) + node T_340 = and(UInt<1>("h00"), T_338) + node T_343 = addw(T_286, UInt<1>("h01")) + node T_344 = mux(T_340, UInt<1>("h00"), T_343) + T_286 := T_344 + skip + when do_deq : + node T_346 = eq(T_288, UInt<1>("h01")) + node T_348 = and(UInt<1>("h00"), T_346) + node T_351 = addw(T_288, UInt<1>("h01")) + node T_352 = mux(T_348, UInt<1>("h00"), T_351) + T_288 := T_352 + skip + node T_353 = neq(do_enq, do_deq) + when T_353 : + maybe_full := do_enq + skip + node T_355 = eq(empty, UInt<1>("h00")) + node T_357 = and(UInt<1>("h00"), enq.valid) + node T_358 = or(T_355, T_357) + deq.valid := T_358 + node T_360 = eq(full, UInt<1>("h00")) + node T_362 = and(UInt<1>("h00"), deq.ready) + node T_363 = or(T_360, T_362) + enq.ready := T_363 + infer accessor T_364 = ram[T_288] + wire T_424 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}} + T_424 <> T_364 + when maybe_flow : + T_424 <> enq.bits + skip + deq.bits <> T_424 + node ptr_diff = subw(T_286, T_288) + node T_455 = and(maybe_full, ptr_match) + node T_456 = cat(T_455, ptr_diff) + count := T_456 + + module Queue_3 : + output count : UInt<2> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.payload.voluntary := UInt<1>("h00") + deq.bits.payload.r_type := UInt<1>("h00") + deq.bits.payload.data := UInt<1>("h00") + deq.bits.payload.addr_beat := UInt<1>("h00") + deq.bits.payload.client_xact_id := UInt<1>("h00") + deq.bits.payload.addr_block := UInt<1>("h00") + deq.bits.header.dst := UInt<1>("h00") + deq.bits.header.src := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[2], clock + reg T_322 : UInt<1>, clock, reset + onreset T_322 := UInt<1>("h00") + reg T_324 : UInt<1>, clock, reset + onreset T_324 := UInt<1>("h00") + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(T_322, T_324) + node T_329 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_329) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_335 = and(enq.ready, enq.valid) + node T_337 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_335, T_337) + node T_339 = and(deq.ready, deq.valid) + node T_341 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_339, T_341) + when do_enq : + infer accessor T_343 = ram[T_322] + T_343 <> enq.bits + node T_378 = eq(T_322, UInt<1>("h01")) + node T_380 = and(UInt<1>("h00"), T_378) + node T_383 = addw(T_322, UInt<1>("h01")) + node T_384 = mux(T_380, UInt<1>("h00"), T_383) + T_322 := T_384 + skip + when do_deq : + node T_386 = eq(T_324, UInt<1>("h01")) + node T_388 = and(UInt<1>("h00"), T_386) + node T_391 = addw(T_324, UInt<1>("h01")) + node T_392 = mux(T_388, UInt<1>("h00"), T_391) + T_324 := T_392 + skip + node T_393 = neq(do_enq, do_deq) + when T_393 : + maybe_full := do_enq + skip + node T_395 = eq(empty, UInt<1>("h00")) + node T_397 = and(UInt<1>("h00"), enq.valid) + node T_398 = or(T_395, T_397) + deq.valid := T_398 + node T_400 = eq(full, UInt<1>("h00")) + node T_402 = and(UInt<1>("h00"), deq.ready) + node T_403 = or(T_400, T_402) + enq.ready := T_403 + infer accessor T_404 = ram[T_324] + wire T_472 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} + T_472 <> T_404 + when maybe_flow : + T_472 <> enq.bits + skip + deq.bits <> T_472 + node ptr_diff = subw(T_322, T_324) + node T_507 = and(maybe_full, ptr_match) + node T_508 = cat(T_507, ptr_diff) + count := T_508 + + module Queue_4 : + output count : UInt<2> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.payload.g_type := UInt<1>("h00") + deq.bits.payload.is_builtin_type := UInt<1>("h00") + deq.bits.payload.manager_xact_id := UInt<1>("h00") + deq.bits.payload.client_xact_id := UInt<1>("h00") + deq.bits.payload.data := UInt<1>("h00") + deq.bits.payload.addr_beat := UInt<1>("h00") + deq.bits.header.dst := UInt<1>("h00") + deq.bits.header.src := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}[2], clock + reg T_322 : UInt<1>, clock, reset + onreset T_322 := UInt<1>("h00") + reg T_324 : UInt<1>, clock, reset + onreset T_324 := UInt<1>("h00") + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(T_322, T_324) + node T_329 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_329) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_335 = and(enq.ready, enq.valid) + node T_337 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_335, T_337) + node T_339 = and(deq.ready, deq.valid) + node T_341 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_339, T_341) + when do_enq : + infer accessor T_343 = ram[T_322] + T_343 <> enq.bits + node T_378 = eq(T_322, UInt<1>("h01")) + node T_380 = and(UInt<1>("h00"), T_378) + node T_383 = addw(T_322, UInt<1>("h01")) + node T_384 = mux(T_380, UInt<1>("h00"), T_383) + T_322 := T_384 + skip + when do_deq : + node T_386 = eq(T_324, UInt<1>("h01")) + node T_388 = and(UInt<1>("h00"), T_386) + node T_391 = addw(T_324, UInt<1>("h01")) + node T_392 = mux(T_388, UInt<1>("h00"), T_391) + T_324 := T_392 + skip + node T_393 = neq(do_enq, do_deq) + when T_393 : + maybe_full := do_enq + skip + node T_395 = eq(empty, UInt<1>("h00")) + node T_397 = and(UInt<1>("h00"), enq.valid) + node T_398 = or(T_395, T_397) + deq.valid := T_398 + node T_400 = eq(full, UInt<1>("h00")) + node T_402 = and(UInt<1>("h00"), deq.ready) + node T_403 = or(T_400, T_402) + enq.ready := T_403 + infer accessor T_404 = ram[T_324] + wire T_472 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} + T_472 <> T_404 + when maybe_flow : + T_472 <> enq.bits + skip + deq.bits <> T_472 + node ptr_diff = subw(T_322, T_324) + node T_507 = and(maybe_full, ptr_match) + node T_508 = cat(T_507, ptr_diff) + count := T_508 + + module Queue_5 : + output count : UInt<2> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.payload.manager_xact_id := UInt<1>("h00") + deq.bits.header.dst := UInt<1>("h00") + deq.bits.header.src := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}[2], clock + reg T_277 : UInt<1>, clock, reset + onreset T_277 := UInt<1>("h00") + reg T_279 : UInt<1>, clock, reset + onreset T_279 := UInt<1>("h00") + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(T_277, T_279) + node T_284 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_284) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_290 = and(enq.ready, enq.valid) + node T_292 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_290, T_292) + node T_294 = and(deq.ready, deq.valid) + node T_296 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_294, T_296) + when do_enq : + infer accessor T_298 = ram[T_277] + T_298 <> enq.bits + node T_328 = eq(T_277, UInt<1>("h01")) + node T_330 = and(UInt<1>("h00"), T_328) + node T_333 = addw(T_277, UInt<1>("h01")) + node T_334 = mux(T_330, UInt<1>("h00"), T_333) + T_277 := T_334 + skip + when do_deq : + node T_336 = eq(T_279, UInt<1>("h01")) + node T_338 = and(UInt<1>("h00"), T_336) + node T_341 = addw(T_279, UInt<1>("h01")) + node T_342 = mux(T_338, UInt<1>("h00"), T_341) + T_279 := T_342 + skip + node T_343 = neq(do_enq, do_deq) + when T_343 : + maybe_full := do_enq + skip + node T_345 = eq(empty, UInt<1>("h00")) + node T_347 = and(UInt<1>("h00"), enq.valid) + node T_348 = or(T_345, T_347) + deq.valid := T_348 + node T_350 = eq(full, UInt<1>("h00")) + node T_352 = and(UInt<1>("h00"), deq.ready) + node T_353 = or(T_350, T_352) + enq.ready := T_353 + infer accessor T_354 = ram[T_279] + wire T_412 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}} + T_412 <> T_354 + when maybe_flow : + T_412 <> enq.bits + skip + deq.bits <> T_412 + node ptr_diff = subw(T_277, T_279) + node T_442 = and(maybe_full, ptr_match) + node T_443 = cat(T_442, ptr_diff) + count := T_443 + + module TileLinkEnqueuer : + output manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} + input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} + input clock : Clock + input reset : UInt<1> + + manager.release.bits.payload.voluntary := UInt<1>("h00") + manager.release.bits.payload.r_type := UInt<1>("h00") + manager.release.bits.payload.data := UInt<1>("h00") + manager.release.bits.payload.addr_beat := UInt<1>("h00") + manager.release.bits.payload.client_xact_id := UInt<1>("h00") + manager.release.bits.payload.addr_block := UInt<1>("h00") + manager.release.bits.header.dst := UInt<1>("h00") + manager.release.bits.header.src := UInt<1>("h00") + manager.release.valid := UInt<1>("h00") + manager.probe.ready := UInt<1>("h00") + manager.finish.bits.payload.manager_xact_id := UInt<1>("h00") + manager.finish.bits.header.dst := UInt<1>("h00") + manager.finish.bits.header.src := UInt<1>("h00") + manager.finish.valid := UInt<1>("h00") + manager.grant.ready := UInt<1>("h00") + manager.acquire.bits.payload.union := UInt<1>("h00") + manager.acquire.bits.payload.a_type := UInt<1>("h00") + manager.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + manager.acquire.bits.payload.data := UInt<1>("h00") + manager.acquire.bits.payload.addr_beat := UInt<1>("h00") + manager.acquire.bits.payload.client_xact_id := UInt<1>("h00") + manager.acquire.bits.payload.addr_block := UInt<1>("h00") + manager.acquire.bits.header.dst := UInt<1>("h00") + manager.acquire.bits.header.src := UInt<1>("h00") + manager.acquire.valid := UInt<1>("h00") + client.release.ready := UInt<1>("h00") + client.probe.bits.payload.p_type := UInt<1>("h00") + client.probe.bits.payload.addr_block := UInt<1>("h00") + client.probe.bits.header.dst := UInt<1>("h00") + client.probe.bits.header.src := UInt<1>("h00") + client.probe.valid := UInt<1>("h00") + client.finish.ready := UInt<1>("h00") + client.grant.bits.payload.g_type := UInt<1>("h00") + client.grant.bits.payload.is_builtin_type := UInt<1>("h00") + client.grant.bits.payload.manager_xact_id := UInt<1>("h00") + client.grant.bits.payload.client_xact_id := UInt<1>("h00") + client.grant.bits.payload.data := UInt<1>("h00") + client.grant.bits.payload.addr_beat := UInt<1>("h00") + client.grant.bits.header.dst := UInt<1>("h00") + client.grant.bits.header.src := UInt<1>("h00") + client.grant.valid := UInt<1>("h00") + client.acquire.ready := UInt<1>("h00") + inst T_2615 of Queue + T_2615.deq.ready := UInt<1>("h00") + T_2615.enq.bits.payload.union := UInt<1>("h00") + T_2615.enq.bits.payload.a_type := UInt<1>("h00") + T_2615.enq.bits.payload.is_builtin_type := UInt<1>("h00") + T_2615.enq.bits.payload.data := UInt<1>("h00") + T_2615.enq.bits.payload.addr_beat := UInt<1>("h00") + T_2615.enq.bits.payload.client_xact_id := UInt<1>("h00") + T_2615.enq.bits.payload.addr_block := UInt<1>("h00") + T_2615.enq.bits.header.dst := UInt<1>("h00") + T_2615.enq.bits.header.src := UInt<1>("h00") + T_2615.enq.valid := UInt<1>("h00") + T_2615.reset := UInt<1>("h00") + T_2615.clock := clock + T_2615.reset := reset + T_2615.enq.valid := client.acquire.valid + T_2615.enq.bits <> client.acquire.bits + client.acquire.ready := T_2615.enq.ready + manager.acquire <> T_2615.deq + inst T_2616 of Queue_2 + T_2616.deq.ready := UInt<1>("h00") + T_2616.enq.bits.payload.p_type := UInt<1>("h00") + T_2616.enq.bits.payload.addr_block := UInt<1>("h00") + T_2616.enq.bits.header.dst := UInt<1>("h00") + T_2616.enq.bits.header.src := UInt<1>("h00") + T_2616.enq.valid := UInt<1>("h00") + T_2616.reset := UInt<1>("h00") + T_2616.clock := clock + T_2616.reset := reset + T_2616.enq.valid := manager.probe.valid + T_2616.enq.bits <> manager.probe.bits + manager.probe.ready := T_2616.enq.ready + client.probe <> T_2616.deq + inst T_2617 of Queue_3 + T_2617.deq.ready := UInt<1>("h00") + T_2617.enq.bits.payload.voluntary := UInt<1>("h00") + T_2617.enq.bits.payload.r_type := UInt<1>("h00") + T_2617.enq.bits.payload.data := UInt<1>("h00") + T_2617.enq.bits.payload.addr_beat := UInt<1>("h00") + T_2617.enq.bits.payload.client_xact_id := UInt<1>("h00") + T_2617.enq.bits.payload.addr_block := UInt<1>("h00") + T_2617.enq.bits.header.dst := UInt<1>("h00") + T_2617.enq.bits.header.src := UInt<1>("h00") + T_2617.enq.valid := UInt<1>("h00") + T_2617.reset := UInt<1>("h00") + T_2617.clock := clock + T_2617.reset := reset + T_2617.enq.valid := client.release.valid + T_2617.enq.bits <> client.release.bits + client.release.ready := T_2617.enq.ready + manager.release <> T_2617.deq + inst T_2618 of Queue_4 + T_2618.deq.ready := UInt<1>("h00") + T_2618.enq.bits.payload.g_type := UInt<1>("h00") + T_2618.enq.bits.payload.is_builtin_type := UInt<1>("h00") + T_2618.enq.bits.payload.manager_xact_id := UInt<1>("h00") + T_2618.enq.bits.payload.client_xact_id := UInt<1>("h00") + T_2618.enq.bits.payload.data := UInt<1>("h00") + T_2618.enq.bits.payload.addr_beat := UInt<1>("h00") + T_2618.enq.bits.header.dst := UInt<1>("h00") + T_2618.enq.bits.header.src := UInt<1>("h00") + T_2618.enq.valid := UInt<1>("h00") + T_2618.reset := UInt<1>("h00") + T_2618.clock := clock + T_2618.reset := reset + T_2618.enq.valid := manager.grant.valid + T_2618.enq.bits <> manager.grant.bits + manager.grant.ready := T_2618.enq.ready + client.grant <> T_2618.deq + inst T_2619 of Queue_5 + T_2619.deq.ready := UInt<1>("h00") + T_2619.enq.bits.payload.manager_xact_id := UInt<1>("h00") + T_2619.enq.bits.header.dst := UInt<1>("h00") + T_2619.enq.bits.header.src := UInt<1>("h00") + T_2619.enq.valid := UInt<1>("h00") + T_2619.reset := UInt<1>("h00") + T_2619.clock := clock + T_2619.reset := reset + T_2619.enq.valid := client.finish.valid + T_2619.enq.bits <> client.finish.bits + client.finish.ready := T_2619.enq.ready + manager.finish <> T_2619.deq + + module FinishUnit_7 : + output ready : UInt<1> + output finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} + output refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} + input grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input clock : Clock + input reset : UInt<1> + + ready := UInt<1>("h00") + finish.bits.payload.manager_xact_id := UInt<1>("h00") + finish.bits.header.dst := UInt<1>("h00") + finish.bits.header.src := UInt<1>("h00") + finish.valid := UInt<1>("h00") + refill.bits.g_type := UInt<1>("h00") + refill.bits.is_builtin_type := UInt<1>("h00") + refill.bits.manager_xact_id := UInt<1>("h00") + refill.bits.client_xact_id := UInt<1>("h00") + refill.bits.data := UInt<1>("h00") + refill.bits.addr_beat := UInt<1>("h00") + refill.valid := UInt<1>("h00") + grant.ready := UInt<1>("h00") + node T_441 = and(grant.ready, grant.valid) + wire T_446 : UInt<3>[1] + T_446[0] := UInt<3>("h05") + node T_449 = eq(T_446[0], grant.bits.payload.g_type) + node T_451 = or(UInt<1>("h00"), T_449) + wire T_453 : UInt<1>[2] + T_453[0] := UInt<1>("h00") + T_453[1] := UInt<1>("h01") + node T_457 = eq(T_453[0], grant.bits.payload.g_type) + node T_458 = eq(T_453[1], grant.bits.payload.g_type) + node T_460 = or(UInt<1>("h00"), T_457) + node T_461 = or(T_460, T_458) + node T_462 = mux(grant.bits.payload.is_builtin_type, T_451, T_461) + node T_463 = and(UInt<1>("h01"), T_462) + node T_464 = and(T_441, T_463) + reg T_466 : UInt<2>, clock, reset + onreset T_466 := UInt<2>("h00") + when T_464 : + node T_468 = eq(T_466, UInt<2>("h03")) + node T_470 = and(UInt<1>("h00"), T_468) + node T_473 = addw(T_466, UInt<1>("h01")) + node T_474 = mux(T_470, UInt<1>("h00"), T_473) + T_466 := T_474 + skip + node T_475 = and(T_464, T_468) + node T_476 = mux(T_463, T_466, UInt<1>("h00")) + node T_477 = mux(T_463, T_475, T_441) + inst T_634 of FinishQueue + T_634.deq.ready := UInt<1>("h00") + T_634.enq.bits.dst := UInt<1>("h00") + T_634.enq.bits.fin.manager_xact_id := UInt<1>("h00") + T_634.enq.valid := UInt<1>("h00") + T_634.reset := UInt<1>("h00") + T_634.clock := clock + T_634.reset := reset + node T_533 = and(grant.ready, grant.valid) + node T_536 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_538 = eq(grant.bits.payload.g_type, UInt<3>("h00")) + node T_539 = and(grant.bits.payload.is_builtin_type, T_538) + node T_541 = eq(T_539, UInt<1>("h00")) + node T_542 = and(T_536, T_541) + node T_543 = and(T_533, T_542) + wire T_547 : UInt<3>[1] + T_547[0] := UInt<3>("h05") + node T_550 = eq(T_547[0], grant.bits.payload.g_type) + node T_552 = or(UInt<1>("h00"), T_550) + wire T_554 : UInt<1>[2] + T_554[0] := UInt<1>("h00") + T_554[1] := UInt<1>("h01") + node T_558 = eq(T_554[0], grant.bits.payload.g_type) + node T_559 = eq(T_554[1], grant.bits.payload.g_type) + node T_561 = or(UInt<1>("h00"), T_558) + node T_562 = or(T_561, T_559) + node T_563 = mux(grant.bits.payload.is_builtin_type, T_552, T_562) + node T_564 = and(UInt<1>("h01"), T_563) + node T_566 = eq(T_564, UInt<1>("h00")) + node T_567 = or(T_566, T_477) + node T_568 = and(T_543, T_567) + T_634.enq.valid := T_568 + wire T_594 : {manager_xact_id : UInt<4>} + T_594.manager_xact_id := UInt<1>("h00") + T_594.manager_xact_id := grant.bits.payload.manager_xact_id + T_634.enq.bits.fin <> T_594 + T_634.enq.bits.dst := grant.bits.header.src + finish.bits.header.src := UInt<1>("h01") + finish.bits.header.dst := T_634.deq.bits.dst + finish.bits.payload <> T_634.deq.bits.fin + finish.valid := T_634.deq.valid + T_634.deq.ready := finish.ready + refill.valid := grant.valid + refill.bits <> grant.bits.payload + node T_623 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_625 = eq(grant.bits.payload.g_type, UInt<3>("h00")) + node T_626 = and(grant.bits.payload.is_builtin_type, T_625) + node T_628 = eq(T_626, UInt<1>("h00")) + node T_629 = and(T_623, T_628) + node T_631 = eq(T_629, UInt<1>("h00")) + node T_632 = or(T_634.enq.ready, T_631) + node T_633 = and(T_632, refill.ready) + grant.ready := T_633 + ready := T_634.enq.ready + + module ClientTileLinkNetworkPort_6 : + output network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} + input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + input clock : Clock + input reset : UInt<1> + + network.release.bits.payload.voluntary := UInt<1>("h00") + network.release.bits.payload.r_type := UInt<1>("h00") + network.release.bits.payload.data := UInt<1>("h00") + network.release.bits.payload.addr_beat := UInt<1>("h00") + network.release.bits.payload.client_xact_id := UInt<1>("h00") + network.release.bits.payload.addr_block := UInt<1>("h00") + network.release.bits.header.dst := UInt<1>("h00") + network.release.bits.header.src := UInt<1>("h00") + network.release.valid := UInt<1>("h00") + network.probe.ready := UInt<1>("h00") + network.finish.bits.payload.manager_xact_id := UInt<1>("h00") + network.finish.bits.header.dst := UInt<1>("h00") + network.finish.bits.header.src := UInt<1>("h00") + network.finish.valid := UInt<1>("h00") + network.grant.ready := UInt<1>("h00") + network.acquire.bits.payload.union := UInt<1>("h00") + network.acquire.bits.payload.a_type := UInt<1>("h00") + network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + network.acquire.bits.payload.data := UInt<1>("h00") + network.acquire.bits.payload.addr_beat := UInt<1>("h00") + network.acquire.bits.payload.client_xact_id := UInt<1>("h00") + network.acquire.bits.payload.addr_block := UInt<1>("h00") + network.acquire.bits.header.dst := UInt<1>("h00") + network.acquire.bits.header.src := UInt<1>("h00") + network.acquire.valid := UInt<1>("h00") + client.release.ready := UInt<1>("h00") + client.probe.bits.p_type := UInt<1>("h00") + client.probe.bits.addr_block := UInt<1>("h00") + client.probe.valid := UInt<1>("h00") + client.grant.bits.g_type := UInt<1>("h00") + client.grant.bits.is_builtin_type := UInt<1>("h00") + client.grant.bits.manager_xact_id := UInt<1>("h00") + client.grant.bits.client_xact_id := UInt<1>("h00") + client.grant.bits.data := UInt<1>("h00") + client.grant.bits.addr_beat := UInt<1>("h00") + client.grant.valid := UInt<1>("h00") + client.acquire.ready := UInt<1>("h00") + inst finisher of FinishUnit_7 + finisher.finish.ready := UInt<1>("h00") + finisher.refill.ready := UInt<1>("h00") + finisher.grant.bits.payload.g_type := UInt<1>("h00") + finisher.grant.bits.payload.is_builtin_type := UInt<1>("h00") + finisher.grant.bits.payload.manager_xact_id := UInt<1>("h00") + finisher.grant.bits.payload.client_xact_id := UInt<1>("h00") + finisher.grant.bits.payload.data := UInt<1>("h00") + finisher.grant.bits.payload.addr_beat := UInt<1>("h00") + finisher.grant.bits.header.dst := UInt<1>("h00") + finisher.grant.bits.header.src := UInt<1>("h00") + finisher.grant.valid := UInt<1>("h00") + finisher.reset := UInt<1>("h00") + finisher.clock := clock + finisher.reset := reset + finisher.grant <> network.grant + network.finish <> finisher.finish + wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} + acq_with_header.bits.payload.union := UInt<1>("h00") + acq_with_header.bits.payload.a_type := UInt<1>("h00") + acq_with_header.bits.payload.is_builtin_type := UInt<1>("h00") + acq_with_header.bits.payload.data := UInt<1>("h00") + acq_with_header.bits.payload.addr_beat := UInt<1>("h00") + acq_with_header.bits.payload.client_xact_id := UInt<1>("h00") + acq_with_header.bits.payload.addr_block := UInt<1>("h00") + acq_with_header.bits.header.dst := UInt<1>("h00") + acq_with_header.bits.header.src := UInt<1>("h00") + acq_with_header.valid := UInt<1>("h00") + acq_with_header.ready := UInt<1>("h00") + acq_with_header.bits.payload <> client.acquire.bits + acq_with_header.bits.header.src := UInt<1>("h01") + acq_with_header.bits.header.dst := UInt<1>("h00") + acq_with_header.valid := client.acquire.valid + client.acquire.ready := acq_with_header.ready + wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + rel_with_header.bits.payload.voluntary := UInt<1>("h00") + rel_with_header.bits.payload.r_type := UInt<1>("h00") + rel_with_header.bits.payload.data := UInt<1>("h00") + rel_with_header.bits.payload.addr_beat := UInt<1>("h00") + rel_with_header.bits.payload.client_xact_id := UInt<1>("h00") + rel_with_header.bits.payload.addr_block := UInt<1>("h00") + rel_with_header.bits.header.dst := UInt<1>("h00") + rel_with_header.bits.header.src := UInt<1>("h00") + rel_with_header.valid := UInt<1>("h00") + rel_with_header.ready := UInt<1>("h00") + rel_with_header.bits.payload <> client.release.bits + rel_with_header.bits.header.src := UInt<1>("h01") + rel_with_header.bits.header.dst := UInt<1>("h00") + rel_with_header.valid := client.release.valid + client.release.ready := rel_with_header.ready + wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} + prb_without_header.bits.p_type := UInt<1>("h00") + prb_without_header.bits.addr_block := UInt<1>("h00") + prb_without_header.valid := UInt<1>("h00") + prb_without_header.ready := UInt<1>("h00") + prb_without_header.valid := network.probe.valid + prb_without_header.bits <> network.probe.bits.payload + network.probe.ready := prb_without_header.ready + network.acquire.bits <> acq_with_header.bits + node T_2345 = and(acq_with_header.valid, finisher.ready) + network.acquire.valid := T_2345 + node T_2346 = and(network.acquire.ready, finisher.ready) + acq_with_header.ready := T_2346 + network.release <> rel_with_header + client.probe <> prb_without_header + client.grant <> finisher.refill + + module FinishUnit_16 : + output ready : UInt<1> + output finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} + output refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} + input grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input clock : Clock + input reset : UInt<1> + + ready := UInt<1>("h00") + finish.bits.payload.manager_xact_id := UInt<1>("h00") + finish.bits.header.dst := UInt<1>("h00") + finish.bits.header.src := UInt<1>("h00") + finish.valid := UInt<1>("h00") + refill.bits.g_type := UInt<1>("h00") + refill.bits.is_builtin_type := UInt<1>("h00") + refill.bits.manager_xact_id := UInt<1>("h00") + refill.bits.client_xact_id := UInt<1>("h00") + refill.bits.data := UInt<1>("h00") + refill.bits.addr_beat := UInt<1>("h00") + refill.valid := UInt<1>("h00") + grant.ready := UInt<1>("h00") + node T_441 = and(grant.ready, grant.valid) + wire T_446 : UInt<3>[1] + T_446[0] := UInt<3>("h05") + node T_449 = eq(T_446[0], grant.bits.payload.g_type) + node T_451 = or(UInt<1>("h00"), T_449) + wire T_453 : UInt<1>[2] + T_453[0] := UInt<1>("h00") + T_453[1] := UInt<1>("h01") + node T_457 = eq(T_453[0], grant.bits.payload.g_type) + node T_458 = eq(T_453[1], grant.bits.payload.g_type) + node T_460 = or(UInt<1>("h00"), T_457) + node T_461 = or(T_460, T_458) + node T_462 = mux(grant.bits.payload.is_builtin_type, T_451, T_461) + node T_463 = and(UInt<1>("h01"), T_462) + node T_464 = and(T_441, T_463) + reg T_466 : UInt<2>, clock, reset + onreset T_466 := UInt<2>("h00") + when T_464 : + node T_468 = eq(T_466, UInt<2>("h03")) + node T_470 = and(UInt<1>("h00"), T_468) + node T_473 = addw(T_466, UInt<1>("h01")) + node T_474 = mux(T_470, UInt<1>("h00"), T_473) + T_466 := T_474 + skip + node T_475 = and(T_464, T_468) + node T_476 = mux(T_463, T_466, UInt<1>("h00")) + node T_477 = mux(T_463, T_475, T_441) + inst T_634 of FinishQueue + T_634.deq.ready := UInt<1>("h00") + T_634.enq.bits.dst := UInt<1>("h00") + T_634.enq.bits.fin.manager_xact_id := UInt<1>("h00") + T_634.enq.valid := UInt<1>("h00") + T_634.reset := UInt<1>("h00") + T_634.clock := clock + T_634.reset := reset + node T_533 = and(grant.ready, grant.valid) + node T_536 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_538 = eq(grant.bits.payload.g_type, UInt<3>("h00")) + node T_539 = and(grant.bits.payload.is_builtin_type, T_538) + node T_541 = eq(T_539, UInt<1>("h00")) + node T_542 = and(T_536, T_541) + node T_543 = and(T_533, T_542) + wire T_547 : UInt<3>[1] + T_547[0] := UInt<3>("h05") + node T_550 = eq(T_547[0], grant.bits.payload.g_type) + node T_552 = or(UInt<1>("h00"), T_550) + wire T_554 : UInt<1>[2] + T_554[0] := UInt<1>("h00") + T_554[1] := UInt<1>("h01") + node T_558 = eq(T_554[0], grant.bits.payload.g_type) + node T_559 = eq(T_554[1], grant.bits.payload.g_type) + node T_561 = or(UInt<1>("h00"), T_558) + node T_562 = or(T_561, T_559) + node T_563 = mux(grant.bits.payload.is_builtin_type, T_552, T_562) + node T_564 = and(UInt<1>("h01"), T_563) + node T_566 = eq(T_564, UInt<1>("h00")) + node T_567 = or(T_566, T_477) + node T_568 = and(T_543, T_567) + T_634.enq.valid := T_568 + wire T_594 : {manager_xact_id : UInt<4>} + T_594.manager_xact_id := UInt<1>("h00") + T_594.manager_xact_id := grant.bits.payload.manager_xact_id + T_634.enq.bits.fin <> T_594 + T_634.enq.bits.dst := grant.bits.header.src + finish.bits.header.src := UInt<2>("h02") + finish.bits.header.dst := T_634.deq.bits.dst + finish.bits.payload <> T_634.deq.bits.fin + finish.valid := T_634.deq.valid + T_634.deq.ready := finish.ready + refill.valid := grant.valid + refill.bits <> grant.bits.payload + node T_623 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_625 = eq(grant.bits.payload.g_type, UInt<3>("h00")) + node T_626 = and(grant.bits.payload.is_builtin_type, T_625) + node T_628 = eq(T_626, UInt<1>("h00")) + node T_629 = and(T_623, T_628) + node T_631 = eq(T_629, UInt<1>("h00")) + node T_632 = or(T_634.enq.ready, T_631) + node T_633 = and(T_632, refill.ready) + grant.ready := T_633 + ready := T_634.enq.ready + + module ClientTileLinkNetworkPort_15 : + output network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} + input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + input clock : Clock + input reset : UInt<1> + + network.release.bits.payload.voluntary := UInt<1>("h00") + network.release.bits.payload.r_type := UInt<1>("h00") + network.release.bits.payload.data := UInt<1>("h00") + network.release.bits.payload.addr_beat := UInt<1>("h00") + network.release.bits.payload.client_xact_id := UInt<1>("h00") + network.release.bits.payload.addr_block := UInt<1>("h00") + network.release.bits.header.dst := UInt<1>("h00") + network.release.bits.header.src := UInt<1>("h00") + network.release.valid := UInt<1>("h00") + network.probe.ready := UInt<1>("h00") + network.finish.bits.payload.manager_xact_id := UInt<1>("h00") + network.finish.bits.header.dst := UInt<1>("h00") + network.finish.bits.header.src := UInt<1>("h00") + network.finish.valid := UInt<1>("h00") + network.grant.ready := UInt<1>("h00") + network.acquire.bits.payload.union := UInt<1>("h00") + network.acquire.bits.payload.a_type := UInt<1>("h00") + network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + network.acquire.bits.payload.data := UInt<1>("h00") + network.acquire.bits.payload.addr_beat := UInt<1>("h00") + network.acquire.bits.payload.client_xact_id := UInt<1>("h00") + network.acquire.bits.payload.addr_block := UInt<1>("h00") + network.acquire.bits.header.dst := UInt<1>("h00") + network.acquire.bits.header.src := UInt<1>("h00") + network.acquire.valid := UInt<1>("h00") + client.release.ready := UInt<1>("h00") + client.probe.bits.p_type := UInt<1>("h00") + client.probe.bits.addr_block := UInt<1>("h00") + client.probe.valid := UInt<1>("h00") + client.grant.bits.g_type := UInt<1>("h00") + client.grant.bits.is_builtin_type := UInt<1>("h00") + client.grant.bits.manager_xact_id := UInt<1>("h00") + client.grant.bits.client_xact_id := UInt<1>("h00") + client.grant.bits.data := UInt<1>("h00") + client.grant.bits.addr_beat := UInt<1>("h00") + client.grant.valid := UInt<1>("h00") + client.acquire.ready := UInt<1>("h00") + inst finisher of FinishUnit_16 + finisher.finish.ready := UInt<1>("h00") + finisher.refill.ready := UInt<1>("h00") + finisher.grant.bits.payload.g_type := UInt<1>("h00") + finisher.grant.bits.payload.is_builtin_type := UInt<1>("h00") + finisher.grant.bits.payload.manager_xact_id := UInt<1>("h00") + finisher.grant.bits.payload.client_xact_id := UInt<1>("h00") + finisher.grant.bits.payload.data := UInt<1>("h00") + finisher.grant.bits.payload.addr_beat := UInt<1>("h00") + finisher.grant.bits.header.dst := UInt<1>("h00") + finisher.grant.bits.header.src := UInt<1>("h00") + finisher.grant.valid := UInt<1>("h00") + finisher.reset := UInt<1>("h00") + finisher.clock := clock + finisher.reset := reset + finisher.grant <> network.grant + network.finish <> finisher.finish + wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} + acq_with_header.bits.payload.union := UInt<1>("h00") + acq_with_header.bits.payload.a_type := UInt<1>("h00") + acq_with_header.bits.payload.is_builtin_type := UInt<1>("h00") + acq_with_header.bits.payload.data := UInt<1>("h00") + acq_with_header.bits.payload.addr_beat := UInt<1>("h00") + acq_with_header.bits.payload.client_xact_id := UInt<1>("h00") + acq_with_header.bits.payload.addr_block := UInt<1>("h00") + acq_with_header.bits.header.dst := UInt<1>("h00") + acq_with_header.bits.header.src := UInt<1>("h00") + acq_with_header.valid := UInt<1>("h00") + acq_with_header.ready := UInt<1>("h00") + acq_with_header.bits.payload <> client.acquire.bits + acq_with_header.bits.header.src := UInt<2>("h02") + acq_with_header.bits.header.dst := UInt<1>("h00") + acq_with_header.valid := client.acquire.valid + client.acquire.ready := acq_with_header.ready + wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + rel_with_header.bits.payload.voluntary := UInt<1>("h00") + rel_with_header.bits.payload.r_type := UInt<1>("h00") + rel_with_header.bits.payload.data := UInt<1>("h00") + rel_with_header.bits.payload.addr_beat := UInt<1>("h00") + rel_with_header.bits.payload.client_xact_id := UInt<1>("h00") + rel_with_header.bits.payload.addr_block := UInt<1>("h00") + rel_with_header.bits.header.dst := UInt<1>("h00") + rel_with_header.bits.header.src := UInt<1>("h00") + rel_with_header.valid := UInt<1>("h00") + rel_with_header.ready := UInt<1>("h00") + rel_with_header.bits.payload <> client.release.bits + rel_with_header.bits.header.src := UInt<2>("h02") + rel_with_header.bits.header.dst := UInt<1>("h00") + rel_with_header.valid := client.release.valid + client.release.ready := rel_with_header.ready + wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} + prb_without_header.bits.p_type := UInt<1>("h00") + prb_without_header.bits.addr_block := UInt<1>("h00") + prb_without_header.valid := UInt<1>("h00") + prb_without_header.ready := UInt<1>("h00") + prb_without_header.valid := network.probe.valid + prb_without_header.bits <> network.probe.bits.payload + network.probe.ready := prb_without_header.ready + network.acquire.bits <> acq_with_header.bits + node T_2345 = and(acq_with_header.valid, finisher.ready) + network.acquire.valid := T_2345 + node T_2346 = and(network.acquire.ready, finisher.ready) + acq_with_header.ready := T_2346 + network.release <> rel_with_header + client.probe <> prb_without_header + client.grant <> finisher.refill + + module ManagerTileLinkNetworkPort : + input network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} + input manager : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} + input clock : Clock + input reset : UInt<1> + + network.release.ready := UInt<1>("h00") + network.probe.bits.payload.p_type := UInt<1>("h00") + network.probe.bits.payload.addr_block := UInt<1>("h00") + network.probe.bits.header.dst := UInt<1>("h00") + network.probe.bits.header.src := UInt<1>("h00") + network.probe.valid := UInt<1>("h00") + network.finish.ready := UInt<1>("h00") + network.grant.bits.payload.g_type := UInt<1>("h00") + network.grant.bits.payload.is_builtin_type := UInt<1>("h00") + network.grant.bits.payload.manager_xact_id := UInt<1>("h00") + network.grant.bits.payload.client_xact_id := UInt<1>("h00") + network.grant.bits.payload.data := UInt<1>("h00") + network.grant.bits.payload.addr_beat := UInt<1>("h00") + network.grant.bits.header.dst := UInt<1>("h00") + network.grant.bits.header.src := UInt<1>("h00") + network.grant.valid := UInt<1>("h00") + network.acquire.ready := UInt<1>("h00") + manager.release.bits.client_id := UInt<1>("h00") + manager.release.bits.voluntary := UInt<1>("h00") + manager.release.bits.r_type := UInt<1>("h00") + manager.release.bits.data := UInt<1>("h00") + manager.release.bits.addr_beat := UInt<1>("h00") + manager.release.bits.client_xact_id := UInt<1>("h00") + manager.release.bits.addr_block := UInt<1>("h00") + manager.release.valid := UInt<1>("h00") + manager.probe.ready := UInt<1>("h00") + manager.finish.bits.manager_xact_id := UInt<1>("h00") + manager.finish.valid := UInt<1>("h00") + manager.grant.ready := UInt<1>("h00") + manager.acquire.bits.client_id := UInt<1>("h00") + manager.acquire.bits.union := UInt<1>("h00") + manager.acquire.bits.a_type := UInt<1>("h00") + manager.acquire.bits.is_builtin_type := UInt<1>("h00") + manager.acquire.bits.data := UInt<1>("h00") + manager.acquire.bits.addr_beat := UInt<1>("h00") + manager.acquire.bits.client_xact_id := UInt<1>("h00") + manager.acquire.bits.addr_block := UInt<1>("h00") + manager.acquire.valid := UInt<1>("h00") + wire T_3060 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}} + T_3060.bits.payload.client_id := UInt<1>("h00") + T_3060.bits.payload.g_type := UInt<1>("h00") + T_3060.bits.payload.is_builtin_type := UInt<1>("h00") + T_3060.bits.payload.manager_xact_id := UInt<1>("h00") + T_3060.bits.payload.client_xact_id := UInt<1>("h00") + T_3060.bits.payload.data := UInt<1>("h00") + T_3060.bits.payload.addr_beat := UInt<1>("h00") + T_3060.bits.header.dst := UInt<1>("h00") + T_3060.bits.header.src := UInt<1>("h00") + T_3060.valid := UInt<1>("h00") + T_3060.ready := UInt<1>("h00") + T_3060.bits.payload <> manager.grant.bits + T_3060.bits.header.src := UInt<1>("h00") + T_3060.bits.header.dst := manager.grant.bits.client_id + T_3060.valid := manager.grant.valid + manager.grant.ready := T_3060.ready + network.grant <> T_3060 + wire T_3241 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}} + T_3241.bits.payload.client_id := UInt<1>("h00") + T_3241.bits.payload.p_type := UInt<1>("h00") + T_3241.bits.payload.addr_block := UInt<1>("h00") + T_3241.bits.header.dst := UInt<1>("h00") + T_3241.bits.header.src := UInt<1>("h00") + T_3241.valid := UInt<1>("h00") + T_3241.ready := UInt<1>("h00") + T_3241.bits.payload <> manager.probe.bits + T_3241.bits.header.src := UInt<1>("h00") + T_3241.bits.header.dst := manager.probe.bits.client_id + T_3241.valid := manager.probe.valid + manager.probe.ready := T_3241.ready + network.probe <> T_3241 + manager.acquire.bits.client_id := network.acquire.bits.header.src + wire T_3379 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} + T_3379.bits.union := UInt<1>("h00") + T_3379.bits.a_type := UInt<1>("h00") + T_3379.bits.is_builtin_type := UInt<1>("h00") + T_3379.bits.data := UInt<1>("h00") + T_3379.bits.addr_beat := UInt<1>("h00") + T_3379.bits.client_xact_id := UInt<1>("h00") + T_3379.bits.addr_block := UInt<1>("h00") + T_3379.valid := UInt<1>("h00") + T_3379.ready := UInt<1>("h00") + T_3379.valid := network.acquire.valid + T_3379.bits <> network.acquire.bits.payload + network.acquire.ready := T_3379.ready + manager.acquire <> T_3379 + manager.release.bits.client_id := network.release.bits.header.src + wire T_3516 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} + T_3516.bits.voluntary := UInt<1>("h00") + T_3516.bits.r_type := UInt<1>("h00") + T_3516.bits.data := UInt<1>("h00") + T_3516.bits.addr_beat := UInt<1>("h00") + T_3516.bits.client_xact_id := UInt<1>("h00") + T_3516.bits.addr_block := UInt<1>("h00") + T_3516.valid := UInt<1>("h00") + T_3516.ready := UInt<1>("h00") + T_3516.valid := network.release.valid + T_3516.bits <> network.release.bits.payload + network.release.ready := T_3516.ready + manager.release <> T_3516 + wire T_3640 : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}} + T_3640.bits.manager_xact_id := UInt<1>("h00") + T_3640.valid := UInt<1>("h00") + T_3640.ready := UInt<1>("h00") + T_3640.valid := network.finish.valid + T_3640.bits <> network.finish.bits.payload + network.finish.ready := T_3640.ready + manager.finish <> T_3640 + + module Queue_25 : + output count : UInt<1> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.payload.voluntary := UInt<1>("h00") + deq.bits.payload.r_type := UInt<1>("h00") + deq.bits.payload.data := UInt<1>("h00") + deq.bits.payload.addr_beat := UInt<1>("h00") + deq.bits.payload.client_xact_id := UInt<1>("h00") + deq.bits.payload.addr_block := UInt<1>("h00") + deq.bits.header.dst := UInt<1>("h00") + deq.bits.header.src := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[1], clock + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_327 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_327) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_333 = and(enq.ready, enq.valid) + node T_335 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_333, T_335) + node T_337 = and(deq.ready, deq.valid) + node T_339 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_337, T_339) + when do_enq : + infer accessor T_341 = ram[UInt<1>("h00")] + T_341 <> enq.bits + skip + when do_deq : + skip + node T_377 = neq(do_enq, do_deq) + when T_377 : + maybe_full := do_enq + skip + node T_379 = eq(empty, UInt<1>("h00")) + node T_381 = and(UInt<1>("h00"), enq.valid) + node T_382 = or(T_379, T_381) + deq.valid := T_382 + node T_384 = eq(full, UInt<1>("h00")) + node T_386 = and(UInt<1>("h00"), deq.ready) + node T_387 = or(T_384, T_386) + enq.ready := T_387 + infer accessor T_388 = ram[UInt<1>("h00")] + wire T_456 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} + T_456 <> T_388 + when maybe_flow : + T_456 <> enq.bits + skip + deq.bits <> T_456 + node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) + node T_491 = and(maybe_full, ptr_match) + node T_492 = cat(T_491, ptr_diff) + count := T_492 + + module TileLinkEnqueuer_24 : + output manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} + input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} + input clock : Clock + input reset : UInt<1> + + manager.release.bits.payload.voluntary := UInt<1>("h00") + manager.release.bits.payload.r_type := UInt<1>("h00") + manager.release.bits.payload.data := UInt<1>("h00") + manager.release.bits.payload.addr_beat := UInt<1>("h00") + manager.release.bits.payload.client_xact_id := UInt<1>("h00") + manager.release.bits.payload.addr_block := UInt<1>("h00") + manager.release.bits.header.dst := UInt<1>("h00") + manager.release.bits.header.src := UInt<1>("h00") + manager.release.valid := UInt<1>("h00") + manager.probe.ready := UInt<1>("h00") + manager.finish.bits.payload.manager_xact_id := UInt<1>("h00") + manager.finish.bits.header.dst := UInt<1>("h00") + manager.finish.bits.header.src := UInt<1>("h00") + manager.finish.valid := UInt<1>("h00") + manager.grant.ready := UInt<1>("h00") + manager.acquire.bits.payload.union := UInt<1>("h00") + manager.acquire.bits.payload.a_type := UInt<1>("h00") + manager.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + manager.acquire.bits.payload.data := UInt<1>("h00") + manager.acquire.bits.payload.addr_beat := UInt<1>("h00") + manager.acquire.bits.payload.client_xact_id := UInt<1>("h00") + manager.acquire.bits.payload.addr_block := UInt<1>("h00") + manager.acquire.bits.header.dst := UInt<1>("h00") + manager.acquire.bits.header.src := UInt<1>("h00") + manager.acquire.valid := UInt<1>("h00") + client.release.ready := UInt<1>("h00") + client.probe.bits.payload.p_type := UInt<1>("h00") + client.probe.bits.payload.addr_block := UInt<1>("h00") + client.probe.bits.header.dst := UInt<1>("h00") + client.probe.bits.header.src := UInt<1>("h00") + client.probe.valid := UInt<1>("h00") + client.finish.ready := UInt<1>("h00") + client.grant.bits.payload.g_type := UInt<1>("h00") + client.grant.bits.payload.is_builtin_type := UInt<1>("h00") + client.grant.bits.payload.manager_xact_id := UInt<1>("h00") + client.grant.bits.payload.client_xact_id := UInt<1>("h00") + client.grant.bits.payload.data := UInt<1>("h00") + client.grant.bits.payload.addr_beat := UInt<1>("h00") + client.grant.bits.header.dst := UInt<1>("h00") + client.grant.bits.header.src := UInt<1>("h00") + client.grant.valid := UInt<1>("h00") + client.acquire.ready := UInt<1>("h00") + manager.acquire <> client.acquire + client.probe <> manager.probe + inst T_2451 of Queue_25 + T_2451.deq.ready := UInt<1>("h00") + T_2451.enq.bits.payload.voluntary := UInt<1>("h00") + T_2451.enq.bits.payload.r_type := UInt<1>("h00") + T_2451.enq.bits.payload.data := UInt<1>("h00") + T_2451.enq.bits.payload.addr_beat := UInt<1>("h00") + T_2451.enq.bits.payload.client_xact_id := UInt<1>("h00") + T_2451.enq.bits.payload.addr_block := UInt<1>("h00") + T_2451.enq.bits.header.dst := UInt<1>("h00") + T_2451.enq.bits.header.src := UInt<1>("h00") + T_2451.enq.valid := UInt<1>("h00") + T_2451.reset := UInt<1>("h00") + T_2451.clock := clock + T_2451.reset := reset + T_2451.enq.valid := client.release.valid + T_2451.enq.bits <> client.release.bits + client.release.ready := T_2451.enq.ready + manager.release <> T_2451.deq + client.grant <> manager.grant + manager.finish <> client.finish + + module LockingRRArbiter : + output chosen : UInt<2> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}[3] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.payload.union := UInt<1>("h00") + out.bits.payload.a_type := UInt<1>("h00") + out.bits.payload.is_builtin_type := UInt<1>("h00") + out.bits.payload.data := UInt<1>("h00") + out.bits.payload.addr_beat := UInt<1>("h00") + out.bits.payload.client_xact_id := UInt<1>("h00") + out.bits.payload.addr_block := UInt<1>("h00") + out.bits.header.dst := UInt<1>("h00") + out.bits.header.src := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + in[2].ready := UInt<1>("h00") + reg T_956 : UInt<1>, clock, reset + onreset T_956 := UInt<1>("h00") + reg T_958 : UInt<?>, clock, reset + onreset T_958 := UInt<2>("h02") + wire T_960 : UInt<2> + T_960 := UInt<1>("h00") + infer accessor T_962 = in[T_960] + out.valid := T_962.valid + infer accessor T_1035 = in[T_960] + out.bits <> T_1035.bits + chosen := T_960 + infer accessor T_1108 = in[T_960] + T_1108.ready := UInt<1>("h00") + reg last_grant : UInt<2>, clock, reset + onreset last_grant := UInt<2>("h00") + node T_1185 = gt(UInt<1>("h00"), last_grant) + node T_1186 = and(in[0].valid, T_1185) + node T_1188 = gt(UInt<1>("h01"), last_grant) + node T_1189 = and(in[1].valid, T_1188) + node T_1191 = gt(UInt<2>("h02"), last_grant) + node T_1192 = and(in[2].valid, T_1191) + node T_1195 = or(UInt<1>("h00"), T_1186) + node T_1197 = eq(T_1195, UInt<1>("h00")) + node T_1199 = or(UInt<1>("h00"), T_1186) + node T_1200 = or(T_1199, T_1189) + node T_1202 = eq(T_1200, UInt<1>("h00")) + node T_1204 = or(UInt<1>("h00"), T_1186) + node T_1205 = or(T_1204, T_1189) + node T_1206 = or(T_1205, T_1192) + node T_1208 = eq(T_1206, UInt<1>("h00")) + node T_1210 = or(UInt<1>("h00"), T_1186) + node T_1211 = or(T_1210, T_1189) + node T_1212 = or(T_1211, T_1192) + node T_1213 = or(T_1212, in[0].valid) + node T_1215 = eq(T_1213, UInt<1>("h00")) + node T_1217 = or(UInt<1>("h00"), T_1186) + node T_1218 = or(T_1217, T_1189) + node T_1219 = or(T_1218, T_1192) + node T_1220 = or(T_1219, in[0].valid) + node T_1221 = or(T_1220, in[1].valid) + node T_1223 = eq(T_1221, UInt<1>("h00")) + node T_1225 = gt(UInt<1>("h00"), last_grant) + node T_1226 = and(UInt<1>("h01"), T_1225) + node T_1227 = or(T_1226, T_1208) + node T_1229 = gt(UInt<1>("h01"), last_grant) + node T_1230 = and(T_1197, T_1229) + node T_1231 = or(T_1230, T_1215) + node T_1233 = gt(UInt<2>("h02"), last_grant) + node T_1234 = and(T_1202, T_1233) + node T_1235 = or(T_1234, T_1223) + node T_1237 = eq(T_958, UInt<1>("h00")) + node T_1238 = mux(T_956, T_1237, T_1227) + node T_1239 = and(T_1238, out.ready) + in[0].ready := T_1239 + node T_1241 = eq(T_958, UInt<1>("h01")) + node T_1242 = mux(T_956, T_1241, T_1231) + node T_1243 = and(T_1242, out.ready) + in[1].ready := T_1243 + node T_1245 = eq(T_958, UInt<2>("h02")) + node T_1246 = mux(T_956, T_1245, T_1235) + node T_1247 = and(T_1246, out.ready) + in[2].ready := T_1247 + reg T_1249 : UInt<2>, clock, reset + onreset T_1249 := UInt<2>("h00") + node T_1251 = addw(T_1249, UInt<1>("h01")) + node T_1252 = and(out.ready, out.valid) + when T_1252 : + node T_1254 = and(UInt<1>("h01"), out.bits.payload.is_builtin_type) + wire T_1257 : UInt<3>[1] + T_1257[0] := UInt<3>("h03") + node T_1260 = eq(T_1257[0], out.bits.payload.a_type) + node T_1262 = or(UInt<1>("h00"), T_1260) + node T_1263 = and(T_1254, T_1262) + when T_1263 : + T_1249 := T_1251 + node T_1265 = eq(T_956, UInt<1>("h00")) + when T_1265 : + T_956 := UInt<1>("h01") + node T_1267 = and(in[0].ready, in[0].valid) + node T_1268 = and(in[1].ready, in[1].valid) + node T_1269 = and(in[2].ready, in[2].valid) + wire T_1271 : UInt<1>[3] + T_1271[0] := T_1267 + T_1271[1] := T_1268 + T_1271[2] := T_1269 + node T_1279 = mux(T_1271[1], UInt<1>("h01"), UInt<2>("h02")) + node T_1280 = mux(T_1271[0], UInt<1>("h00"), T_1279) + T_958 := T_1280 + skip + skip + node T_1282 = eq(T_1251, UInt<1>("h00")) + when T_1282 : + T_956 := UInt<1>("h00") + skip + skip + node T_1286 = mux(in[1].valid, UInt<1>("h01"), UInt<2>("h02")) + node T_1288 = mux(in[0].valid, UInt<1>("h00"), T_1286) + node T_1290 = gt(UInt<2>("h02"), last_grant) + node T_1291 = and(in[2].valid, T_1290) + node T_1293 = mux(T_1291, UInt<2>("h02"), T_1288) + node T_1295 = gt(UInt<1>("h01"), last_grant) + node T_1296 = and(in[1].valid, T_1295) + node choose = mux(T_1296, UInt<1>("h01"), T_1293) + node T_1299 = mux(T_956, T_958, choose) + T_960 := T_1299 + node T_1300 = and(out.ready, out.valid) + when T_1300 : + last_grant := T_960 + skip + + module LockingRRArbiter_26 : + output chosen : UInt<2> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[3] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.payload.voluntary := UInt<1>("h00") + out.bits.payload.r_type := UInt<1>("h00") + out.bits.payload.data := UInt<1>("h00") + out.bits.payload.addr_beat := UInt<1>("h00") + out.bits.payload.client_xact_id := UInt<1>("h00") + out.bits.payload.addr_block := UInt<1>("h00") + out.bits.header.dst := UInt<1>("h00") + out.bits.header.src := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + in[2].ready := UInt<1>("h00") + reg T_930 : UInt<1>, clock, reset + onreset T_930 := UInt<1>("h00") + reg T_932 : UInt<?>, clock, reset + onreset T_932 := UInt<2>("h02") + wire T_934 : UInt<2> + T_934 := UInt<1>("h00") + infer accessor T_936 = in[T_934] + out.valid := T_936.valid + infer accessor T_1007 = in[T_934] + out.bits <> T_1007.bits + chosen := T_934 + infer accessor T_1078 = in[T_934] + T_1078.ready := UInt<1>("h00") + reg last_grant : UInt<2>, clock, reset + onreset last_grant := UInt<2>("h00") + node T_1153 = gt(UInt<1>("h00"), last_grant) + node T_1154 = and(in[0].valid, T_1153) + node T_1156 = gt(UInt<1>("h01"), last_grant) + node T_1157 = and(in[1].valid, T_1156) + node T_1159 = gt(UInt<2>("h02"), last_grant) + node T_1160 = and(in[2].valid, T_1159) + node T_1163 = or(UInt<1>("h00"), T_1154) + node T_1165 = eq(T_1163, UInt<1>("h00")) + node T_1167 = or(UInt<1>("h00"), T_1154) + node T_1168 = or(T_1167, T_1157) + node T_1170 = eq(T_1168, UInt<1>("h00")) + node T_1172 = or(UInt<1>("h00"), T_1154) + node T_1173 = or(T_1172, T_1157) + node T_1174 = or(T_1173, T_1160) + node T_1176 = eq(T_1174, UInt<1>("h00")) + node T_1178 = or(UInt<1>("h00"), T_1154) + node T_1179 = or(T_1178, T_1157) + node T_1180 = or(T_1179, T_1160) + node T_1181 = or(T_1180, in[0].valid) + node T_1183 = eq(T_1181, UInt<1>("h00")) + node T_1185 = or(UInt<1>("h00"), T_1154) + node T_1186 = or(T_1185, T_1157) + node T_1187 = or(T_1186, T_1160) + node T_1188 = or(T_1187, in[0].valid) + node T_1189 = or(T_1188, in[1].valid) + node T_1191 = eq(T_1189, UInt<1>("h00")) + node T_1193 = gt(UInt<1>("h00"), last_grant) + node T_1194 = and(UInt<1>("h01"), T_1193) + node T_1195 = or(T_1194, T_1176) + node T_1197 = gt(UInt<1>("h01"), last_grant) + node T_1198 = and(T_1165, T_1197) + node T_1199 = or(T_1198, T_1183) + node T_1201 = gt(UInt<2>("h02"), last_grant) + node T_1202 = and(T_1170, T_1201) + node T_1203 = or(T_1202, T_1191) + node T_1205 = eq(T_932, UInt<1>("h00")) + node T_1206 = mux(T_930, T_1205, T_1195) + node T_1207 = and(T_1206, out.ready) + in[0].ready := T_1207 + node T_1209 = eq(T_932, UInt<1>("h01")) + node T_1210 = mux(T_930, T_1209, T_1199) + node T_1211 = and(T_1210, out.ready) + in[1].ready := T_1211 + node T_1213 = eq(T_932, UInt<2>("h02")) + node T_1214 = mux(T_930, T_1213, T_1203) + node T_1215 = and(T_1214, out.ready) + in[2].ready := T_1215 + reg T_1217 : UInt<2>, clock, reset + onreset T_1217 := UInt<2>("h00") + node T_1219 = addw(T_1217, UInt<1>("h01")) + node T_1220 = and(out.ready, out.valid) + when T_1220 : + wire T_1223 : UInt<2>[3] + T_1223[0] := UInt<1>("h00") + T_1223[1] := UInt<1>("h01") + T_1223[2] := UInt<2>("h02") + node T_1228 = eq(T_1223[0], out.bits.payload.r_type) + node T_1229 = eq(T_1223[1], out.bits.payload.r_type) + node T_1230 = eq(T_1223[2], out.bits.payload.r_type) + node T_1232 = or(UInt<1>("h00"), T_1228) + node T_1233 = or(T_1232, T_1229) + node T_1234 = or(T_1233, T_1230) + node T_1235 = and(UInt<1>("h01"), T_1234) + when T_1235 : + T_1217 := T_1219 + node T_1237 = eq(T_930, UInt<1>("h00")) + when T_1237 : + T_930 := UInt<1>("h01") + node T_1239 = and(in[0].ready, in[0].valid) + node T_1240 = and(in[1].ready, in[1].valid) + node T_1241 = and(in[2].ready, in[2].valid) + wire T_1243 : UInt<1>[3] + T_1243[0] := T_1239 + T_1243[1] := T_1240 + T_1243[2] := T_1241 + node T_1251 = mux(T_1243[1], UInt<1>("h01"), UInt<2>("h02")) + node T_1252 = mux(T_1243[0], UInt<1>("h00"), T_1251) + T_932 := T_1252 + skip + skip + node T_1254 = eq(T_1219, UInt<1>("h00")) + when T_1254 : + T_930 := UInt<1>("h00") + skip + skip + node T_1258 = mux(in[1].valid, UInt<1>("h01"), UInt<2>("h02")) + node T_1260 = mux(in[0].valid, UInt<1>("h00"), T_1258) + node T_1262 = gt(UInt<2>("h02"), last_grant) + node T_1263 = and(in[2].valid, T_1262) + node T_1265 = mux(T_1263, UInt<2>("h02"), T_1260) + node T_1267 = gt(UInt<1>("h01"), last_grant) + node T_1268 = and(in[1].valid, T_1267) + node choose = mux(T_1268, UInt<1>("h01"), T_1265) + node T_1271 = mux(T_930, T_932, choose) + T_934 := T_1271 + node T_1272 = and(out.ready, out.valid) + when T_1272 : + last_grant := T_934 + skip + + module RRArbiter : + output chosen : UInt<2> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}[3] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.payload.manager_xact_id := UInt<1>("h00") + out.bits.header.dst := UInt<1>("h00") + out.bits.header.src := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + in[2].ready := UInt<1>("h00") + wire T_802 : UInt<2> + T_802 := UInt<1>("h00") + infer accessor T_804 = in[T_802] + out.valid := T_804.valid + infer accessor T_865 = in[T_802] + out.bits <> T_865.bits + chosen := T_802 + infer accessor T_926 = in[T_802] + T_926.ready := UInt<1>("h00") + reg T_990 : UInt<2>, clock, reset + onreset T_990 := UInt<2>("h00") + node T_991 = gt(UInt<1>("h00"), T_990) + node T_992 = and(in[0].valid, T_991) + node T_994 = gt(UInt<1>("h01"), T_990) + node T_995 = and(in[1].valid, T_994) + node T_997 = gt(UInt<2>("h02"), T_990) + node T_998 = and(in[2].valid, T_997) + node T_1001 = or(UInt<1>("h00"), T_992) + node T_1003 = eq(T_1001, UInt<1>("h00")) + node T_1005 = or(UInt<1>("h00"), T_992) + node T_1006 = or(T_1005, T_995) + node T_1008 = eq(T_1006, UInt<1>("h00")) + node T_1010 = or(UInt<1>("h00"), T_992) + node T_1011 = or(T_1010, T_995) + node T_1012 = or(T_1011, T_998) + node T_1014 = eq(T_1012, UInt<1>("h00")) + node T_1016 = or(UInt<1>("h00"), T_992) + node T_1017 = or(T_1016, T_995) + node T_1018 = or(T_1017, T_998) + node T_1019 = or(T_1018, in[0].valid) + node T_1021 = eq(T_1019, UInt<1>("h00")) + node T_1023 = or(UInt<1>("h00"), T_992) + node T_1024 = or(T_1023, T_995) + node T_1025 = or(T_1024, T_998) + node T_1026 = or(T_1025, in[0].valid) + node T_1027 = or(T_1026, in[1].valid) + node T_1029 = eq(T_1027, UInt<1>("h00")) + node T_1031 = gt(UInt<1>("h00"), T_990) + node T_1032 = and(UInt<1>("h01"), T_1031) + node T_1033 = or(T_1032, T_1014) + node T_1035 = gt(UInt<1>("h01"), T_990) + node T_1036 = and(T_1003, T_1035) + node T_1037 = or(T_1036, T_1021) + node T_1039 = gt(UInt<2>("h02"), T_990) + node T_1040 = and(T_1008, T_1039) + node T_1041 = or(T_1040, T_1029) + node T_1043 = eq(UInt<2>("h02"), UInt<1>("h00")) + node T_1044 = mux(UInt<1>("h00"), T_1043, T_1033) + node T_1045 = and(T_1044, out.ready) + in[0].ready := T_1045 + node T_1047 = eq(UInt<2>("h02"), UInt<1>("h01")) + node T_1048 = mux(UInt<1>("h00"), T_1047, T_1037) + node T_1049 = and(T_1048, out.ready) + in[1].ready := T_1049 + node T_1051 = eq(UInt<2>("h02"), UInt<2>("h02")) + node T_1052 = mux(UInt<1>("h00"), T_1051, T_1041) + node T_1053 = and(T_1052, out.ready) + in[2].ready := T_1053 + node T_1056 = mux(in[1].valid, UInt<1>("h01"), UInt<2>("h02")) + node T_1058 = mux(in[0].valid, UInt<1>("h00"), T_1056) + node T_1060 = gt(UInt<2>("h02"), T_990) + node T_1061 = and(in[2].valid, T_1060) + node T_1063 = mux(T_1061, UInt<2>("h02"), T_1058) + node T_1065 = gt(UInt<1>("h01"), T_990) + node T_1066 = and(in[1].valid, T_1065) + node T_1068 = mux(T_1066, UInt<1>("h01"), T_1063) + node T_1069 = mux(UInt<1>("h00"), UInt<2>("h02"), T_1068) + T_802 := T_1069 + node T_1070 = and(out.ready, out.valid) + when T_1070 : + T_990 := T_802 + skip + + module RocketChipTileLinkArbiter : + input managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}[1] + input clients : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[3] + input clock : Clock + input reset : UInt<1> + + managers[0].release.bits.client_id := UInt<1>("h00") + managers[0].release.bits.voluntary := UInt<1>("h00") + managers[0].release.bits.r_type := UInt<1>("h00") + managers[0].release.bits.data := UInt<1>("h00") + managers[0].release.bits.addr_beat := UInt<1>("h00") + managers[0].release.bits.client_xact_id := UInt<1>("h00") + managers[0].release.bits.addr_block := UInt<1>("h00") + managers[0].release.valid := UInt<1>("h00") + managers[0].probe.ready := UInt<1>("h00") + managers[0].finish.bits.manager_xact_id := UInt<1>("h00") + managers[0].finish.valid := UInt<1>("h00") + managers[0].grant.ready := UInt<1>("h00") + managers[0].acquire.bits.client_id := UInt<1>("h00") + managers[0].acquire.bits.union := UInt<1>("h00") + managers[0].acquire.bits.a_type := UInt<1>("h00") + managers[0].acquire.bits.is_builtin_type := UInt<1>("h00") + managers[0].acquire.bits.data := UInt<1>("h00") + managers[0].acquire.bits.addr_beat := UInt<1>("h00") + managers[0].acquire.bits.client_xact_id := UInt<1>("h00") + managers[0].acquire.bits.addr_block := UInt<1>("h00") + managers[0].acquire.valid := UInt<1>("h00") + clients[0].release.ready := UInt<1>("h00") + clients[0].probe.bits.p_type := UInt<1>("h00") + clients[0].probe.bits.addr_block := UInt<1>("h00") + clients[0].probe.valid := UInt<1>("h00") + clients[0].grant.bits.g_type := UInt<1>("h00") + clients[0].grant.bits.is_builtin_type := UInt<1>("h00") + clients[0].grant.bits.manager_xact_id := UInt<1>("h00") + clients[0].grant.bits.client_xact_id := UInt<1>("h00") + clients[0].grant.bits.data := UInt<1>("h00") + clients[0].grant.bits.addr_beat := UInt<1>("h00") + clients[0].grant.valid := UInt<1>("h00") + clients[0].acquire.ready := UInt<1>("h00") + clients[1].release.ready := UInt<1>("h00") + clients[1].probe.bits.p_type := UInt<1>("h00") + clients[1].probe.bits.addr_block := UInt<1>("h00") + clients[1].probe.valid := UInt<1>("h00") + clients[1].grant.bits.g_type := UInt<1>("h00") + clients[1].grant.bits.is_builtin_type := UInt<1>("h00") + clients[1].grant.bits.manager_xact_id := UInt<1>("h00") + clients[1].grant.bits.client_xact_id := UInt<1>("h00") + clients[1].grant.bits.data := UInt<1>("h00") + clients[1].grant.bits.addr_beat := UInt<1>("h00") + clients[1].grant.valid := UInt<1>("h00") + clients[1].acquire.ready := UInt<1>("h00") + clients[2].release.ready := UInt<1>("h00") + clients[2].probe.bits.p_type := UInt<1>("h00") + clients[2].probe.bits.addr_block := UInt<1>("h00") + clients[2].probe.valid := UInt<1>("h00") + clients[2].grant.bits.g_type := UInt<1>("h00") + clients[2].grant.bits.is_builtin_type := UInt<1>("h00") + clients[2].grant.bits.manager_xact_id := UInt<1>("h00") + clients[2].grant.bits.client_xact_id := UInt<1>("h00") + clients[2].grant.bits.data := UInt<1>("h00") + clients[2].grant.bits.addr_beat := UInt<1>("h00") + clients[2].grant.valid := UInt<1>("h00") + clients[2].acquire.ready := UInt<1>("h00") + inst T_11799 of ClientTileLinkNetworkPort + T_11799.network.release.ready := UInt<1>("h00") + T_11799.network.probe.bits.payload.p_type := UInt<1>("h00") + T_11799.network.probe.bits.payload.addr_block := UInt<1>("h00") + T_11799.network.probe.bits.header.dst := UInt<1>("h00") + T_11799.network.probe.bits.header.src := UInt<1>("h00") + T_11799.network.probe.valid := UInt<1>("h00") + T_11799.network.finish.ready := UInt<1>("h00") + T_11799.network.grant.bits.payload.g_type := UInt<1>("h00") + T_11799.network.grant.bits.payload.is_builtin_type := UInt<1>("h00") + T_11799.network.grant.bits.payload.manager_xact_id := UInt<1>("h00") + T_11799.network.grant.bits.payload.client_xact_id := UInt<1>("h00") + T_11799.network.grant.bits.payload.data := UInt<1>("h00") + T_11799.network.grant.bits.payload.addr_beat := UInt<1>("h00") + T_11799.network.grant.bits.header.dst := UInt<1>("h00") + T_11799.network.grant.bits.header.src := UInt<1>("h00") + T_11799.network.grant.valid := UInt<1>("h00") + T_11799.network.acquire.ready := UInt<1>("h00") + T_11799.client.release.bits.voluntary := UInt<1>("h00") + T_11799.client.release.bits.r_type := UInt<1>("h00") + T_11799.client.release.bits.data := UInt<1>("h00") + T_11799.client.release.bits.addr_beat := UInt<1>("h00") + T_11799.client.release.bits.client_xact_id := UInt<1>("h00") + T_11799.client.release.bits.addr_block := UInt<1>("h00") + T_11799.client.release.valid := UInt<1>("h00") + T_11799.client.probe.ready := UInt<1>("h00") + T_11799.client.grant.ready := UInt<1>("h00") + T_11799.client.acquire.bits.union := UInt<1>("h00") + T_11799.client.acquire.bits.a_type := UInt<1>("h00") + T_11799.client.acquire.bits.is_builtin_type := UInt<1>("h00") + T_11799.client.acquire.bits.data := UInt<1>("h00") + T_11799.client.acquire.bits.addr_beat := UInt<1>("h00") + T_11799.client.acquire.bits.client_xact_id := UInt<1>("h00") + T_11799.client.acquire.bits.addr_block := UInt<1>("h00") + T_11799.client.acquire.valid := UInt<1>("h00") + T_11799.reset := UInt<1>("h00") + T_11799.clock := clock + T_11799.reset := reset + inst T_11800 of TileLinkEnqueuer + T_11800.manager.release.ready := UInt<1>("h00") + T_11800.manager.probe.bits.payload.p_type := UInt<1>("h00") + T_11800.manager.probe.bits.payload.addr_block := UInt<1>("h00") + T_11800.manager.probe.bits.header.dst := UInt<1>("h00") + T_11800.manager.probe.bits.header.src := UInt<1>("h00") + T_11800.manager.probe.valid := UInt<1>("h00") + T_11800.manager.finish.ready := UInt<1>("h00") + T_11800.manager.grant.bits.payload.g_type := UInt<1>("h00") + T_11800.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") + T_11800.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") + T_11800.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") + T_11800.manager.grant.bits.payload.data := UInt<1>("h00") + T_11800.manager.grant.bits.payload.addr_beat := UInt<1>("h00") + T_11800.manager.grant.bits.header.dst := UInt<1>("h00") + T_11800.manager.grant.bits.header.src := UInt<1>("h00") + T_11800.manager.grant.valid := UInt<1>("h00") + T_11800.manager.acquire.ready := UInt<1>("h00") + T_11800.client.release.bits.payload.voluntary := UInt<1>("h00") + T_11800.client.release.bits.payload.r_type := UInt<1>("h00") + T_11800.client.release.bits.payload.data := UInt<1>("h00") + T_11800.client.release.bits.payload.addr_beat := UInt<1>("h00") + T_11800.client.release.bits.payload.client_xact_id := UInt<1>("h00") + T_11800.client.release.bits.payload.addr_block := UInt<1>("h00") + T_11800.client.release.bits.header.dst := UInt<1>("h00") + T_11800.client.release.bits.header.src := UInt<1>("h00") + T_11800.client.release.valid := UInt<1>("h00") + T_11800.client.probe.ready := UInt<1>("h00") + T_11800.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") + T_11800.client.finish.bits.header.dst := UInt<1>("h00") + T_11800.client.finish.bits.header.src := UInt<1>("h00") + T_11800.client.finish.valid := UInt<1>("h00") + T_11800.client.grant.ready := UInt<1>("h00") + T_11800.client.acquire.bits.payload.union := UInt<1>("h00") + T_11800.client.acquire.bits.payload.a_type := UInt<1>("h00") + T_11800.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + T_11800.client.acquire.bits.payload.data := UInt<1>("h00") + T_11800.client.acquire.bits.payload.addr_beat := UInt<1>("h00") + T_11800.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") + T_11800.client.acquire.bits.payload.addr_block := UInt<1>("h00") + T_11800.client.acquire.bits.header.dst := UInt<1>("h00") + T_11800.client.acquire.bits.header.src := UInt<1>("h00") + T_11800.client.acquire.valid := UInt<1>("h00") + T_11800.reset := UInt<1>("h00") + T_11800.clock := clock + T_11800.reset := reset + T_11799.client <> clients[0] + T_11800.client <> T_11799.network + inst T_11801 of ClientTileLinkNetworkPort_6 + T_11801.network.release.ready := UInt<1>("h00") + T_11801.network.probe.bits.payload.p_type := UInt<1>("h00") + T_11801.network.probe.bits.payload.addr_block := UInt<1>("h00") + T_11801.network.probe.bits.header.dst := UInt<1>("h00") + T_11801.network.probe.bits.header.src := UInt<1>("h00") + T_11801.network.probe.valid := UInt<1>("h00") + T_11801.network.finish.ready := UInt<1>("h00") + T_11801.network.grant.bits.payload.g_type := UInt<1>("h00") + T_11801.network.grant.bits.payload.is_builtin_type := UInt<1>("h00") + T_11801.network.grant.bits.payload.manager_xact_id := UInt<1>("h00") + T_11801.network.grant.bits.payload.client_xact_id := UInt<1>("h00") + T_11801.network.grant.bits.payload.data := UInt<1>("h00") + T_11801.network.grant.bits.payload.addr_beat := UInt<1>("h00") + T_11801.network.grant.bits.header.dst := UInt<1>("h00") + T_11801.network.grant.bits.header.src := UInt<1>("h00") + T_11801.network.grant.valid := UInt<1>("h00") + T_11801.network.acquire.ready := UInt<1>("h00") + T_11801.client.release.bits.voluntary := UInt<1>("h00") + T_11801.client.release.bits.r_type := UInt<1>("h00") + T_11801.client.release.bits.data := UInt<1>("h00") + T_11801.client.release.bits.addr_beat := UInt<1>("h00") + T_11801.client.release.bits.client_xact_id := UInt<1>("h00") + T_11801.client.release.bits.addr_block := UInt<1>("h00") + T_11801.client.release.valid := UInt<1>("h00") + T_11801.client.probe.ready := UInt<1>("h00") + T_11801.client.grant.ready := UInt<1>("h00") + T_11801.client.acquire.bits.union := UInt<1>("h00") + T_11801.client.acquire.bits.a_type := UInt<1>("h00") + T_11801.client.acquire.bits.is_builtin_type := UInt<1>("h00") + T_11801.client.acquire.bits.data := UInt<1>("h00") + T_11801.client.acquire.bits.addr_beat := UInt<1>("h00") + T_11801.client.acquire.bits.client_xact_id := UInt<1>("h00") + T_11801.client.acquire.bits.addr_block := UInt<1>("h00") + T_11801.client.acquire.valid := UInt<1>("h00") + T_11801.reset := UInt<1>("h00") + T_11801.clock := clock + T_11801.reset := reset + inst T_11802 of TileLinkEnqueuer + T_11802.manager.release.ready := UInt<1>("h00") + T_11802.manager.probe.bits.payload.p_type := UInt<1>("h00") + T_11802.manager.probe.bits.payload.addr_block := UInt<1>("h00") + T_11802.manager.probe.bits.header.dst := UInt<1>("h00") + T_11802.manager.probe.bits.header.src := UInt<1>("h00") + T_11802.manager.probe.valid := UInt<1>("h00") + T_11802.manager.finish.ready := UInt<1>("h00") + T_11802.manager.grant.bits.payload.g_type := UInt<1>("h00") + T_11802.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") + T_11802.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") + T_11802.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") + T_11802.manager.grant.bits.payload.data := UInt<1>("h00") + T_11802.manager.grant.bits.payload.addr_beat := UInt<1>("h00") + T_11802.manager.grant.bits.header.dst := UInt<1>("h00") + T_11802.manager.grant.bits.header.src := UInt<1>("h00") + T_11802.manager.grant.valid := UInt<1>("h00") + T_11802.manager.acquire.ready := UInt<1>("h00") + T_11802.client.release.bits.payload.voluntary := UInt<1>("h00") + T_11802.client.release.bits.payload.r_type := UInt<1>("h00") + T_11802.client.release.bits.payload.data := UInt<1>("h00") + T_11802.client.release.bits.payload.addr_beat := UInt<1>("h00") + T_11802.client.release.bits.payload.client_xact_id := UInt<1>("h00") + T_11802.client.release.bits.payload.addr_block := UInt<1>("h00") + T_11802.client.release.bits.header.dst := UInt<1>("h00") + T_11802.client.release.bits.header.src := UInt<1>("h00") + T_11802.client.release.valid := UInt<1>("h00") + T_11802.client.probe.ready := UInt<1>("h00") + T_11802.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") + T_11802.client.finish.bits.header.dst := UInt<1>("h00") + T_11802.client.finish.bits.header.src := UInt<1>("h00") + T_11802.client.finish.valid := UInt<1>("h00") + T_11802.client.grant.ready := UInt<1>("h00") + T_11802.client.acquire.bits.payload.union := UInt<1>("h00") + T_11802.client.acquire.bits.payload.a_type := UInt<1>("h00") + T_11802.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + T_11802.client.acquire.bits.payload.data := UInt<1>("h00") + T_11802.client.acquire.bits.payload.addr_beat := UInt<1>("h00") + T_11802.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") + T_11802.client.acquire.bits.payload.addr_block := UInt<1>("h00") + T_11802.client.acquire.bits.header.dst := UInt<1>("h00") + T_11802.client.acquire.bits.header.src := UInt<1>("h00") + T_11802.client.acquire.valid := UInt<1>("h00") + T_11802.reset := UInt<1>("h00") + T_11802.clock := clock + T_11802.reset := reset + T_11801.client <> clients[1] + T_11802.client <> T_11801.network + inst T_11803 of ClientTileLinkNetworkPort_15 + T_11803.network.release.ready := UInt<1>("h00") + T_11803.network.probe.bits.payload.p_type := UInt<1>("h00") + T_11803.network.probe.bits.payload.addr_block := UInt<1>("h00") + T_11803.network.probe.bits.header.dst := UInt<1>("h00") + T_11803.network.probe.bits.header.src := UInt<1>("h00") + T_11803.network.probe.valid := UInt<1>("h00") + T_11803.network.finish.ready := UInt<1>("h00") + T_11803.network.grant.bits.payload.g_type := UInt<1>("h00") + T_11803.network.grant.bits.payload.is_builtin_type := UInt<1>("h00") + T_11803.network.grant.bits.payload.manager_xact_id := UInt<1>("h00") + T_11803.network.grant.bits.payload.client_xact_id := UInt<1>("h00") + T_11803.network.grant.bits.payload.data := UInt<1>("h00") + T_11803.network.grant.bits.payload.addr_beat := UInt<1>("h00") + T_11803.network.grant.bits.header.dst := UInt<1>("h00") + T_11803.network.grant.bits.header.src := UInt<1>("h00") + T_11803.network.grant.valid := UInt<1>("h00") + T_11803.network.acquire.ready := UInt<1>("h00") + T_11803.client.release.bits.voluntary := UInt<1>("h00") + T_11803.client.release.bits.r_type := UInt<1>("h00") + T_11803.client.release.bits.data := UInt<1>("h00") + T_11803.client.release.bits.addr_beat := UInt<1>("h00") + T_11803.client.release.bits.client_xact_id := UInt<1>("h00") + T_11803.client.release.bits.addr_block := UInt<1>("h00") + T_11803.client.release.valid := UInt<1>("h00") + T_11803.client.probe.ready := UInt<1>("h00") + T_11803.client.grant.ready := UInt<1>("h00") + T_11803.client.acquire.bits.union := UInt<1>("h00") + T_11803.client.acquire.bits.a_type := UInt<1>("h00") + T_11803.client.acquire.bits.is_builtin_type := UInt<1>("h00") + T_11803.client.acquire.bits.data := UInt<1>("h00") + T_11803.client.acquire.bits.addr_beat := UInt<1>("h00") + T_11803.client.acquire.bits.client_xact_id := UInt<1>("h00") + T_11803.client.acquire.bits.addr_block := UInt<1>("h00") + T_11803.client.acquire.valid := UInt<1>("h00") + T_11803.reset := UInt<1>("h00") + T_11803.clock := clock + T_11803.reset := reset + inst T_11804 of TileLinkEnqueuer + T_11804.manager.release.ready := UInt<1>("h00") + T_11804.manager.probe.bits.payload.p_type := UInt<1>("h00") + T_11804.manager.probe.bits.payload.addr_block := UInt<1>("h00") + T_11804.manager.probe.bits.header.dst := UInt<1>("h00") + T_11804.manager.probe.bits.header.src := UInt<1>("h00") + T_11804.manager.probe.valid := UInt<1>("h00") + T_11804.manager.finish.ready := UInt<1>("h00") + T_11804.manager.grant.bits.payload.g_type := UInt<1>("h00") + T_11804.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") + T_11804.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") + T_11804.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") + T_11804.manager.grant.bits.payload.data := UInt<1>("h00") + T_11804.manager.grant.bits.payload.addr_beat := UInt<1>("h00") + T_11804.manager.grant.bits.header.dst := UInt<1>("h00") + T_11804.manager.grant.bits.header.src := UInt<1>("h00") + T_11804.manager.grant.valid := UInt<1>("h00") + T_11804.manager.acquire.ready := UInt<1>("h00") + T_11804.client.release.bits.payload.voluntary := UInt<1>("h00") + T_11804.client.release.bits.payload.r_type := UInt<1>("h00") + T_11804.client.release.bits.payload.data := UInt<1>("h00") + T_11804.client.release.bits.payload.addr_beat := UInt<1>("h00") + T_11804.client.release.bits.payload.client_xact_id := UInt<1>("h00") + T_11804.client.release.bits.payload.addr_block := UInt<1>("h00") + T_11804.client.release.bits.header.dst := UInt<1>("h00") + T_11804.client.release.bits.header.src := UInt<1>("h00") + T_11804.client.release.valid := UInt<1>("h00") + T_11804.client.probe.ready := UInt<1>("h00") + T_11804.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") + T_11804.client.finish.bits.header.dst := UInt<1>("h00") + T_11804.client.finish.bits.header.src := UInt<1>("h00") + T_11804.client.finish.valid := UInt<1>("h00") + T_11804.client.grant.ready := UInt<1>("h00") + T_11804.client.acquire.bits.payload.union := UInt<1>("h00") + T_11804.client.acquire.bits.payload.a_type := UInt<1>("h00") + T_11804.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + T_11804.client.acquire.bits.payload.data := UInt<1>("h00") + T_11804.client.acquire.bits.payload.addr_beat := UInt<1>("h00") + T_11804.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") + T_11804.client.acquire.bits.payload.addr_block := UInt<1>("h00") + T_11804.client.acquire.bits.header.dst := UInt<1>("h00") + T_11804.client.acquire.bits.header.src := UInt<1>("h00") + T_11804.client.acquire.valid := UInt<1>("h00") + T_11804.reset := UInt<1>("h00") + T_11804.clock := clock + T_11804.reset := reset + T_11803.client <> clients[2] + T_11804.client <> T_11803.network + inst T_11805 of ManagerTileLinkNetworkPort + T_11805.network.release.bits.payload.voluntary := UInt<1>("h00") + T_11805.network.release.bits.payload.r_type := UInt<1>("h00") + T_11805.network.release.bits.payload.data := UInt<1>("h00") + T_11805.network.release.bits.payload.addr_beat := UInt<1>("h00") + T_11805.network.release.bits.payload.client_xact_id := UInt<1>("h00") + T_11805.network.release.bits.payload.addr_block := UInt<1>("h00") + T_11805.network.release.bits.header.dst := UInt<1>("h00") + T_11805.network.release.bits.header.src := UInt<1>("h00") + T_11805.network.release.valid := UInt<1>("h00") + T_11805.network.probe.ready := UInt<1>("h00") + T_11805.network.finish.bits.payload.manager_xact_id := UInt<1>("h00") + T_11805.network.finish.bits.header.dst := UInt<1>("h00") + T_11805.network.finish.bits.header.src := UInt<1>("h00") + T_11805.network.finish.valid := UInt<1>("h00") + T_11805.network.grant.ready := UInt<1>("h00") + T_11805.network.acquire.bits.payload.union := UInt<1>("h00") + T_11805.network.acquire.bits.payload.a_type := UInt<1>("h00") + T_11805.network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + T_11805.network.acquire.bits.payload.data := UInt<1>("h00") + T_11805.network.acquire.bits.payload.addr_beat := UInt<1>("h00") + T_11805.network.acquire.bits.payload.client_xact_id := UInt<1>("h00") + T_11805.network.acquire.bits.payload.addr_block := UInt<1>("h00") + T_11805.network.acquire.bits.header.dst := UInt<1>("h00") + T_11805.network.acquire.bits.header.src := UInt<1>("h00") + T_11805.network.acquire.valid := UInt<1>("h00") + T_11805.manager.release.ready := UInt<1>("h00") + T_11805.manager.probe.bits.client_id := UInt<1>("h00") + T_11805.manager.probe.bits.p_type := UInt<1>("h00") + T_11805.manager.probe.bits.addr_block := UInt<1>("h00") + T_11805.manager.probe.valid := UInt<1>("h00") + T_11805.manager.finish.ready := UInt<1>("h00") + T_11805.manager.grant.bits.client_id := UInt<1>("h00") + T_11805.manager.grant.bits.g_type := UInt<1>("h00") + T_11805.manager.grant.bits.is_builtin_type := UInt<1>("h00") + T_11805.manager.grant.bits.manager_xact_id := UInt<1>("h00") + T_11805.manager.grant.bits.client_xact_id := UInt<1>("h00") + T_11805.manager.grant.bits.data := UInt<1>("h00") + T_11805.manager.grant.bits.addr_beat := UInt<1>("h00") + T_11805.manager.grant.valid := UInt<1>("h00") + T_11805.manager.acquire.ready := UInt<1>("h00") + T_11805.reset := UInt<1>("h00") + T_11805.clock := clock + T_11805.reset := reset + inst T_11806 of TileLinkEnqueuer_24 + T_11806.manager.release.ready := UInt<1>("h00") + T_11806.manager.probe.bits.payload.p_type := UInt<1>("h00") + T_11806.manager.probe.bits.payload.addr_block := UInt<1>("h00") + T_11806.manager.probe.bits.header.dst := UInt<1>("h00") + T_11806.manager.probe.bits.header.src := UInt<1>("h00") + T_11806.manager.probe.valid := UInt<1>("h00") + T_11806.manager.finish.ready := UInt<1>("h00") + T_11806.manager.grant.bits.payload.g_type := UInt<1>("h00") + T_11806.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") + T_11806.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") + T_11806.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") + T_11806.manager.grant.bits.payload.data := UInt<1>("h00") + T_11806.manager.grant.bits.payload.addr_beat := UInt<1>("h00") + T_11806.manager.grant.bits.header.dst := UInt<1>("h00") + T_11806.manager.grant.bits.header.src := UInt<1>("h00") + T_11806.manager.grant.valid := UInt<1>("h00") + T_11806.manager.acquire.ready := UInt<1>("h00") + T_11806.client.release.bits.payload.voluntary := UInt<1>("h00") + T_11806.client.release.bits.payload.r_type := UInt<1>("h00") + T_11806.client.release.bits.payload.data := UInt<1>("h00") + T_11806.client.release.bits.payload.addr_beat := UInt<1>("h00") + T_11806.client.release.bits.payload.client_xact_id := UInt<1>("h00") + T_11806.client.release.bits.payload.addr_block := UInt<1>("h00") + T_11806.client.release.bits.header.dst := UInt<1>("h00") + T_11806.client.release.bits.header.src := UInt<1>("h00") + T_11806.client.release.valid := UInt<1>("h00") + T_11806.client.probe.ready := UInt<1>("h00") + T_11806.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") + T_11806.client.finish.bits.header.dst := UInt<1>("h00") + T_11806.client.finish.bits.header.src := UInt<1>("h00") + T_11806.client.finish.valid := UInt<1>("h00") + T_11806.client.grant.ready := UInt<1>("h00") + T_11806.client.acquire.bits.payload.union := UInt<1>("h00") + T_11806.client.acquire.bits.payload.a_type := UInt<1>("h00") + T_11806.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + T_11806.client.acquire.bits.payload.data := UInt<1>("h00") + T_11806.client.acquire.bits.payload.addr_beat := UInt<1>("h00") + T_11806.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") + T_11806.client.acquire.bits.payload.addr_block := UInt<1>("h00") + T_11806.client.acquire.bits.header.dst := UInt<1>("h00") + T_11806.client.acquire.bits.header.src := UInt<1>("h00") + T_11806.client.acquire.valid := UInt<1>("h00") + T_11806.reset := UInt<1>("h00") + T_11806.clock := clock + T_11806.reset := reset + T_11805.manager <> managers[0] + T_11805.network <> T_11806.manager + inst T_11807 of LockingRRArbiter + T_11807.out.ready := UInt<1>("h00") + T_11807.in[0].bits.payload.union := UInt<1>("h00") + T_11807.in[0].bits.payload.a_type := UInt<1>("h00") + T_11807.in[0].bits.payload.is_builtin_type := UInt<1>("h00") + T_11807.in[0].bits.payload.data := UInt<1>("h00") + T_11807.in[0].bits.payload.addr_beat := UInt<1>("h00") + T_11807.in[0].bits.payload.client_xact_id := UInt<1>("h00") + T_11807.in[0].bits.payload.addr_block := UInt<1>("h00") + T_11807.in[0].bits.header.dst := UInt<1>("h00") + T_11807.in[0].bits.header.src := UInt<1>("h00") + T_11807.in[0].valid := UInt<1>("h00") + T_11807.in[1].bits.payload.union := UInt<1>("h00") + T_11807.in[1].bits.payload.a_type := UInt<1>("h00") + T_11807.in[1].bits.payload.is_builtin_type := UInt<1>("h00") + T_11807.in[1].bits.payload.data := UInt<1>("h00") + T_11807.in[1].bits.payload.addr_beat := UInt<1>("h00") + T_11807.in[1].bits.payload.client_xact_id := UInt<1>("h00") + T_11807.in[1].bits.payload.addr_block := UInt<1>("h00") + T_11807.in[1].bits.header.dst := UInt<1>("h00") + T_11807.in[1].bits.header.src := UInt<1>("h00") + T_11807.in[1].valid := UInt<1>("h00") + T_11807.in[2].bits.payload.union := UInt<1>("h00") + T_11807.in[2].bits.payload.a_type := UInt<1>("h00") + T_11807.in[2].bits.payload.is_builtin_type := UInt<1>("h00") + T_11807.in[2].bits.payload.data := UInt<1>("h00") + T_11807.in[2].bits.payload.addr_beat := UInt<1>("h00") + T_11807.in[2].bits.payload.client_xact_id := UInt<1>("h00") + T_11807.in[2].bits.payload.addr_block := UInt<1>("h00") + T_11807.in[2].bits.header.dst := UInt<1>("h00") + T_11807.in[2].bits.header.src := UInt<1>("h00") + T_11807.in[2].valid := UInt<1>("h00") + T_11807.reset := UInt<1>("h00") + T_11807.clock := clock + T_11807.reset := reset + T_11807.in[0].valid := T_11800.manager.acquire.valid + T_11807.in[0].bits <> T_11800.manager.acquire.bits + T_11807.in[0].bits.payload.client_xact_id := T_11800.manager.acquire.bits.payload.client_xact_id + T_11800.manager.acquire.ready := T_11807.in[0].ready + T_11807.in[1].valid := T_11802.manager.acquire.valid + T_11807.in[1].bits <> T_11802.manager.acquire.bits + T_11807.in[1].bits.payload.client_xact_id := T_11802.manager.acquire.bits.payload.client_xact_id + T_11802.manager.acquire.ready := T_11807.in[1].ready + T_11807.in[2].valid := T_11804.manager.acquire.valid + T_11807.in[2].bits <> T_11804.manager.acquire.bits + T_11807.in[2].bits.payload.client_xact_id := T_11804.manager.acquire.bits.payload.client_xact_id + T_11804.manager.acquire.ready := T_11807.in[2].ready + T_11806.client.acquire <> T_11807.out + inst T_11808 of LockingRRArbiter_26 + T_11808.out.ready := UInt<1>("h00") + T_11808.in[0].bits.payload.voluntary := UInt<1>("h00") + T_11808.in[0].bits.payload.r_type := UInt<1>("h00") + T_11808.in[0].bits.payload.data := UInt<1>("h00") + T_11808.in[0].bits.payload.addr_beat := UInt<1>("h00") + T_11808.in[0].bits.payload.client_xact_id := UInt<1>("h00") + T_11808.in[0].bits.payload.addr_block := UInt<1>("h00") + T_11808.in[0].bits.header.dst := UInt<1>("h00") + T_11808.in[0].bits.header.src := UInt<1>("h00") + T_11808.in[0].valid := UInt<1>("h00") + T_11808.in[1].bits.payload.voluntary := UInt<1>("h00") + T_11808.in[1].bits.payload.r_type := UInt<1>("h00") + T_11808.in[1].bits.payload.data := UInt<1>("h00") + T_11808.in[1].bits.payload.addr_beat := UInt<1>("h00") + T_11808.in[1].bits.payload.client_xact_id := UInt<1>("h00") + T_11808.in[1].bits.payload.addr_block := UInt<1>("h00") + T_11808.in[1].bits.header.dst := UInt<1>("h00") + T_11808.in[1].bits.header.src := UInt<1>("h00") + T_11808.in[1].valid := UInt<1>("h00") + T_11808.in[2].bits.payload.voluntary := UInt<1>("h00") + T_11808.in[2].bits.payload.r_type := UInt<1>("h00") + T_11808.in[2].bits.payload.data := UInt<1>("h00") + T_11808.in[2].bits.payload.addr_beat := UInt<1>("h00") + T_11808.in[2].bits.payload.client_xact_id := UInt<1>("h00") + T_11808.in[2].bits.payload.addr_block := UInt<1>("h00") + T_11808.in[2].bits.header.dst := UInt<1>("h00") + T_11808.in[2].bits.header.src := UInt<1>("h00") + T_11808.in[2].valid := UInt<1>("h00") + T_11808.reset := UInt<1>("h00") + T_11808.clock := clock + T_11808.reset := reset + T_11808.in[0].valid := T_11800.manager.release.valid + T_11808.in[0].bits <> T_11800.manager.release.bits + T_11808.in[0].bits.payload.client_xact_id := T_11800.manager.release.bits.payload.client_xact_id + T_11800.manager.release.ready := T_11808.in[0].ready + T_11808.in[1].valid := T_11802.manager.release.valid + T_11808.in[1].bits <> T_11802.manager.release.bits + T_11808.in[1].bits.payload.client_xact_id := T_11802.manager.release.bits.payload.client_xact_id + T_11802.manager.release.ready := T_11808.in[1].ready + T_11808.in[2].valid := T_11804.manager.release.valid + T_11808.in[2].bits <> T_11804.manager.release.bits + T_11808.in[2].bits.payload.client_xact_id := T_11804.manager.release.bits.payload.client_xact_id + T_11804.manager.release.ready := T_11808.in[2].ready + T_11806.client.release <> T_11808.out + inst T_11809 of RRArbiter + T_11809.out.ready := UInt<1>("h00") + T_11809.in[0].bits.payload.manager_xact_id := UInt<1>("h00") + T_11809.in[0].bits.header.dst := UInt<1>("h00") + T_11809.in[0].bits.header.src := UInt<1>("h00") + T_11809.in[0].valid := UInt<1>("h00") + T_11809.in[1].bits.payload.manager_xact_id := UInt<1>("h00") + T_11809.in[1].bits.header.dst := UInt<1>("h00") + T_11809.in[1].bits.header.src := UInt<1>("h00") + T_11809.in[1].valid := UInt<1>("h00") + T_11809.in[2].bits.payload.manager_xact_id := UInt<1>("h00") + T_11809.in[2].bits.header.dst := UInt<1>("h00") + T_11809.in[2].bits.header.src := UInt<1>("h00") + T_11809.in[2].valid := UInt<1>("h00") + T_11809.reset := UInt<1>("h00") + T_11809.clock := clock + T_11809.reset := reset + T_11809.in[0] <> T_11800.manager.finish + T_11809.in[1] <> T_11802.manager.finish + T_11809.in[2] <> T_11804.manager.finish + T_11806.client.finish <> T_11809.out + T_11806.client.probe.ready := UInt<1>("h00") + T_11800.manager.probe.valid := UInt<1>("h00") + node T_11782 = eq(T_11806.client.probe.bits.header.dst, UInt<1>("h00")) + when T_11782 : + T_11800.manager.probe.valid := T_11806.client.probe.valid + T_11806.client.probe.ready := T_11800.manager.probe.ready + skip + T_11800.manager.probe.bits <> T_11806.client.probe.bits + T_11802.manager.probe.valid := UInt<1>("h00") + node T_11785 = eq(T_11806.client.probe.bits.header.dst, UInt<1>("h01")) + when T_11785 : + T_11802.manager.probe.valid := T_11806.client.probe.valid + T_11806.client.probe.ready := T_11802.manager.probe.ready + skip + T_11802.manager.probe.bits <> T_11806.client.probe.bits + T_11804.manager.probe.valid := UInt<1>("h00") + node T_11788 = eq(T_11806.client.probe.bits.header.dst, UInt<2>("h02")) + when T_11788 : + T_11804.manager.probe.valid := T_11806.client.probe.valid + T_11806.client.probe.ready := T_11804.manager.probe.ready + skip + T_11804.manager.probe.bits <> T_11806.client.probe.bits + T_11806.client.grant.ready := UInt<1>("h00") + T_11800.manager.grant.valid := UInt<1>("h00") + node T_11792 = eq(T_11806.client.grant.bits.header.dst, UInt<1>("h00")) + when T_11792 : + T_11800.manager.grant.valid := T_11806.client.grant.valid + T_11806.client.grant.ready := T_11800.manager.grant.ready + skip + T_11800.manager.grant.bits <> T_11806.client.grant.bits + T_11802.manager.grant.valid := UInt<1>("h00") + node T_11795 = eq(T_11806.client.grant.bits.header.dst, UInt<1>("h01")) + when T_11795 : + T_11802.manager.grant.valid := T_11806.client.grant.valid + T_11806.client.grant.ready := T_11802.manager.grant.ready + skip + T_11802.manager.grant.bits <> T_11806.client.grant.bits + T_11804.manager.grant.valid := UInt<1>("h00") + node T_11798 = eq(T_11806.client.grant.bits.header.dst, UInt<2>("h02")) + when T_11798 : + T_11804.manager.grant.valid := T_11806.client.grant.valid + T_11806.client.grant.ready := T_11804.manager.grant.ready + skip + T_11804.manager.grant.bits <> T_11806.client.grant.bits + + module BroadcastVoluntaryReleaseTracker : + output has_release_match : UInt<1> + output has_acquire_match : UInt<1> + output has_acquire_conflict : UInt<1> + output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input incoherent : UInt<1>[1] + output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} + input clock : Clock + input reset : UInt<1> + + has_release_match := UInt<1>("h00") + has_acquire_match := UInt<1>("h00") + has_acquire_conflict := UInt<1>("h00") + outer.grant.ready := UInt<1>("h00") + outer.acquire.bits.union := UInt<1>("h00") + outer.acquire.bits.a_type := UInt<1>("h00") + outer.acquire.bits.is_builtin_type := UInt<1>("h00") + outer.acquire.bits.data := UInt<1>("h00") + outer.acquire.bits.addr_beat := UInt<1>("h00") + outer.acquire.bits.client_xact_id := UInt<1>("h00") + outer.acquire.bits.addr_block := UInt<1>("h00") + outer.acquire.valid := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.probe.bits.client_id := UInt<1>("h00") + inner.probe.bits.p_type := UInt<1>("h00") + inner.probe.bits.addr_block := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + inner.grant.bits.client_id := UInt<1>("h00") + inner.grant.bits.g_type := UInt<1>("h00") + inner.grant.bits.is_builtin_type := UInt<1>("h00") + inner.grant.bits.manager_xact_id := UInt<1>("h00") + inner.grant.bits.client_xact_id := UInt<1>("h00") + inner.grant.bits.data := UInt<1>("h00") + inner.grant.bits.addr_beat := UInt<1>("h00") + inner.grant.valid := UInt<1>("h00") + inner.acquire.ready := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}, clock, reset + reg data_buffer : UInt<4>[4], clock, reset + wire coh : {sharers : UInt<1>} + coh.sharers := UInt<1>("h00") + coh.sharers := UInt<1>("h00") + reg collect_irel_data : UInt<1>, clock, reset + onreset collect_irel_data := UInt<1>("h00") + reg irel_data_valid : UInt<4>, clock, reset + onreset irel_data_valid := UInt<4>("h00") + node T_1091 = and(inner.release.ready, inner.release.valid) + wire T_1095 : UInt<2>[3] + T_1095[0] := UInt<1>("h00") + T_1095[1] := UInt<1>("h01") + T_1095[2] := UInt<2>("h02") + node T_1100 = eq(T_1095[0], inner.release.bits.r_type) + node T_1101 = eq(T_1095[1], inner.release.bits.r_type) + node T_1102 = eq(T_1095[2], inner.release.bits.r_type) + node T_1104 = or(UInt<1>("h00"), T_1100) + node T_1105 = or(T_1104, T_1101) + node T_1106 = or(T_1105, T_1102) + node T_1107 = and(UInt<1>("h01"), T_1106) + node T_1108 = and(T_1091, T_1107) + reg T_1110 : UInt<2>, clock, reset + onreset T_1110 := UInt<2>("h00") + when T_1108 : + node T_1112 = eq(T_1110, UInt<2>("h03")) + node T_1114 = and(UInt<1>("h00"), T_1112) + node T_1117 = addw(T_1110, UInt<1>("h01")) + node T_1118 = mux(T_1114, UInt<1>("h00"), T_1117) + T_1110 := T_1118 + skip + node T_1119 = and(T_1108, T_1112) + node T_1120 = mux(T_1107, T_1110, UInt<1>("h00")) + node irel_data_done = mux(T_1107, T_1119, T_1091) + node T_1123 = and(outer.acquire.ready, outer.acquire.valid) + node T_1125 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) + wire T_1128 : UInt<3>[1] + T_1128[0] := UInt<3>("h03") + node T_1131 = eq(T_1128[0], outer.acquire.bits.a_type) + node T_1133 = or(UInt<1>("h00"), T_1131) + node T_1134 = and(T_1125, T_1133) + node T_1135 = and(T_1123, T_1134) + reg T_1137 : UInt<2>, clock, reset + onreset T_1137 := UInt<2>("h00") + when T_1135 : + node T_1139 = eq(T_1137, UInt<2>("h03")) + node T_1141 = and(UInt<1>("h00"), T_1139) + node T_1144 = addw(T_1137, UInt<1>("h01")) + node T_1145 = mux(T_1141, UInt<1>("h00"), T_1144) + T_1137 := T_1145 + skip + node T_1146 = and(T_1135, T_1139) + node oacq_data_cnt = mux(T_1134, T_1137, UInt<1>("h00")) + node oacq_data_done = mux(T_1134, T_1146, T_1123) + has_acquire_conflict := UInt<1>("h00") + has_release_match := inner.release.bits.voluntary + has_acquire_match := UInt<1>("h00") + outer.acquire.valid := UInt<1>("h00") + outer.grant.ready := UInt<1>("h00") + inner.acquire.ready := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.grant.valid := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + wire T_1194 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1194.client_id := UInt<1>("h00") + T_1194.g_type := UInt<1>("h00") + T_1194.is_builtin_type := UInt<1>("h00") + T_1194.manager_xact_id := UInt<1>("h00") + T_1194.client_xact_id := UInt<1>("h00") + T_1194.data := UInt<1>("h00") + T_1194.addr_beat := UInt<1>("h00") + T_1194.client_id := xact.client_id + T_1194.is_builtin_type := UInt<1>("h01") + T_1194.g_type := UInt<3>("h00") + T_1194.client_xact_id := xact.client_xact_id + T_1194.manager_xact_id := UInt<1>("h00") + T_1194.addr_beat := UInt<1>("h00") + T_1194.data := UInt<1>("h00") + inner.grant.bits <> T_1194 + infer accessor T_1233 = data_buffer[oacq_data_cnt] + node T_1266 = asUInt(asSInt(UInt<1>("h01"))) + node T_1267 = cat(T_1266, UInt<1>("h01")) + wire T_1296 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + T_1296.union := UInt<1>("h00") + T_1296.a_type := UInt<1>("h00") + T_1296.is_builtin_type := UInt<1>("h00") + T_1296.data := UInt<1>("h00") + T_1296.addr_beat := UInt<1>("h00") + T_1296.client_xact_id := UInt<1>("h00") + T_1296.addr_block := UInt<1>("h00") + T_1296.is_builtin_type := UInt<1>("h01") + T_1296.a_type := UInt<3>("h03") + T_1296.client_xact_id := UInt<1>("h00") + T_1296.addr_block := xact.addr_block + T_1296.addr_beat := oacq_data_cnt + T_1296.data := T_1233 + T_1296.union := T_1267 + outer.acquire.bits <> T_1296 + when collect_irel_data : + inner.release.ready := UInt<1>("h01") + when inner.release.valid : + infer accessor T_1332 = data_buffer[inner.release.bits.addr_beat] + T_1332 := inner.release.bits.data + node T_1335 = dshl(UInt<1>("h01"), inner.release.bits.addr_beat) + node T_1336 = or(irel_data_valid, T_1335) + node T_1337 = not(irel_data_valid) + node T_1338 = or(T_1337, T_1335) + node T_1339 = not(T_1338) + node T_1340 = mux(UInt<1>("h01"), T_1336, T_1339) + irel_data_valid := T_1340 + skip + when irel_data_done : + collect_irel_data := UInt<1>("h00") + skip + skip + node T_1342 = eq(UInt<1>("h00"), state) + when T_1342 : + inner.release.ready := UInt<1>("h01") + when inner.release.valid : + xact <> inner.release.bits + infer accessor T_1345 = data_buffer[UInt<1>("h00")] + T_1345 := inner.release.bits.data + wire T_1348 : UInt<2>[3] + T_1348[0] := UInt<1>("h00") + T_1348[1] := UInt<1>("h01") + T_1348[2] := UInt<2>("h02") + node T_1353 = eq(T_1348[0], inner.release.bits.r_type) + node T_1354 = eq(T_1348[1], inner.release.bits.r_type) + node T_1355 = eq(T_1348[2], inner.release.bits.r_type) + node T_1357 = or(UInt<1>("h00"), T_1353) + node T_1358 = or(T_1357, T_1354) + node T_1359 = or(T_1358, T_1355) + node T_1360 = and(UInt<1>("h01"), T_1359) + collect_irel_data := T_1360 + wire T_1362 : UInt<2>[3] + T_1362[0] := UInt<1>("h00") + T_1362[1] := UInt<1>("h01") + T_1362[2] := UInt<2>("h02") + node T_1367 = eq(T_1362[0], inner.release.bits.r_type) + node T_1368 = eq(T_1362[1], inner.release.bits.r_type) + node T_1369 = eq(T_1362[2], inner.release.bits.r_type) + node T_1371 = or(UInt<1>("h00"), T_1367) + node T_1372 = or(T_1371, T_1368) + node T_1373 = or(T_1372, T_1369) + node T_1374 = dshl(T_1373, inner.release.bits.addr_beat) + irel_data_valid := T_1374 + wire T_1376 : UInt<2>[3] + T_1376[0] := UInt<1>("h00") + T_1376[1] := UInt<1>("h01") + T_1376[2] := UInt<2>("h02") + node T_1381 = eq(T_1376[0], inner.release.bits.r_type) + node T_1382 = eq(T_1376[1], inner.release.bits.r_type) + node T_1383 = eq(T_1376[2], inner.release.bits.r_type) + node T_1385 = or(UInt<1>("h00"), T_1381) + node T_1386 = or(T_1385, T_1382) + node T_1387 = or(T_1386, T_1383) + node T_1390 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1391 = mux(T_1390, UInt<2>("h03"), UInt<1>("h00")) + node T_1392 = mux(T_1387, UInt<1>("h01"), T_1391) + state := T_1392 + skip + skip + node T_1393 = eq(UInt<1>("h01"), state) + when T_1393 : + node T_1395 = eq(collect_irel_data, UInt<1>("h00")) + node T_1396 = dshr(irel_data_valid, oacq_data_cnt) + node T_1397 = bit(T_1396, 0) + node T_1398 = or(T_1395, T_1397) + outer.acquire.valid := T_1398 + when oacq_data_done : + state := UInt<2>("h02") + skip + skip + node T_1399 = eq(UInt<2>("h02"), state) + when T_1399 : + outer.grant.ready := inner.grant.ready + inner.grant.valid := outer.grant.valid + node T_1400 = and(inner.grant.ready, inner.grant.valid) + when T_1400 : + node T_1403 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1405 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_1406 = and(inner.grant.bits.is_builtin_type, T_1405) + node T_1408 = eq(T_1406, UInt<1>("h00")) + node T_1409 = and(T_1403, T_1408) + node T_1410 = mux(T_1409, UInt<2>("h03"), UInt<1>("h00")) + state := T_1410 + skip + skip + node T_1411 = eq(UInt<2>("h03"), state) + when T_1411 : + inner.finish.ready := UInt<1>("h01") + when inner.finish.valid : + state := UInt<1>("h00") + skip + skip + + module BroadcastAcquireTracker : + output has_release_match : UInt<1> + output has_acquire_match : UInt<1> + output has_acquire_conflict : UInt<1> + output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input incoherent : UInt<1>[1] + output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} + input clock : Clock + input reset : UInt<1> + + has_release_match := UInt<1>("h00") + has_acquire_match := UInt<1>("h00") + has_acquire_conflict := UInt<1>("h00") + outer.grant.ready := UInt<1>("h00") + outer.acquire.bits.union := UInt<1>("h00") + outer.acquire.bits.a_type := UInt<1>("h00") + outer.acquire.bits.is_builtin_type := UInt<1>("h00") + outer.acquire.bits.data := UInt<1>("h00") + outer.acquire.bits.addr_beat := UInt<1>("h00") + outer.acquire.bits.client_xact_id := UInt<1>("h00") + outer.acquire.bits.addr_block := UInt<1>("h00") + outer.acquire.valid := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.probe.bits.client_id := UInt<1>("h00") + inner.probe.bits.p_type := UInt<1>("h00") + inner.probe.bits.addr_block := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + inner.grant.bits.client_id := UInt<1>("h00") + inner.grant.bits.g_type := UInt<1>("h00") + inner.grant.bits.is_builtin_type := UInt<1>("h00") + inner.grant.bits.manager_xact_id := UInt<1>("h00") + inner.grant.bits.client_xact_id := UInt<1>("h00") + inner.grant.bits.data := UInt<1>("h00") + inner.grant.bits.addr_beat := UInt<1>("h00") + inner.grant.valid := UInt<1>("h00") + inner.acquire.ready := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}, clock, reset + reg data_buffer : UInt<4>[4], clock, reset + wire coh : {sharers : UInt<1>} + coh.sharers := UInt<1>("h00") + coh.sharers := UInt<1>("h00") + node T_1092 = neq(state, UInt<1>("h00")) + node T_1093 = and(T_1092, xact.is_builtin_type) + wire T_1099 : UInt<3>[4] + T_1099[0] := UInt<3>("h00") + T_1099[1] := UInt<3>("h02") + T_1099[2] := UInt<3>("h04") + T_1099[3] := UInt<3>("h05") + node T_1105 = eq(T_1099[0], xact.a_type) + node T_1106 = eq(T_1099[1], xact.a_type) + node T_1107 = eq(T_1099[2], xact.a_type) + node T_1108 = eq(T_1099[3], xact.a_type) + node T_1110 = or(UInt<1>("h00"), T_1105) + node T_1111 = or(T_1110, T_1106) + node T_1112 = or(T_1111, T_1107) + node T_1113 = or(T_1112, T_1108) + node T_1114 = and(T_1093, T_1113) + node T_1116 = eq(T_1114, UInt<1>("h00")) + reg release_count : UInt<1>, clock, reset + onreset release_count := UInt<1>("h00") + reg pending_probes : UInt<1>, clock, reset + onreset pending_probes := UInt<1>("h00") + node T_1121 = bit(pending_probes, 0) + wire T_1123 : UInt<1>[1] + T_1123[0] := T_1121 + node T_1128 = asUInt(asSInt(UInt<1>("h01"))) + node T_1131 = dshl(UInt<1>("h01"), inner.acquire.bits.client_id) + node T_1132 = or(T_1128, T_1131) + node T_1133 = not(T_1128) + node T_1134 = or(T_1133, T_1131) + node T_1135 = not(T_1134) + node mask_self = mux(UInt<1>("h00"), T_1132, T_1135) + node T_1137 = not(incoherent[0]) + node mask_incoherent = and(mask_self, T_1137) + reg collect_iacq_data : UInt<1>, clock, reset + onreset collect_iacq_data := UInt<1>("h00") + reg iacq_data_valid : UInt<4>, clock, reset + onreset iacq_data_valid := UInt<4>("h00") + node T_1143 = and(inner.acquire.ready, inner.acquire.valid) + node T_1146 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) + wire T_1149 : UInt<3>[1] + T_1149[0] := UInt<3>("h03") + node T_1152 = eq(T_1149[0], inner.acquire.bits.a_type) + node T_1154 = or(UInt<1>("h00"), T_1152) + node T_1155 = and(T_1146, T_1154) + node T_1156 = and(T_1143, T_1155) + reg T_1158 : UInt<2>, clock, reset + onreset T_1158 := UInt<2>("h00") + when T_1156 : + node T_1160 = eq(T_1158, UInt<2>("h03")) + node T_1162 = and(UInt<1>("h00"), T_1160) + node T_1165 = addw(T_1158, UInt<1>("h01")) + node T_1166 = mux(T_1162, UInt<1>("h00"), T_1165) + T_1158 := T_1166 + skip + node T_1167 = and(T_1156, T_1160) + node T_1168 = mux(T_1155, T_1158, UInt<1>("h00")) + node iacq_data_done = mux(T_1155, T_1167, T_1143) + node T_1170 = and(inner.release.ready, inner.release.valid) + wire T_1174 : UInt<2>[3] + T_1174[0] := UInt<1>("h00") + T_1174[1] := UInt<1>("h01") + T_1174[2] := UInt<2>("h02") + node T_1179 = eq(T_1174[0], inner.release.bits.r_type) + node T_1180 = eq(T_1174[1], inner.release.bits.r_type) + node T_1181 = eq(T_1174[2], inner.release.bits.r_type) + node T_1183 = or(UInt<1>("h00"), T_1179) + node T_1184 = or(T_1183, T_1180) + node T_1185 = or(T_1184, T_1181) + node T_1186 = and(UInt<1>("h01"), T_1185) + node T_1187 = and(T_1170, T_1186) + reg T_1189 : UInt<2>, clock, reset + onreset T_1189 := UInt<2>("h00") + when T_1187 : + node T_1191 = eq(T_1189, UInt<2>("h03")) + node T_1193 = and(UInt<1>("h00"), T_1191) + node T_1196 = addw(T_1189, UInt<1>("h01")) + node T_1197 = mux(T_1193, UInt<1>("h00"), T_1196) + T_1189 := T_1197 + skip + node T_1198 = and(T_1187, T_1191) + node T_1199 = mux(T_1186, T_1189, UInt<1>("h00")) + node irel_data_done = mux(T_1186, T_1198, T_1170) + node T_1202 = and(inner.grant.ready, inner.grant.valid) + wire T_1206 : UInt<3>[1] + T_1206[0] := UInt<3>("h05") + node T_1209 = eq(T_1206[0], inner.grant.bits.g_type) + node T_1211 = or(UInt<1>("h00"), T_1209) + wire T_1213 : UInt<1>[2] + T_1213[0] := UInt<1>("h00") + T_1213[1] := UInt<1>("h01") + node T_1217 = eq(T_1213[0], inner.grant.bits.g_type) + node T_1218 = eq(T_1213[1], inner.grant.bits.g_type) + node T_1220 = or(UInt<1>("h00"), T_1217) + node T_1221 = or(T_1220, T_1218) + node T_1222 = mux(inner.grant.bits.is_builtin_type, T_1211, T_1221) + node T_1223 = and(UInt<1>("h01"), T_1222) + node T_1224 = and(T_1202, T_1223) + reg T_1226 : UInt<2>, clock, reset + onreset T_1226 := UInt<2>("h00") + when T_1224 : + node T_1228 = eq(T_1226, UInt<2>("h03")) + node T_1230 = and(UInt<1>("h00"), T_1228) + node T_1233 = addw(T_1226, UInt<1>("h01")) + node T_1234 = mux(T_1230, UInt<1>("h00"), T_1233) + T_1226 := T_1234 + skip + node T_1235 = and(T_1224, T_1228) + node ignt_data_cnt = mux(T_1223, T_1226, UInt<1>("h00")) + node ignt_data_done = mux(T_1223, T_1235, T_1202) + node T_1239 = and(outer.acquire.ready, outer.acquire.valid) + node T_1241 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) + wire T_1244 : UInt<3>[1] + T_1244[0] := UInt<3>("h03") + node T_1247 = eq(T_1244[0], outer.acquire.bits.a_type) + node T_1249 = or(UInt<1>("h00"), T_1247) + node T_1250 = and(T_1241, T_1249) + node T_1251 = and(T_1239, T_1250) + reg T_1253 : UInt<2>, clock, reset + onreset T_1253 := UInt<2>("h00") + when T_1251 : + node T_1255 = eq(T_1253, UInt<2>("h03")) + node T_1257 = and(UInt<1>("h00"), T_1255) + node T_1260 = addw(T_1253, UInt<1>("h01")) + node T_1261 = mux(T_1257, UInt<1>("h00"), T_1260) + T_1253 := T_1261 + skip + node T_1262 = and(T_1251, T_1255) + node oacq_data_cnt = mux(T_1250, T_1253, UInt<1>("h00")) + node oacq_data_done = mux(T_1250, T_1262, T_1239) + node T_1265 = and(outer.grant.ready, outer.grant.valid) + wire T_1270 : UInt<3>[1] + T_1270[0] := UInt<3>("h05") + node T_1273 = eq(T_1270[0], outer.grant.bits.g_type) + node T_1275 = or(UInt<1>("h00"), T_1273) + wire T_1277 : UInt<1>[1] + T_1277[0] := UInt<1>("h00") + node T_1280 = eq(T_1277[0], outer.grant.bits.g_type) + node T_1282 = or(UInt<1>("h00"), T_1280) + node T_1283 = mux(outer.grant.bits.is_builtin_type, T_1275, T_1282) + node T_1284 = and(UInt<1>("h01"), T_1283) + node T_1285 = and(T_1265, T_1284) + reg T_1287 : UInt<2>, clock, reset + onreset T_1287 := UInt<2>("h00") + when T_1285 : + node T_1289 = eq(T_1287, UInt<2>("h03")) + node T_1291 = and(UInt<1>("h00"), T_1289) + node T_1294 = addw(T_1287, UInt<1>("h01")) + node T_1295 = mux(T_1291, UInt<1>("h00"), T_1294) + T_1287 := T_1295 + skip + node T_1296 = and(T_1285, T_1289) + node T_1297 = mux(T_1284, T_1287, UInt<1>("h00")) + node ognt_data_done = mux(T_1284, T_1296, T_1265) + reg pending_ognt_ack : UInt<1>, clock, reset + onreset pending_ognt_ack := UInt<1>("h00") + wire T_1305 : UInt<3>[3] + T_1305[0] := UInt<3>("h02") + T_1305[1] := UInt<3>("h03") + T_1305[2] := UInt<3>("h04") + node T_1310 = eq(T_1305[0], xact.a_type) + node T_1311 = eq(T_1305[1], xact.a_type) + node T_1312 = eq(T_1305[2], xact.a_type) + node T_1314 = or(UInt<1>("h00"), T_1310) + node T_1315 = or(T_1314, T_1311) + node T_1316 = or(T_1315, T_1312) + node pending_outer_write = and(xact.is_builtin_type, T_1316) + wire T_1322 : UInt<3>[3] + T_1322[0] := UInt<3>("h02") + T_1322[1] := UInt<3>("h03") + T_1322[2] := UInt<3>("h04") + node T_1327 = eq(T_1322[0], inner.acquire.bits.a_type) + node T_1328 = eq(T_1322[1], inner.acquire.bits.a_type) + node T_1329 = eq(T_1322[2], inner.acquire.bits.a_type) + node T_1331 = or(UInt<1>("h00"), T_1327) + node T_1332 = or(T_1331, T_1328) + node T_1333 = or(T_1332, T_1329) + node pending_outer_write_ = and(inner.acquire.bits.is_builtin_type, T_1333) + wire T_1338 : UInt<3>[2] + T_1338[0] := UInt<3>("h05") + T_1338[1] := UInt<3>("h04") + node T_1342 = eq(T_1338[0], inner.grant.bits.g_type) + node T_1343 = eq(T_1338[1], inner.grant.bits.g_type) + node T_1345 = or(UInt<1>("h00"), T_1342) + node T_1346 = or(T_1345, T_1343) + wire T_1348 : UInt<1>[2] + T_1348[0] := UInt<1>("h00") + T_1348[1] := UInt<1>("h01") + node T_1352 = eq(T_1348[0], inner.grant.bits.g_type) + node T_1353 = eq(T_1348[1], inner.grant.bits.g_type) + node T_1355 = or(UInt<1>("h00"), T_1352) + node T_1356 = or(T_1355, T_1353) + node pending_outer_read = mux(inner.grant.bits.is_builtin_type, T_1346, T_1356) + node T_1374 = eq(UInt<3>("h05"), inner.acquire.bits.a_type) + node T_1375 = mux(T_1374, UInt<3>("h01"), UInt<3>("h03")) + node T_1376 = eq(UInt<3>("h04"), inner.acquire.bits.a_type) + node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) + node T_1378 = eq(UInt<3>("h03"), inner.acquire.bits.a_type) + node T_1379 = mux(T_1378, UInt<3>("h03"), T_1377) + node T_1380 = eq(UInt<3>("h02"), inner.acquire.bits.a_type) + node T_1381 = mux(T_1380, UInt<3>("h03"), T_1379) + node T_1382 = eq(UInt<3>("h01"), inner.acquire.bits.a_type) + node T_1383 = mux(T_1382, UInt<3>("h05"), T_1381) + node T_1384 = eq(UInt<3>("h00"), inner.acquire.bits.a_type) + node T_1385 = mux(T_1384, UInt<3>("h04"), T_1383) + node T_1386 = eq(inner.acquire.bits.a_type, UInt<1>("h00")) + node T_1389 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1390 = mux(T_1389, UInt<1>("h00"), UInt<1>("h01")) + node T_1391 = mux(T_1386, T_1390, UInt<1>("h01")) + node T_1392 = mux(inner.acquire.bits.is_builtin_type, T_1385, T_1391) + wire T_1424 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1424.client_id := UInt<1>("h00") + T_1424.g_type := UInt<1>("h00") + T_1424.is_builtin_type := UInt<1>("h00") + T_1424.manager_xact_id := UInt<1>("h00") + T_1424.client_xact_id := UInt<1>("h00") + T_1424.data := UInt<1>("h00") + T_1424.addr_beat := UInt<1>("h00") + T_1424.client_id := inner.acquire.bits.client_id + T_1424.is_builtin_type := inner.acquire.bits.is_builtin_type + T_1424.g_type := T_1392 + T_1424.client_xact_id := inner.acquire.bits.client_xact_id + T_1424.manager_xact_id := UInt<1>("h01") + T_1424.addr_beat := UInt<1>("h00") + T_1424.data := UInt<1>("h00") + wire T_1465 : UInt<3>[2] + T_1465[0] := UInt<3>("h05") + T_1465[1] := UInt<3>("h04") + node T_1469 = eq(T_1465[0], T_1424.g_type) + node T_1470 = eq(T_1465[1], T_1424.g_type) + node T_1472 = or(UInt<1>("h00"), T_1469) + node T_1473 = or(T_1472, T_1470) + wire T_1475 : UInt<1>[2] + T_1475[0] := UInt<1>("h00") + T_1475[1] := UInt<1>("h01") + node T_1479 = eq(T_1475[0], T_1424.g_type) + node T_1480 = eq(T_1475[1], T_1424.g_type) + node T_1482 = or(UInt<1>("h00"), T_1479) + node T_1483 = or(T_1482, T_1480) + node pending_outer_read_ = mux(T_1424.is_builtin_type, T_1473, T_1483) + node T_1485 = eq(xact.addr_block, inner.acquire.bits.addr_block) + node T_1486 = neq(state, UInt<1>("h00")) + node T_1487 = and(T_1485, T_1486) + node T_1489 = eq(collect_iacq_data, UInt<1>("h00")) + node T_1490 = and(T_1487, T_1489) + has_acquire_conflict := T_1490 + node T_1491 = eq(xact.addr_block, inner.acquire.bits.addr_block) + node T_1492 = and(T_1491, collect_iacq_data) + has_acquire_match := T_1492 + node T_1493 = eq(xact.addr_block, inner.release.bits.addr_block) + node T_1495 = eq(inner.release.bits.voluntary, UInt<1>("h00")) + node T_1496 = and(T_1493, T_1495) + node T_1497 = eq(state, UInt<1>("h01")) + node T_1498 = and(T_1496, T_1497) + has_release_match := T_1498 + infer accessor T_1500 = data_buffer[oacq_data_cnt] + node T_1533 = asUInt(asSInt(UInt<1>("h01"))) + node T_1534 = cat(T_1533, UInt<1>("h01")) + wire outer_write_acq : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_write_acq.union := UInt<1>("h00") + outer_write_acq.a_type := UInt<1>("h00") + outer_write_acq.is_builtin_type := UInt<1>("h00") + outer_write_acq.data := UInt<1>("h00") + outer_write_acq.addr_beat := UInt<1>("h00") + outer_write_acq.client_xact_id := UInt<1>("h00") + outer_write_acq.addr_block := UInt<1>("h00") + outer_write_acq.is_builtin_type := UInt<1>("h01") + outer_write_acq.a_type := UInt<3>("h03") + outer_write_acq.client_xact_id := UInt<1>("h01") + outer_write_acq.addr_block := xact.addr_block + outer_write_acq.addr_beat := oacq_data_cnt + outer_write_acq.data := T_1500 + outer_write_acq.union := T_1534 + node T_1631 = asUInt(asSInt(UInt<1>("h01"))) + node T_1632 = cat(T_1631, UInt<1>("h01")) + wire outer_write_rel : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_write_rel.union := UInt<1>("h00") + outer_write_rel.a_type := UInt<1>("h00") + outer_write_rel.is_builtin_type := UInt<1>("h00") + outer_write_rel.data := UInt<1>("h00") + outer_write_rel.addr_beat := UInt<1>("h00") + outer_write_rel.client_xact_id := UInt<1>("h00") + outer_write_rel.addr_block := UInt<1>("h00") + outer_write_rel.is_builtin_type := UInt<1>("h01") + outer_write_rel.a_type := UInt<3>("h03") + outer_write_rel.client_xact_id := UInt<1>("h01") + outer_write_rel.addr_block := xact.addr_block + outer_write_rel.addr_beat := inner.release.bits.addr_beat + outer_write_rel.data := inner.release.bits.data + outer_write_rel.union := T_1632 + node T_1700 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1701 = cat(UInt<3>("h07"), T_1700) + wire outer_read : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_read.union := UInt<1>("h00") + outer_read.a_type := UInt<1>("h00") + outer_read.is_builtin_type := UInt<1>("h00") + outer_read.data := UInt<1>("h00") + outer_read.addr_beat := UInt<1>("h00") + outer_read.client_xact_id := UInt<1>("h00") + outer_read.addr_block := UInt<1>("h00") + outer_read.is_builtin_type := UInt<1>("h01") + outer_read.a_type := UInt<3>("h01") + outer_read.client_xact_id := UInt<1>("h01") + outer_read.addr_block := xact.addr_block + outer_read.addr_beat := UInt<1>("h00") + outer_read.data := UInt<1>("h00") + outer_read.union := T_1701 + outer.acquire.valid := UInt<1>("h00") + outer.acquire.bits <> outer_read + outer.grant.ready := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + node T_1775 = eq(UInt<3>("h04"), xact.a_type) + node T_1776 = mux(T_1775, UInt<1>("h00"), UInt<2>("h02")) + node T_1777 = eq(UInt<3>("h02"), xact.a_type) + node T_1778 = mux(T_1777, UInt<1>("h00"), T_1776) + node T_1779 = eq(UInt<3>("h00"), xact.a_type) + node T_1780 = mux(T_1779, UInt<2>("h02"), T_1778) + node T_1781 = eq(UInt<3>("h03"), xact.a_type) + node T_1782 = mux(T_1781, UInt<1>("h00"), T_1780) + node T_1783 = eq(UInt<3>("h01"), xact.a_type) + node T_1784 = mux(T_1783, UInt<2>("h02"), T_1782) + node T_1785 = eq(UInt<1>("h01"), xact.a_type) + node T_1786 = mux(T_1785, UInt<1>("h00"), UInt<2>("h02")) + node T_1787 = eq(UInt<1>("h00"), xact.a_type) + node T_1788 = mux(T_1787, UInt<1>("h01"), T_1786) + node T_1789 = mux(xact.is_builtin_type, T_1784, T_1788) + wire T_1817 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} + T_1817.client_id := UInt<1>("h00") + T_1817.p_type := UInt<1>("h00") + T_1817.addr_block := UInt<1>("h00") + T_1817.client_id := UInt<1>("h00") + T_1817.p_type := T_1789 + T_1817.addr_block := xact.addr_block + inner.probe.bits <> T_1817 + inner.grant.valid := UInt<1>("h00") + node T_1864 = eq(UInt<3>("h05"), xact.a_type) + node T_1865 = mux(T_1864, UInt<3>("h01"), UInt<3>("h03")) + node T_1866 = eq(UInt<3>("h04"), xact.a_type) + node T_1867 = mux(T_1866, UInt<3>("h04"), T_1865) + node T_1868 = eq(UInt<3>("h03"), xact.a_type) + node T_1869 = mux(T_1868, UInt<3>("h03"), T_1867) + node T_1870 = eq(UInt<3>("h02"), xact.a_type) + node T_1871 = mux(T_1870, UInt<3>("h03"), T_1869) + node T_1872 = eq(UInt<3>("h01"), xact.a_type) + node T_1873 = mux(T_1872, UInt<3>("h05"), T_1871) + node T_1874 = eq(UInt<3>("h00"), xact.a_type) + node T_1875 = mux(T_1874, UInt<3>("h04"), T_1873) + node T_1876 = eq(xact.a_type, UInt<1>("h00")) + node T_1879 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1880 = mux(T_1879, UInt<1>("h00"), UInt<1>("h01")) + node T_1881 = mux(T_1876, T_1880, UInt<1>("h01")) + node T_1882 = mux(xact.is_builtin_type, T_1875, T_1881) + wire T_1914 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1914.client_id := UInt<1>("h00") + T_1914.g_type := UInt<1>("h00") + T_1914.is_builtin_type := UInt<1>("h00") + T_1914.manager_xact_id := UInt<1>("h00") + T_1914.client_xact_id := UInt<1>("h00") + T_1914.data := UInt<1>("h00") + T_1914.addr_beat := UInt<1>("h00") + T_1914.client_id := xact.client_id + T_1914.is_builtin_type := xact.is_builtin_type + T_1914.g_type := T_1882 + T_1914.client_xact_id := xact.client_xact_id + T_1914.manager_xact_id := UInt<1>("h01") + T_1914.addr_beat := UInt<1>("h00") + T_1914.data := UInt<1>("h00") + inner.grant.bits <> T_1914 + inner.acquire.ready := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + node T_1955 = neq(state, UInt<1>("h00")) + node T_1956 = and(T_1955, collect_iacq_data) + node T_1957 = and(inner.acquire.ready, inner.acquire.valid) + node T_1958 = and(T_1956, T_1957) + node T_1959 = neq(inner.acquire.bits.client_id, xact.client_id) + node T_1960 = and(T_1958, T_1959) + node T_1962 = eq(T_1960, UInt<1>("h00")) + node T_1963 = neq(state, UInt<1>("h00")) + node T_1964 = and(T_1963, collect_iacq_data) + node T_1965 = and(inner.acquire.ready, inner.acquire.valid) + node T_1966 = and(T_1964, T_1965) + node T_1967 = neq(inner.acquire.bits.client_xact_id, xact.client_xact_id) + node T_1968 = and(T_1966, T_1967) + node T_1970 = eq(T_1968, UInt<1>("h00")) + node T_1971 = eq(state, UInt<1>("h00")) + node T_1972 = and(inner.acquire.ready, inner.acquire.valid) + node T_1973 = and(T_1971, T_1972) + node T_1975 = neq(inner.acquire.bits.addr_beat, UInt<1>("h00")) + node T_1976 = and(T_1973, T_1975) + node T_1978 = eq(T_1976, UInt<1>("h00")) + when collect_iacq_data : + inner.acquire.ready := UInt<1>("h01") + when inner.acquire.valid : + infer accessor T_1980 = data_buffer[inner.acquire.bits.addr_beat] + T_1980 := inner.acquire.bits.data + node T_1983 = dshl(UInt<1>("h01"), inner.acquire.bits.addr_beat) + node T_1984 = or(iacq_data_valid, T_1983) + node T_1985 = not(iacq_data_valid) + node T_1986 = or(T_1985, T_1983) + node T_1987 = not(T_1986) + node T_1988 = mux(UInt<1>("h01"), T_1984, T_1987) + iacq_data_valid := T_1988 + skip + when iacq_data_done : + collect_iacq_data := UInt<1>("h00") + skip + skip + when pending_ognt_ack : + outer.grant.ready := UInt<1>("h01") + when outer.grant.valid : + pending_ognt_ack := UInt<1>("h00") + skip + skip + node T_1992 = eq(UInt<1>("h00"), state) + when T_1992 : + inner.acquire.ready := UInt<1>("h01") + when inner.acquire.valid : + xact <> inner.acquire.bits + infer accessor T_1995 = data_buffer[UInt<1>("h00")] + T_1995 := inner.acquire.bits.data + node T_1997 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) + wire T_2000 : UInt<3>[1] + T_2000[0] := UInt<3>("h03") + node T_2003 = eq(T_2000[0], inner.acquire.bits.a_type) + node T_2005 = or(UInt<1>("h00"), T_2003) + node T_2006 = and(T_1997, T_2005) + collect_iacq_data := T_2006 + wire T_2011 : UInt<3>[3] + T_2011[0] := UInt<3>("h02") + T_2011[1] := UInt<3>("h03") + T_2011[2] := UInt<3>("h04") + node T_2016 = eq(T_2011[0], inner.acquire.bits.a_type) + node T_2017 = eq(T_2011[1], inner.acquire.bits.a_type) + node T_2018 = eq(T_2011[2], inner.acquire.bits.a_type) + node T_2020 = or(UInt<1>("h00"), T_2016) + node T_2021 = or(T_2020, T_2017) + node T_2022 = or(T_2021, T_2018) + node T_2023 = and(inner.acquire.bits.is_builtin_type, T_2022) + node T_2024 = dshl(T_2023, inner.acquire.bits.addr_beat) + iacq_data_valid := T_2024 + node T_2026 = neq(mask_incoherent, UInt<1>("h00")) + when T_2026 : + pending_probes := mask_incoherent + node T_2027 = bit(mask_incoherent, 0) + node T_2028 = bit(mask_incoherent, 1) + node T_2029 = bit(mask_incoherent, 2) + node T_2030 = bit(mask_incoherent, 3) + node T_2032 = cat(UInt<1>("h00"), T_2028) + node T_2033 = addw(T_2027, T_2032) + node T_2036 = cat(UInt<1>("h00"), T_2030) + node T_2037 = addw(T_2029, T_2036) + node T_2038 = cat(UInt<1>("h00"), T_2037) + node T_2039 = addw(T_2033, T_2038) + release_count := T_2039 + skip + node T_2040 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) + node T_2041 = mux(pending_outer_write_, UInt<2>("h03"), T_2040) + node T_2042 = mux(T_2026, UInt<1>("h01"), T_2041) + state := T_2042 + skip + skip + node T_2043 = eq(UInt<1>("h01"), state) + when T_2043 : + node T_2045 = neq(pending_probes, UInt<1>("h00")) + inner.probe.valid := T_2045 + when inner.probe.ready : + node T_2047 = dshl(UInt<1>("h01"), UInt<1>("h00")) + node T_2048 = not(T_2047) + node T_2049 = and(pending_probes, T_2048) + pending_probes := T_2049 + skip + wire T_2051 : UInt<2>[3] + T_2051[0] := UInt<1>("h00") + T_2051[1] := UInt<1>("h01") + T_2051[2] := UInt<2>("h02") + node T_2056 = eq(T_2051[0], inner.release.bits.r_type) + node T_2057 = eq(T_2051[1], inner.release.bits.r_type) + node T_2058 = eq(T_2051[2], inner.release.bits.r_type) + node T_2060 = or(UInt<1>("h00"), T_2056) + node T_2061 = or(T_2060, T_2057) + node T_2062 = or(T_2061, T_2058) + node T_2064 = eq(T_2062, UInt<1>("h00")) + node T_2065 = or(T_2064, outer.acquire.ready) + inner.release.ready := T_2065 + when inner.release.valid : + wire T_2067 : UInt<2>[3] + T_2067[0] := UInt<1>("h00") + T_2067[1] := UInt<1>("h01") + T_2067[2] := UInt<2>("h02") + node T_2072 = eq(T_2067[0], inner.release.bits.r_type) + node T_2073 = eq(T_2067[1], inner.release.bits.r_type) + node T_2074 = eq(T_2067[2], inner.release.bits.r_type) + node T_2076 = or(UInt<1>("h00"), T_2072) + node T_2077 = or(T_2076, T_2073) + node T_2078 = or(T_2077, T_2074) + when T_2078 : + outer.acquire.valid := UInt<1>("h01") + outer.acquire.bits <> outer_write_rel + when outer.acquire.ready : + when oacq_data_done : + pending_ognt_ack := UInt<1>("h01") + node T_2082 = subw(release_count, UInt<1>("h01")) + release_count := T_2082 + node T_2084 = eq(release_count, UInt<1>("h01")) + when T_2084 : + node T_2085 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_2086 = mux(pending_outer_write, UInt<2>("h03"), T_2085) + state := T_2086 + skip + skip + skip + skip + else : + node T_2088 = subw(release_count, UInt<1>("h01")) + release_count := T_2088 + node T_2090 = eq(release_count, UInt<1>("h01")) + when T_2090 : + node T_2091 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_2092 = mux(pending_outer_write, UInt<2>("h03"), T_2091) + state := T_2092 + skip + skip + skip + skip + node T_2093 = eq(UInt<2>("h03"), state) + when T_2093 : + node T_2095 = eq(pending_ognt_ack, UInt<1>("h00")) + node T_2097 = eq(collect_iacq_data, UInt<1>("h00")) + node T_2098 = or(T_2095, T_2097) + node T_2099 = dshr(iacq_data_valid, oacq_data_cnt) + node T_2100 = bit(T_2099, 0) + node T_2101 = or(T_2098, T_2100) + outer.acquire.valid := T_2101 + outer.acquire.bits <> outer_write_acq + when oacq_data_done : + pending_ognt_ack := UInt<1>("h01") + node T_2103 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) + state := T_2103 + skip + skip + node T_2104 = eq(UInt<2>("h02"), state) + when T_2104 : + node T_2106 = eq(pending_ognt_ack, UInt<1>("h00")) + outer.acquire.valid := T_2106 + outer.acquire.bits <> outer_read + node T_2107 = and(outer.acquire.ready, outer.acquire.valid) + when T_2107 : + state := UInt<3>("h05") + skip + skip + node T_2108 = eq(UInt<3>("h05"), state) + when T_2108 : + outer.grant.ready := inner.grant.ready + inner.grant.valid := outer.grant.valid + when ignt_data_done : + node T_2111 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_2113 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_2114 = and(inner.grant.bits.is_builtin_type, T_2113) + node T_2116 = eq(T_2114, UInt<1>("h00")) + node T_2117 = and(T_2111, T_2116) + node T_2118 = mux(T_2117, UInt<3>("h06"), UInt<1>("h00")) + state := T_2118 + skip + skip + node T_2119 = eq(UInt<3>("h04"), state) + when T_2119 : + inner.grant.valid := UInt<1>("h01") + when inner.grant.ready : + node T_2123 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_2125 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_2126 = and(inner.grant.bits.is_builtin_type, T_2125) + node T_2128 = eq(T_2126, UInt<1>("h00")) + node T_2129 = and(T_2123, T_2128) + node T_2130 = mux(T_2129, UInt<3>("h06"), UInt<1>("h00")) + state := T_2130 + skip + skip + node T_2131 = eq(UInt<3>("h06"), state) + when T_2131 : + inner.finish.ready := UInt<1>("h01") + when inner.finish.valid : + state := UInt<1>("h00") + skip + skip + + module BroadcastAcquireTracker_27 : + output has_release_match : UInt<1> + output has_acquire_match : UInt<1> + output has_acquire_conflict : UInt<1> + output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input incoherent : UInt<1>[1] + output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} + input clock : Clock + input reset : UInt<1> + + has_release_match := UInt<1>("h00") + has_acquire_match := UInt<1>("h00") + has_acquire_conflict := UInt<1>("h00") + outer.grant.ready := UInt<1>("h00") + outer.acquire.bits.union := UInt<1>("h00") + outer.acquire.bits.a_type := UInt<1>("h00") + outer.acquire.bits.is_builtin_type := UInt<1>("h00") + outer.acquire.bits.data := UInt<1>("h00") + outer.acquire.bits.addr_beat := UInt<1>("h00") + outer.acquire.bits.client_xact_id := UInt<1>("h00") + outer.acquire.bits.addr_block := UInt<1>("h00") + outer.acquire.valid := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.probe.bits.client_id := UInt<1>("h00") + inner.probe.bits.p_type := UInt<1>("h00") + inner.probe.bits.addr_block := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + inner.grant.bits.client_id := UInt<1>("h00") + inner.grant.bits.g_type := UInt<1>("h00") + inner.grant.bits.is_builtin_type := UInt<1>("h00") + inner.grant.bits.manager_xact_id := UInt<1>("h00") + inner.grant.bits.client_xact_id := UInt<1>("h00") + inner.grant.bits.data := UInt<1>("h00") + inner.grant.bits.addr_beat := UInt<1>("h00") + inner.grant.valid := UInt<1>("h00") + inner.acquire.ready := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}, clock, reset + reg data_buffer : UInt<4>[4], clock, reset + wire coh : {sharers : UInt<1>} + coh.sharers := UInt<1>("h00") + coh.sharers := UInt<1>("h00") + node T_1092 = neq(state, UInt<1>("h00")) + node T_1093 = and(T_1092, xact.is_builtin_type) + wire T_1099 : UInt<3>[4] + T_1099[0] := UInt<3>("h00") + T_1099[1] := UInt<3>("h02") + T_1099[2] := UInt<3>("h04") + T_1099[3] := UInt<3>("h05") + node T_1105 = eq(T_1099[0], xact.a_type) + node T_1106 = eq(T_1099[1], xact.a_type) + node T_1107 = eq(T_1099[2], xact.a_type) + node T_1108 = eq(T_1099[3], xact.a_type) + node T_1110 = or(UInt<1>("h00"), T_1105) + node T_1111 = or(T_1110, T_1106) + node T_1112 = or(T_1111, T_1107) + node T_1113 = or(T_1112, T_1108) + node T_1114 = and(T_1093, T_1113) + node T_1116 = eq(T_1114, UInt<1>("h00")) + reg release_count : UInt<1>, clock, reset + onreset release_count := UInt<1>("h00") + reg pending_probes : UInt<1>, clock, reset + onreset pending_probes := UInt<1>("h00") + node T_1121 = bit(pending_probes, 0) + wire T_1123 : UInt<1>[1] + T_1123[0] := T_1121 + node T_1128 = asUInt(asSInt(UInt<1>("h01"))) + node T_1131 = dshl(UInt<1>("h01"), inner.acquire.bits.client_id) + node T_1132 = or(T_1128, T_1131) + node T_1133 = not(T_1128) + node T_1134 = or(T_1133, T_1131) + node T_1135 = not(T_1134) + node mask_self = mux(UInt<1>("h00"), T_1132, T_1135) + node T_1137 = not(incoherent[0]) + node mask_incoherent = and(mask_self, T_1137) + reg collect_iacq_data : UInt<1>, clock, reset + onreset collect_iacq_data := UInt<1>("h00") + reg iacq_data_valid : UInt<4>, clock, reset + onreset iacq_data_valid := UInt<4>("h00") + node T_1143 = and(inner.acquire.ready, inner.acquire.valid) + node T_1146 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) + wire T_1149 : UInt<3>[1] + T_1149[0] := UInt<3>("h03") + node T_1152 = eq(T_1149[0], inner.acquire.bits.a_type) + node T_1154 = or(UInt<1>("h00"), T_1152) + node T_1155 = and(T_1146, T_1154) + node T_1156 = and(T_1143, T_1155) + reg T_1158 : UInt<2>, clock, reset + onreset T_1158 := UInt<2>("h00") + when T_1156 : + node T_1160 = eq(T_1158, UInt<2>("h03")) + node T_1162 = and(UInt<1>("h00"), T_1160) + node T_1165 = addw(T_1158, UInt<1>("h01")) + node T_1166 = mux(T_1162, UInt<1>("h00"), T_1165) + T_1158 := T_1166 + skip + node T_1167 = and(T_1156, T_1160) + node T_1168 = mux(T_1155, T_1158, UInt<1>("h00")) + node iacq_data_done = mux(T_1155, T_1167, T_1143) + node T_1170 = and(inner.release.ready, inner.release.valid) + wire T_1174 : UInt<2>[3] + T_1174[0] := UInt<1>("h00") + T_1174[1] := UInt<1>("h01") + T_1174[2] := UInt<2>("h02") + node T_1179 = eq(T_1174[0], inner.release.bits.r_type) + node T_1180 = eq(T_1174[1], inner.release.bits.r_type) + node T_1181 = eq(T_1174[2], inner.release.bits.r_type) + node T_1183 = or(UInt<1>("h00"), T_1179) + node T_1184 = or(T_1183, T_1180) + node T_1185 = or(T_1184, T_1181) + node T_1186 = and(UInt<1>("h01"), T_1185) + node T_1187 = and(T_1170, T_1186) + reg T_1189 : UInt<2>, clock, reset + onreset T_1189 := UInt<2>("h00") + when T_1187 : + node T_1191 = eq(T_1189, UInt<2>("h03")) + node T_1193 = and(UInt<1>("h00"), T_1191) + node T_1196 = addw(T_1189, UInt<1>("h01")) + node T_1197 = mux(T_1193, UInt<1>("h00"), T_1196) + T_1189 := T_1197 + skip + node T_1198 = and(T_1187, T_1191) + node T_1199 = mux(T_1186, T_1189, UInt<1>("h00")) + node irel_data_done = mux(T_1186, T_1198, T_1170) + node T_1202 = and(inner.grant.ready, inner.grant.valid) + wire T_1206 : UInt<3>[1] + T_1206[0] := UInt<3>("h05") + node T_1209 = eq(T_1206[0], inner.grant.bits.g_type) + node T_1211 = or(UInt<1>("h00"), T_1209) + wire T_1213 : UInt<1>[2] + T_1213[0] := UInt<1>("h00") + T_1213[1] := UInt<1>("h01") + node T_1217 = eq(T_1213[0], inner.grant.bits.g_type) + node T_1218 = eq(T_1213[1], inner.grant.bits.g_type) + node T_1220 = or(UInt<1>("h00"), T_1217) + node T_1221 = or(T_1220, T_1218) + node T_1222 = mux(inner.grant.bits.is_builtin_type, T_1211, T_1221) + node T_1223 = and(UInt<1>("h01"), T_1222) + node T_1224 = and(T_1202, T_1223) + reg T_1226 : UInt<2>, clock, reset + onreset T_1226 := UInt<2>("h00") + when T_1224 : + node T_1228 = eq(T_1226, UInt<2>("h03")) + node T_1230 = and(UInt<1>("h00"), T_1228) + node T_1233 = addw(T_1226, UInt<1>("h01")) + node T_1234 = mux(T_1230, UInt<1>("h00"), T_1233) + T_1226 := T_1234 + skip + node T_1235 = and(T_1224, T_1228) + node ignt_data_cnt = mux(T_1223, T_1226, UInt<1>("h00")) + node ignt_data_done = mux(T_1223, T_1235, T_1202) + node T_1239 = and(outer.acquire.ready, outer.acquire.valid) + node T_1241 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) + wire T_1244 : UInt<3>[1] + T_1244[0] := UInt<3>("h03") + node T_1247 = eq(T_1244[0], outer.acquire.bits.a_type) + node T_1249 = or(UInt<1>("h00"), T_1247) + node T_1250 = and(T_1241, T_1249) + node T_1251 = and(T_1239, T_1250) + reg T_1253 : UInt<2>, clock, reset + onreset T_1253 := UInt<2>("h00") + when T_1251 : + node T_1255 = eq(T_1253, UInt<2>("h03")) + node T_1257 = and(UInt<1>("h00"), T_1255) + node T_1260 = addw(T_1253, UInt<1>("h01")) + node T_1261 = mux(T_1257, UInt<1>("h00"), T_1260) + T_1253 := T_1261 + skip + node T_1262 = and(T_1251, T_1255) + node oacq_data_cnt = mux(T_1250, T_1253, UInt<1>("h00")) + node oacq_data_done = mux(T_1250, T_1262, T_1239) + node T_1265 = and(outer.grant.ready, outer.grant.valid) + wire T_1270 : UInt<3>[1] + T_1270[0] := UInt<3>("h05") + node T_1273 = eq(T_1270[0], outer.grant.bits.g_type) + node T_1275 = or(UInt<1>("h00"), T_1273) + wire T_1277 : UInt<1>[1] + T_1277[0] := UInt<1>("h00") + node T_1280 = eq(T_1277[0], outer.grant.bits.g_type) + node T_1282 = or(UInt<1>("h00"), T_1280) + node T_1283 = mux(outer.grant.bits.is_builtin_type, T_1275, T_1282) + node T_1284 = and(UInt<1>("h01"), T_1283) + node T_1285 = and(T_1265, T_1284) + reg T_1287 : UInt<2>, clock, reset + onreset T_1287 := UInt<2>("h00") + when T_1285 : + node T_1289 = eq(T_1287, UInt<2>("h03")) + node T_1291 = and(UInt<1>("h00"), T_1289) + node T_1294 = addw(T_1287, UInt<1>("h01")) + node T_1295 = mux(T_1291, UInt<1>("h00"), T_1294) + T_1287 := T_1295 + skip + node T_1296 = and(T_1285, T_1289) + node T_1297 = mux(T_1284, T_1287, UInt<1>("h00")) + node ognt_data_done = mux(T_1284, T_1296, T_1265) + reg pending_ognt_ack : UInt<1>, clock, reset + onreset pending_ognt_ack := UInt<1>("h00") + wire T_1305 : UInt<3>[3] + T_1305[0] := UInt<3>("h02") + T_1305[1] := UInt<3>("h03") + T_1305[2] := UInt<3>("h04") + node T_1310 = eq(T_1305[0], xact.a_type) + node T_1311 = eq(T_1305[1], xact.a_type) + node T_1312 = eq(T_1305[2], xact.a_type) + node T_1314 = or(UInt<1>("h00"), T_1310) + node T_1315 = or(T_1314, T_1311) + node T_1316 = or(T_1315, T_1312) + node pending_outer_write = and(xact.is_builtin_type, T_1316) + wire T_1322 : UInt<3>[3] + T_1322[0] := UInt<3>("h02") + T_1322[1] := UInt<3>("h03") + T_1322[2] := UInt<3>("h04") + node T_1327 = eq(T_1322[0], inner.acquire.bits.a_type) + node T_1328 = eq(T_1322[1], inner.acquire.bits.a_type) + node T_1329 = eq(T_1322[2], inner.acquire.bits.a_type) + node T_1331 = or(UInt<1>("h00"), T_1327) + node T_1332 = or(T_1331, T_1328) + node T_1333 = or(T_1332, T_1329) + node pending_outer_write_ = and(inner.acquire.bits.is_builtin_type, T_1333) + wire T_1338 : UInt<3>[2] + T_1338[0] := UInt<3>("h05") + T_1338[1] := UInt<3>("h04") + node T_1342 = eq(T_1338[0], inner.grant.bits.g_type) + node T_1343 = eq(T_1338[1], inner.grant.bits.g_type) + node T_1345 = or(UInt<1>("h00"), T_1342) + node T_1346 = or(T_1345, T_1343) + wire T_1348 : UInt<1>[2] + T_1348[0] := UInt<1>("h00") + T_1348[1] := UInt<1>("h01") + node T_1352 = eq(T_1348[0], inner.grant.bits.g_type) + node T_1353 = eq(T_1348[1], inner.grant.bits.g_type) + node T_1355 = or(UInt<1>("h00"), T_1352) + node T_1356 = or(T_1355, T_1353) + node pending_outer_read = mux(inner.grant.bits.is_builtin_type, T_1346, T_1356) + node T_1374 = eq(UInt<3>("h05"), inner.acquire.bits.a_type) + node T_1375 = mux(T_1374, UInt<3>("h01"), UInt<3>("h03")) + node T_1376 = eq(UInt<3>("h04"), inner.acquire.bits.a_type) + node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) + node T_1378 = eq(UInt<3>("h03"), inner.acquire.bits.a_type) + node T_1379 = mux(T_1378, UInt<3>("h03"), T_1377) + node T_1380 = eq(UInt<3>("h02"), inner.acquire.bits.a_type) + node T_1381 = mux(T_1380, UInt<3>("h03"), T_1379) + node T_1382 = eq(UInt<3>("h01"), inner.acquire.bits.a_type) + node T_1383 = mux(T_1382, UInt<3>("h05"), T_1381) + node T_1384 = eq(UInt<3>("h00"), inner.acquire.bits.a_type) + node T_1385 = mux(T_1384, UInt<3>("h04"), T_1383) + node T_1386 = eq(inner.acquire.bits.a_type, UInt<1>("h00")) + node T_1389 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1390 = mux(T_1389, UInt<1>("h00"), UInt<1>("h01")) + node T_1391 = mux(T_1386, T_1390, UInt<1>("h01")) + node T_1392 = mux(inner.acquire.bits.is_builtin_type, T_1385, T_1391) + wire T_1424 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1424.client_id := UInt<1>("h00") + T_1424.g_type := UInt<1>("h00") + T_1424.is_builtin_type := UInt<1>("h00") + T_1424.manager_xact_id := UInt<1>("h00") + T_1424.client_xact_id := UInt<1>("h00") + T_1424.data := UInt<1>("h00") + T_1424.addr_beat := UInt<1>("h00") + T_1424.client_id := inner.acquire.bits.client_id + T_1424.is_builtin_type := inner.acquire.bits.is_builtin_type + T_1424.g_type := T_1392 + T_1424.client_xact_id := inner.acquire.bits.client_xact_id + T_1424.manager_xact_id := UInt<2>("h02") + T_1424.addr_beat := UInt<1>("h00") + T_1424.data := UInt<1>("h00") + wire T_1465 : UInt<3>[2] + T_1465[0] := UInt<3>("h05") + T_1465[1] := UInt<3>("h04") + node T_1469 = eq(T_1465[0], T_1424.g_type) + node T_1470 = eq(T_1465[1], T_1424.g_type) + node T_1472 = or(UInt<1>("h00"), T_1469) + node T_1473 = or(T_1472, T_1470) + wire T_1475 : UInt<1>[2] + T_1475[0] := UInt<1>("h00") + T_1475[1] := UInt<1>("h01") + node T_1479 = eq(T_1475[0], T_1424.g_type) + node T_1480 = eq(T_1475[1], T_1424.g_type) + node T_1482 = or(UInt<1>("h00"), T_1479) + node T_1483 = or(T_1482, T_1480) + node pending_outer_read_ = mux(T_1424.is_builtin_type, T_1473, T_1483) + node T_1485 = eq(xact.addr_block, inner.acquire.bits.addr_block) + node T_1486 = neq(state, UInt<1>("h00")) + node T_1487 = and(T_1485, T_1486) + node T_1489 = eq(collect_iacq_data, UInt<1>("h00")) + node T_1490 = and(T_1487, T_1489) + has_acquire_conflict := T_1490 + node T_1491 = eq(xact.addr_block, inner.acquire.bits.addr_block) + node T_1492 = and(T_1491, collect_iacq_data) + has_acquire_match := T_1492 + node T_1493 = eq(xact.addr_block, inner.release.bits.addr_block) + node T_1495 = eq(inner.release.bits.voluntary, UInt<1>("h00")) + node T_1496 = and(T_1493, T_1495) + node T_1497 = eq(state, UInt<1>("h01")) + node T_1498 = and(T_1496, T_1497) + has_release_match := T_1498 + infer accessor T_1500 = data_buffer[oacq_data_cnt] + node T_1533 = asUInt(asSInt(UInt<1>("h01"))) + node T_1534 = cat(T_1533, UInt<1>("h01")) + wire outer_write_acq : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_write_acq.union := UInt<1>("h00") + outer_write_acq.a_type := UInt<1>("h00") + outer_write_acq.is_builtin_type := UInt<1>("h00") + outer_write_acq.data := UInt<1>("h00") + outer_write_acq.addr_beat := UInt<1>("h00") + outer_write_acq.client_xact_id := UInt<1>("h00") + outer_write_acq.addr_block := UInt<1>("h00") + outer_write_acq.is_builtin_type := UInt<1>("h01") + outer_write_acq.a_type := UInt<3>("h03") + outer_write_acq.client_xact_id := UInt<2>("h02") + outer_write_acq.addr_block := xact.addr_block + outer_write_acq.addr_beat := oacq_data_cnt + outer_write_acq.data := T_1500 + outer_write_acq.union := T_1534 + node T_1631 = asUInt(asSInt(UInt<1>("h01"))) + node T_1632 = cat(T_1631, UInt<1>("h01")) + wire outer_write_rel : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_write_rel.union := UInt<1>("h00") + outer_write_rel.a_type := UInt<1>("h00") + outer_write_rel.is_builtin_type := UInt<1>("h00") + outer_write_rel.data := UInt<1>("h00") + outer_write_rel.addr_beat := UInt<1>("h00") + outer_write_rel.client_xact_id := UInt<1>("h00") + outer_write_rel.addr_block := UInt<1>("h00") + outer_write_rel.is_builtin_type := UInt<1>("h01") + outer_write_rel.a_type := UInt<3>("h03") + outer_write_rel.client_xact_id := UInt<2>("h02") + outer_write_rel.addr_block := xact.addr_block + outer_write_rel.addr_beat := inner.release.bits.addr_beat + outer_write_rel.data := inner.release.bits.data + outer_write_rel.union := T_1632 + node T_1700 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1701 = cat(UInt<3>("h07"), T_1700) + wire outer_read : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_read.union := UInt<1>("h00") + outer_read.a_type := UInt<1>("h00") + outer_read.is_builtin_type := UInt<1>("h00") + outer_read.data := UInt<1>("h00") + outer_read.addr_beat := UInt<1>("h00") + outer_read.client_xact_id := UInt<1>("h00") + outer_read.addr_block := UInt<1>("h00") + outer_read.is_builtin_type := UInt<1>("h01") + outer_read.a_type := UInt<3>("h01") + outer_read.client_xact_id := UInt<2>("h02") + outer_read.addr_block := xact.addr_block + outer_read.addr_beat := UInt<1>("h00") + outer_read.data := UInt<1>("h00") + outer_read.union := T_1701 + outer.acquire.valid := UInt<1>("h00") + outer.acquire.bits <> outer_read + outer.grant.ready := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + node T_1775 = eq(UInt<3>("h04"), xact.a_type) + node T_1776 = mux(T_1775, UInt<1>("h00"), UInt<2>("h02")) + node T_1777 = eq(UInt<3>("h02"), xact.a_type) + node T_1778 = mux(T_1777, UInt<1>("h00"), T_1776) + node T_1779 = eq(UInt<3>("h00"), xact.a_type) + node T_1780 = mux(T_1779, UInt<2>("h02"), T_1778) + node T_1781 = eq(UInt<3>("h03"), xact.a_type) + node T_1782 = mux(T_1781, UInt<1>("h00"), T_1780) + node T_1783 = eq(UInt<3>("h01"), xact.a_type) + node T_1784 = mux(T_1783, UInt<2>("h02"), T_1782) + node T_1785 = eq(UInt<1>("h01"), xact.a_type) + node T_1786 = mux(T_1785, UInt<1>("h00"), UInt<2>("h02")) + node T_1787 = eq(UInt<1>("h00"), xact.a_type) + node T_1788 = mux(T_1787, UInt<1>("h01"), T_1786) + node T_1789 = mux(xact.is_builtin_type, T_1784, T_1788) + wire T_1817 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} + T_1817.client_id := UInt<1>("h00") + T_1817.p_type := UInt<1>("h00") + T_1817.addr_block := UInt<1>("h00") + T_1817.client_id := UInt<1>("h00") + T_1817.p_type := T_1789 + T_1817.addr_block := xact.addr_block + inner.probe.bits <> T_1817 + inner.grant.valid := UInt<1>("h00") + node T_1864 = eq(UInt<3>("h05"), xact.a_type) + node T_1865 = mux(T_1864, UInt<3>("h01"), UInt<3>("h03")) + node T_1866 = eq(UInt<3>("h04"), xact.a_type) + node T_1867 = mux(T_1866, UInt<3>("h04"), T_1865) + node T_1868 = eq(UInt<3>("h03"), xact.a_type) + node T_1869 = mux(T_1868, UInt<3>("h03"), T_1867) + node T_1870 = eq(UInt<3>("h02"), xact.a_type) + node T_1871 = mux(T_1870, UInt<3>("h03"), T_1869) + node T_1872 = eq(UInt<3>("h01"), xact.a_type) + node T_1873 = mux(T_1872, UInt<3>("h05"), T_1871) + node T_1874 = eq(UInt<3>("h00"), xact.a_type) + node T_1875 = mux(T_1874, UInt<3>("h04"), T_1873) + node T_1876 = eq(xact.a_type, UInt<1>("h00")) + node T_1879 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1880 = mux(T_1879, UInt<1>("h00"), UInt<1>("h01")) + node T_1881 = mux(T_1876, T_1880, UInt<1>("h01")) + node T_1882 = mux(xact.is_builtin_type, T_1875, T_1881) + wire T_1914 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1914.client_id := UInt<1>("h00") + T_1914.g_type := UInt<1>("h00") + T_1914.is_builtin_type := UInt<1>("h00") + T_1914.manager_xact_id := UInt<1>("h00") + T_1914.client_xact_id := UInt<1>("h00") + T_1914.data := UInt<1>("h00") + T_1914.addr_beat := UInt<1>("h00") + T_1914.client_id := xact.client_id + T_1914.is_builtin_type := xact.is_builtin_type + T_1914.g_type := T_1882 + T_1914.client_xact_id := xact.client_xact_id + T_1914.manager_xact_id := UInt<2>("h02") + T_1914.addr_beat := UInt<1>("h00") + T_1914.data := UInt<1>("h00") + inner.grant.bits <> T_1914 + inner.acquire.ready := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + node T_1955 = neq(state, UInt<1>("h00")) + node T_1956 = and(T_1955, collect_iacq_data) + node T_1957 = and(inner.acquire.ready, inner.acquire.valid) + node T_1958 = and(T_1956, T_1957) + node T_1959 = neq(inner.acquire.bits.client_id, xact.client_id) + node T_1960 = and(T_1958, T_1959) + node T_1962 = eq(T_1960, UInt<1>("h00")) + node T_1963 = neq(state, UInt<1>("h00")) + node T_1964 = and(T_1963, collect_iacq_data) + node T_1965 = and(inner.acquire.ready, inner.acquire.valid) + node T_1966 = and(T_1964, T_1965) + node T_1967 = neq(inner.acquire.bits.client_xact_id, xact.client_xact_id) + node T_1968 = and(T_1966, T_1967) + node T_1970 = eq(T_1968, UInt<1>("h00")) + node T_1971 = eq(state, UInt<1>("h00")) + node T_1972 = and(inner.acquire.ready, inner.acquire.valid) + node T_1973 = and(T_1971, T_1972) + node T_1975 = neq(inner.acquire.bits.addr_beat, UInt<1>("h00")) + node T_1976 = and(T_1973, T_1975) + node T_1978 = eq(T_1976, UInt<1>("h00")) + when collect_iacq_data : + inner.acquire.ready := UInt<1>("h01") + when inner.acquire.valid : + infer accessor T_1980 = data_buffer[inner.acquire.bits.addr_beat] + T_1980 := inner.acquire.bits.data + node T_1983 = dshl(UInt<1>("h01"), inner.acquire.bits.addr_beat) + node T_1984 = or(iacq_data_valid, T_1983) + node T_1985 = not(iacq_data_valid) + node T_1986 = or(T_1985, T_1983) + node T_1987 = not(T_1986) + node T_1988 = mux(UInt<1>("h01"), T_1984, T_1987) + iacq_data_valid := T_1988 + skip + when iacq_data_done : + collect_iacq_data := UInt<1>("h00") + skip + skip + when pending_ognt_ack : + outer.grant.ready := UInt<1>("h01") + when outer.grant.valid : + pending_ognt_ack := UInt<1>("h00") + skip + skip + node T_1992 = eq(UInt<1>("h00"), state) + when T_1992 : + inner.acquire.ready := UInt<1>("h01") + when inner.acquire.valid : + xact <> inner.acquire.bits + infer accessor T_1995 = data_buffer[UInt<1>("h00")] + T_1995 := inner.acquire.bits.data + node T_1997 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) + wire T_2000 : UInt<3>[1] + T_2000[0] := UInt<3>("h03") + node T_2003 = eq(T_2000[0], inner.acquire.bits.a_type) + node T_2005 = or(UInt<1>("h00"), T_2003) + node T_2006 = and(T_1997, T_2005) + collect_iacq_data := T_2006 + wire T_2011 : UInt<3>[3] + T_2011[0] := UInt<3>("h02") + T_2011[1] := UInt<3>("h03") + T_2011[2] := UInt<3>("h04") + node T_2016 = eq(T_2011[0], inner.acquire.bits.a_type) + node T_2017 = eq(T_2011[1], inner.acquire.bits.a_type) + node T_2018 = eq(T_2011[2], inner.acquire.bits.a_type) + node T_2020 = or(UInt<1>("h00"), T_2016) + node T_2021 = or(T_2020, T_2017) + node T_2022 = or(T_2021, T_2018) + node T_2023 = and(inner.acquire.bits.is_builtin_type, T_2022) + node T_2024 = dshl(T_2023, inner.acquire.bits.addr_beat) + iacq_data_valid := T_2024 + node T_2026 = neq(mask_incoherent, UInt<1>("h00")) + when T_2026 : + pending_probes := mask_incoherent + node T_2027 = bit(mask_incoherent, 0) + node T_2028 = bit(mask_incoherent, 1) + node T_2029 = bit(mask_incoherent, 2) + node T_2030 = bit(mask_incoherent, 3) + node T_2032 = cat(UInt<1>("h00"), T_2028) + node T_2033 = addw(T_2027, T_2032) + node T_2036 = cat(UInt<1>("h00"), T_2030) + node T_2037 = addw(T_2029, T_2036) + node T_2038 = cat(UInt<1>("h00"), T_2037) + node T_2039 = addw(T_2033, T_2038) + release_count := T_2039 + skip + node T_2040 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) + node T_2041 = mux(pending_outer_write_, UInt<2>("h03"), T_2040) + node T_2042 = mux(T_2026, UInt<1>("h01"), T_2041) + state := T_2042 + skip + skip + node T_2043 = eq(UInt<1>("h01"), state) + when T_2043 : + node T_2045 = neq(pending_probes, UInt<1>("h00")) + inner.probe.valid := T_2045 + when inner.probe.ready : + node T_2047 = dshl(UInt<1>("h01"), UInt<1>("h00")) + node T_2048 = not(T_2047) + node T_2049 = and(pending_probes, T_2048) + pending_probes := T_2049 + skip + wire T_2051 : UInt<2>[3] + T_2051[0] := UInt<1>("h00") + T_2051[1] := UInt<1>("h01") + T_2051[2] := UInt<2>("h02") + node T_2056 = eq(T_2051[0], inner.release.bits.r_type) + node T_2057 = eq(T_2051[1], inner.release.bits.r_type) + node T_2058 = eq(T_2051[2], inner.release.bits.r_type) + node T_2060 = or(UInt<1>("h00"), T_2056) + node T_2061 = or(T_2060, T_2057) + node T_2062 = or(T_2061, T_2058) + node T_2064 = eq(T_2062, UInt<1>("h00")) + node T_2065 = or(T_2064, outer.acquire.ready) + inner.release.ready := T_2065 + when inner.release.valid : + wire T_2067 : UInt<2>[3] + T_2067[0] := UInt<1>("h00") + T_2067[1] := UInt<1>("h01") + T_2067[2] := UInt<2>("h02") + node T_2072 = eq(T_2067[0], inner.release.bits.r_type) + node T_2073 = eq(T_2067[1], inner.release.bits.r_type) + node T_2074 = eq(T_2067[2], inner.release.bits.r_type) + node T_2076 = or(UInt<1>("h00"), T_2072) + node T_2077 = or(T_2076, T_2073) + node T_2078 = or(T_2077, T_2074) + when T_2078 : + outer.acquire.valid := UInt<1>("h01") + outer.acquire.bits <> outer_write_rel + when outer.acquire.ready : + when oacq_data_done : + pending_ognt_ack := UInt<1>("h01") + node T_2082 = subw(release_count, UInt<1>("h01")) + release_count := T_2082 + node T_2084 = eq(release_count, UInt<1>("h01")) + when T_2084 : + node T_2085 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_2086 = mux(pending_outer_write, UInt<2>("h03"), T_2085) + state := T_2086 + skip + skip + skip + skip + else : + node T_2088 = subw(release_count, UInt<1>("h01")) + release_count := T_2088 + node T_2090 = eq(release_count, UInt<1>("h01")) + when T_2090 : + node T_2091 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_2092 = mux(pending_outer_write, UInt<2>("h03"), T_2091) + state := T_2092 + skip + skip + skip + skip + node T_2093 = eq(UInt<2>("h03"), state) + when T_2093 : + node T_2095 = eq(pending_ognt_ack, UInt<1>("h00")) + node T_2097 = eq(collect_iacq_data, UInt<1>("h00")) + node T_2098 = or(T_2095, T_2097) + node T_2099 = dshr(iacq_data_valid, oacq_data_cnt) + node T_2100 = bit(T_2099, 0) + node T_2101 = or(T_2098, T_2100) + outer.acquire.valid := T_2101 + outer.acquire.bits <> outer_write_acq + when oacq_data_done : + pending_ognt_ack := UInt<1>("h01") + node T_2103 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) + state := T_2103 + skip + skip + node T_2104 = eq(UInt<2>("h02"), state) + when T_2104 : + node T_2106 = eq(pending_ognt_ack, UInt<1>("h00")) + outer.acquire.valid := T_2106 + outer.acquire.bits <> outer_read + node T_2107 = and(outer.acquire.ready, outer.acquire.valid) + when T_2107 : + state := UInt<3>("h05") + skip + skip + node T_2108 = eq(UInt<3>("h05"), state) + when T_2108 : + outer.grant.ready := inner.grant.ready + inner.grant.valid := outer.grant.valid + when ignt_data_done : + node T_2111 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_2113 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_2114 = and(inner.grant.bits.is_builtin_type, T_2113) + node T_2116 = eq(T_2114, UInt<1>("h00")) + node T_2117 = and(T_2111, T_2116) + node T_2118 = mux(T_2117, UInt<3>("h06"), UInt<1>("h00")) + state := T_2118 + skip + skip + node T_2119 = eq(UInt<3>("h04"), state) + when T_2119 : + inner.grant.valid := UInt<1>("h01") + when inner.grant.ready : + node T_2123 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_2125 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_2126 = and(inner.grant.bits.is_builtin_type, T_2125) + node T_2128 = eq(T_2126, UInt<1>("h00")) + node T_2129 = and(T_2123, T_2128) + node T_2130 = mux(T_2129, UInt<3>("h06"), UInt<1>("h00")) + state := T_2130 + skip + skip + node T_2131 = eq(UInt<3>("h06"), state) + when T_2131 : + inner.finish.ready := UInt<1>("h01") + when inner.finish.valid : + state := UInt<1>("h00") + skip + skip + + module BroadcastAcquireTracker_28 : + output has_release_match : UInt<1> + output has_acquire_match : UInt<1> + output has_acquire_conflict : UInt<1> + output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input incoherent : UInt<1>[1] + output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} + input clock : Clock + input reset : UInt<1> + + has_release_match := UInt<1>("h00") + has_acquire_match := UInt<1>("h00") + has_acquire_conflict := UInt<1>("h00") + outer.grant.ready := UInt<1>("h00") + outer.acquire.bits.union := UInt<1>("h00") + outer.acquire.bits.a_type := UInt<1>("h00") + outer.acquire.bits.is_builtin_type := UInt<1>("h00") + outer.acquire.bits.data := UInt<1>("h00") + outer.acquire.bits.addr_beat := UInt<1>("h00") + outer.acquire.bits.client_xact_id := UInt<1>("h00") + outer.acquire.bits.addr_block := UInt<1>("h00") + outer.acquire.valid := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.probe.bits.client_id := UInt<1>("h00") + inner.probe.bits.p_type := UInt<1>("h00") + inner.probe.bits.addr_block := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + inner.grant.bits.client_id := UInt<1>("h00") + inner.grant.bits.g_type := UInt<1>("h00") + inner.grant.bits.is_builtin_type := UInt<1>("h00") + inner.grant.bits.manager_xact_id := UInt<1>("h00") + inner.grant.bits.client_xact_id := UInt<1>("h00") + inner.grant.bits.data := UInt<1>("h00") + inner.grant.bits.addr_beat := UInt<1>("h00") + inner.grant.valid := UInt<1>("h00") + inner.acquire.ready := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}, clock, reset + reg data_buffer : UInt<4>[4], clock, reset + wire coh : {sharers : UInt<1>} + coh.sharers := UInt<1>("h00") + coh.sharers := UInt<1>("h00") + node T_1092 = neq(state, UInt<1>("h00")) + node T_1093 = and(T_1092, xact.is_builtin_type) + wire T_1099 : UInt<3>[4] + T_1099[0] := UInt<3>("h00") + T_1099[1] := UInt<3>("h02") + T_1099[2] := UInt<3>("h04") + T_1099[3] := UInt<3>("h05") + node T_1105 = eq(T_1099[0], xact.a_type) + node T_1106 = eq(T_1099[1], xact.a_type) + node T_1107 = eq(T_1099[2], xact.a_type) + node T_1108 = eq(T_1099[3], xact.a_type) + node T_1110 = or(UInt<1>("h00"), T_1105) + node T_1111 = or(T_1110, T_1106) + node T_1112 = or(T_1111, T_1107) + node T_1113 = or(T_1112, T_1108) + node T_1114 = and(T_1093, T_1113) + node T_1116 = eq(T_1114, UInt<1>("h00")) + reg release_count : UInt<1>, clock, reset + onreset release_count := UInt<1>("h00") + reg pending_probes : UInt<1>, clock, reset + onreset pending_probes := UInt<1>("h00") + node T_1121 = bit(pending_probes, 0) + wire T_1123 : UInt<1>[1] + T_1123[0] := T_1121 + node T_1128 = asUInt(asSInt(UInt<1>("h01"))) + node T_1131 = dshl(UInt<1>("h01"), inner.acquire.bits.client_id) + node T_1132 = or(T_1128, T_1131) + node T_1133 = not(T_1128) + node T_1134 = or(T_1133, T_1131) + node T_1135 = not(T_1134) + node mask_self = mux(UInt<1>("h00"), T_1132, T_1135) + node T_1137 = not(incoherent[0]) + node mask_incoherent = and(mask_self, T_1137) + reg collect_iacq_data : UInt<1>, clock, reset + onreset collect_iacq_data := UInt<1>("h00") + reg iacq_data_valid : UInt<4>, clock, reset + onreset iacq_data_valid := UInt<4>("h00") + node T_1143 = and(inner.acquire.ready, inner.acquire.valid) + node T_1146 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) + wire T_1149 : UInt<3>[1] + T_1149[0] := UInt<3>("h03") + node T_1152 = eq(T_1149[0], inner.acquire.bits.a_type) + node T_1154 = or(UInt<1>("h00"), T_1152) + node T_1155 = and(T_1146, T_1154) + node T_1156 = and(T_1143, T_1155) + reg T_1158 : UInt<2>, clock, reset + onreset T_1158 := UInt<2>("h00") + when T_1156 : + node T_1160 = eq(T_1158, UInt<2>("h03")) + node T_1162 = and(UInt<1>("h00"), T_1160) + node T_1165 = addw(T_1158, UInt<1>("h01")) + node T_1166 = mux(T_1162, UInt<1>("h00"), T_1165) + T_1158 := T_1166 + skip + node T_1167 = and(T_1156, T_1160) + node T_1168 = mux(T_1155, T_1158, UInt<1>("h00")) + node iacq_data_done = mux(T_1155, T_1167, T_1143) + node T_1170 = and(inner.release.ready, inner.release.valid) + wire T_1174 : UInt<2>[3] + T_1174[0] := UInt<1>("h00") + T_1174[1] := UInt<1>("h01") + T_1174[2] := UInt<2>("h02") + node T_1179 = eq(T_1174[0], inner.release.bits.r_type) + node T_1180 = eq(T_1174[1], inner.release.bits.r_type) + node T_1181 = eq(T_1174[2], inner.release.bits.r_type) + node T_1183 = or(UInt<1>("h00"), T_1179) + node T_1184 = or(T_1183, T_1180) + node T_1185 = or(T_1184, T_1181) + node T_1186 = and(UInt<1>("h01"), T_1185) + node T_1187 = and(T_1170, T_1186) + reg T_1189 : UInt<2>, clock, reset + onreset T_1189 := UInt<2>("h00") + when T_1187 : + node T_1191 = eq(T_1189, UInt<2>("h03")) + node T_1193 = and(UInt<1>("h00"), T_1191) + node T_1196 = addw(T_1189, UInt<1>("h01")) + node T_1197 = mux(T_1193, UInt<1>("h00"), T_1196) + T_1189 := T_1197 + skip + node T_1198 = and(T_1187, T_1191) + node T_1199 = mux(T_1186, T_1189, UInt<1>("h00")) + node irel_data_done = mux(T_1186, T_1198, T_1170) + node T_1202 = and(inner.grant.ready, inner.grant.valid) + wire T_1206 : UInt<3>[1] + T_1206[0] := UInt<3>("h05") + node T_1209 = eq(T_1206[0], inner.grant.bits.g_type) + node T_1211 = or(UInt<1>("h00"), T_1209) + wire T_1213 : UInt<1>[2] + T_1213[0] := UInt<1>("h00") + T_1213[1] := UInt<1>("h01") + node T_1217 = eq(T_1213[0], inner.grant.bits.g_type) + node T_1218 = eq(T_1213[1], inner.grant.bits.g_type) + node T_1220 = or(UInt<1>("h00"), T_1217) + node T_1221 = or(T_1220, T_1218) + node T_1222 = mux(inner.grant.bits.is_builtin_type, T_1211, T_1221) + node T_1223 = and(UInt<1>("h01"), T_1222) + node T_1224 = and(T_1202, T_1223) + reg T_1226 : UInt<2>, clock, reset + onreset T_1226 := UInt<2>("h00") + when T_1224 : + node T_1228 = eq(T_1226, UInt<2>("h03")) + node T_1230 = and(UInt<1>("h00"), T_1228) + node T_1233 = addw(T_1226, UInt<1>("h01")) + node T_1234 = mux(T_1230, UInt<1>("h00"), T_1233) + T_1226 := T_1234 + skip + node T_1235 = and(T_1224, T_1228) + node ignt_data_cnt = mux(T_1223, T_1226, UInt<1>("h00")) + node ignt_data_done = mux(T_1223, T_1235, T_1202) + node T_1239 = and(outer.acquire.ready, outer.acquire.valid) + node T_1241 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) + wire T_1244 : UInt<3>[1] + T_1244[0] := UInt<3>("h03") + node T_1247 = eq(T_1244[0], outer.acquire.bits.a_type) + node T_1249 = or(UInt<1>("h00"), T_1247) + node T_1250 = and(T_1241, T_1249) + node T_1251 = and(T_1239, T_1250) + reg T_1253 : UInt<2>, clock, reset + onreset T_1253 := UInt<2>("h00") + when T_1251 : + node T_1255 = eq(T_1253, UInt<2>("h03")) + node T_1257 = and(UInt<1>("h00"), T_1255) + node T_1260 = addw(T_1253, UInt<1>("h01")) + node T_1261 = mux(T_1257, UInt<1>("h00"), T_1260) + T_1253 := T_1261 + skip + node T_1262 = and(T_1251, T_1255) + node oacq_data_cnt = mux(T_1250, T_1253, UInt<1>("h00")) + node oacq_data_done = mux(T_1250, T_1262, T_1239) + node T_1265 = and(outer.grant.ready, outer.grant.valid) + wire T_1270 : UInt<3>[1] + T_1270[0] := UInt<3>("h05") + node T_1273 = eq(T_1270[0], outer.grant.bits.g_type) + node T_1275 = or(UInt<1>("h00"), T_1273) + wire T_1277 : UInt<1>[1] + T_1277[0] := UInt<1>("h00") + node T_1280 = eq(T_1277[0], outer.grant.bits.g_type) + node T_1282 = or(UInt<1>("h00"), T_1280) + node T_1283 = mux(outer.grant.bits.is_builtin_type, T_1275, T_1282) + node T_1284 = and(UInt<1>("h01"), T_1283) + node T_1285 = and(T_1265, T_1284) + reg T_1287 : UInt<2>, clock, reset + onreset T_1287 := UInt<2>("h00") + when T_1285 : + node T_1289 = eq(T_1287, UInt<2>("h03")) + node T_1291 = and(UInt<1>("h00"), T_1289) + node T_1294 = addw(T_1287, UInt<1>("h01")) + node T_1295 = mux(T_1291, UInt<1>("h00"), T_1294) + T_1287 := T_1295 + skip + node T_1296 = and(T_1285, T_1289) + node T_1297 = mux(T_1284, T_1287, UInt<1>("h00")) + node ognt_data_done = mux(T_1284, T_1296, T_1265) + reg pending_ognt_ack : UInt<1>, clock, reset + onreset pending_ognt_ack := UInt<1>("h00") + wire T_1305 : UInt<3>[3] + T_1305[0] := UInt<3>("h02") + T_1305[1] := UInt<3>("h03") + T_1305[2] := UInt<3>("h04") + node T_1310 = eq(T_1305[0], xact.a_type) + node T_1311 = eq(T_1305[1], xact.a_type) + node T_1312 = eq(T_1305[2], xact.a_type) + node T_1314 = or(UInt<1>("h00"), T_1310) + node T_1315 = or(T_1314, T_1311) + node T_1316 = or(T_1315, T_1312) + node pending_outer_write = and(xact.is_builtin_type, T_1316) + wire T_1322 : UInt<3>[3] + T_1322[0] := UInt<3>("h02") + T_1322[1] := UInt<3>("h03") + T_1322[2] := UInt<3>("h04") + node T_1327 = eq(T_1322[0], inner.acquire.bits.a_type) + node T_1328 = eq(T_1322[1], inner.acquire.bits.a_type) + node T_1329 = eq(T_1322[2], inner.acquire.bits.a_type) + node T_1331 = or(UInt<1>("h00"), T_1327) + node T_1332 = or(T_1331, T_1328) + node T_1333 = or(T_1332, T_1329) + node pending_outer_write_ = and(inner.acquire.bits.is_builtin_type, T_1333) + wire T_1338 : UInt<3>[2] + T_1338[0] := UInt<3>("h05") + T_1338[1] := UInt<3>("h04") + node T_1342 = eq(T_1338[0], inner.grant.bits.g_type) + node T_1343 = eq(T_1338[1], inner.grant.bits.g_type) + node T_1345 = or(UInt<1>("h00"), T_1342) + node T_1346 = or(T_1345, T_1343) + wire T_1348 : UInt<1>[2] + T_1348[0] := UInt<1>("h00") + T_1348[1] := UInt<1>("h01") + node T_1352 = eq(T_1348[0], inner.grant.bits.g_type) + node T_1353 = eq(T_1348[1], inner.grant.bits.g_type) + node T_1355 = or(UInt<1>("h00"), T_1352) + node T_1356 = or(T_1355, T_1353) + node pending_outer_read = mux(inner.grant.bits.is_builtin_type, T_1346, T_1356) + node T_1374 = eq(UInt<3>("h05"), inner.acquire.bits.a_type) + node T_1375 = mux(T_1374, UInt<3>("h01"), UInt<3>("h03")) + node T_1376 = eq(UInt<3>("h04"), inner.acquire.bits.a_type) + node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) + node T_1378 = eq(UInt<3>("h03"), inner.acquire.bits.a_type) + node T_1379 = mux(T_1378, UInt<3>("h03"), T_1377) + node T_1380 = eq(UInt<3>("h02"), inner.acquire.bits.a_type) + node T_1381 = mux(T_1380, UInt<3>("h03"), T_1379) + node T_1382 = eq(UInt<3>("h01"), inner.acquire.bits.a_type) + node T_1383 = mux(T_1382, UInt<3>("h05"), T_1381) + node T_1384 = eq(UInt<3>("h00"), inner.acquire.bits.a_type) + node T_1385 = mux(T_1384, UInt<3>("h04"), T_1383) + node T_1386 = eq(inner.acquire.bits.a_type, UInt<1>("h00")) + node T_1389 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1390 = mux(T_1389, UInt<1>("h00"), UInt<1>("h01")) + node T_1391 = mux(T_1386, T_1390, UInt<1>("h01")) + node T_1392 = mux(inner.acquire.bits.is_builtin_type, T_1385, T_1391) + wire T_1424 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1424.client_id := UInt<1>("h00") + T_1424.g_type := UInt<1>("h00") + T_1424.is_builtin_type := UInt<1>("h00") + T_1424.manager_xact_id := UInt<1>("h00") + T_1424.client_xact_id := UInt<1>("h00") + T_1424.data := UInt<1>("h00") + T_1424.addr_beat := UInt<1>("h00") + T_1424.client_id := inner.acquire.bits.client_id + T_1424.is_builtin_type := inner.acquire.bits.is_builtin_type + T_1424.g_type := T_1392 + T_1424.client_xact_id := inner.acquire.bits.client_xact_id + T_1424.manager_xact_id := UInt<2>("h03") + T_1424.addr_beat := UInt<1>("h00") + T_1424.data := UInt<1>("h00") + wire T_1465 : UInt<3>[2] + T_1465[0] := UInt<3>("h05") + T_1465[1] := UInt<3>("h04") + node T_1469 = eq(T_1465[0], T_1424.g_type) + node T_1470 = eq(T_1465[1], T_1424.g_type) + node T_1472 = or(UInt<1>("h00"), T_1469) + node T_1473 = or(T_1472, T_1470) + wire T_1475 : UInt<1>[2] + T_1475[0] := UInt<1>("h00") + T_1475[1] := UInt<1>("h01") + node T_1479 = eq(T_1475[0], T_1424.g_type) + node T_1480 = eq(T_1475[1], T_1424.g_type) + node T_1482 = or(UInt<1>("h00"), T_1479) + node T_1483 = or(T_1482, T_1480) + node pending_outer_read_ = mux(T_1424.is_builtin_type, T_1473, T_1483) + node T_1485 = eq(xact.addr_block, inner.acquire.bits.addr_block) + node T_1486 = neq(state, UInt<1>("h00")) + node T_1487 = and(T_1485, T_1486) + node T_1489 = eq(collect_iacq_data, UInt<1>("h00")) + node T_1490 = and(T_1487, T_1489) + has_acquire_conflict := T_1490 + node T_1491 = eq(xact.addr_block, inner.acquire.bits.addr_block) + node T_1492 = and(T_1491, collect_iacq_data) + has_acquire_match := T_1492 + node T_1493 = eq(xact.addr_block, inner.release.bits.addr_block) + node T_1495 = eq(inner.release.bits.voluntary, UInt<1>("h00")) + node T_1496 = and(T_1493, T_1495) + node T_1497 = eq(state, UInt<1>("h01")) + node T_1498 = and(T_1496, T_1497) + has_release_match := T_1498 + infer accessor T_1500 = data_buffer[oacq_data_cnt] + node T_1533 = asUInt(asSInt(UInt<1>("h01"))) + node T_1534 = cat(T_1533, UInt<1>("h01")) + wire outer_write_acq : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_write_acq.union := UInt<1>("h00") + outer_write_acq.a_type := UInt<1>("h00") + outer_write_acq.is_builtin_type := UInt<1>("h00") + outer_write_acq.data := UInt<1>("h00") + outer_write_acq.addr_beat := UInt<1>("h00") + outer_write_acq.client_xact_id := UInt<1>("h00") + outer_write_acq.addr_block := UInt<1>("h00") + outer_write_acq.is_builtin_type := UInt<1>("h01") + outer_write_acq.a_type := UInt<3>("h03") + outer_write_acq.client_xact_id := UInt<2>("h03") + outer_write_acq.addr_block := xact.addr_block + outer_write_acq.addr_beat := oacq_data_cnt + outer_write_acq.data := T_1500 + outer_write_acq.union := T_1534 + node T_1631 = asUInt(asSInt(UInt<1>("h01"))) + node T_1632 = cat(T_1631, UInt<1>("h01")) + wire outer_write_rel : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_write_rel.union := UInt<1>("h00") + outer_write_rel.a_type := UInt<1>("h00") + outer_write_rel.is_builtin_type := UInt<1>("h00") + outer_write_rel.data := UInt<1>("h00") + outer_write_rel.addr_beat := UInt<1>("h00") + outer_write_rel.client_xact_id := UInt<1>("h00") + outer_write_rel.addr_block := UInt<1>("h00") + outer_write_rel.is_builtin_type := UInt<1>("h01") + outer_write_rel.a_type := UInt<3>("h03") + outer_write_rel.client_xact_id := UInt<2>("h03") + outer_write_rel.addr_block := xact.addr_block + outer_write_rel.addr_beat := inner.release.bits.addr_beat + outer_write_rel.data := inner.release.bits.data + outer_write_rel.union := T_1632 + node T_1700 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1701 = cat(UInt<3>("h07"), T_1700) + wire outer_read : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_read.union := UInt<1>("h00") + outer_read.a_type := UInt<1>("h00") + outer_read.is_builtin_type := UInt<1>("h00") + outer_read.data := UInt<1>("h00") + outer_read.addr_beat := UInt<1>("h00") + outer_read.client_xact_id := UInt<1>("h00") + outer_read.addr_block := UInt<1>("h00") + outer_read.is_builtin_type := UInt<1>("h01") + outer_read.a_type := UInt<3>("h01") + outer_read.client_xact_id := UInt<2>("h03") + outer_read.addr_block := xact.addr_block + outer_read.addr_beat := UInt<1>("h00") + outer_read.data := UInt<1>("h00") + outer_read.union := T_1701 + outer.acquire.valid := UInt<1>("h00") + outer.acquire.bits <> outer_read + outer.grant.ready := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + node T_1775 = eq(UInt<3>("h04"), xact.a_type) + node T_1776 = mux(T_1775, UInt<1>("h00"), UInt<2>("h02")) + node T_1777 = eq(UInt<3>("h02"), xact.a_type) + node T_1778 = mux(T_1777, UInt<1>("h00"), T_1776) + node T_1779 = eq(UInt<3>("h00"), xact.a_type) + node T_1780 = mux(T_1779, UInt<2>("h02"), T_1778) + node T_1781 = eq(UInt<3>("h03"), xact.a_type) + node T_1782 = mux(T_1781, UInt<1>("h00"), T_1780) + node T_1783 = eq(UInt<3>("h01"), xact.a_type) + node T_1784 = mux(T_1783, UInt<2>("h02"), T_1782) + node T_1785 = eq(UInt<1>("h01"), xact.a_type) + node T_1786 = mux(T_1785, UInt<1>("h00"), UInt<2>("h02")) + node T_1787 = eq(UInt<1>("h00"), xact.a_type) + node T_1788 = mux(T_1787, UInt<1>("h01"), T_1786) + node T_1789 = mux(xact.is_builtin_type, T_1784, T_1788) + wire T_1817 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} + T_1817.client_id := UInt<1>("h00") + T_1817.p_type := UInt<1>("h00") + T_1817.addr_block := UInt<1>("h00") + T_1817.client_id := UInt<1>("h00") + T_1817.p_type := T_1789 + T_1817.addr_block := xact.addr_block + inner.probe.bits <> T_1817 + inner.grant.valid := UInt<1>("h00") + node T_1864 = eq(UInt<3>("h05"), xact.a_type) + node T_1865 = mux(T_1864, UInt<3>("h01"), UInt<3>("h03")) + node T_1866 = eq(UInt<3>("h04"), xact.a_type) + node T_1867 = mux(T_1866, UInt<3>("h04"), T_1865) + node T_1868 = eq(UInt<3>("h03"), xact.a_type) + node T_1869 = mux(T_1868, UInt<3>("h03"), T_1867) + node T_1870 = eq(UInt<3>("h02"), xact.a_type) + node T_1871 = mux(T_1870, UInt<3>("h03"), T_1869) + node T_1872 = eq(UInt<3>("h01"), xact.a_type) + node T_1873 = mux(T_1872, UInt<3>("h05"), T_1871) + node T_1874 = eq(UInt<3>("h00"), xact.a_type) + node T_1875 = mux(T_1874, UInt<3>("h04"), T_1873) + node T_1876 = eq(xact.a_type, UInt<1>("h00")) + node T_1879 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1880 = mux(T_1879, UInt<1>("h00"), UInt<1>("h01")) + node T_1881 = mux(T_1876, T_1880, UInt<1>("h01")) + node T_1882 = mux(xact.is_builtin_type, T_1875, T_1881) + wire T_1914 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1914.client_id := UInt<1>("h00") + T_1914.g_type := UInt<1>("h00") + T_1914.is_builtin_type := UInt<1>("h00") + T_1914.manager_xact_id := UInt<1>("h00") + T_1914.client_xact_id := UInt<1>("h00") + T_1914.data := UInt<1>("h00") + T_1914.addr_beat := UInt<1>("h00") + T_1914.client_id := xact.client_id + T_1914.is_builtin_type := xact.is_builtin_type + T_1914.g_type := T_1882 + T_1914.client_xact_id := xact.client_xact_id + T_1914.manager_xact_id := UInt<2>("h03") + T_1914.addr_beat := UInt<1>("h00") + T_1914.data := UInt<1>("h00") + inner.grant.bits <> T_1914 + inner.acquire.ready := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + node T_1955 = neq(state, UInt<1>("h00")) + node T_1956 = and(T_1955, collect_iacq_data) + node T_1957 = and(inner.acquire.ready, inner.acquire.valid) + node T_1958 = and(T_1956, T_1957) + node T_1959 = neq(inner.acquire.bits.client_id, xact.client_id) + node T_1960 = and(T_1958, T_1959) + node T_1962 = eq(T_1960, UInt<1>("h00")) + node T_1963 = neq(state, UInt<1>("h00")) + node T_1964 = and(T_1963, collect_iacq_data) + node T_1965 = and(inner.acquire.ready, inner.acquire.valid) + node T_1966 = and(T_1964, T_1965) + node T_1967 = neq(inner.acquire.bits.client_xact_id, xact.client_xact_id) + node T_1968 = and(T_1966, T_1967) + node T_1970 = eq(T_1968, UInt<1>("h00")) + node T_1971 = eq(state, UInt<1>("h00")) + node T_1972 = and(inner.acquire.ready, inner.acquire.valid) + node T_1973 = and(T_1971, T_1972) + node T_1975 = neq(inner.acquire.bits.addr_beat, UInt<1>("h00")) + node T_1976 = and(T_1973, T_1975) + node T_1978 = eq(T_1976, UInt<1>("h00")) + when collect_iacq_data : + inner.acquire.ready := UInt<1>("h01") + when inner.acquire.valid : + infer accessor T_1980 = data_buffer[inner.acquire.bits.addr_beat] + T_1980 := inner.acquire.bits.data + node T_1983 = dshl(UInt<1>("h01"), inner.acquire.bits.addr_beat) + node T_1984 = or(iacq_data_valid, T_1983) + node T_1985 = not(iacq_data_valid) + node T_1986 = or(T_1985, T_1983) + node T_1987 = not(T_1986) + node T_1988 = mux(UInt<1>("h01"), T_1984, T_1987) + iacq_data_valid := T_1988 + skip + when iacq_data_done : + collect_iacq_data := UInt<1>("h00") + skip + skip + when pending_ognt_ack : + outer.grant.ready := UInt<1>("h01") + when outer.grant.valid : + pending_ognt_ack := UInt<1>("h00") + skip + skip + node T_1992 = eq(UInt<1>("h00"), state) + when T_1992 : + inner.acquire.ready := UInt<1>("h01") + when inner.acquire.valid : + xact <> inner.acquire.bits + infer accessor T_1995 = data_buffer[UInt<1>("h00")] + T_1995 := inner.acquire.bits.data + node T_1997 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) + wire T_2000 : UInt<3>[1] + T_2000[0] := UInt<3>("h03") + node T_2003 = eq(T_2000[0], inner.acquire.bits.a_type) + node T_2005 = or(UInt<1>("h00"), T_2003) + node T_2006 = and(T_1997, T_2005) + collect_iacq_data := T_2006 + wire T_2011 : UInt<3>[3] + T_2011[0] := UInt<3>("h02") + T_2011[1] := UInt<3>("h03") + T_2011[2] := UInt<3>("h04") + node T_2016 = eq(T_2011[0], inner.acquire.bits.a_type) + node T_2017 = eq(T_2011[1], inner.acquire.bits.a_type) + node T_2018 = eq(T_2011[2], inner.acquire.bits.a_type) + node T_2020 = or(UInt<1>("h00"), T_2016) + node T_2021 = or(T_2020, T_2017) + node T_2022 = or(T_2021, T_2018) + node T_2023 = and(inner.acquire.bits.is_builtin_type, T_2022) + node T_2024 = dshl(T_2023, inner.acquire.bits.addr_beat) + iacq_data_valid := T_2024 + node T_2026 = neq(mask_incoherent, UInt<1>("h00")) + when T_2026 : + pending_probes := mask_incoherent + node T_2027 = bit(mask_incoherent, 0) + node T_2028 = bit(mask_incoherent, 1) + node T_2029 = bit(mask_incoherent, 2) + node T_2030 = bit(mask_incoherent, 3) + node T_2032 = cat(UInt<1>("h00"), T_2028) + node T_2033 = addw(T_2027, T_2032) + node T_2036 = cat(UInt<1>("h00"), T_2030) + node T_2037 = addw(T_2029, T_2036) + node T_2038 = cat(UInt<1>("h00"), T_2037) + node T_2039 = addw(T_2033, T_2038) + release_count := T_2039 + skip + node T_2040 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) + node T_2041 = mux(pending_outer_write_, UInt<2>("h03"), T_2040) + node T_2042 = mux(T_2026, UInt<1>("h01"), T_2041) + state := T_2042 + skip + skip + node T_2043 = eq(UInt<1>("h01"), state) + when T_2043 : + node T_2045 = neq(pending_probes, UInt<1>("h00")) + inner.probe.valid := T_2045 + when inner.probe.ready : + node T_2047 = dshl(UInt<1>("h01"), UInt<1>("h00")) + node T_2048 = not(T_2047) + node T_2049 = and(pending_probes, T_2048) + pending_probes := T_2049 + skip + wire T_2051 : UInt<2>[3] + T_2051[0] := UInt<1>("h00") + T_2051[1] := UInt<1>("h01") + T_2051[2] := UInt<2>("h02") + node T_2056 = eq(T_2051[0], inner.release.bits.r_type) + node T_2057 = eq(T_2051[1], inner.release.bits.r_type) + node T_2058 = eq(T_2051[2], inner.release.bits.r_type) + node T_2060 = or(UInt<1>("h00"), T_2056) + node T_2061 = or(T_2060, T_2057) + node T_2062 = or(T_2061, T_2058) + node T_2064 = eq(T_2062, UInt<1>("h00")) + node T_2065 = or(T_2064, outer.acquire.ready) + inner.release.ready := T_2065 + when inner.release.valid : + wire T_2067 : UInt<2>[3] + T_2067[0] := UInt<1>("h00") + T_2067[1] := UInt<1>("h01") + T_2067[2] := UInt<2>("h02") + node T_2072 = eq(T_2067[0], inner.release.bits.r_type) + node T_2073 = eq(T_2067[1], inner.release.bits.r_type) + node T_2074 = eq(T_2067[2], inner.release.bits.r_type) + node T_2076 = or(UInt<1>("h00"), T_2072) + node T_2077 = or(T_2076, T_2073) + node T_2078 = or(T_2077, T_2074) + when T_2078 : + outer.acquire.valid := UInt<1>("h01") + outer.acquire.bits <> outer_write_rel + when outer.acquire.ready : + when oacq_data_done : + pending_ognt_ack := UInt<1>("h01") + node T_2082 = subw(release_count, UInt<1>("h01")) + release_count := T_2082 + node T_2084 = eq(release_count, UInt<1>("h01")) + when T_2084 : + node T_2085 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_2086 = mux(pending_outer_write, UInt<2>("h03"), T_2085) + state := T_2086 + skip + skip + skip + skip + else : + node T_2088 = subw(release_count, UInt<1>("h01")) + release_count := T_2088 + node T_2090 = eq(release_count, UInt<1>("h01")) + when T_2090 : + node T_2091 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_2092 = mux(pending_outer_write, UInt<2>("h03"), T_2091) + state := T_2092 + skip + skip + skip + skip + node T_2093 = eq(UInt<2>("h03"), state) + when T_2093 : + node T_2095 = eq(pending_ognt_ack, UInt<1>("h00")) + node T_2097 = eq(collect_iacq_data, UInt<1>("h00")) + node T_2098 = or(T_2095, T_2097) + node T_2099 = dshr(iacq_data_valid, oacq_data_cnt) + node T_2100 = bit(T_2099, 0) + node T_2101 = or(T_2098, T_2100) + outer.acquire.valid := T_2101 + outer.acquire.bits <> outer_write_acq + when oacq_data_done : + pending_ognt_ack := UInt<1>("h01") + node T_2103 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) + state := T_2103 + skip + skip + node T_2104 = eq(UInt<2>("h02"), state) + when T_2104 : + node T_2106 = eq(pending_ognt_ack, UInt<1>("h00")) + outer.acquire.valid := T_2106 + outer.acquire.bits <> outer_read + node T_2107 = and(outer.acquire.ready, outer.acquire.valid) + when T_2107 : + state := UInt<3>("h05") + skip + skip + node T_2108 = eq(UInt<3>("h05"), state) + when T_2108 : + outer.grant.ready := inner.grant.ready + inner.grant.valid := outer.grant.valid + when ignt_data_done : + node T_2111 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_2113 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_2114 = and(inner.grant.bits.is_builtin_type, T_2113) + node T_2116 = eq(T_2114, UInt<1>("h00")) + node T_2117 = and(T_2111, T_2116) + node T_2118 = mux(T_2117, UInt<3>("h06"), UInt<1>("h00")) + state := T_2118 + skip + skip + node T_2119 = eq(UInt<3>("h04"), state) + when T_2119 : + inner.grant.valid := UInt<1>("h01") + when inner.grant.ready : + node T_2123 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_2125 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_2126 = and(inner.grant.bits.is_builtin_type, T_2125) + node T_2128 = eq(T_2126, UInt<1>("h00")) + node T_2129 = and(T_2123, T_2128) + node T_2130 = mux(T_2129, UInt<3>("h06"), UInt<1>("h00")) + state := T_2130 + skip + skip + node T_2131 = eq(UInt<3>("h06"), state) + when T_2131 : + inner.finish.ready := UInt<1>("h01") + when inner.finish.valid : + state := UInt<1>("h00") + skip + skip + + module BroadcastAcquireTracker_29 : + output has_release_match : UInt<1> + output has_acquire_match : UInt<1> + output has_acquire_conflict : UInt<1> + output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input incoherent : UInt<1>[1] + output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} + input clock : Clock + input reset : UInt<1> + + has_release_match := UInt<1>("h00") + has_acquire_match := UInt<1>("h00") + has_acquire_conflict := UInt<1>("h00") + outer.grant.ready := UInt<1>("h00") + outer.acquire.bits.union := UInt<1>("h00") + outer.acquire.bits.a_type := UInt<1>("h00") + outer.acquire.bits.is_builtin_type := UInt<1>("h00") + outer.acquire.bits.data := UInt<1>("h00") + outer.acquire.bits.addr_beat := UInt<1>("h00") + outer.acquire.bits.client_xact_id := UInt<1>("h00") + outer.acquire.bits.addr_block := UInt<1>("h00") + outer.acquire.valid := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.probe.bits.client_id := UInt<1>("h00") + inner.probe.bits.p_type := UInt<1>("h00") + inner.probe.bits.addr_block := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + inner.grant.bits.client_id := UInt<1>("h00") + inner.grant.bits.g_type := UInt<1>("h00") + inner.grant.bits.is_builtin_type := UInt<1>("h00") + inner.grant.bits.manager_xact_id := UInt<1>("h00") + inner.grant.bits.client_xact_id := UInt<1>("h00") + inner.grant.bits.data := UInt<1>("h00") + inner.grant.bits.addr_beat := UInt<1>("h00") + inner.grant.valid := UInt<1>("h00") + inner.acquire.ready := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}, clock, reset + reg data_buffer : UInt<4>[4], clock, reset + wire coh : {sharers : UInt<1>} + coh.sharers := UInt<1>("h00") + coh.sharers := UInt<1>("h00") + node T_1092 = neq(state, UInt<1>("h00")) + node T_1093 = and(T_1092, xact.is_builtin_type) + wire T_1099 : UInt<3>[4] + T_1099[0] := UInt<3>("h00") + T_1099[1] := UInt<3>("h02") + T_1099[2] := UInt<3>("h04") + T_1099[3] := UInt<3>("h05") + node T_1105 = eq(T_1099[0], xact.a_type) + node T_1106 = eq(T_1099[1], xact.a_type) + node T_1107 = eq(T_1099[2], xact.a_type) + node T_1108 = eq(T_1099[3], xact.a_type) + node T_1110 = or(UInt<1>("h00"), T_1105) + node T_1111 = or(T_1110, T_1106) + node T_1112 = or(T_1111, T_1107) + node T_1113 = or(T_1112, T_1108) + node T_1114 = and(T_1093, T_1113) + node T_1116 = eq(T_1114, UInt<1>("h00")) + reg release_count : UInt<1>, clock, reset + onreset release_count := UInt<1>("h00") + reg pending_probes : UInt<1>, clock, reset + onreset pending_probes := UInt<1>("h00") + node T_1121 = bit(pending_probes, 0) + wire T_1123 : UInt<1>[1] + T_1123[0] := T_1121 + node T_1128 = asUInt(asSInt(UInt<1>("h01"))) + node T_1131 = dshl(UInt<1>("h01"), inner.acquire.bits.client_id) + node T_1132 = or(T_1128, T_1131) + node T_1133 = not(T_1128) + node T_1134 = or(T_1133, T_1131) + node T_1135 = not(T_1134) + node mask_self = mux(UInt<1>("h00"), T_1132, T_1135) + node T_1137 = not(incoherent[0]) + node mask_incoherent = and(mask_self, T_1137) + reg collect_iacq_data : UInt<1>, clock, reset + onreset collect_iacq_data := UInt<1>("h00") + reg iacq_data_valid : UInt<4>, clock, reset + onreset iacq_data_valid := UInt<4>("h00") + node T_1143 = and(inner.acquire.ready, inner.acquire.valid) + node T_1146 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) + wire T_1149 : UInt<3>[1] + T_1149[0] := UInt<3>("h03") + node T_1152 = eq(T_1149[0], inner.acquire.bits.a_type) + node T_1154 = or(UInt<1>("h00"), T_1152) + node T_1155 = and(T_1146, T_1154) + node T_1156 = and(T_1143, T_1155) + reg T_1158 : UInt<2>, clock, reset + onreset T_1158 := UInt<2>("h00") + when T_1156 : + node T_1160 = eq(T_1158, UInt<2>("h03")) + node T_1162 = and(UInt<1>("h00"), T_1160) + node T_1165 = addw(T_1158, UInt<1>("h01")) + node T_1166 = mux(T_1162, UInt<1>("h00"), T_1165) + T_1158 := T_1166 + skip + node T_1167 = and(T_1156, T_1160) + node T_1168 = mux(T_1155, T_1158, UInt<1>("h00")) + node iacq_data_done = mux(T_1155, T_1167, T_1143) + node T_1170 = and(inner.release.ready, inner.release.valid) + wire T_1174 : UInt<2>[3] + T_1174[0] := UInt<1>("h00") + T_1174[1] := UInt<1>("h01") + T_1174[2] := UInt<2>("h02") + node T_1179 = eq(T_1174[0], inner.release.bits.r_type) + node T_1180 = eq(T_1174[1], inner.release.bits.r_type) + node T_1181 = eq(T_1174[2], inner.release.bits.r_type) + node T_1183 = or(UInt<1>("h00"), T_1179) + node T_1184 = or(T_1183, T_1180) + node T_1185 = or(T_1184, T_1181) + node T_1186 = and(UInt<1>("h01"), T_1185) + node T_1187 = and(T_1170, T_1186) + reg T_1189 : UInt<2>, clock, reset + onreset T_1189 := UInt<2>("h00") + when T_1187 : + node T_1191 = eq(T_1189, UInt<2>("h03")) + node T_1193 = and(UInt<1>("h00"), T_1191) + node T_1196 = addw(T_1189, UInt<1>("h01")) + node T_1197 = mux(T_1193, UInt<1>("h00"), T_1196) + T_1189 := T_1197 + skip + node T_1198 = and(T_1187, T_1191) + node T_1199 = mux(T_1186, T_1189, UInt<1>("h00")) + node irel_data_done = mux(T_1186, T_1198, T_1170) + node T_1202 = and(inner.grant.ready, inner.grant.valid) + wire T_1206 : UInt<3>[1] + T_1206[0] := UInt<3>("h05") + node T_1209 = eq(T_1206[0], inner.grant.bits.g_type) + node T_1211 = or(UInt<1>("h00"), T_1209) + wire T_1213 : UInt<1>[2] + T_1213[0] := UInt<1>("h00") + T_1213[1] := UInt<1>("h01") + node T_1217 = eq(T_1213[0], inner.grant.bits.g_type) + node T_1218 = eq(T_1213[1], inner.grant.bits.g_type) + node T_1220 = or(UInt<1>("h00"), T_1217) + node T_1221 = or(T_1220, T_1218) + node T_1222 = mux(inner.grant.bits.is_builtin_type, T_1211, T_1221) + node T_1223 = and(UInt<1>("h01"), T_1222) + node T_1224 = and(T_1202, T_1223) + reg T_1226 : UInt<2>, clock, reset + onreset T_1226 := UInt<2>("h00") + when T_1224 : + node T_1228 = eq(T_1226, UInt<2>("h03")) + node T_1230 = and(UInt<1>("h00"), T_1228) + node T_1233 = addw(T_1226, UInt<1>("h01")) + node T_1234 = mux(T_1230, UInt<1>("h00"), T_1233) + T_1226 := T_1234 + skip + node T_1235 = and(T_1224, T_1228) + node ignt_data_cnt = mux(T_1223, T_1226, UInt<1>("h00")) + node ignt_data_done = mux(T_1223, T_1235, T_1202) + node T_1239 = and(outer.acquire.ready, outer.acquire.valid) + node T_1241 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) + wire T_1244 : UInt<3>[1] + T_1244[0] := UInt<3>("h03") + node T_1247 = eq(T_1244[0], outer.acquire.bits.a_type) + node T_1249 = or(UInt<1>("h00"), T_1247) + node T_1250 = and(T_1241, T_1249) + node T_1251 = and(T_1239, T_1250) + reg T_1253 : UInt<2>, clock, reset + onreset T_1253 := UInt<2>("h00") + when T_1251 : + node T_1255 = eq(T_1253, UInt<2>("h03")) + node T_1257 = and(UInt<1>("h00"), T_1255) + node T_1260 = addw(T_1253, UInt<1>("h01")) + node T_1261 = mux(T_1257, UInt<1>("h00"), T_1260) + T_1253 := T_1261 + skip + node T_1262 = and(T_1251, T_1255) + node oacq_data_cnt = mux(T_1250, T_1253, UInt<1>("h00")) + node oacq_data_done = mux(T_1250, T_1262, T_1239) + node T_1265 = and(outer.grant.ready, outer.grant.valid) + wire T_1270 : UInt<3>[1] + T_1270[0] := UInt<3>("h05") + node T_1273 = eq(T_1270[0], outer.grant.bits.g_type) + node T_1275 = or(UInt<1>("h00"), T_1273) + wire T_1277 : UInt<1>[1] + T_1277[0] := UInt<1>("h00") + node T_1280 = eq(T_1277[0], outer.grant.bits.g_type) + node T_1282 = or(UInt<1>("h00"), T_1280) + node T_1283 = mux(outer.grant.bits.is_builtin_type, T_1275, T_1282) + node T_1284 = and(UInt<1>("h01"), T_1283) + node T_1285 = and(T_1265, T_1284) + reg T_1287 : UInt<2>, clock, reset + onreset T_1287 := UInt<2>("h00") + when T_1285 : + node T_1289 = eq(T_1287, UInt<2>("h03")) + node T_1291 = and(UInt<1>("h00"), T_1289) + node T_1294 = addw(T_1287, UInt<1>("h01")) + node T_1295 = mux(T_1291, UInt<1>("h00"), T_1294) + T_1287 := T_1295 + skip + node T_1296 = and(T_1285, T_1289) + node T_1297 = mux(T_1284, T_1287, UInt<1>("h00")) + node ognt_data_done = mux(T_1284, T_1296, T_1265) + reg pending_ognt_ack : UInt<1>, clock, reset + onreset pending_ognt_ack := UInt<1>("h00") + wire T_1305 : UInt<3>[3] + T_1305[0] := UInt<3>("h02") + T_1305[1] := UInt<3>("h03") + T_1305[2] := UInt<3>("h04") + node T_1310 = eq(T_1305[0], xact.a_type) + node T_1311 = eq(T_1305[1], xact.a_type) + node T_1312 = eq(T_1305[2], xact.a_type) + node T_1314 = or(UInt<1>("h00"), T_1310) + node T_1315 = or(T_1314, T_1311) + node T_1316 = or(T_1315, T_1312) + node pending_outer_write = and(xact.is_builtin_type, T_1316) + wire T_1322 : UInt<3>[3] + T_1322[0] := UInt<3>("h02") + T_1322[1] := UInt<3>("h03") + T_1322[2] := UInt<3>("h04") + node T_1327 = eq(T_1322[0], inner.acquire.bits.a_type) + node T_1328 = eq(T_1322[1], inner.acquire.bits.a_type) + node T_1329 = eq(T_1322[2], inner.acquire.bits.a_type) + node T_1331 = or(UInt<1>("h00"), T_1327) + node T_1332 = or(T_1331, T_1328) + node T_1333 = or(T_1332, T_1329) + node pending_outer_write_ = and(inner.acquire.bits.is_builtin_type, T_1333) + wire T_1338 : UInt<3>[2] + T_1338[0] := UInt<3>("h05") + T_1338[1] := UInt<3>("h04") + node T_1342 = eq(T_1338[0], inner.grant.bits.g_type) + node T_1343 = eq(T_1338[1], inner.grant.bits.g_type) + node T_1345 = or(UInt<1>("h00"), T_1342) + node T_1346 = or(T_1345, T_1343) + wire T_1348 : UInt<1>[2] + T_1348[0] := UInt<1>("h00") + T_1348[1] := UInt<1>("h01") + node T_1352 = eq(T_1348[0], inner.grant.bits.g_type) + node T_1353 = eq(T_1348[1], inner.grant.bits.g_type) + node T_1355 = or(UInt<1>("h00"), T_1352) + node T_1356 = or(T_1355, T_1353) + node pending_outer_read = mux(inner.grant.bits.is_builtin_type, T_1346, T_1356) + node T_1374 = eq(UInt<3>("h05"), inner.acquire.bits.a_type) + node T_1375 = mux(T_1374, UInt<3>("h01"), UInt<3>("h03")) + node T_1376 = eq(UInt<3>("h04"), inner.acquire.bits.a_type) + node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) + node T_1378 = eq(UInt<3>("h03"), inner.acquire.bits.a_type) + node T_1379 = mux(T_1378, UInt<3>("h03"), T_1377) + node T_1380 = eq(UInt<3>("h02"), inner.acquire.bits.a_type) + node T_1381 = mux(T_1380, UInt<3>("h03"), T_1379) + node T_1382 = eq(UInt<3>("h01"), inner.acquire.bits.a_type) + node T_1383 = mux(T_1382, UInt<3>("h05"), T_1381) + node T_1384 = eq(UInt<3>("h00"), inner.acquire.bits.a_type) + node T_1385 = mux(T_1384, UInt<3>("h04"), T_1383) + node T_1386 = eq(inner.acquire.bits.a_type, UInt<1>("h00")) + node T_1389 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1390 = mux(T_1389, UInt<1>("h00"), UInt<1>("h01")) + node T_1391 = mux(T_1386, T_1390, UInt<1>("h01")) + node T_1392 = mux(inner.acquire.bits.is_builtin_type, T_1385, T_1391) + wire T_1424 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1424.client_id := UInt<1>("h00") + T_1424.g_type := UInt<1>("h00") + T_1424.is_builtin_type := UInt<1>("h00") + T_1424.manager_xact_id := UInt<1>("h00") + T_1424.client_xact_id := UInt<1>("h00") + T_1424.data := UInt<1>("h00") + T_1424.addr_beat := UInt<1>("h00") + T_1424.client_id := inner.acquire.bits.client_id + T_1424.is_builtin_type := inner.acquire.bits.is_builtin_type + T_1424.g_type := T_1392 + T_1424.client_xact_id := inner.acquire.bits.client_xact_id + T_1424.manager_xact_id := UInt<3>("h04") + T_1424.addr_beat := UInt<1>("h00") + T_1424.data := UInt<1>("h00") + wire T_1465 : UInt<3>[2] + T_1465[0] := UInt<3>("h05") + T_1465[1] := UInt<3>("h04") + node T_1469 = eq(T_1465[0], T_1424.g_type) + node T_1470 = eq(T_1465[1], T_1424.g_type) + node T_1472 = or(UInt<1>("h00"), T_1469) + node T_1473 = or(T_1472, T_1470) + wire T_1475 : UInt<1>[2] + T_1475[0] := UInt<1>("h00") + T_1475[1] := UInt<1>("h01") + node T_1479 = eq(T_1475[0], T_1424.g_type) + node T_1480 = eq(T_1475[1], T_1424.g_type) + node T_1482 = or(UInt<1>("h00"), T_1479) + node T_1483 = or(T_1482, T_1480) + node pending_outer_read_ = mux(T_1424.is_builtin_type, T_1473, T_1483) + node T_1485 = eq(xact.addr_block, inner.acquire.bits.addr_block) + node T_1486 = neq(state, UInt<1>("h00")) + node T_1487 = and(T_1485, T_1486) + node T_1489 = eq(collect_iacq_data, UInt<1>("h00")) + node T_1490 = and(T_1487, T_1489) + has_acquire_conflict := T_1490 + node T_1491 = eq(xact.addr_block, inner.acquire.bits.addr_block) + node T_1492 = and(T_1491, collect_iacq_data) + has_acquire_match := T_1492 + node T_1493 = eq(xact.addr_block, inner.release.bits.addr_block) + node T_1495 = eq(inner.release.bits.voluntary, UInt<1>("h00")) + node T_1496 = and(T_1493, T_1495) + node T_1497 = eq(state, UInt<1>("h01")) + node T_1498 = and(T_1496, T_1497) + has_release_match := T_1498 + infer accessor T_1500 = data_buffer[oacq_data_cnt] + node T_1533 = asUInt(asSInt(UInt<1>("h01"))) + node T_1534 = cat(T_1533, UInt<1>("h01")) + wire outer_write_acq : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_write_acq.union := UInt<1>("h00") + outer_write_acq.a_type := UInt<1>("h00") + outer_write_acq.is_builtin_type := UInt<1>("h00") + outer_write_acq.data := UInt<1>("h00") + outer_write_acq.addr_beat := UInt<1>("h00") + outer_write_acq.client_xact_id := UInt<1>("h00") + outer_write_acq.addr_block := UInt<1>("h00") + outer_write_acq.is_builtin_type := UInt<1>("h01") + outer_write_acq.a_type := UInt<3>("h03") + outer_write_acq.client_xact_id := UInt<3>("h04") + outer_write_acq.addr_block := xact.addr_block + outer_write_acq.addr_beat := oacq_data_cnt + outer_write_acq.data := T_1500 + outer_write_acq.union := T_1534 + node T_1631 = asUInt(asSInt(UInt<1>("h01"))) + node T_1632 = cat(T_1631, UInt<1>("h01")) + wire outer_write_rel : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_write_rel.union := UInt<1>("h00") + outer_write_rel.a_type := UInt<1>("h00") + outer_write_rel.is_builtin_type := UInt<1>("h00") + outer_write_rel.data := UInt<1>("h00") + outer_write_rel.addr_beat := UInt<1>("h00") + outer_write_rel.client_xact_id := UInt<1>("h00") + outer_write_rel.addr_block := UInt<1>("h00") + outer_write_rel.is_builtin_type := UInt<1>("h01") + outer_write_rel.a_type := UInt<3>("h03") + outer_write_rel.client_xact_id := UInt<3>("h04") + outer_write_rel.addr_block := xact.addr_block + outer_write_rel.addr_beat := inner.release.bits.addr_beat + outer_write_rel.data := inner.release.bits.data + outer_write_rel.union := T_1632 + node T_1700 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1701 = cat(UInt<3>("h07"), T_1700) + wire outer_read : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_read.union := UInt<1>("h00") + outer_read.a_type := UInt<1>("h00") + outer_read.is_builtin_type := UInt<1>("h00") + outer_read.data := UInt<1>("h00") + outer_read.addr_beat := UInt<1>("h00") + outer_read.client_xact_id := UInt<1>("h00") + outer_read.addr_block := UInt<1>("h00") + outer_read.is_builtin_type := UInt<1>("h01") + outer_read.a_type := UInt<3>("h01") + outer_read.client_xact_id := UInt<3>("h04") + outer_read.addr_block := xact.addr_block + outer_read.addr_beat := UInt<1>("h00") + outer_read.data := UInt<1>("h00") + outer_read.union := T_1701 + outer.acquire.valid := UInt<1>("h00") + outer.acquire.bits <> outer_read + outer.grant.ready := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + node T_1775 = eq(UInt<3>("h04"), xact.a_type) + node T_1776 = mux(T_1775, UInt<1>("h00"), UInt<2>("h02")) + node T_1777 = eq(UInt<3>("h02"), xact.a_type) + node T_1778 = mux(T_1777, UInt<1>("h00"), T_1776) + node T_1779 = eq(UInt<3>("h00"), xact.a_type) + node T_1780 = mux(T_1779, UInt<2>("h02"), T_1778) + node T_1781 = eq(UInt<3>("h03"), xact.a_type) + node T_1782 = mux(T_1781, UInt<1>("h00"), T_1780) + node T_1783 = eq(UInt<3>("h01"), xact.a_type) + node T_1784 = mux(T_1783, UInt<2>("h02"), T_1782) + node T_1785 = eq(UInt<1>("h01"), xact.a_type) + node T_1786 = mux(T_1785, UInt<1>("h00"), UInt<2>("h02")) + node T_1787 = eq(UInt<1>("h00"), xact.a_type) + node T_1788 = mux(T_1787, UInt<1>("h01"), T_1786) + node T_1789 = mux(xact.is_builtin_type, T_1784, T_1788) + wire T_1817 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} + T_1817.client_id := UInt<1>("h00") + T_1817.p_type := UInt<1>("h00") + T_1817.addr_block := UInt<1>("h00") + T_1817.client_id := UInt<1>("h00") + T_1817.p_type := T_1789 + T_1817.addr_block := xact.addr_block + inner.probe.bits <> T_1817 + inner.grant.valid := UInt<1>("h00") + node T_1864 = eq(UInt<3>("h05"), xact.a_type) + node T_1865 = mux(T_1864, UInt<3>("h01"), UInt<3>("h03")) + node T_1866 = eq(UInt<3>("h04"), xact.a_type) + node T_1867 = mux(T_1866, UInt<3>("h04"), T_1865) + node T_1868 = eq(UInt<3>("h03"), xact.a_type) + node T_1869 = mux(T_1868, UInt<3>("h03"), T_1867) + node T_1870 = eq(UInt<3>("h02"), xact.a_type) + node T_1871 = mux(T_1870, UInt<3>("h03"), T_1869) + node T_1872 = eq(UInt<3>("h01"), xact.a_type) + node T_1873 = mux(T_1872, UInt<3>("h05"), T_1871) + node T_1874 = eq(UInt<3>("h00"), xact.a_type) + node T_1875 = mux(T_1874, UInt<3>("h04"), T_1873) + node T_1876 = eq(xact.a_type, UInt<1>("h00")) + node T_1879 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1880 = mux(T_1879, UInt<1>("h00"), UInt<1>("h01")) + node T_1881 = mux(T_1876, T_1880, UInt<1>("h01")) + node T_1882 = mux(xact.is_builtin_type, T_1875, T_1881) + wire T_1914 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1914.client_id := UInt<1>("h00") + T_1914.g_type := UInt<1>("h00") + T_1914.is_builtin_type := UInt<1>("h00") + T_1914.manager_xact_id := UInt<1>("h00") + T_1914.client_xact_id := UInt<1>("h00") + T_1914.data := UInt<1>("h00") + T_1914.addr_beat := UInt<1>("h00") + T_1914.client_id := xact.client_id + T_1914.is_builtin_type := xact.is_builtin_type + T_1914.g_type := T_1882 + T_1914.client_xact_id := xact.client_xact_id + T_1914.manager_xact_id := UInt<3>("h04") + T_1914.addr_beat := UInt<1>("h00") + T_1914.data := UInt<1>("h00") + inner.grant.bits <> T_1914 + inner.acquire.ready := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + node T_1955 = neq(state, UInt<1>("h00")) + node T_1956 = and(T_1955, collect_iacq_data) + node T_1957 = and(inner.acquire.ready, inner.acquire.valid) + node T_1958 = and(T_1956, T_1957) + node T_1959 = neq(inner.acquire.bits.client_id, xact.client_id) + node T_1960 = and(T_1958, T_1959) + node T_1962 = eq(T_1960, UInt<1>("h00")) + node T_1963 = neq(state, UInt<1>("h00")) + node T_1964 = and(T_1963, collect_iacq_data) + node T_1965 = and(inner.acquire.ready, inner.acquire.valid) + node T_1966 = and(T_1964, T_1965) + node T_1967 = neq(inner.acquire.bits.client_xact_id, xact.client_xact_id) + node T_1968 = and(T_1966, T_1967) + node T_1970 = eq(T_1968, UInt<1>("h00")) + node T_1971 = eq(state, UInt<1>("h00")) + node T_1972 = and(inner.acquire.ready, inner.acquire.valid) + node T_1973 = and(T_1971, T_1972) + node T_1975 = neq(inner.acquire.bits.addr_beat, UInt<1>("h00")) + node T_1976 = and(T_1973, T_1975) + node T_1978 = eq(T_1976, UInt<1>("h00")) + when collect_iacq_data : + inner.acquire.ready := UInt<1>("h01") + when inner.acquire.valid : + infer accessor T_1980 = data_buffer[inner.acquire.bits.addr_beat] + T_1980 := inner.acquire.bits.data + node T_1983 = dshl(UInt<1>("h01"), inner.acquire.bits.addr_beat) + node T_1984 = or(iacq_data_valid, T_1983) + node T_1985 = not(iacq_data_valid) + node T_1986 = or(T_1985, T_1983) + node T_1987 = not(T_1986) + node T_1988 = mux(UInt<1>("h01"), T_1984, T_1987) + iacq_data_valid := T_1988 + skip + when iacq_data_done : + collect_iacq_data := UInt<1>("h00") + skip + skip + when pending_ognt_ack : + outer.grant.ready := UInt<1>("h01") + when outer.grant.valid : + pending_ognt_ack := UInt<1>("h00") + skip + skip + node T_1992 = eq(UInt<1>("h00"), state) + when T_1992 : + inner.acquire.ready := UInt<1>("h01") + when inner.acquire.valid : + xact <> inner.acquire.bits + infer accessor T_1995 = data_buffer[UInt<1>("h00")] + T_1995 := inner.acquire.bits.data + node T_1997 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) + wire T_2000 : UInt<3>[1] + T_2000[0] := UInt<3>("h03") + node T_2003 = eq(T_2000[0], inner.acquire.bits.a_type) + node T_2005 = or(UInt<1>("h00"), T_2003) + node T_2006 = and(T_1997, T_2005) + collect_iacq_data := T_2006 + wire T_2011 : UInt<3>[3] + T_2011[0] := UInt<3>("h02") + T_2011[1] := UInt<3>("h03") + T_2011[2] := UInt<3>("h04") + node T_2016 = eq(T_2011[0], inner.acquire.bits.a_type) + node T_2017 = eq(T_2011[1], inner.acquire.bits.a_type) + node T_2018 = eq(T_2011[2], inner.acquire.bits.a_type) + node T_2020 = or(UInt<1>("h00"), T_2016) + node T_2021 = or(T_2020, T_2017) + node T_2022 = or(T_2021, T_2018) + node T_2023 = and(inner.acquire.bits.is_builtin_type, T_2022) + node T_2024 = dshl(T_2023, inner.acquire.bits.addr_beat) + iacq_data_valid := T_2024 + node T_2026 = neq(mask_incoherent, UInt<1>("h00")) + when T_2026 : + pending_probes := mask_incoherent + node T_2027 = bit(mask_incoherent, 0) + node T_2028 = bit(mask_incoherent, 1) + node T_2029 = bit(mask_incoherent, 2) + node T_2030 = bit(mask_incoherent, 3) + node T_2032 = cat(UInt<1>("h00"), T_2028) + node T_2033 = addw(T_2027, T_2032) + node T_2036 = cat(UInt<1>("h00"), T_2030) + node T_2037 = addw(T_2029, T_2036) + node T_2038 = cat(UInt<1>("h00"), T_2037) + node T_2039 = addw(T_2033, T_2038) + release_count := T_2039 + skip + node T_2040 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) + node T_2041 = mux(pending_outer_write_, UInt<2>("h03"), T_2040) + node T_2042 = mux(T_2026, UInt<1>("h01"), T_2041) + state := T_2042 + skip + skip + node T_2043 = eq(UInt<1>("h01"), state) + when T_2043 : + node T_2045 = neq(pending_probes, UInt<1>("h00")) + inner.probe.valid := T_2045 + when inner.probe.ready : + node T_2047 = dshl(UInt<1>("h01"), UInt<1>("h00")) + node T_2048 = not(T_2047) + node T_2049 = and(pending_probes, T_2048) + pending_probes := T_2049 + skip + wire T_2051 : UInt<2>[3] + T_2051[0] := UInt<1>("h00") + T_2051[1] := UInt<1>("h01") + T_2051[2] := UInt<2>("h02") + node T_2056 = eq(T_2051[0], inner.release.bits.r_type) + node T_2057 = eq(T_2051[1], inner.release.bits.r_type) + node T_2058 = eq(T_2051[2], inner.release.bits.r_type) + node T_2060 = or(UInt<1>("h00"), T_2056) + node T_2061 = or(T_2060, T_2057) + node T_2062 = or(T_2061, T_2058) + node T_2064 = eq(T_2062, UInt<1>("h00")) + node T_2065 = or(T_2064, outer.acquire.ready) + inner.release.ready := T_2065 + when inner.release.valid : + wire T_2067 : UInt<2>[3] + T_2067[0] := UInt<1>("h00") + T_2067[1] := UInt<1>("h01") + T_2067[2] := UInt<2>("h02") + node T_2072 = eq(T_2067[0], inner.release.bits.r_type) + node T_2073 = eq(T_2067[1], inner.release.bits.r_type) + node T_2074 = eq(T_2067[2], inner.release.bits.r_type) + node T_2076 = or(UInt<1>("h00"), T_2072) + node T_2077 = or(T_2076, T_2073) + node T_2078 = or(T_2077, T_2074) + when T_2078 : + outer.acquire.valid := UInt<1>("h01") + outer.acquire.bits <> outer_write_rel + when outer.acquire.ready : + when oacq_data_done : + pending_ognt_ack := UInt<1>("h01") + node T_2082 = subw(release_count, UInt<1>("h01")) + release_count := T_2082 + node T_2084 = eq(release_count, UInt<1>("h01")) + when T_2084 : + node T_2085 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_2086 = mux(pending_outer_write, UInt<2>("h03"), T_2085) + state := T_2086 + skip + skip + skip + skip + else : + node T_2088 = subw(release_count, UInt<1>("h01")) + release_count := T_2088 + node T_2090 = eq(release_count, UInt<1>("h01")) + when T_2090 : + node T_2091 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_2092 = mux(pending_outer_write, UInt<2>("h03"), T_2091) + state := T_2092 + skip + skip + skip + skip + node T_2093 = eq(UInt<2>("h03"), state) + when T_2093 : + node T_2095 = eq(pending_ognt_ack, UInt<1>("h00")) + node T_2097 = eq(collect_iacq_data, UInt<1>("h00")) + node T_2098 = or(T_2095, T_2097) + node T_2099 = dshr(iacq_data_valid, oacq_data_cnt) + node T_2100 = bit(T_2099, 0) + node T_2101 = or(T_2098, T_2100) + outer.acquire.valid := T_2101 + outer.acquire.bits <> outer_write_acq + when oacq_data_done : + pending_ognt_ack := UInt<1>("h01") + node T_2103 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) + state := T_2103 + skip + skip + node T_2104 = eq(UInt<2>("h02"), state) + when T_2104 : + node T_2106 = eq(pending_ognt_ack, UInt<1>("h00")) + outer.acquire.valid := T_2106 + outer.acquire.bits <> outer_read + node T_2107 = and(outer.acquire.ready, outer.acquire.valid) + when T_2107 : + state := UInt<3>("h05") + skip + skip + node T_2108 = eq(UInt<3>("h05"), state) + when T_2108 : + outer.grant.ready := inner.grant.ready + inner.grant.valid := outer.grant.valid + when ignt_data_done : + node T_2111 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_2113 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_2114 = and(inner.grant.bits.is_builtin_type, T_2113) + node T_2116 = eq(T_2114, UInt<1>("h00")) + node T_2117 = and(T_2111, T_2116) + node T_2118 = mux(T_2117, UInt<3>("h06"), UInt<1>("h00")) + state := T_2118 + skip + skip + node T_2119 = eq(UInt<3>("h04"), state) + when T_2119 : + inner.grant.valid := UInt<1>("h01") + when inner.grant.ready : + node T_2123 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_2125 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_2126 = and(inner.grant.bits.is_builtin_type, T_2125) + node T_2128 = eq(T_2126, UInt<1>("h00")) + node T_2129 = and(T_2123, T_2128) + node T_2130 = mux(T_2129, UInt<3>("h06"), UInt<1>("h00")) + state := T_2130 + skip + skip + node T_2131 = eq(UInt<3>("h06"), state) + when T_2131 : + inner.finish.ready := UInt<1>("h01") + when inner.finish.valid : + state := UInt<1>("h00") + skip + skip + + module BroadcastAcquireTracker_30 : + output has_release_match : UInt<1> + output has_acquire_match : UInt<1> + output has_acquire_conflict : UInt<1> + output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input incoherent : UInt<1>[1] + output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} + input clock : Clock + input reset : UInt<1> + + has_release_match := UInt<1>("h00") + has_acquire_match := UInt<1>("h00") + has_acquire_conflict := UInt<1>("h00") + outer.grant.ready := UInt<1>("h00") + outer.acquire.bits.union := UInt<1>("h00") + outer.acquire.bits.a_type := UInt<1>("h00") + outer.acquire.bits.is_builtin_type := UInt<1>("h00") + outer.acquire.bits.data := UInt<1>("h00") + outer.acquire.bits.addr_beat := UInt<1>("h00") + outer.acquire.bits.client_xact_id := UInt<1>("h00") + outer.acquire.bits.addr_block := UInt<1>("h00") + outer.acquire.valid := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.probe.bits.client_id := UInt<1>("h00") + inner.probe.bits.p_type := UInt<1>("h00") + inner.probe.bits.addr_block := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + inner.grant.bits.client_id := UInt<1>("h00") + inner.grant.bits.g_type := UInt<1>("h00") + inner.grant.bits.is_builtin_type := UInt<1>("h00") + inner.grant.bits.manager_xact_id := UInt<1>("h00") + inner.grant.bits.client_xact_id := UInt<1>("h00") + inner.grant.bits.data := UInt<1>("h00") + inner.grant.bits.addr_beat := UInt<1>("h00") + inner.grant.valid := UInt<1>("h00") + inner.acquire.ready := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}, clock, reset + reg data_buffer : UInt<4>[4], clock, reset + wire coh : {sharers : UInt<1>} + coh.sharers := UInt<1>("h00") + coh.sharers := UInt<1>("h00") + node T_1092 = neq(state, UInt<1>("h00")) + node T_1093 = and(T_1092, xact.is_builtin_type) + wire T_1099 : UInt<3>[4] + T_1099[0] := UInt<3>("h00") + T_1099[1] := UInt<3>("h02") + T_1099[2] := UInt<3>("h04") + T_1099[3] := UInt<3>("h05") + node T_1105 = eq(T_1099[0], xact.a_type) + node T_1106 = eq(T_1099[1], xact.a_type) + node T_1107 = eq(T_1099[2], xact.a_type) + node T_1108 = eq(T_1099[3], xact.a_type) + node T_1110 = or(UInt<1>("h00"), T_1105) + node T_1111 = or(T_1110, T_1106) + node T_1112 = or(T_1111, T_1107) + node T_1113 = or(T_1112, T_1108) + node T_1114 = and(T_1093, T_1113) + node T_1116 = eq(T_1114, UInt<1>("h00")) + reg release_count : UInt<1>, clock, reset + onreset release_count := UInt<1>("h00") + reg pending_probes : UInt<1>, clock, reset + onreset pending_probes := UInt<1>("h00") + node T_1121 = bit(pending_probes, 0) + wire T_1123 : UInt<1>[1] + T_1123[0] := T_1121 + node T_1128 = asUInt(asSInt(UInt<1>("h01"))) + node T_1131 = dshl(UInt<1>("h01"), inner.acquire.bits.client_id) + node T_1132 = or(T_1128, T_1131) + node T_1133 = not(T_1128) + node T_1134 = or(T_1133, T_1131) + node T_1135 = not(T_1134) + node mask_self = mux(UInt<1>("h00"), T_1132, T_1135) + node T_1137 = not(incoherent[0]) + node mask_incoherent = and(mask_self, T_1137) + reg collect_iacq_data : UInt<1>, clock, reset + onreset collect_iacq_data := UInt<1>("h00") + reg iacq_data_valid : UInt<4>, clock, reset + onreset iacq_data_valid := UInt<4>("h00") + node T_1143 = and(inner.acquire.ready, inner.acquire.valid) + node T_1146 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) + wire T_1149 : UInt<3>[1] + T_1149[0] := UInt<3>("h03") + node T_1152 = eq(T_1149[0], inner.acquire.bits.a_type) + node T_1154 = or(UInt<1>("h00"), T_1152) + node T_1155 = and(T_1146, T_1154) + node T_1156 = and(T_1143, T_1155) + reg T_1158 : UInt<2>, clock, reset + onreset T_1158 := UInt<2>("h00") + when T_1156 : + node T_1160 = eq(T_1158, UInt<2>("h03")) + node T_1162 = and(UInt<1>("h00"), T_1160) + node T_1165 = addw(T_1158, UInt<1>("h01")) + node T_1166 = mux(T_1162, UInt<1>("h00"), T_1165) + T_1158 := T_1166 + skip + node T_1167 = and(T_1156, T_1160) + node T_1168 = mux(T_1155, T_1158, UInt<1>("h00")) + node iacq_data_done = mux(T_1155, T_1167, T_1143) + node T_1170 = and(inner.release.ready, inner.release.valid) + wire T_1174 : UInt<2>[3] + T_1174[0] := UInt<1>("h00") + T_1174[1] := UInt<1>("h01") + T_1174[2] := UInt<2>("h02") + node T_1179 = eq(T_1174[0], inner.release.bits.r_type) + node T_1180 = eq(T_1174[1], inner.release.bits.r_type) + node T_1181 = eq(T_1174[2], inner.release.bits.r_type) + node T_1183 = or(UInt<1>("h00"), T_1179) + node T_1184 = or(T_1183, T_1180) + node T_1185 = or(T_1184, T_1181) + node T_1186 = and(UInt<1>("h01"), T_1185) + node T_1187 = and(T_1170, T_1186) + reg T_1189 : UInt<2>, clock, reset + onreset T_1189 := UInt<2>("h00") + when T_1187 : + node T_1191 = eq(T_1189, UInt<2>("h03")) + node T_1193 = and(UInt<1>("h00"), T_1191) + node T_1196 = addw(T_1189, UInt<1>("h01")) + node T_1197 = mux(T_1193, UInt<1>("h00"), T_1196) + T_1189 := T_1197 + skip + node T_1198 = and(T_1187, T_1191) + node T_1199 = mux(T_1186, T_1189, UInt<1>("h00")) + node irel_data_done = mux(T_1186, T_1198, T_1170) + node T_1202 = and(inner.grant.ready, inner.grant.valid) + wire T_1206 : UInt<3>[1] + T_1206[0] := UInt<3>("h05") + node T_1209 = eq(T_1206[0], inner.grant.bits.g_type) + node T_1211 = or(UInt<1>("h00"), T_1209) + wire T_1213 : UInt<1>[2] + T_1213[0] := UInt<1>("h00") + T_1213[1] := UInt<1>("h01") + node T_1217 = eq(T_1213[0], inner.grant.bits.g_type) + node T_1218 = eq(T_1213[1], inner.grant.bits.g_type) + node T_1220 = or(UInt<1>("h00"), T_1217) + node T_1221 = or(T_1220, T_1218) + node T_1222 = mux(inner.grant.bits.is_builtin_type, T_1211, T_1221) + node T_1223 = and(UInt<1>("h01"), T_1222) + node T_1224 = and(T_1202, T_1223) + reg T_1226 : UInt<2>, clock, reset + onreset T_1226 := UInt<2>("h00") + when T_1224 : + node T_1228 = eq(T_1226, UInt<2>("h03")) + node T_1230 = and(UInt<1>("h00"), T_1228) + node T_1233 = addw(T_1226, UInt<1>("h01")) + node T_1234 = mux(T_1230, UInt<1>("h00"), T_1233) + T_1226 := T_1234 + skip + node T_1235 = and(T_1224, T_1228) + node ignt_data_cnt = mux(T_1223, T_1226, UInt<1>("h00")) + node ignt_data_done = mux(T_1223, T_1235, T_1202) + node T_1239 = and(outer.acquire.ready, outer.acquire.valid) + node T_1241 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) + wire T_1244 : UInt<3>[1] + T_1244[0] := UInt<3>("h03") + node T_1247 = eq(T_1244[0], outer.acquire.bits.a_type) + node T_1249 = or(UInt<1>("h00"), T_1247) + node T_1250 = and(T_1241, T_1249) + node T_1251 = and(T_1239, T_1250) + reg T_1253 : UInt<2>, clock, reset + onreset T_1253 := UInt<2>("h00") + when T_1251 : + node T_1255 = eq(T_1253, UInt<2>("h03")) + node T_1257 = and(UInt<1>("h00"), T_1255) + node T_1260 = addw(T_1253, UInt<1>("h01")) + node T_1261 = mux(T_1257, UInt<1>("h00"), T_1260) + T_1253 := T_1261 + skip + node T_1262 = and(T_1251, T_1255) + node oacq_data_cnt = mux(T_1250, T_1253, UInt<1>("h00")) + node oacq_data_done = mux(T_1250, T_1262, T_1239) + node T_1265 = and(outer.grant.ready, outer.grant.valid) + wire T_1270 : UInt<3>[1] + T_1270[0] := UInt<3>("h05") + node T_1273 = eq(T_1270[0], outer.grant.bits.g_type) + node T_1275 = or(UInt<1>("h00"), T_1273) + wire T_1277 : UInt<1>[1] + T_1277[0] := UInt<1>("h00") + node T_1280 = eq(T_1277[0], outer.grant.bits.g_type) + node T_1282 = or(UInt<1>("h00"), T_1280) + node T_1283 = mux(outer.grant.bits.is_builtin_type, T_1275, T_1282) + node T_1284 = and(UInt<1>("h01"), T_1283) + node T_1285 = and(T_1265, T_1284) + reg T_1287 : UInt<2>, clock, reset + onreset T_1287 := UInt<2>("h00") + when T_1285 : + node T_1289 = eq(T_1287, UInt<2>("h03")) + node T_1291 = and(UInt<1>("h00"), T_1289) + node T_1294 = addw(T_1287, UInt<1>("h01")) + node T_1295 = mux(T_1291, UInt<1>("h00"), T_1294) + T_1287 := T_1295 + skip + node T_1296 = and(T_1285, T_1289) + node T_1297 = mux(T_1284, T_1287, UInt<1>("h00")) + node ognt_data_done = mux(T_1284, T_1296, T_1265) + reg pending_ognt_ack : UInt<1>, clock, reset + onreset pending_ognt_ack := UInt<1>("h00") + wire T_1305 : UInt<3>[3] + T_1305[0] := UInt<3>("h02") + T_1305[1] := UInt<3>("h03") + T_1305[2] := UInt<3>("h04") + node T_1310 = eq(T_1305[0], xact.a_type) + node T_1311 = eq(T_1305[1], xact.a_type) + node T_1312 = eq(T_1305[2], xact.a_type) + node T_1314 = or(UInt<1>("h00"), T_1310) + node T_1315 = or(T_1314, T_1311) + node T_1316 = or(T_1315, T_1312) + node pending_outer_write = and(xact.is_builtin_type, T_1316) + wire T_1322 : UInt<3>[3] + T_1322[0] := UInt<3>("h02") + T_1322[1] := UInt<3>("h03") + T_1322[2] := UInt<3>("h04") + node T_1327 = eq(T_1322[0], inner.acquire.bits.a_type) + node T_1328 = eq(T_1322[1], inner.acquire.bits.a_type) + node T_1329 = eq(T_1322[2], inner.acquire.bits.a_type) + node T_1331 = or(UInt<1>("h00"), T_1327) + node T_1332 = or(T_1331, T_1328) + node T_1333 = or(T_1332, T_1329) + node pending_outer_write_ = and(inner.acquire.bits.is_builtin_type, T_1333) + wire T_1338 : UInt<3>[2] + T_1338[0] := UInt<3>("h05") + T_1338[1] := UInt<3>("h04") + node T_1342 = eq(T_1338[0], inner.grant.bits.g_type) + node T_1343 = eq(T_1338[1], inner.grant.bits.g_type) + node T_1345 = or(UInt<1>("h00"), T_1342) + node T_1346 = or(T_1345, T_1343) + wire T_1348 : UInt<1>[2] + T_1348[0] := UInt<1>("h00") + T_1348[1] := UInt<1>("h01") + node T_1352 = eq(T_1348[0], inner.grant.bits.g_type) + node T_1353 = eq(T_1348[1], inner.grant.bits.g_type) + node T_1355 = or(UInt<1>("h00"), T_1352) + node T_1356 = or(T_1355, T_1353) + node pending_outer_read = mux(inner.grant.bits.is_builtin_type, T_1346, T_1356) + node T_1374 = eq(UInt<3>("h05"), inner.acquire.bits.a_type) + node T_1375 = mux(T_1374, UInt<3>("h01"), UInt<3>("h03")) + node T_1376 = eq(UInt<3>("h04"), inner.acquire.bits.a_type) + node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) + node T_1378 = eq(UInt<3>("h03"), inner.acquire.bits.a_type) + node T_1379 = mux(T_1378, UInt<3>("h03"), T_1377) + node T_1380 = eq(UInt<3>("h02"), inner.acquire.bits.a_type) + node T_1381 = mux(T_1380, UInt<3>("h03"), T_1379) + node T_1382 = eq(UInt<3>("h01"), inner.acquire.bits.a_type) + node T_1383 = mux(T_1382, UInt<3>("h05"), T_1381) + node T_1384 = eq(UInt<3>("h00"), inner.acquire.bits.a_type) + node T_1385 = mux(T_1384, UInt<3>("h04"), T_1383) + node T_1386 = eq(inner.acquire.bits.a_type, UInt<1>("h00")) + node T_1389 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1390 = mux(T_1389, UInt<1>("h00"), UInt<1>("h01")) + node T_1391 = mux(T_1386, T_1390, UInt<1>("h01")) + node T_1392 = mux(inner.acquire.bits.is_builtin_type, T_1385, T_1391) + wire T_1424 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1424.client_id := UInt<1>("h00") + T_1424.g_type := UInt<1>("h00") + T_1424.is_builtin_type := UInt<1>("h00") + T_1424.manager_xact_id := UInt<1>("h00") + T_1424.client_xact_id := UInt<1>("h00") + T_1424.data := UInt<1>("h00") + T_1424.addr_beat := UInt<1>("h00") + T_1424.client_id := inner.acquire.bits.client_id + T_1424.is_builtin_type := inner.acquire.bits.is_builtin_type + T_1424.g_type := T_1392 + T_1424.client_xact_id := inner.acquire.bits.client_xact_id + T_1424.manager_xact_id := UInt<3>("h05") + T_1424.addr_beat := UInt<1>("h00") + T_1424.data := UInt<1>("h00") + wire T_1465 : UInt<3>[2] + T_1465[0] := UInt<3>("h05") + T_1465[1] := UInt<3>("h04") + node T_1469 = eq(T_1465[0], T_1424.g_type) + node T_1470 = eq(T_1465[1], T_1424.g_type) + node T_1472 = or(UInt<1>("h00"), T_1469) + node T_1473 = or(T_1472, T_1470) + wire T_1475 : UInt<1>[2] + T_1475[0] := UInt<1>("h00") + T_1475[1] := UInt<1>("h01") + node T_1479 = eq(T_1475[0], T_1424.g_type) + node T_1480 = eq(T_1475[1], T_1424.g_type) + node T_1482 = or(UInt<1>("h00"), T_1479) + node T_1483 = or(T_1482, T_1480) + node pending_outer_read_ = mux(T_1424.is_builtin_type, T_1473, T_1483) + node T_1485 = eq(xact.addr_block, inner.acquire.bits.addr_block) + node T_1486 = neq(state, UInt<1>("h00")) + node T_1487 = and(T_1485, T_1486) + node T_1489 = eq(collect_iacq_data, UInt<1>("h00")) + node T_1490 = and(T_1487, T_1489) + has_acquire_conflict := T_1490 + node T_1491 = eq(xact.addr_block, inner.acquire.bits.addr_block) + node T_1492 = and(T_1491, collect_iacq_data) + has_acquire_match := T_1492 + node T_1493 = eq(xact.addr_block, inner.release.bits.addr_block) + node T_1495 = eq(inner.release.bits.voluntary, UInt<1>("h00")) + node T_1496 = and(T_1493, T_1495) + node T_1497 = eq(state, UInt<1>("h01")) + node T_1498 = and(T_1496, T_1497) + has_release_match := T_1498 + infer accessor T_1500 = data_buffer[oacq_data_cnt] + node T_1533 = asUInt(asSInt(UInt<1>("h01"))) + node T_1534 = cat(T_1533, UInt<1>("h01")) + wire outer_write_acq : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_write_acq.union := UInt<1>("h00") + outer_write_acq.a_type := UInt<1>("h00") + outer_write_acq.is_builtin_type := UInt<1>("h00") + outer_write_acq.data := UInt<1>("h00") + outer_write_acq.addr_beat := UInt<1>("h00") + outer_write_acq.client_xact_id := UInt<1>("h00") + outer_write_acq.addr_block := UInt<1>("h00") + outer_write_acq.is_builtin_type := UInt<1>("h01") + outer_write_acq.a_type := UInt<3>("h03") + outer_write_acq.client_xact_id := UInt<3>("h05") + outer_write_acq.addr_block := xact.addr_block + outer_write_acq.addr_beat := oacq_data_cnt + outer_write_acq.data := T_1500 + outer_write_acq.union := T_1534 + node T_1631 = asUInt(asSInt(UInt<1>("h01"))) + node T_1632 = cat(T_1631, UInt<1>("h01")) + wire outer_write_rel : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_write_rel.union := UInt<1>("h00") + outer_write_rel.a_type := UInt<1>("h00") + outer_write_rel.is_builtin_type := UInt<1>("h00") + outer_write_rel.data := UInt<1>("h00") + outer_write_rel.addr_beat := UInt<1>("h00") + outer_write_rel.client_xact_id := UInt<1>("h00") + outer_write_rel.addr_block := UInt<1>("h00") + outer_write_rel.is_builtin_type := UInt<1>("h01") + outer_write_rel.a_type := UInt<3>("h03") + outer_write_rel.client_xact_id := UInt<3>("h05") + outer_write_rel.addr_block := xact.addr_block + outer_write_rel.addr_beat := inner.release.bits.addr_beat + outer_write_rel.data := inner.release.bits.data + outer_write_rel.union := T_1632 + node T_1700 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1701 = cat(UInt<3>("h07"), T_1700) + wire outer_read : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_read.union := UInt<1>("h00") + outer_read.a_type := UInt<1>("h00") + outer_read.is_builtin_type := UInt<1>("h00") + outer_read.data := UInt<1>("h00") + outer_read.addr_beat := UInt<1>("h00") + outer_read.client_xact_id := UInt<1>("h00") + outer_read.addr_block := UInt<1>("h00") + outer_read.is_builtin_type := UInt<1>("h01") + outer_read.a_type := UInt<3>("h01") + outer_read.client_xact_id := UInt<3>("h05") + outer_read.addr_block := xact.addr_block + outer_read.addr_beat := UInt<1>("h00") + outer_read.data := UInt<1>("h00") + outer_read.union := T_1701 + outer.acquire.valid := UInt<1>("h00") + outer.acquire.bits <> outer_read + outer.grant.ready := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + node T_1775 = eq(UInt<3>("h04"), xact.a_type) + node T_1776 = mux(T_1775, UInt<1>("h00"), UInt<2>("h02")) + node T_1777 = eq(UInt<3>("h02"), xact.a_type) + node T_1778 = mux(T_1777, UInt<1>("h00"), T_1776) + node T_1779 = eq(UInt<3>("h00"), xact.a_type) + node T_1780 = mux(T_1779, UInt<2>("h02"), T_1778) + node T_1781 = eq(UInt<3>("h03"), xact.a_type) + node T_1782 = mux(T_1781, UInt<1>("h00"), T_1780) + node T_1783 = eq(UInt<3>("h01"), xact.a_type) + node T_1784 = mux(T_1783, UInt<2>("h02"), T_1782) + node T_1785 = eq(UInt<1>("h01"), xact.a_type) + node T_1786 = mux(T_1785, UInt<1>("h00"), UInt<2>("h02")) + node T_1787 = eq(UInt<1>("h00"), xact.a_type) + node T_1788 = mux(T_1787, UInt<1>("h01"), T_1786) + node T_1789 = mux(xact.is_builtin_type, T_1784, T_1788) + wire T_1817 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} + T_1817.client_id := UInt<1>("h00") + T_1817.p_type := UInt<1>("h00") + T_1817.addr_block := UInt<1>("h00") + T_1817.client_id := UInt<1>("h00") + T_1817.p_type := T_1789 + T_1817.addr_block := xact.addr_block + inner.probe.bits <> T_1817 + inner.grant.valid := UInt<1>("h00") + node T_1864 = eq(UInt<3>("h05"), xact.a_type) + node T_1865 = mux(T_1864, UInt<3>("h01"), UInt<3>("h03")) + node T_1866 = eq(UInt<3>("h04"), xact.a_type) + node T_1867 = mux(T_1866, UInt<3>("h04"), T_1865) + node T_1868 = eq(UInt<3>("h03"), xact.a_type) + node T_1869 = mux(T_1868, UInt<3>("h03"), T_1867) + node T_1870 = eq(UInt<3>("h02"), xact.a_type) + node T_1871 = mux(T_1870, UInt<3>("h03"), T_1869) + node T_1872 = eq(UInt<3>("h01"), xact.a_type) + node T_1873 = mux(T_1872, UInt<3>("h05"), T_1871) + node T_1874 = eq(UInt<3>("h00"), xact.a_type) + node T_1875 = mux(T_1874, UInt<3>("h04"), T_1873) + node T_1876 = eq(xact.a_type, UInt<1>("h00")) + node T_1879 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1880 = mux(T_1879, UInt<1>("h00"), UInt<1>("h01")) + node T_1881 = mux(T_1876, T_1880, UInt<1>("h01")) + node T_1882 = mux(xact.is_builtin_type, T_1875, T_1881) + wire T_1914 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1914.client_id := UInt<1>("h00") + T_1914.g_type := UInt<1>("h00") + T_1914.is_builtin_type := UInt<1>("h00") + T_1914.manager_xact_id := UInt<1>("h00") + T_1914.client_xact_id := UInt<1>("h00") + T_1914.data := UInt<1>("h00") + T_1914.addr_beat := UInt<1>("h00") + T_1914.client_id := xact.client_id + T_1914.is_builtin_type := xact.is_builtin_type + T_1914.g_type := T_1882 + T_1914.client_xact_id := xact.client_xact_id + T_1914.manager_xact_id := UInt<3>("h05") + T_1914.addr_beat := UInt<1>("h00") + T_1914.data := UInt<1>("h00") + inner.grant.bits <> T_1914 + inner.acquire.ready := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + node T_1955 = neq(state, UInt<1>("h00")) + node T_1956 = and(T_1955, collect_iacq_data) + node T_1957 = and(inner.acquire.ready, inner.acquire.valid) + node T_1958 = and(T_1956, T_1957) + node T_1959 = neq(inner.acquire.bits.client_id, xact.client_id) + node T_1960 = and(T_1958, T_1959) + node T_1962 = eq(T_1960, UInt<1>("h00")) + node T_1963 = neq(state, UInt<1>("h00")) + node T_1964 = and(T_1963, collect_iacq_data) + node T_1965 = and(inner.acquire.ready, inner.acquire.valid) + node T_1966 = and(T_1964, T_1965) + node T_1967 = neq(inner.acquire.bits.client_xact_id, xact.client_xact_id) + node T_1968 = and(T_1966, T_1967) + node T_1970 = eq(T_1968, UInt<1>("h00")) + node T_1971 = eq(state, UInt<1>("h00")) + node T_1972 = and(inner.acquire.ready, inner.acquire.valid) + node T_1973 = and(T_1971, T_1972) + node T_1975 = neq(inner.acquire.bits.addr_beat, UInt<1>("h00")) + node T_1976 = and(T_1973, T_1975) + node T_1978 = eq(T_1976, UInt<1>("h00")) + when collect_iacq_data : + inner.acquire.ready := UInt<1>("h01") + when inner.acquire.valid : + infer accessor T_1980 = data_buffer[inner.acquire.bits.addr_beat] + T_1980 := inner.acquire.bits.data + node T_1983 = dshl(UInt<1>("h01"), inner.acquire.bits.addr_beat) + node T_1984 = or(iacq_data_valid, T_1983) + node T_1985 = not(iacq_data_valid) + node T_1986 = or(T_1985, T_1983) + node T_1987 = not(T_1986) + node T_1988 = mux(UInt<1>("h01"), T_1984, T_1987) + iacq_data_valid := T_1988 + skip + when iacq_data_done : + collect_iacq_data := UInt<1>("h00") + skip + skip + when pending_ognt_ack : + outer.grant.ready := UInt<1>("h01") + when outer.grant.valid : + pending_ognt_ack := UInt<1>("h00") + skip + skip + node T_1992 = eq(UInt<1>("h00"), state) + when T_1992 : + inner.acquire.ready := UInt<1>("h01") + when inner.acquire.valid : + xact <> inner.acquire.bits + infer accessor T_1995 = data_buffer[UInt<1>("h00")] + T_1995 := inner.acquire.bits.data + node T_1997 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) + wire T_2000 : UInt<3>[1] + T_2000[0] := UInt<3>("h03") + node T_2003 = eq(T_2000[0], inner.acquire.bits.a_type) + node T_2005 = or(UInt<1>("h00"), T_2003) + node T_2006 = and(T_1997, T_2005) + collect_iacq_data := T_2006 + wire T_2011 : UInt<3>[3] + T_2011[0] := UInt<3>("h02") + T_2011[1] := UInt<3>("h03") + T_2011[2] := UInt<3>("h04") + node T_2016 = eq(T_2011[0], inner.acquire.bits.a_type) + node T_2017 = eq(T_2011[1], inner.acquire.bits.a_type) + node T_2018 = eq(T_2011[2], inner.acquire.bits.a_type) + node T_2020 = or(UInt<1>("h00"), T_2016) + node T_2021 = or(T_2020, T_2017) + node T_2022 = or(T_2021, T_2018) + node T_2023 = and(inner.acquire.bits.is_builtin_type, T_2022) + node T_2024 = dshl(T_2023, inner.acquire.bits.addr_beat) + iacq_data_valid := T_2024 + node T_2026 = neq(mask_incoherent, UInt<1>("h00")) + when T_2026 : + pending_probes := mask_incoherent + node T_2027 = bit(mask_incoherent, 0) + node T_2028 = bit(mask_incoherent, 1) + node T_2029 = bit(mask_incoherent, 2) + node T_2030 = bit(mask_incoherent, 3) + node T_2032 = cat(UInt<1>("h00"), T_2028) + node T_2033 = addw(T_2027, T_2032) + node T_2036 = cat(UInt<1>("h00"), T_2030) + node T_2037 = addw(T_2029, T_2036) + node T_2038 = cat(UInt<1>("h00"), T_2037) + node T_2039 = addw(T_2033, T_2038) + release_count := T_2039 + skip + node T_2040 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) + node T_2041 = mux(pending_outer_write_, UInt<2>("h03"), T_2040) + node T_2042 = mux(T_2026, UInt<1>("h01"), T_2041) + state := T_2042 + skip + skip + node T_2043 = eq(UInt<1>("h01"), state) + when T_2043 : + node T_2045 = neq(pending_probes, UInt<1>("h00")) + inner.probe.valid := T_2045 + when inner.probe.ready : + node T_2047 = dshl(UInt<1>("h01"), UInt<1>("h00")) + node T_2048 = not(T_2047) + node T_2049 = and(pending_probes, T_2048) + pending_probes := T_2049 + skip + wire T_2051 : UInt<2>[3] + T_2051[0] := UInt<1>("h00") + T_2051[1] := UInt<1>("h01") + T_2051[2] := UInt<2>("h02") + node T_2056 = eq(T_2051[0], inner.release.bits.r_type) + node T_2057 = eq(T_2051[1], inner.release.bits.r_type) + node T_2058 = eq(T_2051[2], inner.release.bits.r_type) + node T_2060 = or(UInt<1>("h00"), T_2056) + node T_2061 = or(T_2060, T_2057) + node T_2062 = or(T_2061, T_2058) + node T_2064 = eq(T_2062, UInt<1>("h00")) + node T_2065 = or(T_2064, outer.acquire.ready) + inner.release.ready := T_2065 + when inner.release.valid : + wire T_2067 : UInt<2>[3] + T_2067[0] := UInt<1>("h00") + T_2067[1] := UInt<1>("h01") + T_2067[2] := UInt<2>("h02") + node T_2072 = eq(T_2067[0], inner.release.bits.r_type) + node T_2073 = eq(T_2067[1], inner.release.bits.r_type) + node T_2074 = eq(T_2067[2], inner.release.bits.r_type) + node T_2076 = or(UInt<1>("h00"), T_2072) + node T_2077 = or(T_2076, T_2073) + node T_2078 = or(T_2077, T_2074) + when T_2078 : + outer.acquire.valid := UInt<1>("h01") + outer.acquire.bits <> outer_write_rel + when outer.acquire.ready : + when oacq_data_done : + pending_ognt_ack := UInt<1>("h01") + node T_2082 = subw(release_count, UInt<1>("h01")) + release_count := T_2082 + node T_2084 = eq(release_count, UInt<1>("h01")) + when T_2084 : + node T_2085 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_2086 = mux(pending_outer_write, UInt<2>("h03"), T_2085) + state := T_2086 + skip + skip + skip + skip + else : + node T_2088 = subw(release_count, UInt<1>("h01")) + release_count := T_2088 + node T_2090 = eq(release_count, UInt<1>("h01")) + when T_2090 : + node T_2091 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_2092 = mux(pending_outer_write, UInt<2>("h03"), T_2091) + state := T_2092 + skip + skip + skip + skip + node T_2093 = eq(UInt<2>("h03"), state) + when T_2093 : + node T_2095 = eq(pending_ognt_ack, UInt<1>("h00")) + node T_2097 = eq(collect_iacq_data, UInt<1>("h00")) + node T_2098 = or(T_2095, T_2097) + node T_2099 = dshr(iacq_data_valid, oacq_data_cnt) + node T_2100 = bit(T_2099, 0) + node T_2101 = or(T_2098, T_2100) + outer.acquire.valid := T_2101 + outer.acquire.bits <> outer_write_acq + when oacq_data_done : + pending_ognt_ack := UInt<1>("h01") + node T_2103 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) + state := T_2103 + skip + skip + node T_2104 = eq(UInt<2>("h02"), state) + when T_2104 : + node T_2106 = eq(pending_ognt_ack, UInt<1>("h00")) + outer.acquire.valid := T_2106 + outer.acquire.bits <> outer_read + node T_2107 = and(outer.acquire.ready, outer.acquire.valid) + when T_2107 : + state := UInt<3>("h05") + skip + skip + node T_2108 = eq(UInt<3>("h05"), state) + when T_2108 : + outer.grant.ready := inner.grant.ready + inner.grant.valid := outer.grant.valid + when ignt_data_done : + node T_2111 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_2113 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_2114 = and(inner.grant.bits.is_builtin_type, T_2113) + node T_2116 = eq(T_2114, UInt<1>("h00")) + node T_2117 = and(T_2111, T_2116) + node T_2118 = mux(T_2117, UInt<3>("h06"), UInt<1>("h00")) + state := T_2118 + skip + skip + node T_2119 = eq(UInt<3>("h04"), state) + when T_2119 : + inner.grant.valid := UInt<1>("h01") + when inner.grant.ready : + node T_2123 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_2125 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_2126 = and(inner.grant.bits.is_builtin_type, T_2125) + node T_2128 = eq(T_2126, UInt<1>("h00")) + node T_2129 = and(T_2123, T_2128) + node T_2130 = mux(T_2129, UInt<3>("h06"), UInt<1>("h00")) + state := T_2130 + skip + skip + node T_2131 = eq(UInt<3>("h06"), state) + when T_2131 : + inner.finish.ready := UInt<1>("h01") + when inner.finish.valid : + state := UInt<1>("h00") + skip + skip + + module BroadcastAcquireTracker_31 : + output has_release_match : UInt<1> + output has_acquire_match : UInt<1> + output has_acquire_conflict : UInt<1> + output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input incoherent : UInt<1>[1] + output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} + input clock : Clock + input reset : UInt<1> + + has_release_match := UInt<1>("h00") + has_acquire_match := UInt<1>("h00") + has_acquire_conflict := UInt<1>("h00") + outer.grant.ready := UInt<1>("h00") + outer.acquire.bits.union := UInt<1>("h00") + outer.acquire.bits.a_type := UInt<1>("h00") + outer.acquire.bits.is_builtin_type := UInt<1>("h00") + outer.acquire.bits.data := UInt<1>("h00") + outer.acquire.bits.addr_beat := UInt<1>("h00") + outer.acquire.bits.client_xact_id := UInt<1>("h00") + outer.acquire.bits.addr_block := UInt<1>("h00") + outer.acquire.valid := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.probe.bits.client_id := UInt<1>("h00") + inner.probe.bits.p_type := UInt<1>("h00") + inner.probe.bits.addr_block := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + inner.grant.bits.client_id := UInt<1>("h00") + inner.grant.bits.g_type := UInt<1>("h00") + inner.grant.bits.is_builtin_type := UInt<1>("h00") + inner.grant.bits.manager_xact_id := UInt<1>("h00") + inner.grant.bits.client_xact_id := UInt<1>("h00") + inner.grant.bits.data := UInt<1>("h00") + inner.grant.bits.addr_beat := UInt<1>("h00") + inner.grant.valid := UInt<1>("h00") + inner.acquire.ready := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}, clock, reset + reg data_buffer : UInt<4>[4], clock, reset + wire coh : {sharers : UInt<1>} + coh.sharers := UInt<1>("h00") + coh.sharers := UInt<1>("h00") + node T_1092 = neq(state, UInt<1>("h00")) + node T_1093 = and(T_1092, xact.is_builtin_type) + wire T_1099 : UInt<3>[4] + T_1099[0] := UInt<3>("h00") + T_1099[1] := UInt<3>("h02") + T_1099[2] := UInt<3>("h04") + T_1099[3] := UInt<3>("h05") + node T_1105 = eq(T_1099[0], xact.a_type) + node T_1106 = eq(T_1099[1], xact.a_type) + node T_1107 = eq(T_1099[2], xact.a_type) + node T_1108 = eq(T_1099[3], xact.a_type) + node T_1110 = or(UInt<1>("h00"), T_1105) + node T_1111 = or(T_1110, T_1106) + node T_1112 = or(T_1111, T_1107) + node T_1113 = or(T_1112, T_1108) + node T_1114 = and(T_1093, T_1113) + node T_1116 = eq(T_1114, UInt<1>("h00")) + reg release_count : UInt<1>, clock, reset + onreset release_count := UInt<1>("h00") + reg pending_probes : UInt<1>, clock, reset + onreset pending_probes := UInt<1>("h00") + node T_1121 = bit(pending_probes, 0) + wire T_1123 : UInt<1>[1] + T_1123[0] := T_1121 + node T_1128 = asUInt(asSInt(UInt<1>("h01"))) + node T_1131 = dshl(UInt<1>("h01"), inner.acquire.bits.client_id) + node T_1132 = or(T_1128, T_1131) + node T_1133 = not(T_1128) + node T_1134 = or(T_1133, T_1131) + node T_1135 = not(T_1134) + node mask_self = mux(UInt<1>("h00"), T_1132, T_1135) + node T_1137 = not(incoherent[0]) + node mask_incoherent = and(mask_self, T_1137) + reg collect_iacq_data : UInt<1>, clock, reset + onreset collect_iacq_data := UInt<1>("h00") + reg iacq_data_valid : UInt<4>, clock, reset + onreset iacq_data_valid := UInt<4>("h00") + node T_1143 = and(inner.acquire.ready, inner.acquire.valid) + node T_1146 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) + wire T_1149 : UInt<3>[1] + T_1149[0] := UInt<3>("h03") + node T_1152 = eq(T_1149[0], inner.acquire.bits.a_type) + node T_1154 = or(UInt<1>("h00"), T_1152) + node T_1155 = and(T_1146, T_1154) + node T_1156 = and(T_1143, T_1155) + reg T_1158 : UInt<2>, clock, reset + onreset T_1158 := UInt<2>("h00") + when T_1156 : + node T_1160 = eq(T_1158, UInt<2>("h03")) + node T_1162 = and(UInt<1>("h00"), T_1160) + node T_1165 = addw(T_1158, UInt<1>("h01")) + node T_1166 = mux(T_1162, UInt<1>("h00"), T_1165) + T_1158 := T_1166 + skip + node T_1167 = and(T_1156, T_1160) + node T_1168 = mux(T_1155, T_1158, UInt<1>("h00")) + node iacq_data_done = mux(T_1155, T_1167, T_1143) + node T_1170 = and(inner.release.ready, inner.release.valid) + wire T_1174 : UInt<2>[3] + T_1174[0] := UInt<1>("h00") + T_1174[1] := UInt<1>("h01") + T_1174[2] := UInt<2>("h02") + node T_1179 = eq(T_1174[0], inner.release.bits.r_type) + node T_1180 = eq(T_1174[1], inner.release.bits.r_type) + node T_1181 = eq(T_1174[2], inner.release.bits.r_type) + node T_1183 = or(UInt<1>("h00"), T_1179) + node T_1184 = or(T_1183, T_1180) + node T_1185 = or(T_1184, T_1181) + node T_1186 = and(UInt<1>("h01"), T_1185) + node T_1187 = and(T_1170, T_1186) + reg T_1189 : UInt<2>, clock, reset + onreset T_1189 := UInt<2>("h00") + when T_1187 : + node T_1191 = eq(T_1189, UInt<2>("h03")) + node T_1193 = and(UInt<1>("h00"), T_1191) + node T_1196 = addw(T_1189, UInt<1>("h01")) + node T_1197 = mux(T_1193, UInt<1>("h00"), T_1196) + T_1189 := T_1197 + skip + node T_1198 = and(T_1187, T_1191) + node T_1199 = mux(T_1186, T_1189, UInt<1>("h00")) + node irel_data_done = mux(T_1186, T_1198, T_1170) + node T_1202 = and(inner.grant.ready, inner.grant.valid) + wire T_1206 : UInt<3>[1] + T_1206[0] := UInt<3>("h05") + node T_1209 = eq(T_1206[0], inner.grant.bits.g_type) + node T_1211 = or(UInt<1>("h00"), T_1209) + wire T_1213 : UInt<1>[2] + T_1213[0] := UInt<1>("h00") + T_1213[1] := UInt<1>("h01") + node T_1217 = eq(T_1213[0], inner.grant.bits.g_type) + node T_1218 = eq(T_1213[1], inner.grant.bits.g_type) + node T_1220 = or(UInt<1>("h00"), T_1217) + node T_1221 = or(T_1220, T_1218) + node T_1222 = mux(inner.grant.bits.is_builtin_type, T_1211, T_1221) + node T_1223 = and(UInt<1>("h01"), T_1222) + node T_1224 = and(T_1202, T_1223) + reg T_1226 : UInt<2>, clock, reset + onreset T_1226 := UInt<2>("h00") + when T_1224 : + node T_1228 = eq(T_1226, UInt<2>("h03")) + node T_1230 = and(UInt<1>("h00"), T_1228) + node T_1233 = addw(T_1226, UInt<1>("h01")) + node T_1234 = mux(T_1230, UInt<1>("h00"), T_1233) + T_1226 := T_1234 + skip + node T_1235 = and(T_1224, T_1228) + node ignt_data_cnt = mux(T_1223, T_1226, UInt<1>("h00")) + node ignt_data_done = mux(T_1223, T_1235, T_1202) + node T_1239 = and(outer.acquire.ready, outer.acquire.valid) + node T_1241 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) + wire T_1244 : UInt<3>[1] + T_1244[0] := UInt<3>("h03") + node T_1247 = eq(T_1244[0], outer.acquire.bits.a_type) + node T_1249 = or(UInt<1>("h00"), T_1247) + node T_1250 = and(T_1241, T_1249) + node T_1251 = and(T_1239, T_1250) + reg T_1253 : UInt<2>, clock, reset + onreset T_1253 := UInt<2>("h00") + when T_1251 : + node T_1255 = eq(T_1253, UInt<2>("h03")) + node T_1257 = and(UInt<1>("h00"), T_1255) + node T_1260 = addw(T_1253, UInt<1>("h01")) + node T_1261 = mux(T_1257, UInt<1>("h00"), T_1260) + T_1253 := T_1261 + skip + node T_1262 = and(T_1251, T_1255) + node oacq_data_cnt = mux(T_1250, T_1253, UInt<1>("h00")) + node oacq_data_done = mux(T_1250, T_1262, T_1239) + node T_1265 = and(outer.grant.ready, outer.grant.valid) + wire T_1270 : UInt<3>[1] + T_1270[0] := UInt<3>("h05") + node T_1273 = eq(T_1270[0], outer.grant.bits.g_type) + node T_1275 = or(UInt<1>("h00"), T_1273) + wire T_1277 : UInt<1>[1] + T_1277[0] := UInt<1>("h00") + node T_1280 = eq(T_1277[0], outer.grant.bits.g_type) + node T_1282 = or(UInt<1>("h00"), T_1280) + node T_1283 = mux(outer.grant.bits.is_builtin_type, T_1275, T_1282) + node T_1284 = and(UInt<1>("h01"), T_1283) + node T_1285 = and(T_1265, T_1284) + reg T_1287 : UInt<2>, clock, reset + onreset T_1287 := UInt<2>("h00") + when T_1285 : + node T_1289 = eq(T_1287, UInt<2>("h03")) + node T_1291 = and(UInt<1>("h00"), T_1289) + node T_1294 = addw(T_1287, UInt<1>("h01")) + node T_1295 = mux(T_1291, UInt<1>("h00"), T_1294) + T_1287 := T_1295 + skip + node T_1296 = and(T_1285, T_1289) + node T_1297 = mux(T_1284, T_1287, UInt<1>("h00")) + node ognt_data_done = mux(T_1284, T_1296, T_1265) + reg pending_ognt_ack : UInt<1>, clock, reset + onreset pending_ognt_ack := UInt<1>("h00") + wire T_1305 : UInt<3>[3] + T_1305[0] := UInt<3>("h02") + T_1305[1] := UInt<3>("h03") + T_1305[2] := UInt<3>("h04") + node T_1310 = eq(T_1305[0], xact.a_type) + node T_1311 = eq(T_1305[1], xact.a_type) + node T_1312 = eq(T_1305[2], xact.a_type) + node T_1314 = or(UInt<1>("h00"), T_1310) + node T_1315 = or(T_1314, T_1311) + node T_1316 = or(T_1315, T_1312) + node pending_outer_write = and(xact.is_builtin_type, T_1316) + wire T_1322 : UInt<3>[3] + T_1322[0] := UInt<3>("h02") + T_1322[1] := UInt<3>("h03") + T_1322[2] := UInt<3>("h04") + node T_1327 = eq(T_1322[0], inner.acquire.bits.a_type) + node T_1328 = eq(T_1322[1], inner.acquire.bits.a_type) + node T_1329 = eq(T_1322[2], inner.acquire.bits.a_type) + node T_1331 = or(UInt<1>("h00"), T_1327) + node T_1332 = or(T_1331, T_1328) + node T_1333 = or(T_1332, T_1329) + node pending_outer_write_ = and(inner.acquire.bits.is_builtin_type, T_1333) + wire T_1338 : UInt<3>[2] + T_1338[0] := UInt<3>("h05") + T_1338[1] := UInt<3>("h04") + node T_1342 = eq(T_1338[0], inner.grant.bits.g_type) + node T_1343 = eq(T_1338[1], inner.grant.bits.g_type) + node T_1345 = or(UInt<1>("h00"), T_1342) + node T_1346 = or(T_1345, T_1343) + wire T_1348 : UInt<1>[2] + T_1348[0] := UInt<1>("h00") + T_1348[1] := UInt<1>("h01") + node T_1352 = eq(T_1348[0], inner.grant.bits.g_type) + node T_1353 = eq(T_1348[1], inner.grant.bits.g_type) + node T_1355 = or(UInt<1>("h00"), T_1352) + node T_1356 = or(T_1355, T_1353) + node pending_outer_read = mux(inner.grant.bits.is_builtin_type, T_1346, T_1356) + node T_1374 = eq(UInt<3>("h05"), inner.acquire.bits.a_type) + node T_1375 = mux(T_1374, UInt<3>("h01"), UInt<3>("h03")) + node T_1376 = eq(UInt<3>("h04"), inner.acquire.bits.a_type) + node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) + node T_1378 = eq(UInt<3>("h03"), inner.acquire.bits.a_type) + node T_1379 = mux(T_1378, UInt<3>("h03"), T_1377) + node T_1380 = eq(UInt<3>("h02"), inner.acquire.bits.a_type) + node T_1381 = mux(T_1380, UInt<3>("h03"), T_1379) + node T_1382 = eq(UInt<3>("h01"), inner.acquire.bits.a_type) + node T_1383 = mux(T_1382, UInt<3>("h05"), T_1381) + node T_1384 = eq(UInt<3>("h00"), inner.acquire.bits.a_type) + node T_1385 = mux(T_1384, UInt<3>("h04"), T_1383) + node T_1386 = eq(inner.acquire.bits.a_type, UInt<1>("h00")) + node T_1389 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1390 = mux(T_1389, UInt<1>("h00"), UInt<1>("h01")) + node T_1391 = mux(T_1386, T_1390, UInt<1>("h01")) + node T_1392 = mux(inner.acquire.bits.is_builtin_type, T_1385, T_1391) + wire T_1424 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1424.client_id := UInt<1>("h00") + T_1424.g_type := UInt<1>("h00") + T_1424.is_builtin_type := UInt<1>("h00") + T_1424.manager_xact_id := UInt<1>("h00") + T_1424.client_xact_id := UInt<1>("h00") + T_1424.data := UInt<1>("h00") + T_1424.addr_beat := UInt<1>("h00") + T_1424.client_id := inner.acquire.bits.client_id + T_1424.is_builtin_type := inner.acquire.bits.is_builtin_type + T_1424.g_type := T_1392 + T_1424.client_xact_id := inner.acquire.bits.client_xact_id + T_1424.manager_xact_id := UInt<3>("h06") + T_1424.addr_beat := UInt<1>("h00") + T_1424.data := UInt<1>("h00") + wire T_1465 : UInt<3>[2] + T_1465[0] := UInt<3>("h05") + T_1465[1] := UInt<3>("h04") + node T_1469 = eq(T_1465[0], T_1424.g_type) + node T_1470 = eq(T_1465[1], T_1424.g_type) + node T_1472 = or(UInt<1>("h00"), T_1469) + node T_1473 = or(T_1472, T_1470) + wire T_1475 : UInt<1>[2] + T_1475[0] := UInt<1>("h00") + T_1475[1] := UInt<1>("h01") + node T_1479 = eq(T_1475[0], T_1424.g_type) + node T_1480 = eq(T_1475[1], T_1424.g_type) + node T_1482 = or(UInt<1>("h00"), T_1479) + node T_1483 = or(T_1482, T_1480) + node pending_outer_read_ = mux(T_1424.is_builtin_type, T_1473, T_1483) + node T_1485 = eq(xact.addr_block, inner.acquire.bits.addr_block) + node T_1486 = neq(state, UInt<1>("h00")) + node T_1487 = and(T_1485, T_1486) + node T_1489 = eq(collect_iacq_data, UInt<1>("h00")) + node T_1490 = and(T_1487, T_1489) + has_acquire_conflict := T_1490 + node T_1491 = eq(xact.addr_block, inner.acquire.bits.addr_block) + node T_1492 = and(T_1491, collect_iacq_data) + has_acquire_match := T_1492 + node T_1493 = eq(xact.addr_block, inner.release.bits.addr_block) + node T_1495 = eq(inner.release.bits.voluntary, UInt<1>("h00")) + node T_1496 = and(T_1493, T_1495) + node T_1497 = eq(state, UInt<1>("h01")) + node T_1498 = and(T_1496, T_1497) + has_release_match := T_1498 + infer accessor T_1500 = data_buffer[oacq_data_cnt] + node T_1533 = asUInt(asSInt(UInt<1>("h01"))) + node T_1534 = cat(T_1533, UInt<1>("h01")) + wire outer_write_acq : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_write_acq.union := UInt<1>("h00") + outer_write_acq.a_type := UInt<1>("h00") + outer_write_acq.is_builtin_type := UInt<1>("h00") + outer_write_acq.data := UInt<1>("h00") + outer_write_acq.addr_beat := UInt<1>("h00") + outer_write_acq.client_xact_id := UInt<1>("h00") + outer_write_acq.addr_block := UInt<1>("h00") + outer_write_acq.is_builtin_type := UInt<1>("h01") + outer_write_acq.a_type := UInt<3>("h03") + outer_write_acq.client_xact_id := UInt<3>("h06") + outer_write_acq.addr_block := xact.addr_block + outer_write_acq.addr_beat := oacq_data_cnt + outer_write_acq.data := T_1500 + outer_write_acq.union := T_1534 + node T_1631 = asUInt(asSInt(UInt<1>("h01"))) + node T_1632 = cat(T_1631, UInt<1>("h01")) + wire outer_write_rel : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_write_rel.union := UInt<1>("h00") + outer_write_rel.a_type := UInt<1>("h00") + outer_write_rel.is_builtin_type := UInt<1>("h00") + outer_write_rel.data := UInt<1>("h00") + outer_write_rel.addr_beat := UInt<1>("h00") + outer_write_rel.client_xact_id := UInt<1>("h00") + outer_write_rel.addr_block := UInt<1>("h00") + outer_write_rel.is_builtin_type := UInt<1>("h01") + outer_write_rel.a_type := UInt<3>("h03") + outer_write_rel.client_xact_id := UInt<3>("h06") + outer_write_rel.addr_block := xact.addr_block + outer_write_rel.addr_beat := inner.release.bits.addr_beat + outer_write_rel.data := inner.release.bits.data + outer_write_rel.union := T_1632 + node T_1700 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1701 = cat(UInt<3>("h07"), T_1700) + wire outer_read : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_read.union := UInt<1>("h00") + outer_read.a_type := UInt<1>("h00") + outer_read.is_builtin_type := UInt<1>("h00") + outer_read.data := UInt<1>("h00") + outer_read.addr_beat := UInt<1>("h00") + outer_read.client_xact_id := UInt<1>("h00") + outer_read.addr_block := UInt<1>("h00") + outer_read.is_builtin_type := UInt<1>("h01") + outer_read.a_type := UInt<3>("h01") + outer_read.client_xact_id := UInt<3>("h06") + outer_read.addr_block := xact.addr_block + outer_read.addr_beat := UInt<1>("h00") + outer_read.data := UInt<1>("h00") + outer_read.union := T_1701 + outer.acquire.valid := UInt<1>("h00") + outer.acquire.bits <> outer_read + outer.grant.ready := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + node T_1775 = eq(UInt<3>("h04"), xact.a_type) + node T_1776 = mux(T_1775, UInt<1>("h00"), UInt<2>("h02")) + node T_1777 = eq(UInt<3>("h02"), xact.a_type) + node T_1778 = mux(T_1777, UInt<1>("h00"), T_1776) + node T_1779 = eq(UInt<3>("h00"), xact.a_type) + node T_1780 = mux(T_1779, UInt<2>("h02"), T_1778) + node T_1781 = eq(UInt<3>("h03"), xact.a_type) + node T_1782 = mux(T_1781, UInt<1>("h00"), T_1780) + node T_1783 = eq(UInt<3>("h01"), xact.a_type) + node T_1784 = mux(T_1783, UInt<2>("h02"), T_1782) + node T_1785 = eq(UInt<1>("h01"), xact.a_type) + node T_1786 = mux(T_1785, UInt<1>("h00"), UInt<2>("h02")) + node T_1787 = eq(UInt<1>("h00"), xact.a_type) + node T_1788 = mux(T_1787, UInt<1>("h01"), T_1786) + node T_1789 = mux(xact.is_builtin_type, T_1784, T_1788) + wire T_1817 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} + T_1817.client_id := UInt<1>("h00") + T_1817.p_type := UInt<1>("h00") + T_1817.addr_block := UInt<1>("h00") + T_1817.client_id := UInt<1>("h00") + T_1817.p_type := T_1789 + T_1817.addr_block := xact.addr_block + inner.probe.bits <> T_1817 + inner.grant.valid := UInt<1>("h00") + node T_1864 = eq(UInt<3>("h05"), xact.a_type) + node T_1865 = mux(T_1864, UInt<3>("h01"), UInt<3>("h03")) + node T_1866 = eq(UInt<3>("h04"), xact.a_type) + node T_1867 = mux(T_1866, UInt<3>("h04"), T_1865) + node T_1868 = eq(UInt<3>("h03"), xact.a_type) + node T_1869 = mux(T_1868, UInt<3>("h03"), T_1867) + node T_1870 = eq(UInt<3>("h02"), xact.a_type) + node T_1871 = mux(T_1870, UInt<3>("h03"), T_1869) + node T_1872 = eq(UInt<3>("h01"), xact.a_type) + node T_1873 = mux(T_1872, UInt<3>("h05"), T_1871) + node T_1874 = eq(UInt<3>("h00"), xact.a_type) + node T_1875 = mux(T_1874, UInt<3>("h04"), T_1873) + node T_1876 = eq(xact.a_type, UInt<1>("h00")) + node T_1879 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1880 = mux(T_1879, UInt<1>("h00"), UInt<1>("h01")) + node T_1881 = mux(T_1876, T_1880, UInt<1>("h01")) + node T_1882 = mux(xact.is_builtin_type, T_1875, T_1881) + wire T_1914 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1914.client_id := UInt<1>("h00") + T_1914.g_type := UInt<1>("h00") + T_1914.is_builtin_type := UInt<1>("h00") + T_1914.manager_xact_id := UInt<1>("h00") + T_1914.client_xact_id := UInt<1>("h00") + T_1914.data := UInt<1>("h00") + T_1914.addr_beat := UInt<1>("h00") + T_1914.client_id := xact.client_id + T_1914.is_builtin_type := xact.is_builtin_type + T_1914.g_type := T_1882 + T_1914.client_xact_id := xact.client_xact_id + T_1914.manager_xact_id := UInt<3>("h06") + T_1914.addr_beat := UInt<1>("h00") + T_1914.data := UInt<1>("h00") + inner.grant.bits <> T_1914 + inner.acquire.ready := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + node T_1955 = neq(state, UInt<1>("h00")) + node T_1956 = and(T_1955, collect_iacq_data) + node T_1957 = and(inner.acquire.ready, inner.acquire.valid) + node T_1958 = and(T_1956, T_1957) + node T_1959 = neq(inner.acquire.bits.client_id, xact.client_id) + node T_1960 = and(T_1958, T_1959) + node T_1962 = eq(T_1960, UInt<1>("h00")) + node T_1963 = neq(state, UInt<1>("h00")) + node T_1964 = and(T_1963, collect_iacq_data) + node T_1965 = and(inner.acquire.ready, inner.acquire.valid) + node T_1966 = and(T_1964, T_1965) + node T_1967 = neq(inner.acquire.bits.client_xact_id, xact.client_xact_id) + node T_1968 = and(T_1966, T_1967) + node T_1970 = eq(T_1968, UInt<1>("h00")) + node T_1971 = eq(state, UInt<1>("h00")) + node T_1972 = and(inner.acquire.ready, inner.acquire.valid) + node T_1973 = and(T_1971, T_1972) + node T_1975 = neq(inner.acquire.bits.addr_beat, UInt<1>("h00")) + node T_1976 = and(T_1973, T_1975) + node T_1978 = eq(T_1976, UInt<1>("h00")) + when collect_iacq_data : + inner.acquire.ready := UInt<1>("h01") + when inner.acquire.valid : + infer accessor T_1980 = data_buffer[inner.acquire.bits.addr_beat] + T_1980 := inner.acquire.bits.data + node T_1983 = dshl(UInt<1>("h01"), inner.acquire.bits.addr_beat) + node T_1984 = or(iacq_data_valid, T_1983) + node T_1985 = not(iacq_data_valid) + node T_1986 = or(T_1985, T_1983) + node T_1987 = not(T_1986) + node T_1988 = mux(UInt<1>("h01"), T_1984, T_1987) + iacq_data_valid := T_1988 + skip + when iacq_data_done : + collect_iacq_data := UInt<1>("h00") + skip + skip + when pending_ognt_ack : + outer.grant.ready := UInt<1>("h01") + when outer.grant.valid : + pending_ognt_ack := UInt<1>("h00") + skip + skip + node T_1992 = eq(UInt<1>("h00"), state) + when T_1992 : + inner.acquire.ready := UInt<1>("h01") + when inner.acquire.valid : + xact <> inner.acquire.bits + infer accessor T_1995 = data_buffer[UInt<1>("h00")] + T_1995 := inner.acquire.bits.data + node T_1997 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) + wire T_2000 : UInt<3>[1] + T_2000[0] := UInt<3>("h03") + node T_2003 = eq(T_2000[0], inner.acquire.bits.a_type) + node T_2005 = or(UInt<1>("h00"), T_2003) + node T_2006 = and(T_1997, T_2005) + collect_iacq_data := T_2006 + wire T_2011 : UInt<3>[3] + T_2011[0] := UInt<3>("h02") + T_2011[1] := UInt<3>("h03") + T_2011[2] := UInt<3>("h04") + node T_2016 = eq(T_2011[0], inner.acquire.bits.a_type) + node T_2017 = eq(T_2011[1], inner.acquire.bits.a_type) + node T_2018 = eq(T_2011[2], inner.acquire.bits.a_type) + node T_2020 = or(UInt<1>("h00"), T_2016) + node T_2021 = or(T_2020, T_2017) + node T_2022 = or(T_2021, T_2018) + node T_2023 = and(inner.acquire.bits.is_builtin_type, T_2022) + node T_2024 = dshl(T_2023, inner.acquire.bits.addr_beat) + iacq_data_valid := T_2024 + node T_2026 = neq(mask_incoherent, UInt<1>("h00")) + when T_2026 : + pending_probes := mask_incoherent + node T_2027 = bit(mask_incoherent, 0) + node T_2028 = bit(mask_incoherent, 1) + node T_2029 = bit(mask_incoherent, 2) + node T_2030 = bit(mask_incoherent, 3) + node T_2032 = cat(UInt<1>("h00"), T_2028) + node T_2033 = addw(T_2027, T_2032) + node T_2036 = cat(UInt<1>("h00"), T_2030) + node T_2037 = addw(T_2029, T_2036) + node T_2038 = cat(UInt<1>("h00"), T_2037) + node T_2039 = addw(T_2033, T_2038) + release_count := T_2039 + skip + node T_2040 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) + node T_2041 = mux(pending_outer_write_, UInt<2>("h03"), T_2040) + node T_2042 = mux(T_2026, UInt<1>("h01"), T_2041) + state := T_2042 + skip + skip + node T_2043 = eq(UInt<1>("h01"), state) + when T_2043 : + node T_2045 = neq(pending_probes, UInt<1>("h00")) + inner.probe.valid := T_2045 + when inner.probe.ready : + node T_2047 = dshl(UInt<1>("h01"), UInt<1>("h00")) + node T_2048 = not(T_2047) + node T_2049 = and(pending_probes, T_2048) + pending_probes := T_2049 + skip + wire T_2051 : UInt<2>[3] + T_2051[0] := UInt<1>("h00") + T_2051[1] := UInt<1>("h01") + T_2051[2] := UInt<2>("h02") + node T_2056 = eq(T_2051[0], inner.release.bits.r_type) + node T_2057 = eq(T_2051[1], inner.release.bits.r_type) + node T_2058 = eq(T_2051[2], inner.release.bits.r_type) + node T_2060 = or(UInt<1>("h00"), T_2056) + node T_2061 = or(T_2060, T_2057) + node T_2062 = or(T_2061, T_2058) + node T_2064 = eq(T_2062, UInt<1>("h00")) + node T_2065 = or(T_2064, outer.acquire.ready) + inner.release.ready := T_2065 + when inner.release.valid : + wire T_2067 : UInt<2>[3] + T_2067[0] := UInt<1>("h00") + T_2067[1] := UInt<1>("h01") + T_2067[2] := UInt<2>("h02") + node T_2072 = eq(T_2067[0], inner.release.bits.r_type) + node T_2073 = eq(T_2067[1], inner.release.bits.r_type) + node T_2074 = eq(T_2067[2], inner.release.bits.r_type) + node T_2076 = or(UInt<1>("h00"), T_2072) + node T_2077 = or(T_2076, T_2073) + node T_2078 = or(T_2077, T_2074) + when T_2078 : + outer.acquire.valid := UInt<1>("h01") + outer.acquire.bits <> outer_write_rel + when outer.acquire.ready : + when oacq_data_done : + pending_ognt_ack := UInt<1>("h01") + node T_2082 = subw(release_count, UInt<1>("h01")) + release_count := T_2082 + node T_2084 = eq(release_count, UInt<1>("h01")) + when T_2084 : + node T_2085 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_2086 = mux(pending_outer_write, UInt<2>("h03"), T_2085) + state := T_2086 + skip + skip + skip + skip + else : + node T_2088 = subw(release_count, UInt<1>("h01")) + release_count := T_2088 + node T_2090 = eq(release_count, UInt<1>("h01")) + when T_2090 : + node T_2091 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_2092 = mux(pending_outer_write, UInt<2>("h03"), T_2091) + state := T_2092 + skip + skip + skip + skip + node T_2093 = eq(UInt<2>("h03"), state) + when T_2093 : + node T_2095 = eq(pending_ognt_ack, UInt<1>("h00")) + node T_2097 = eq(collect_iacq_data, UInt<1>("h00")) + node T_2098 = or(T_2095, T_2097) + node T_2099 = dshr(iacq_data_valid, oacq_data_cnt) + node T_2100 = bit(T_2099, 0) + node T_2101 = or(T_2098, T_2100) + outer.acquire.valid := T_2101 + outer.acquire.bits <> outer_write_acq + when oacq_data_done : + pending_ognt_ack := UInt<1>("h01") + node T_2103 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) + state := T_2103 + skip + skip + node T_2104 = eq(UInt<2>("h02"), state) + when T_2104 : + node T_2106 = eq(pending_ognt_ack, UInt<1>("h00")) + outer.acquire.valid := T_2106 + outer.acquire.bits <> outer_read + node T_2107 = and(outer.acquire.ready, outer.acquire.valid) + when T_2107 : + state := UInt<3>("h05") + skip + skip + node T_2108 = eq(UInt<3>("h05"), state) + when T_2108 : + outer.grant.ready := inner.grant.ready + inner.grant.valid := outer.grant.valid + when ignt_data_done : + node T_2111 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_2113 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_2114 = and(inner.grant.bits.is_builtin_type, T_2113) + node T_2116 = eq(T_2114, UInt<1>("h00")) + node T_2117 = and(T_2111, T_2116) + node T_2118 = mux(T_2117, UInt<3>("h06"), UInt<1>("h00")) + state := T_2118 + skip + skip + node T_2119 = eq(UInt<3>("h04"), state) + when T_2119 : + inner.grant.valid := UInt<1>("h01") + when inner.grant.ready : + node T_2123 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_2125 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_2126 = and(inner.grant.bits.is_builtin_type, T_2125) + node T_2128 = eq(T_2126, UInt<1>("h00")) + node T_2129 = and(T_2123, T_2128) + node T_2130 = mux(T_2129, UInt<3>("h06"), UInt<1>("h00")) + state := T_2130 + skip + skip + node T_2131 = eq(UInt<3>("h06"), state) + when T_2131 : + inner.finish.ready := UInt<1>("h01") + when inner.finish.valid : + state := UInt<1>("h00") + skip + skip + + module BroadcastAcquireTracker_32 : + output has_release_match : UInt<1> + output has_acquire_match : UInt<1> + output has_acquire_conflict : UInt<1> + output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input incoherent : UInt<1>[1] + output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} + input clock : Clock + input reset : UInt<1> + + has_release_match := UInt<1>("h00") + has_acquire_match := UInt<1>("h00") + has_acquire_conflict := UInt<1>("h00") + outer.grant.ready := UInt<1>("h00") + outer.acquire.bits.union := UInt<1>("h00") + outer.acquire.bits.a_type := UInt<1>("h00") + outer.acquire.bits.is_builtin_type := UInt<1>("h00") + outer.acquire.bits.data := UInt<1>("h00") + outer.acquire.bits.addr_beat := UInt<1>("h00") + outer.acquire.bits.client_xact_id := UInt<1>("h00") + outer.acquire.bits.addr_block := UInt<1>("h00") + outer.acquire.valid := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.probe.bits.client_id := UInt<1>("h00") + inner.probe.bits.p_type := UInt<1>("h00") + inner.probe.bits.addr_block := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + inner.grant.bits.client_id := UInt<1>("h00") + inner.grant.bits.g_type := UInt<1>("h00") + inner.grant.bits.is_builtin_type := UInt<1>("h00") + inner.grant.bits.manager_xact_id := UInt<1>("h00") + inner.grant.bits.client_xact_id := UInt<1>("h00") + inner.grant.bits.data := UInt<1>("h00") + inner.grant.bits.addr_beat := UInt<1>("h00") + inner.grant.valid := UInt<1>("h00") + inner.acquire.ready := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>, client_id : UInt<2>}, clock, reset + reg data_buffer : UInt<4>[4], clock, reset + wire coh : {sharers : UInt<1>} + coh.sharers := UInt<1>("h00") + coh.sharers := UInt<1>("h00") + node T_1092 = neq(state, UInt<1>("h00")) + node T_1093 = and(T_1092, xact.is_builtin_type) + wire T_1099 : UInt<3>[4] + T_1099[0] := UInt<3>("h00") + T_1099[1] := UInt<3>("h02") + T_1099[2] := UInt<3>("h04") + T_1099[3] := UInt<3>("h05") + node T_1105 = eq(T_1099[0], xact.a_type) + node T_1106 = eq(T_1099[1], xact.a_type) + node T_1107 = eq(T_1099[2], xact.a_type) + node T_1108 = eq(T_1099[3], xact.a_type) + node T_1110 = or(UInt<1>("h00"), T_1105) + node T_1111 = or(T_1110, T_1106) + node T_1112 = or(T_1111, T_1107) + node T_1113 = or(T_1112, T_1108) + node T_1114 = and(T_1093, T_1113) + node T_1116 = eq(T_1114, UInt<1>("h00")) + reg release_count : UInt<1>, clock, reset + onreset release_count := UInt<1>("h00") + reg pending_probes : UInt<1>, clock, reset + onreset pending_probes := UInt<1>("h00") + node T_1121 = bit(pending_probes, 0) + wire T_1123 : UInt<1>[1] + T_1123[0] := T_1121 + node T_1128 = asUInt(asSInt(UInt<1>("h01"))) + node T_1131 = dshl(UInt<1>("h01"), inner.acquire.bits.client_id) + node T_1132 = or(T_1128, T_1131) + node T_1133 = not(T_1128) + node T_1134 = or(T_1133, T_1131) + node T_1135 = not(T_1134) + node mask_self = mux(UInt<1>("h00"), T_1132, T_1135) + node T_1137 = not(incoherent[0]) + node mask_incoherent = and(mask_self, T_1137) + reg collect_iacq_data : UInt<1>, clock, reset + onreset collect_iacq_data := UInt<1>("h00") + reg iacq_data_valid : UInt<4>, clock, reset + onreset iacq_data_valid := UInt<4>("h00") + node T_1143 = and(inner.acquire.ready, inner.acquire.valid) + node T_1146 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) + wire T_1149 : UInt<3>[1] + T_1149[0] := UInt<3>("h03") + node T_1152 = eq(T_1149[0], inner.acquire.bits.a_type) + node T_1154 = or(UInt<1>("h00"), T_1152) + node T_1155 = and(T_1146, T_1154) + node T_1156 = and(T_1143, T_1155) + reg T_1158 : UInt<2>, clock, reset + onreset T_1158 := UInt<2>("h00") + when T_1156 : + node T_1160 = eq(T_1158, UInt<2>("h03")) + node T_1162 = and(UInt<1>("h00"), T_1160) + node T_1165 = addw(T_1158, UInt<1>("h01")) + node T_1166 = mux(T_1162, UInt<1>("h00"), T_1165) + T_1158 := T_1166 + skip + node T_1167 = and(T_1156, T_1160) + node T_1168 = mux(T_1155, T_1158, UInt<1>("h00")) + node iacq_data_done = mux(T_1155, T_1167, T_1143) + node T_1170 = and(inner.release.ready, inner.release.valid) + wire T_1174 : UInt<2>[3] + T_1174[0] := UInt<1>("h00") + T_1174[1] := UInt<1>("h01") + T_1174[2] := UInt<2>("h02") + node T_1179 = eq(T_1174[0], inner.release.bits.r_type) + node T_1180 = eq(T_1174[1], inner.release.bits.r_type) + node T_1181 = eq(T_1174[2], inner.release.bits.r_type) + node T_1183 = or(UInt<1>("h00"), T_1179) + node T_1184 = or(T_1183, T_1180) + node T_1185 = or(T_1184, T_1181) + node T_1186 = and(UInt<1>("h01"), T_1185) + node T_1187 = and(T_1170, T_1186) + reg T_1189 : UInt<2>, clock, reset + onreset T_1189 := UInt<2>("h00") + when T_1187 : + node T_1191 = eq(T_1189, UInt<2>("h03")) + node T_1193 = and(UInt<1>("h00"), T_1191) + node T_1196 = addw(T_1189, UInt<1>("h01")) + node T_1197 = mux(T_1193, UInt<1>("h00"), T_1196) + T_1189 := T_1197 + skip + node T_1198 = and(T_1187, T_1191) + node T_1199 = mux(T_1186, T_1189, UInt<1>("h00")) + node irel_data_done = mux(T_1186, T_1198, T_1170) + node T_1202 = and(inner.grant.ready, inner.grant.valid) + wire T_1206 : UInt<3>[1] + T_1206[0] := UInt<3>("h05") + node T_1209 = eq(T_1206[0], inner.grant.bits.g_type) + node T_1211 = or(UInt<1>("h00"), T_1209) + wire T_1213 : UInt<1>[2] + T_1213[0] := UInt<1>("h00") + T_1213[1] := UInt<1>("h01") + node T_1217 = eq(T_1213[0], inner.grant.bits.g_type) + node T_1218 = eq(T_1213[1], inner.grant.bits.g_type) + node T_1220 = or(UInt<1>("h00"), T_1217) + node T_1221 = or(T_1220, T_1218) + node T_1222 = mux(inner.grant.bits.is_builtin_type, T_1211, T_1221) + node T_1223 = and(UInt<1>("h01"), T_1222) + node T_1224 = and(T_1202, T_1223) + reg T_1226 : UInt<2>, clock, reset + onreset T_1226 := UInt<2>("h00") + when T_1224 : + node T_1228 = eq(T_1226, UInt<2>("h03")) + node T_1230 = and(UInt<1>("h00"), T_1228) + node T_1233 = addw(T_1226, UInt<1>("h01")) + node T_1234 = mux(T_1230, UInt<1>("h00"), T_1233) + T_1226 := T_1234 + skip + node T_1235 = and(T_1224, T_1228) + node ignt_data_cnt = mux(T_1223, T_1226, UInt<1>("h00")) + node ignt_data_done = mux(T_1223, T_1235, T_1202) + node T_1239 = and(outer.acquire.ready, outer.acquire.valid) + node T_1241 = and(UInt<1>("h01"), outer.acquire.bits.is_builtin_type) + wire T_1244 : UInt<3>[1] + T_1244[0] := UInt<3>("h03") + node T_1247 = eq(T_1244[0], outer.acquire.bits.a_type) + node T_1249 = or(UInt<1>("h00"), T_1247) + node T_1250 = and(T_1241, T_1249) + node T_1251 = and(T_1239, T_1250) + reg T_1253 : UInt<2>, clock, reset + onreset T_1253 := UInt<2>("h00") + when T_1251 : + node T_1255 = eq(T_1253, UInt<2>("h03")) + node T_1257 = and(UInt<1>("h00"), T_1255) + node T_1260 = addw(T_1253, UInt<1>("h01")) + node T_1261 = mux(T_1257, UInt<1>("h00"), T_1260) + T_1253 := T_1261 + skip + node T_1262 = and(T_1251, T_1255) + node oacq_data_cnt = mux(T_1250, T_1253, UInt<1>("h00")) + node oacq_data_done = mux(T_1250, T_1262, T_1239) + node T_1265 = and(outer.grant.ready, outer.grant.valid) + wire T_1270 : UInt<3>[1] + T_1270[0] := UInt<3>("h05") + node T_1273 = eq(T_1270[0], outer.grant.bits.g_type) + node T_1275 = or(UInt<1>("h00"), T_1273) + wire T_1277 : UInt<1>[1] + T_1277[0] := UInt<1>("h00") + node T_1280 = eq(T_1277[0], outer.grant.bits.g_type) + node T_1282 = or(UInt<1>("h00"), T_1280) + node T_1283 = mux(outer.grant.bits.is_builtin_type, T_1275, T_1282) + node T_1284 = and(UInt<1>("h01"), T_1283) + node T_1285 = and(T_1265, T_1284) + reg T_1287 : UInt<2>, clock, reset + onreset T_1287 := UInt<2>("h00") + when T_1285 : + node T_1289 = eq(T_1287, UInt<2>("h03")) + node T_1291 = and(UInt<1>("h00"), T_1289) + node T_1294 = addw(T_1287, UInt<1>("h01")) + node T_1295 = mux(T_1291, UInt<1>("h00"), T_1294) + T_1287 := T_1295 + skip + node T_1296 = and(T_1285, T_1289) + node T_1297 = mux(T_1284, T_1287, UInt<1>("h00")) + node ognt_data_done = mux(T_1284, T_1296, T_1265) + reg pending_ognt_ack : UInt<1>, clock, reset + onreset pending_ognt_ack := UInt<1>("h00") + wire T_1305 : UInt<3>[3] + T_1305[0] := UInt<3>("h02") + T_1305[1] := UInt<3>("h03") + T_1305[2] := UInt<3>("h04") + node T_1310 = eq(T_1305[0], xact.a_type) + node T_1311 = eq(T_1305[1], xact.a_type) + node T_1312 = eq(T_1305[2], xact.a_type) + node T_1314 = or(UInt<1>("h00"), T_1310) + node T_1315 = or(T_1314, T_1311) + node T_1316 = or(T_1315, T_1312) + node pending_outer_write = and(xact.is_builtin_type, T_1316) + wire T_1322 : UInt<3>[3] + T_1322[0] := UInt<3>("h02") + T_1322[1] := UInt<3>("h03") + T_1322[2] := UInt<3>("h04") + node T_1327 = eq(T_1322[0], inner.acquire.bits.a_type) + node T_1328 = eq(T_1322[1], inner.acquire.bits.a_type) + node T_1329 = eq(T_1322[2], inner.acquire.bits.a_type) + node T_1331 = or(UInt<1>("h00"), T_1327) + node T_1332 = or(T_1331, T_1328) + node T_1333 = or(T_1332, T_1329) + node pending_outer_write_ = and(inner.acquire.bits.is_builtin_type, T_1333) + wire T_1338 : UInt<3>[2] + T_1338[0] := UInt<3>("h05") + T_1338[1] := UInt<3>("h04") + node T_1342 = eq(T_1338[0], inner.grant.bits.g_type) + node T_1343 = eq(T_1338[1], inner.grant.bits.g_type) + node T_1345 = or(UInt<1>("h00"), T_1342) + node T_1346 = or(T_1345, T_1343) + wire T_1348 : UInt<1>[2] + T_1348[0] := UInt<1>("h00") + T_1348[1] := UInt<1>("h01") + node T_1352 = eq(T_1348[0], inner.grant.bits.g_type) + node T_1353 = eq(T_1348[1], inner.grant.bits.g_type) + node T_1355 = or(UInt<1>("h00"), T_1352) + node T_1356 = or(T_1355, T_1353) + node pending_outer_read = mux(inner.grant.bits.is_builtin_type, T_1346, T_1356) + node T_1374 = eq(UInt<3>("h05"), inner.acquire.bits.a_type) + node T_1375 = mux(T_1374, UInt<3>("h01"), UInt<3>("h03")) + node T_1376 = eq(UInt<3>("h04"), inner.acquire.bits.a_type) + node T_1377 = mux(T_1376, UInt<3>("h04"), T_1375) + node T_1378 = eq(UInt<3>("h03"), inner.acquire.bits.a_type) + node T_1379 = mux(T_1378, UInt<3>("h03"), T_1377) + node T_1380 = eq(UInt<3>("h02"), inner.acquire.bits.a_type) + node T_1381 = mux(T_1380, UInt<3>("h03"), T_1379) + node T_1382 = eq(UInt<3>("h01"), inner.acquire.bits.a_type) + node T_1383 = mux(T_1382, UInt<3>("h05"), T_1381) + node T_1384 = eq(UInt<3>("h00"), inner.acquire.bits.a_type) + node T_1385 = mux(T_1384, UInt<3>("h04"), T_1383) + node T_1386 = eq(inner.acquire.bits.a_type, UInt<1>("h00")) + node T_1389 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1390 = mux(T_1389, UInt<1>("h00"), UInt<1>("h01")) + node T_1391 = mux(T_1386, T_1390, UInt<1>("h01")) + node T_1392 = mux(inner.acquire.bits.is_builtin_type, T_1385, T_1391) + wire T_1424 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1424.client_id := UInt<1>("h00") + T_1424.g_type := UInt<1>("h00") + T_1424.is_builtin_type := UInt<1>("h00") + T_1424.manager_xact_id := UInt<1>("h00") + T_1424.client_xact_id := UInt<1>("h00") + T_1424.data := UInt<1>("h00") + T_1424.addr_beat := UInt<1>("h00") + T_1424.client_id := inner.acquire.bits.client_id + T_1424.is_builtin_type := inner.acquire.bits.is_builtin_type + T_1424.g_type := T_1392 + T_1424.client_xact_id := inner.acquire.bits.client_xact_id + T_1424.manager_xact_id := UInt<3>("h07") + T_1424.addr_beat := UInt<1>("h00") + T_1424.data := UInt<1>("h00") + wire T_1465 : UInt<3>[2] + T_1465[0] := UInt<3>("h05") + T_1465[1] := UInt<3>("h04") + node T_1469 = eq(T_1465[0], T_1424.g_type) + node T_1470 = eq(T_1465[1], T_1424.g_type) + node T_1472 = or(UInt<1>("h00"), T_1469) + node T_1473 = or(T_1472, T_1470) + wire T_1475 : UInt<1>[2] + T_1475[0] := UInt<1>("h00") + T_1475[1] := UInt<1>("h01") + node T_1479 = eq(T_1475[0], T_1424.g_type) + node T_1480 = eq(T_1475[1], T_1424.g_type) + node T_1482 = or(UInt<1>("h00"), T_1479) + node T_1483 = or(T_1482, T_1480) + node pending_outer_read_ = mux(T_1424.is_builtin_type, T_1473, T_1483) + node T_1485 = eq(xact.addr_block, inner.acquire.bits.addr_block) + node T_1486 = neq(state, UInt<1>("h00")) + node T_1487 = and(T_1485, T_1486) + node T_1489 = eq(collect_iacq_data, UInt<1>("h00")) + node T_1490 = and(T_1487, T_1489) + has_acquire_conflict := T_1490 + node T_1491 = eq(xact.addr_block, inner.acquire.bits.addr_block) + node T_1492 = and(T_1491, collect_iacq_data) + has_acquire_match := T_1492 + node T_1493 = eq(xact.addr_block, inner.release.bits.addr_block) + node T_1495 = eq(inner.release.bits.voluntary, UInt<1>("h00")) + node T_1496 = and(T_1493, T_1495) + node T_1497 = eq(state, UInt<1>("h01")) + node T_1498 = and(T_1496, T_1497) + has_release_match := T_1498 + infer accessor T_1500 = data_buffer[oacq_data_cnt] + node T_1533 = asUInt(asSInt(UInt<1>("h01"))) + node T_1534 = cat(T_1533, UInt<1>("h01")) + wire outer_write_acq : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_write_acq.union := UInt<1>("h00") + outer_write_acq.a_type := UInt<1>("h00") + outer_write_acq.is_builtin_type := UInt<1>("h00") + outer_write_acq.data := UInt<1>("h00") + outer_write_acq.addr_beat := UInt<1>("h00") + outer_write_acq.client_xact_id := UInt<1>("h00") + outer_write_acq.addr_block := UInt<1>("h00") + outer_write_acq.is_builtin_type := UInt<1>("h01") + outer_write_acq.a_type := UInt<3>("h03") + outer_write_acq.client_xact_id := UInt<3>("h07") + outer_write_acq.addr_block := xact.addr_block + outer_write_acq.addr_beat := oacq_data_cnt + outer_write_acq.data := T_1500 + outer_write_acq.union := T_1534 + node T_1631 = asUInt(asSInt(UInt<1>("h01"))) + node T_1632 = cat(T_1631, UInt<1>("h01")) + wire outer_write_rel : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_write_rel.union := UInt<1>("h00") + outer_write_rel.a_type := UInt<1>("h00") + outer_write_rel.is_builtin_type := UInt<1>("h00") + outer_write_rel.data := UInt<1>("h00") + outer_write_rel.addr_beat := UInt<1>("h00") + outer_write_rel.client_xact_id := UInt<1>("h00") + outer_write_rel.addr_block := UInt<1>("h00") + outer_write_rel.is_builtin_type := UInt<1>("h01") + outer_write_rel.a_type := UInt<3>("h03") + outer_write_rel.client_xact_id := UInt<3>("h07") + outer_write_rel.addr_block := xact.addr_block + outer_write_rel.addr_beat := inner.release.bits.addr_beat + outer_write_rel.data := inner.release.bits.data + outer_write_rel.union := T_1632 + node T_1700 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1701 = cat(UInt<3>("h07"), T_1700) + wire outer_read : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>} + outer_read.union := UInt<1>("h00") + outer_read.a_type := UInt<1>("h00") + outer_read.is_builtin_type := UInt<1>("h00") + outer_read.data := UInt<1>("h00") + outer_read.addr_beat := UInt<1>("h00") + outer_read.client_xact_id := UInt<1>("h00") + outer_read.addr_block := UInt<1>("h00") + outer_read.is_builtin_type := UInt<1>("h01") + outer_read.a_type := UInt<3>("h01") + outer_read.client_xact_id := UInt<3>("h07") + outer_read.addr_block := xact.addr_block + outer_read.addr_beat := UInt<1>("h00") + outer_read.data := UInt<1>("h00") + outer_read.union := T_1701 + outer.acquire.valid := UInt<1>("h00") + outer.acquire.bits <> outer_read + outer.grant.ready := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + node T_1775 = eq(UInt<3>("h04"), xact.a_type) + node T_1776 = mux(T_1775, UInt<1>("h00"), UInt<2>("h02")) + node T_1777 = eq(UInt<3>("h02"), xact.a_type) + node T_1778 = mux(T_1777, UInt<1>("h00"), T_1776) + node T_1779 = eq(UInt<3>("h00"), xact.a_type) + node T_1780 = mux(T_1779, UInt<2>("h02"), T_1778) + node T_1781 = eq(UInt<3>("h03"), xact.a_type) + node T_1782 = mux(T_1781, UInt<1>("h00"), T_1780) + node T_1783 = eq(UInt<3>("h01"), xact.a_type) + node T_1784 = mux(T_1783, UInt<2>("h02"), T_1782) + node T_1785 = eq(UInt<1>("h01"), xact.a_type) + node T_1786 = mux(T_1785, UInt<1>("h00"), UInt<2>("h02")) + node T_1787 = eq(UInt<1>("h00"), xact.a_type) + node T_1788 = mux(T_1787, UInt<1>("h01"), T_1786) + node T_1789 = mux(xact.is_builtin_type, T_1784, T_1788) + wire T_1817 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} + T_1817.client_id := UInt<1>("h00") + T_1817.p_type := UInt<1>("h00") + T_1817.addr_block := UInt<1>("h00") + T_1817.client_id := UInt<1>("h00") + T_1817.p_type := T_1789 + T_1817.addr_block := xact.addr_block + inner.probe.bits <> T_1817 + inner.grant.valid := UInt<1>("h00") + node T_1864 = eq(UInt<3>("h05"), xact.a_type) + node T_1865 = mux(T_1864, UInt<3>("h01"), UInt<3>("h03")) + node T_1866 = eq(UInt<3>("h04"), xact.a_type) + node T_1867 = mux(T_1866, UInt<3>("h04"), T_1865) + node T_1868 = eq(UInt<3>("h03"), xact.a_type) + node T_1869 = mux(T_1868, UInt<3>("h03"), T_1867) + node T_1870 = eq(UInt<3>("h02"), xact.a_type) + node T_1871 = mux(T_1870, UInt<3>("h03"), T_1869) + node T_1872 = eq(UInt<3>("h01"), xact.a_type) + node T_1873 = mux(T_1872, UInt<3>("h05"), T_1871) + node T_1874 = eq(UInt<3>("h00"), xact.a_type) + node T_1875 = mux(T_1874, UInt<3>("h04"), T_1873) + node T_1876 = eq(xact.a_type, UInt<1>("h00")) + node T_1879 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1880 = mux(T_1879, UInt<1>("h00"), UInt<1>("h01")) + node T_1881 = mux(T_1876, T_1880, UInt<1>("h01")) + node T_1882 = mux(xact.is_builtin_type, T_1875, T_1881) + wire T_1914 : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>} + T_1914.client_id := UInt<1>("h00") + T_1914.g_type := UInt<1>("h00") + T_1914.is_builtin_type := UInt<1>("h00") + T_1914.manager_xact_id := UInt<1>("h00") + T_1914.client_xact_id := UInt<1>("h00") + T_1914.data := UInt<1>("h00") + T_1914.addr_beat := UInt<1>("h00") + T_1914.client_id := xact.client_id + T_1914.is_builtin_type := xact.is_builtin_type + T_1914.g_type := T_1882 + T_1914.client_xact_id := xact.client_xact_id + T_1914.manager_xact_id := UInt<3>("h07") + T_1914.addr_beat := UInt<1>("h00") + T_1914.data := UInt<1>("h00") + inner.grant.bits <> T_1914 + inner.acquire.ready := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + node T_1955 = neq(state, UInt<1>("h00")) + node T_1956 = and(T_1955, collect_iacq_data) + node T_1957 = and(inner.acquire.ready, inner.acquire.valid) + node T_1958 = and(T_1956, T_1957) + node T_1959 = neq(inner.acquire.bits.client_id, xact.client_id) + node T_1960 = and(T_1958, T_1959) + node T_1962 = eq(T_1960, UInt<1>("h00")) + node T_1963 = neq(state, UInt<1>("h00")) + node T_1964 = and(T_1963, collect_iacq_data) + node T_1965 = and(inner.acquire.ready, inner.acquire.valid) + node T_1966 = and(T_1964, T_1965) + node T_1967 = neq(inner.acquire.bits.client_xact_id, xact.client_xact_id) + node T_1968 = and(T_1966, T_1967) + node T_1970 = eq(T_1968, UInt<1>("h00")) + node T_1971 = eq(state, UInt<1>("h00")) + node T_1972 = and(inner.acquire.ready, inner.acquire.valid) + node T_1973 = and(T_1971, T_1972) + node T_1975 = neq(inner.acquire.bits.addr_beat, UInt<1>("h00")) + node T_1976 = and(T_1973, T_1975) + node T_1978 = eq(T_1976, UInt<1>("h00")) + when collect_iacq_data : + inner.acquire.ready := UInt<1>("h01") + when inner.acquire.valid : + infer accessor T_1980 = data_buffer[inner.acquire.bits.addr_beat] + T_1980 := inner.acquire.bits.data + node T_1983 = dshl(UInt<1>("h01"), inner.acquire.bits.addr_beat) + node T_1984 = or(iacq_data_valid, T_1983) + node T_1985 = not(iacq_data_valid) + node T_1986 = or(T_1985, T_1983) + node T_1987 = not(T_1986) + node T_1988 = mux(UInt<1>("h01"), T_1984, T_1987) + iacq_data_valid := T_1988 + skip + when iacq_data_done : + collect_iacq_data := UInt<1>("h00") + skip + skip + when pending_ognt_ack : + outer.grant.ready := UInt<1>("h01") + when outer.grant.valid : + pending_ognt_ack := UInt<1>("h00") + skip + skip + node T_1992 = eq(UInt<1>("h00"), state) + when T_1992 : + inner.acquire.ready := UInt<1>("h01") + when inner.acquire.valid : + xact <> inner.acquire.bits + infer accessor T_1995 = data_buffer[UInt<1>("h00")] + T_1995 := inner.acquire.bits.data + node T_1997 = and(UInt<1>("h01"), inner.acquire.bits.is_builtin_type) + wire T_2000 : UInt<3>[1] + T_2000[0] := UInt<3>("h03") + node T_2003 = eq(T_2000[0], inner.acquire.bits.a_type) + node T_2005 = or(UInt<1>("h00"), T_2003) + node T_2006 = and(T_1997, T_2005) + collect_iacq_data := T_2006 + wire T_2011 : UInt<3>[3] + T_2011[0] := UInt<3>("h02") + T_2011[1] := UInt<3>("h03") + T_2011[2] := UInt<3>("h04") + node T_2016 = eq(T_2011[0], inner.acquire.bits.a_type) + node T_2017 = eq(T_2011[1], inner.acquire.bits.a_type) + node T_2018 = eq(T_2011[2], inner.acquire.bits.a_type) + node T_2020 = or(UInt<1>("h00"), T_2016) + node T_2021 = or(T_2020, T_2017) + node T_2022 = or(T_2021, T_2018) + node T_2023 = and(inner.acquire.bits.is_builtin_type, T_2022) + node T_2024 = dshl(T_2023, inner.acquire.bits.addr_beat) + iacq_data_valid := T_2024 + node T_2026 = neq(mask_incoherent, UInt<1>("h00")) + when T_2026 : + pending_probes := mask_incoherent + node T_2027 = bit(mask_incoherent, 0) + node T_2028 = bit(mask_incoherent, 1) + node T_2029 = bit(mask_incoherent, 2) + node T_2030 = bit(mask_incoherent, 3) + node T_2032 = cat(UInt<1>("h00"), T_2028) + node T_2033 = addw(T_2027, T_2032) + node T_2036 = cat(UInt<1>("h00"), T_2030) + node T_2037 = addw(T_2029, T_2036) + node T_2038 = cat(UInt<1>("h00"), T_2037) + node T_2039 = addw(T_2033, T_2038) + release_count := T_2039 + skip + node T_2040 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) + node T_2041 = mux(pending_outer_write_, UInt<2>("h03"), T_2040) + node T_2042 = mux(T_2026, UInt<1>("h01"), T_2041) + state := T_2042 + skip + skip + node T_2043 = eq(UInt<1>("h01"), state) + when T_2043 : + node T_2045 = neq(pending_probes, UInt<1>("h00")) + inner.probe.valid := T_2045 + when inner.probe.ready : + node T_2047 = dshl(UInt<1>("h01"), UInt<1>("h00")) + node T_2048 = not(T_2047) + node T_2049 = and(pending_probes, T_2048) + pending_probes := T_2049 + skip + wire T_2051 : UInt<2>[3] + T_2051[0] := UInt<1>("h00") + T_2051[1] := UInt<1>("h01") + T_2051[2] := UInt<2>("h02") + node T_2056 = eq(T_2051[0], inner.release.bits.r_type) + node T_2057 = eq(T_2051[1], inner.release.bits.r_type) + node T_2058 = eq(T_2051[2], inner.release.bits.r_type) + node T_2060 = or(UInt<1>("h00"), T_2056) + node T_2061 = or(T_2060, T_2057) + node T_2062 = or(T_2061, T_2058) + node T_2064 = eq(T_2062, UInt<1>("h00")) + node T_2065 = or(T_2064, outer.acquire.ready) + inner.release.ready := T_2065 + when inner.release.valid : + wire T_2067 : UInt<2>[3] + T_2067[0] := UInt<1>("h00") + T_2067[1] := UInt<1>("h01") + T_2067[2] := UInt<2>("h02") + node T_2072 = eq(T_2067[0], inner.release.bits.r_type) + node T_2073 = eq(T_2067[1], inner.release.bits.r_type) + node T_2074 = eq(T_2067[2], inner.release.bits.r_type) + node T_2076 = or(UInt<1>("h00"), T_2072) + node T_2077 = or(T_2076, T_2073) + node T_2078 = or(T_2077, T_2074) + when T_2078 : + outer.acquire.valid := UInt<1>("h01") + outer.acquire.bits <> outer_write_rel + when outer.acquire.ready : + when oacq_data_done : + pending_ognt_ack := UInt<1>("h01") + node T_2082 = subw(release_count, UInt<1>("h01")) + release_count := T_2082 + node T_2084 = eq(release_count, UInt<1>("h01")) + when T_2084 : + node T_2085 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_2086 = mux(pending_outer_write, UInt<2>("h03"), T_2085) + state := T_2086 + skip + skip + skip + skip + else : + node T_2088 = subw(release_count, UInt<1>("h01")) + release_count := T_2088 + node T_2090 = eq(release_count, UInt<1>("h01")) + when T_2090 : + node T_2091 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_2092 = mux(pending_outer_write, UInt<2>("h03"), T_2091) + state := T_2092 + skip + skip + skip + skip + node T_2093 = eq(UInt<2>("h03"), state) + when T_2093 : + node T_2095 = eq(pending_ognt_ack, UInt<1>("h00")) + node T_2097 = eq(collect_iacq_data, UInt<1>("h00")) + node T_2098 = or(T_2095, T_2097) + node T_2099 = dshr(iacq_data_valid, oacq_data_cnt) + node T_2100 = bit(T_2099, 0) + node T_2101 = or(T_2098, T_2100) + outer.acquire.valid := T_2101 + outer.acquire.bits <> outer_write_acq + when oacq_data_done : + pending_ognt_ack := UInt<1>("h01") + node T_2103 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) + state := T_2103 + skip + skip + node T_2104 = eq(UInt<2>("h02"), state) + when T_2104 : + node T_2106 = eq(pending_ognt_ack, UInt<1>("h00")) + outer.acquire.valid := T_2106 + outer.acquire.bits <> outer_read + node T_2107 = and(outer.acquire.ready, outer.acquire.valid) + when T_2107 : + state := UInt<3>("h05") + skip + skip + node T_2108 = eq(UInt<3>("h05"), state) + when T_2108 : + outer.grant.ready := inner.grant.ready + inner.grant.valid := outer.grant.valid + when ignt_data_done : + node T_2111 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_2113 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_2114 = and(inner.grant.bits.is_builtin_type, T_2113) + node T_2116 = eq(T_2114, UInt<1>("h00")) + node T_2117 = and(T_2111, T_2116) + node T_2118 = mux(T_2117, UInt<3>("h06"), UInt<1>("h00")) + state := T_2118 + skip + skip + node T_2119 = eq(UInt<3>("h04"), state) + when T_2119 : + inner.grant.valid := UInt<1>("h01") + when inner.grant.ready : + node T_2123 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_2125 = eq(inner.grant.bits.g_type, UInt<3>("h00")) + node T_2126 = and(inner.grant.bits.is_builtin_type, T_2125) + node T_2128 = eq(T_2126, UInt<1>("h00")) + node T_2129 = and(T_2123, T_2128) + node T_2130 = mux(T_2129, UInt<3>("h06"), UInt<1>("h00")) + state := T_2130 + skip + skip + node T_2131 = eq(UInt<3>("h06"), state) + when T_2131 : + inner.finish.ready := UInt<1>("h01") + when inner.finish.valid : + state := UInt<1>("h00") + skip + skip + + module LockingRRArbiter_33 : + output chosen : UInt<3> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}[8] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.client_id := UInt<1>("h00") + out.bits.g_type := UInt<1>("h00") + out.bits.is_builtin_type := UInt<1>("h00") + out.bits.manager_xact_id := UInt<1>("h00") + out.bits.client_xact_id := UInt<1>("h00") + out.bits.data := UInt<1>("h00") + out.bits.addr_beat := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + in[2].ready := UInt<1>("h00") + in[3].ready := UInt<1>("h00") + in[4].ready := UInt<1>("h00") + in[5].ready := UInt<1>("h00") + in[6].ready := UInt<1>("h00") + in[7].ready := UInt<1>("h00") + reg T_1502 : UInt<1>, clock, reset + onreset T_1502 := UInt<1>("h00") + reg T_1504 : UInt<?>, clock, reset + onreset T_1504 := UInt<3>("h07") + wire T_1506 : UInt<3> + T_1506 := UInt<1>("h00") + infer accessor T_1508 = in[T_1506] + out.valid := T_1508.valid + infer accessor T_1573 = in[T_1506] + out.bits <> T_1573.bits + chosen := T_1506 + infer accessor T_1638 = in[T_1506] + T_1638.ready := UInt<1>("h00") + reg last_grant : UInt<3>, clock, reset + onreset last_grant := UInt<3>("h00") + node T_1707 = gt(UInt<1>("h00"), last_grant) + node T_1708 = and(in[0].valid, T_1707) + node T_1710 = gt(UInt<1>("h01"), last_grant) + node T_1711 = and(in[1].valid, T_1710) + node T_1713 = gt(UInt<2>("h02"), last_grant) + node T_1714 = and(in[2].valid, T_1713) + node T_1716 = gt(UInt<2>("h03"), last_grant) + node T_1717 = and(in[3].valid, T_1716) + node T_1719 = gt(UInt<3>("h04"), last_grant) + node T_1720 = and(in[4].valid, T_1719) + node T_1722 = gt(UInt<3>("h05"), last_grant) + node T_1723 = and(in[5].valid, T_1722) + node T_1725 = gt(UInt<3>("h06"), last_grant) + node T_1726 = and(in[6].valid, T_1725) + node T_1728 = gt(UInt<3>("h07"), last_grant) + node T_1729 = and(in[7].valid, T_1728) + node T_1732 = or(UInt<1>("h00"), T_1708) + node T_1734 = eq(T_1732, UInt<1>("h00")) + node T_1736 = or(UInt<1>("h00"), T_1708) + node T_1737 = or(T_1736, T_1711) + node T_1739 = eq(T_1737, UInt<1>("h00")) + node T_1741 = or(UInt<1>("h00"), T_1708) + node T_1742 = or(T_1741, T_1711) + node T_1743 = or(T_1742, T_1714) + node T_1745 = eq(T_1743, UInt<1>("h00")) + node T_1747 = or(UInt<1>("h00"), T_1708) + node T_1748 = or(T_1747, T_1711) + node T_1749 = or(T_1748, T_1714) + node T_1750 = or(T_1749, T_1717) + node T_1752 = eq(T_1750, UInt<1>("h00")) + node T_1754 = or(UInt<1>("h00"), T_1708) + node T_1755 = or(T_1754, T_1711) + node T_1756 = or(T_1755, T_1714) + node T_1757 = or(T_1756, T_1717) + node T_1758 = or(T_1757, T_1720) + node T_1760 = eq(T_1758, UInt<1>("h00")) + node T_1762 = or(UInt<1>("h00"), T_1708) + node T_1763 = or(T_1762, T_1711) + node T_1764 = or(T_1763, T_1714) + node T_1765 = or(T_1764, T_1717) + node T_1766 = or(T_1765, T_1720) + node T_1767 = or(T_1766, T_1723) + node T_1769 = eq(T_1767, UInt<1>("h00")) + node T_1771 = or(UInt<1>("h00"), T_1708) + node T_1772 = or(T_1771, T_1711) + node T_1773 = or(T_1772, T_1714) + node T_1774 = or(T_1773, T_1717) + node T_1775 = or(T_1774, T_1720) + node T_1776 = or(T_1775, T_1723) + node T_1777 = or(T_1776, T_1726) + node T_1779 = eq(T_1777, UInt<1>("h00")) + node T_1781 = or(UInt<1>("h00"), T_1708) + node T_1782 = or(T_1781, T_1711) + node T_1783 = or(T_1782, T_1714) + node T_1784 = or(T_1783, T_1717) + node T_1785 = or(T_1784, T_1720) + node T_1786 = or(T_1785, T_1723) + node T_1787 = or(T_1786, T_1726) + node T_1788 = or(T_1787, T_1729) + node T_1790 = eq(T_1788, UInt<1>("h00")) + node T_1792 = or(UInt<1>("h00"), T_1708) + node T_1793 = or(T_1792, T_1711) + node T_1794 = or(T_1793, T_1714) + node T_1795 = or(T_1794, T_1717) + node T_1796 = or(T_1795, T_1720) + node T_1797 = or(T_1796, T_1723) + node T_1798 = or(T_1797, T_1726) + node T_1799 = or(T_1798, T_1729) + node T_1800 = or(T_1799, in[0].valid) + node T_1802 = eq(T_1800, UInt<1>("h00")) + node T_1804 = or(UInt<1>("h00"), T_1708) + node T_1805 = or(T_1804, T_1711) + node T_1806 = or(T_1805, T_1714) + node T_1807 = or(T_1806, T_1717) + node T_1808 = or(T_1807, T_1720) + node T_1809 = or(T_1808, T_1723) + node T_1810 = or(T_1809, T_1726) + node T_1811 = or(T_1810, T_1729) + node T_1812 = or(T_1811, in[0].valid) + node T_1813 = or(T_1812, in[1].valid) + node T_1815 = eq(T_1813, UInt<1>("h00")) + node T_1817 = or(UInt<1>("h00"), T_1708) + node T_1818 = or(T_1817, T_1711) + node T_1819 = or(T_1818, T_1714) + node T_1820 = or(T_1819, T_1717) + node T_1821 = or(T_1820, T_1720) + node T_1822 = or(T_1821, T_1723) + node T_1823 = or(T_1822, T_1726) + node T_1824 = or(T_1823, T_1729) + node T_1825 = or(T_1824, in[0].valid) + node T_1826 = or(T_1825, in[1].valid) + node T_1827 = or(T_1826, in[2].valid) + node T_1829 = eq(T_1827, UInt<1>("h00")) + node T_1831 = or(UInt<1>("h00"), T_1708) + node T_1832 = or(T_1831, T_1711) + node T_1833 = or(T_1832, T_1714) + node T_1834 = or(T_1833, T_1717) + node T_1835 = or(T_1834, T_1720) + node T_1836 = or(T_1835, T_1723) + node T_1837 = or(T_1836, T_1726) + node T_1838 = or(T_1837, T_1729) + node T_1839 = or(T_1838, in[0].valid) + node T_1840 = or(T_1839, in[1].valid) + node T_1841 = or(T_1840, in[2].valid) + node T_1842 = or(T_1841, in[3].valid) + node T_1844 = eq(T_1842, UInt<1>("h00")) + node T_1846 = or(UInt<1>("h00"), T_1708) + node T_1847 = or(T_1846, T_1711) + node T_1848 = or(T_1847, T_1714) + node T_1849 = or(T_1848, T_1717) + node T_1850 = or(T_1849, T_1720) + node T_1851 = or(T_1850, T_1723) + node T_1852 = or(T_1851, T_1726) + node T_1853 = or(T_1852, T_1729) + node T_1854 = or(T_1853, in[0].valid) + node T_1855 = or(T_1854, in[1].valid) + node T_1856 = or(T_1855, in[2].valid) + node T_1857 = or(T_1856, in[3].valid) + node T_1858 = or(T_1857, in[4].valid) + node T_1860 = eq(T_1858, UInt<1>("h00")) + node T_1862 = or(UInt<1>("h00"), T_1708) + node T_1863 = or(T_1862, T_1711) + node T_1864 = or(T_1863, T_1714) + node T_1865 = or(T_1864, T_1717) + node T_1866 = or(T_1865, T_1720) + node T_1867 = or(T_1866, T_1723) + node T_1868 = or(T_1867, T_1726) + node T_1869 = or(T_1868, T_1729) + node T_1870 = or(T_1869, in[0].valid) + node T_1871 = or(T_1870, in[1].valid) + node T_1872 = or(T_1871, in[2].valid) + node T_1873 = or(T_1872, in[3].valid) + node T_1874 = or(T_1873, in[4].valid) + node T_1875 = or(T_1874, in[5].valid) + node T_1877 = eq(T_1875, UInt<1>("h00")) + node T_1879 = or(UInt<1>("h00"), T_1708) + node T_1880 = or(T_1879, T_1711) + node T_1881 = or(T_1880, T_1714) + node T_1882 = or(T_1881, T_1717) + node T_1883 = or(T_1882, T_1720) + node T_1884 = or(T_1883, T_1723) + node T_1885 = or(T_1884, T_1726) + node T_1886 = or(T_1885, T_1729) + node T_1887 = or(T_1886, in[0].valid) + node T_1888 = or(T_1887, in[1].valid) + node T_1889 = or(T_1888, in[2].valid) + node T_1890 = or(T_1889, in[3].valid) + node T_1891 = or(T_1890, in[4].valid) + node T_1892 = or(T_1891, in[5].valid) + node T_1893 = or(T_1892, in[6].valid) + node T_1895 = eq(T_1893, UInt<1>("h00")) + node T_1897 = gt(UInt<1>("h00"), last_grant) + node T_1898 = and(UInt<1>("h01"), T_1897) + node T_1899 = or(T_1898, T_1790) + node T_1901 = gt(UInt<1>("h01"), last_grant) + node T_1902 = and(T_1734, T_1901) + node T_1903 = or(T_1902, T_1802) + node T_1905 = gt(UInt<2>("h02"), last_grant) + node T_1906 = and(T_1739, T_1905) + node T_1907 = or(T_1906, T_1815) + node T_1909 = gt(UInt<2>("h03"), last_grant) + node T_1910 = and(T_1745, T_1909) + node T_1911 = or(T_1910, T_1829) + node T_1913 = gt(UInt<3>("h04"), last_grant) + node T_1914 = and(T_1752, T_1913) + node T_1915 = or(T_1914, T_1844) + node T_1917 = gt(UInt<3>("h05"), last_grant) + node T_1918 = and(T_1760, T_1917) + node T_1919 = or(T_1918, T_1860) + node T_1921 = gt(UInt<3>("h06"), last_grant) + node T_1922 = and(T_1769, T_1921) + node T_1923 = or(T_1922, T_1877) + node T_1925 = gt(UInt<3>("h07"), last_grant) + node T_1926 = and(T_1779, T_1925) + node T_1927 = or(T_1926, T_1895) + node T_1929 = eq(T_1504, UInt<1>("h00")) + node T_1930 = mux(T_1502, T_1929, T_1899) + node T_1931 = and(T_1930, out.ready) + in[0].ready := T_1931 + node T_1933 = eq(T_1504, UInt<1>("h01")) + node T_1934 = mux(T_1502, T_1933, T_1903) + node T_1935 = and(T_1934, out.ready) + in[1].ready := T_1935 + node T_1937 = eq(T_1504, UInt<2>("h02")) + node T_1938 = mux(T_1502, T_1937, T_1907) + node T_1939 = and(T_1938, out.ready) + in[2].ready := T_1939 + node T_1941 = eq(T_1504, UInt<2>("h03")) + node T_1942 = mux(T_1502, T_1941, T_1911) + node T_1943 = and(T_1942, out.ready) + in[3].ready := T_1943 + node T_1945 = eq(T_1504, UInt<3>("h04")) + node T_1946 = mux(T_1502, T_1945, T_1915) + node T_1947 = and(T_1946, out.ready) + in[4].ready := T_1947 + node T_1949 = eq(T_1504, UInt<3>("h05")) + node T_1950 = mux(T_1502, T_1949, T_1919) + node T_1951 = and(T_1950, out.ready) + in[5].ready := T_1951 + node T_1953 = eq(T_1504, UInt<3>("h06")) + node T_1954 = mux(T_1502, T_1953, T_1923) + node T_1955 = and(T_1954, out.ready) + in[6].ready := T_1955 + node T_1957 = eq(T_1504, UInt<3>("h07")) + node T_1958 = mux(T_1502, T_1957, T_1927) + node T_1959 = and(T_1958, out.ready) + in[7].ready := T_1959 + reg T_1961 : UInt<2>, clock, reset + onreset T_1961 := UInt<2>("h00") + node T_1963 = addw(T_1961, UInt<1>("h01")) + node T_1964 = and(out.ready, out.valid) + when T_1964 : + wire T_1968 : UInt<3>[1] + T_1968[0] := UInt<3>("h05") + node T_1971 = eq(T_1968[0], out.bits.g_type) + node T_1973 = or(UInt<1>("h00"), T_1971) + wire T_1975 : UInt<1>[2] + T_1975[0] := UInt<1>("h00") + T_1975[1] := UInt<1>("h01") + node T_1979 = eq(T_1975[0], out.bits.g_type) + node T_1980 = eq(T_1975[1], out.bits.g_type) + node T_1982 = or(UInt<1>("h00"), T_1979) + node T_1983 = or(T_1982, T_1980) + node T_1984 = mux(out.bits.is_builtin_type, T_1973, T_1983) + node T_1985 = and(UInt<1>("h01"), T_1984) + when T_1985 : + T_1961 := T_1963 + node T_1987 = eq(T_1502, UInt<1>("h00")) + when T_1987 : + T_1502 := UInt<1>("h01") + node T_1989 = and(in[0].ready, in[0].valid) + node T_1990 = and(in[1].ready, in[1].valid) + node T_1991 = and(in[2].ready, in[2].valid) + node T_1992 = and(in[3].ready, in[3].valid) + node T_1993 = and(in[4].ready, in[4].valid) + node T_1994 = and(in[5].ready, in[5].valid) + node T_1995 = and(in[6].ready, in[6].valid) + node T_1996 = and(in[7].ready, in[7].valid) + wire T_1998 : UInt<1>[8] + T_1998[0] := T_1989 + T_1998[1] := T_1990 + T_1998[2] := T_1991 + T_1998[3] := T_1992 + T_1998[4] := T_1993 + T_1998[5] := T_1994 + T_1998[6] := T_1995 + T_1998[7] := T_1996 + node T_2016 = mux(T_1998[6], UInt<3>("h06"), UInt<3>("h07")) + node T_2017 = mux(T_1998[5], UInt<3>("h05"), T_2016) + node T_2018 = mux(T_1998[4], UInt<3>("h04"), T_2017) + node T_2019 = mux(T_1998[3], UInt<2>("h03"), T_2018) + node T_2020 = mux(T_1998[2], UInt<2>("h02"), T_2019) + node T_2021 = mux(T_1998[1], UInt<1>("h01"), T_2020) + node T_2022 = mux(T_1998[0], UInt<1>("h00"), T_2021) + T_1504 := T_2022 + skip + skip + node T_2024 = eq(T_1963, UInt<1>("h00")) + when T_2024 : + T_1502 := UInt<1>("h00") + skip + skip + node T_2028 = mux(in[6].valid, UInt<3>("h06"), UInt<3>("h07")) + node T_2030 = mux(in[5].valid, UInt<3>("h05"), T_2028) + node T_2032 = mux(in[4].valid, UInt<3>("h04"), T_2030) + node T_2034 = mux(in[3].valid, UInt<2>("h03"), T_2032) + node T_2036 = mux(in[2].valid, UInt<2>("h02"), T_2034) + node T_2038 = mux(in[1].valid, UInt<1>("h01"), T_2036) + node T_2040 = mux(in[0].valid, UInt<1>("h00"), T_2038) + node T_2042 = gt(UInt<3>("h07"), last_grant) + node T_2043 = and(in[7].valid, T_2042) + node T_2045 = mux(T_2043, UInt<3>("h07"), T_2040) + node T_2047 = gt(UInt<3>("h06"), last_grant) + node T_2048 = and(in[6].valid, T_2047) + node T_2050 = mux(T_2048, UInt<3>("h06"), T_2045) + node T_2052 = gt(UInt<3>("h05"), last_grant) + node T_2053 = and(in[5].valid, T_2052) + node T_2055 = mux(T_2053, UInt<3>("h05"), T_2050) + node T_2057 = gt(UInt<3>("h04"), last_grant) + node T_2058 = and(in[4].valid, T_2057) + node T_2060 = mux(T_2058, UInt<3>("h04"), T_2055) + node T_2062 = gt(UInt<2>("h03"), last_grant) + node T_2063 = and(in[3].valid, T_2062) + node T_2065 = mux(T_2063, UInt<2>("h03"), T_2060) + node T_2067 = gt(UInt<2>("h02"), last_grant) + node T_2068 = and(in[2].valid, T_2067) + node T_2070 = mux(T_2068, UInt<2>("h02"), T_2065) + node T_2072 = gt(UInt<1>("h01"), last_grant) + node T_2073 = and(in[1].valid, T_2072) + node choose = mux(T_2073, UInt<1>("h01"), T_2070) + node T_2076 = mux(T_1502, T_1504, choose) + T_1506 := T_2076 + node T_2077 = and(out.ready, out.valid) + when T_2077 : + last_grant := T_1506 + skip + + module LockingRRArbiter_34 : + output chosen : UInt<3> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}[8] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.client_id := UInt<1>("h00") + out.bits.p_type := UInt<1>("h00") + out.bits.addr_block := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + in[2].ready := UInt<1>("h00") + in[3].ready := UInt<1>("h00") + in[4].ready := UInt<1>("h00") + in[5].ready := UInt<1>("h00") + in[6].ready := UInt<1>("h00") + in[7].ready := UInt<1>("h00") + reg T_1318 : UInt<1>, clock, reset + onreset T_1318 := UInt<1>("h00") + reg T_1320 : UInt<?>, clock, reset + onreset T_1320 := UInt<3>("h07") + wire T_1322 : UInt<3> + T_1322 := UInt<1>("h00") + infer accessor T_1324 = in[T_1322] + out.valid := T_1324.valid + infer accessor T_1381 = in[T_1322] + out.bits <> T_1381.bits + chosen := T_1322 + infer accessor T_1438 = in[T_1322] + T_1438.ready := UInt<1>("h00") + reg last_grant : UInt<3>, clock, reset + onreset last_grant := UInt<3>("h00") + node T_1499 = gt(UInt<1>("h00"), last_grant) + node T_1500 = and(in[0].valid, T_1499) + node T_1502 = gt(UInt<1>("h01"), last_grant) + node T_1503 = and(in[1].valid, T_1502) + node T_1505 = gt(UInt<2>("h02"), last_grant) + node T_1506 = and(in[2].valid, T_1505) + node T_1508 = gt(UInt<2>("h03"), last_grant) + node T_1509 = and(in[3].valid, T_1508) + node T_1511 = gt(UInt<3>("h04"), last_grant) + node T_1512 = and(in[4].valid, T_1511) + node T_1514 = gt(UInt<3>("h05"), last_grant) + node T_1515 = and(in[5].valid, T_1514) + node T_1517 = gt(UInt<3>("h06"), last_grant) + node T_1518 = and(in[6].valid, T_1517) + node T_1520 = gt(UInt<3>("h07"), last_grant) + node T_1521 = and(in[7].valid, T_1520) + node T_1524 = or(UInt<1>("h00"), T_1500) + node T_1526 = eq(T_1524, UInt<1>("h00")) + node T_1528 = or(UInt<1>("h00"), T_1500) + node T_1529 = or(T_1528, T_1503) + node T_1531 = eq(T_1529, UInt<1>("h00")) + node T_1533 = or(UInt<1>("h00"), T_1500) + node T_1534 = or(T_1533, T_1503) + node T_1535 = or(T_1534, T_1506) + node T_1537 = eq(T_1535, UInt<1>("h00")) + node T_1539 = or(UInt<1>("h00"), T_1500) + node T_1540 = or(T_1539, T_1503) + node T_1541 = or(T_1540, T_1506) + node T_1542 = or(T_1541, T_1509) + node T_1544 = eq(T_1542, UInt<1>("h00")) + node T_1546 = or(UInt<1>("h00"), T_1500) + node T_1547 = or(T_1546, T_1503) + node T_1548 = or(T_1547, T_1506) + node T_1549 = or(T_1548, T_1509) + node T_1550 = or(T_1549, T_1512) + node T_1552 = eq(T_1550, UInt<1>("h00")) + node T_1554 = or(UInt<1>("h00"), T_1500) + node T_1555 = or(T_1554, T_1503) + node T_1556 = or(T_1555, T_1506) + node T_1557 = or(T_1556, T_1509) + node T_1558 = or(T_1557, T_1512) + node T_1559 = or(T_1558, T_1515) + node T_1561 = eq(T_1559, UInt<1>("h00")) + node T_1563 = or(UInt<1>("h00"), T_1500) + node T_1564 = or(T_1563, T_1503) + node T_1565 = or(T_1564, T_1506) + node T_1566 = or(T_1565, T_1509) + node T_1567 = or(T_1566, T_1512) + node T_1568 = or(T_1567, T_1515) + node T_1569 = or(T_1568, T_1518) + node T_1571 = eq(T_1569, UInt<1>("h00")) + node T_1573 = or(UInt<1>("h00"), T_1500) + node T_1574 = or(T_1573, T_1503) + node T_1575 = or(T_1574, T_1506) + node T_1576 = or(T_1575, T_1509) + node T_1577 = or(T_1576, T_1512) + node T_1578 = or(T_1577, T_1515) + node T_1579 = or(T_1578, T_1518) + node T_1580 = or(T_1579, T_1521) + node T_1582 = eq(T_1580, UInt<1>("h00")) + node T_1584 = or(UInt<1>("h00"), T_1500) + node T_1585 = or(T_1584, T_1503) + node T_1586 = or(T_1585, T_1506) + node T_1587 = or(T_1586, T_1509) + node T_1588 = or(T_1587, T_1512) + node T_1589 = or(T_1588, T_1515) + node T_1590 = or(T_1589, T_1518) + node T_1591 = or(T_1590, T_1521) + node T_1592 = or(T_1591, in[0].valid) + node T_1594 = eq(T_1592, UInt<1>("h00")) + node T_1596 = or(UInt<1>("h00"), T_1500) + node T_1597 = or(T_1596, T_1503) + node T_1598 = or(T_1597, T_1506) + node T_1599 = or(T_1598, T_1509) + node T_1600 = or(T_1599, T_1512) + node T_1601 = or(T_1600, T_1515) + node T_1602 = or(T_1601, T_1518) + node T_1603 = or(T_1602, T_1521) + node T_1604 = or(T_1603, in[0].valid) + node T_1605 = or(T_1604, in[1].valid) + node T_1607 = eq(T_1605, UInt<1>("h00")) + node T_1609 = or(UInt<1>("h00"), T_1500) + node T_1610 = or(T_1609, T_1503) + node T_1611 = or(T_1610, T_1506) + node T_1612 = or(T_1611, T_1509) + node T_1613 = or(T_1612, T_1512) + node T_1614 = or(T_1613, T_1515) + node T_1615 = or(T_1614, T_1518) + node T_1616 = or(T_1615, T_1521) + node T_1617 = or(T_1616, in[0].valid) + node T_1618 = or(T_1617, in[1].valid) + node T_1619 = or(T_1618, in[2].valid) + node T_1621 = eq(T_1619, UInt<1>("h00")) + node T_1623 = or(UInt<1>("h00"), T_1500) + node T_1624 = or(T_1623, T_1503) + node T_1625 = or(T_1624, T_1506) + node T_1626 = or(T_1625, T_1509) + node T_1627 = or(T_1626, T_1512) + node T_1628 = or(T_1627, T_1515) + node T_1629 = or(T_1628, T_1518) + node T_1630 = or(T_1629, T_1521) + node T_1631 = or(T_1630, in[0].valid) + node T_1632 = or(T_1631, in[1].valid) + node T_1633 = or(T_1632, in[2].valid) + node T_1634 = or(T_1633, in[3].valid) + node T_1636 = eq(T_1634, UInt<1>("h00")) + node T_1638 = or(UInt<1>("h00"), T_1500) + node T_1639 = or(T_1638, T_1503) + node T_1640 = or(T_1639, T_1506) + node T_1641 = or(T_1640, T_1509) + node T_1642 = or(T_1641, T_1512) + node T_1643 = or(T_1642, T_1515) + node T_1644 = or(T_1643, T_1518) + node T_1645 = or(T_1644, T_1521) + node T_1646 = or(T_1645, in[0].valid) + node T_1647 = or(T_1646, in[1].valid) + node T_1648 = or(T_1647, in[2].valid) + node T_1649 = or(T_1648, in[3].valid) + node T_1650 = or(T_1649, in[4].valid) + node T_1652 = eq(T_1650, UInt<1>("h00")) + node T_1654 = or(UInt<1>("h00"), T_1500) + node T_1655 = or(T_1654, T_1503) + node T_1656 = or(T_1655, T_1506) + node T_1657 = or(T_1656, T_1509) + node T_1658 = or(T_1657, T_1512) + node T_1659 = or(T_1658, T_1515) + node T_1660 = or(T_1659, T_1518) + node T_1661 = or(T_1660, T_1521) + node T_1662 = or(T_1661, in[0].valid) + node T_1663 = or(T_1662, in[1].valid) + node T_1664 = or(T_1663, in[2].valid) + node T_1665 = or(T_1664, in[3].valid) + node T_1666 = or(T_1665, in[4].valid) + node T_1667 = or(T_1666, in[5].valid) + node T_1669 = eq(T_1667, UInt<1>("h00")) + node T_1671 = or(UInt<1>("h00"), T_1500) + node T_1672 = or(T_1671, T_1503) + node T_1673 = or(T_1672, T_1506) + node T_1674 = or(T_1673, T_1509) + node T_1675 = or(T_1674, T_1512) + node T_1676 = or(T_1675, T_1515) + node T_1677 = or(T_1676, T_1518) + node T_1678 = or(T_1677, T_1521) + node T_1679 = or(T_1678, in[0].valid) + node T_1680 = or(T_1679, in[1].valid) + node T_1681 = or(T_1680, in[2].valid) + node T_1682 = or(T_1681, in[3].valid) + node T_1683 = or(T_1682, in[4].valid) + node T_1684 = or(T_1683, in[5].valid) + node T_1685 = or(T_1684, in[6].valid) + node T_1687 = eq(T_1685, UInt<1>("h00")) + node T_1689 = gt(UInt<1>("h00"), last_grant) + node T_1690 = and(UInt<1>("h01"), T_1689) + node T_1691 = or(T_1690, T_1582) + node T_1693 = gt(UInt<1>("h01"), last_grant) + node T_1694 = and(T_1526, T_1693) + node T_1695 = or(T_1694, T_1594) + node T_1697 = gt(UInt<2>("h02"), last_grant) + node T_1698 = and(T_1531, T_1697) + node T_1699 = or(T_1698, T_1607) + node T_1701 = gt(UInt<2>("h03"), last_grant) + node T_1702 = and(T_1537, T_1701) + node T_1703 = or(T_1702, T_1621) + node T_1705 = gt(UInt<3>("h04"), last_grant) + node T_1706 = and(T_1544, T_1705) + node T_1707 = or(T_1706, T_1636) + node T_1709 = gt(UInt<3>("h05"), last_grant) + node T_1710 = and(T_1552, T_1709) + node T_1711 = or(T_1710, T_1652) + node T_1713 = gt(UInt<3>("h06"), last_grant) + node T_1714 = and(T_1561, T_1713) + node T_1715 = or(T_1714, T_1669) + node T_1717 = gt(UInt<3>("h07"), last_grant) + node T_1718 = and(T_1571, T_1717) + node T_1719 = or(T_1718, T_1687) + node T_1721 = eq(T_1320, UInt<1>("h00")) + node T_1722 = mux(T_1318, T_1721, T_1691) + node T_1723 = and(T_1722, out.ready) + in[0].ready := T_1723 + node T_1725 = eq(T_1320, UInt<1>("h01")) + node T_1726 = mux(T_1318, T_1725, T_1695) + node T_1727 = and(T_1726, out.ready) + in[1].ready := T_1727 + node T_1729 = eq(T_1320, UInt<2>("h02")) + node T_1730 = mux(T_1318, T_1729, T_1699) + node T_1731 = and(T_1730, out.ready) + in[2].ready := T_1731 + node T_1733 = eq(T_1320, UInt<2>("h03")) + node T_1734 = mux(T_1318, T_1733, T_1703) + node T_1735 = and(T_1734, out.ready) + in[3].ready := T_1735 + node T_1737 = eq(T_1320, UInt<3>("h04")) + node T_1738 = mux(T_1318, T_1737, T_1707) + node T_1739 = and(T_1738, out.ready) + in[4].ready := T_1739 + node T_1741 = eq(T_1320, UInt<3>("h05")) + node T_1742 = mux(T_1318, T_1741, T_1711) + node T_1743 = and(T_1742, out.ready) + in[5].ready := T_1743 + node T_1745 = eq(T_1320, UInt<3>("h06")) + node T_1746 = mux(T_1318, T_1745, T_1715) + node T_1747 = and(T_1746, out.ready) + in[6].ready := T_1747 + node T_1749 = eq(T_1320, UInt<3>("h07")) + node T_1750 = mux(T_1318, T_1749, T_1719) + node T_1751 = and(T_1750, out.ready) + in[7].ready := T_1751 + reg T_1753 : UInt<2>, clock, reset + onreset T_1753 := UInt<2>("h00") + node T_1755 = addw(T_1753, UInt<1>("h01")) + node T_1756 = and(out.ready, out.valid) + when T_1756 : + when UInt<1>("h00") : + T_1753 := T_1755 + node T_1759 = eq(T_1318, UInt<1>("h00")) + when T_1759 : + T_1318 := UInt<1>("h01") + node T_1761 = and(in[0].ready, in[0].valid) + node T_1762 = and(in[1].ready, in[1].valid) + node T_1763 = and(in[2].ready, in[2].valid) + node T_1764 = and(in[3].ready, in[3].valid) + node T_1765 = and(in[4].ready, in[4].valid) + node T_1766 = and(in[5].ready, in[5].valid) + node T_1767 = and(in[6].ready, in[6].valid) + node T_1768 = and(in[7].ready, in[7].valid) + wire T_1770 : UInt<1>[8] + T_1770[0] := T_1761 + T_1770[1] := T_1762 + T_1770[2] := T_1763 + T_1770[3] := T_1764 + T_1770[4] := T_1765 + T_1770[5] := T_1766 + T_1770[6] := T_1767 + T_1770[7] := T_1768 + node T_1788 = mux(T_1770[6], UInt<3>("h06"), UInt<3>("h07")) + node T_1789 = mux(T_1770[5], UInt<3>("h05"), T_1788) + node T_1790 = mux(T_1770[4], UInt<3>("h04"), T_1789) + node T_1791 = mux(T_1770[3], UInt<2>("h03"), T_1790) + node T_1792 = mux(T_1770[2], UInt<2>("h02"), T_1791) + node T_1793 = mux(T_1770[1], UInt<1>("h01"), T_1792) + node T_1794 = mux(T_1770[0], UInt<1>("h00"), T_1793) + T_1320 := T_1794 + skip + skip + node T_1796 = eq(T_1755, UInt<1>("h00")) + when T_1796 : + T_1318 := UInt<1>("h00") + skip + skip + node T_1800 = mux(in[6].valid, UInt<3>("h06"), UInt<3>("h07")) + node T_1802 = mux(in[5].valid, UInt<3>("h05"), T_1800) + node T_1804 = mux(in[4].valid, UInt<3>("h04"), T_1802) + node T_1806 = mux(in[3].valid, UInt<2>("h03"), T_1804) + node T_1808 = mux(in[2].valid, UInt<2>("h02"), T_1806) + node T_1810 = mux(in[1].valid, UInt<1>("h01"), T_1808) + node T_1812 = mux(in[0].valid, UInt<1>("h00"), T_1810) + node T_1814 = gt(UInt<3>("h07"), last_grant) + node T_1815 = and(in[7].valid, T_1814) + node T_1817 = mux(T_1815, UInt<3>("h07"), T_1812) + node T_1819 = gt(UInt<3>("h06"), last_grant) + node T_1820 = and(in[6].valid, T_1819) + node T_1822 = mux(T_1820, UInt<3>("h06"), T_1817) + node T_1824 = gt(UInt<3>("h05"), last_grant) + node T_1825 = and(in[5].valid, T_1824) + node T_1827 = mux(T_1825, UInt<3>("h05"), T_1822) + node T_1829 = gt(UInt<3>("h04"), last_grant) + node T_1830 = and(in[4].valid, T_1829) + node T_1832 = mux(T_1830, UInt<3>("h04"), T_1827) + node T_1834 = gt(UInt<2>("h03"), last_grant) + node T_1835 = and(in[3].valid, T_1834) + node T_1837 = mux(T_1835, UInt<2>("h03"), T_1832) + node T_1839 = gt(UInt<2>("h02"), last_grant) + node T_1840 = and(in[2].valid, T_1839) + node T_1842 = mux(T_1840, UInt<2>("h02"), T_1837) + node T_1844 = gt(UInt<1>("h01"), last_grant) + node T_1845 = and(in[1].valid, T_1844) + node choose = mux(T_1845, UInt<1>("h01"), T_1842) + node T_1848 = mux(T_1318, T_1320, choose) + T_1322 := T_1848 + node T_1849 = and(out.ready, out.valid) + when T_1849 : + last_grant := T_1322 + skip + + module LockingRRArbiter_35 : + output chosen : UInt<3> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}[8] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.union := UInt<1>("h00") + out.bits.a_type := UInt<1>("h00") + out.bits.is_builtin_type := UInt<1>("h00") + out.bits.data := UInt<1>("h00") + out.bits.addr_beat := UInt<1>("h00") + out.bits.client_xact_id := UInt<1>("h00") + out.bits.addr_block := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + in[2].ready := UInt<1>("h00") + in[3].ready := UInt<1>("h00") + in[4].ready := UInt<1>("h00") + in[5].ready := UInt<1>("h00") + in[6].ready := UInt<1>("h00") + in[7].ready := UInt<1>("h00") + reg T_1364 : UInt<1>, clock, reset + onreset T_1364 := UInt<1>("h00") + reg T_1366 : UInt<?>, clock, reset + onreset T_1366 := UInt<3>("h07") + wire T_1368 : UInt<3> + T_1368 := UInt<1>("h00") + infer accessor T_1370 = in[T_1368] + out.valid := T_1370.valid + infer accessor T_1429 = in[T_1368] + out.bits <> T_1429.bits + chosen := T_1368 + infer accessor T_1488 = in[T_1368] + T_1488.ready := UInt<1>("h00") + reg last_grant : UInt<3>, clock, reset + onreset last_grant := UInt<3>("h00") + node T_1551 = gt(UInt<1>("h00"), last_grant) + node T_1552 = and(in[0].valid, T_1551) + node T_1554 = gt(UInt<1>("h01"), last_grant) + node T_1555 = and(in[1].valid, T_1554) + node T_1557 = gt(UInt<2>("h02"), last_grant) + node T_1558 = and(in[2].valid, T_1557) + node T_1560 = gt(UInt<2>("h03"), last_grant) + node T_1561 = and(in[3].valid, T_1560) + node T_1563 = gt(UInt<3>("h04"), last_grant) + node T_1564 = and(in[4].valid, T_1563) + node T_1566 = gt(UInt<3>("h05"), last_grant) + node T_1567 = and(in[5].valid, T_1566) + node T_1569 = gt(UInt<3>("h06"), last_grant) + node T_1570 = and(in[6].valid, T_1569) + node T_1572 = gt(UInt<3>("h07"), last_grant) + node T_1573 = and(in[7].valid, T_1572) + node T_1576 = or(UInt<1>("h00"), T_1552) + node T_1578 = eq(T_1576, UInt<1>("h00")) + node T_1580 = or(UInt<1>("h00"), T_1552) + node T_1581 = or(T_1580, T_1555) + node T_1583 = eq(T_1581, UInt<1>("h00")) + node T_1585 = or(UInt<1>("h00"), T_1552) + node T_1586 = or(T_1585, T_1555) + node T_1587 = or(T_1586, T_1558) + node T_1589 = eq(T_1587, UInt<1>("h00")) + node T_1591 = or(UInt<1>("h00"), T_1552) + node T_1592 = or(T_1591, T_1555) + node T_1593 = or(T_1592, T_1558) + node T_1594 = or(T_1593, T_1561) + node T_1596 = eq(T_1594, UInt<1>("h00")) + node T_1598 = or(UInt<1>("h00"), T_1552) + node T_1599 = or(T_1598, T_1555) + node T_1600 = or(T_1599, T_1558) + node T_1601 = or(T_1600, T_1561) + node T_1602 = or(T_1601, T_1564) + node T_1604 = eq(T_1602, UInt<1>("h00")) + node T_1606 = or(UInt<1>("h00"), T_1552) + node T_1607 = or(T_1606, T_1555) + node T_1608 = or(T_1607, T_1558) + node T_1609 = or(T_1608, T_1561) + node T_1610 = or(T_1609, T_1564) + node T_1611 = or(T_1610, T_1567) + node T_1613 = eq(T_1611, UInt<1>("h00")) + node T_1615 = or(UInt<1>("h00"), T_1552) + node T_1616 = or(T_1615, T_1555) + node T_1617 = or(T_1616, T_1558) + node T_1618 = or(T_1617, T_1561) + node T_1619 = or(T_1618, T_1564) + node T_1620 = or(T_1619, T_1567) + node T_1621 = or(T_1620, T_1570) + node T_1623 = eq(T_1621, UInt<1>("h00")) + node T_1625 = or(UInt<1>("h00"), T_1552) + node T_1626 = or(T_1625, T_1555) + node T_1627 = or(T_1626, T_1558) + node T_1628 = or(T_1627, T_1561) + node T_1629 = or(T_1628, T_1564) + node T_1630 = or(T_1629, T_1567) + node T_1631 = or(T_1630, T_1570) + node T_1632 = or(T_1631, T_1573) + node T_1634 = eq(T_1632, UInt<1>("h00")) + node T_1636 = or(UInt<1>("h00"), T_1552) + node T_1637 = or(T_1636, T_1555) + node T_1638 = or(T_1637, T_1558) + node T_1639 = or(T_1638, T_1561) + node T_1640 = or(T_1639, T_1564) + node T_1641 = or(T_1640, T_1567) + node T_1642 = or(T_1641, T_1570) + node T_1643 = or(T_1642, T_1573) + node T_1644 = or(T_1643, in[0].valid) + node T_1646 = eq(T_1644, UInt<1>("h00")) + node T_1648 = or(UInt<1>("h00"), T_1552) + node T_1649 = or(T_1648, T_1555) + node T_1650 = or(T_1649, T_1558) + node T_1651 = or(T_1650, T_1561) + node T_1652 = or(T_1651, T_1564) + node T_1653 = or(T_1652, T_1567) + node T_1654 = or(T_1653, T_1570) + node T_1655 = or(T_1654, T_1573) + node T_1656 = or(T_1655, in[0].valid) + node T_1657 = or(T_1656, in[1].valid) + node T_1659 = eq(T_1657, UInt<1>("h00")) + node T_1661 = or(UInt<1>("h00"), T_1552) + node T_1662 = or(T_1661, T_1555) + node T_1663 = or(T_1662, T_1558) + node T_1664 = or(T_1663, T_1561) + node T_1665 = or(T_1664, T_1564) + node T_1666 = or(T_1665, T_1567) + node T_1667 = or(T_1666, T_1570) + node T_1668 = or(T_1667, T_1573) + node T_1669 = or(T_1668, in[0].valid) + node T_1670 = or(T_1669, in[1].valid) + node T_1671 = or(T_1670, in[2].valid) + node T_1673 = eq(T_1671, UInt<1>("h00")) + node T_1675 = or(UInt<1>("h00"), T_1552) + node T_1676 = or(T_1675, T_1555) + node T_1677 = or(T_1676, T_1558) + node T_1678 = or(T_1677, T_1561) + node T_1679 = or(T_1678, T_1564) + node T_1680 = or(T_1679, T_1567) + node T_1681 = or(T_1680, T_1570) + node T_1682 = or(T_1681, T_1573) + node T_1683 = or(T_1682, in[0].valid) + node T_1684 = or(T_1683, in[1].valid) + node T_1685 = or(T_1684, in[2].valid) + node T_1686 = or(T_1685, in[3].valid) + node T_1688 = eq(T_1686, UInt<1>("h00")) + node T_1690 = or(UInt<1>("h00"), T_1552) + node T_1691 = or(T_1690, T_1555) + node T_1692 = or(T_1691, T_1558) + node T_1693 = or(T_1692, T_1561) + node T_1694 = or(T_1693, T_1564) + node T_1695 = or(T_1694, T_1567) + node T_1696 = or(T_1695, T_1570) + node T_1697 = or(T_1696, T_1573) + node T_1698 = or(T_1697, in[0].valid) + node T_1699 = or(T_1698, in[1].valid) + node T_1700 = or(T_1699, in[2].valid) + node T_1701 = or(T_1700, in[3].valid) + node T_1702 = or(T_1701, in[4].valid) + node T_1704 = eq(T_1702, UInt<1>("h00")) + node T_1706 = or(UInt<1>("h00"), T_1552) + node T_1707 = or(T_1706, T_1555) + node T_1708 = or(T_1707, T_1558) + node T_1709 = or(T_1708, T_1561) + node T_1710 = or(T_1709, T_1564) + node T_1711 = or(T_1710, T_1567) + node T_1712 = or(T_1711, T_1570) + node T_1713 = or(T_1712, T_1573) + node T_1714 = or(T_1713, in[0].valid) + node T_1715 = or(T_1714, in[1].valid) + node T_1716 = or(T_1715, in[2].valid) + node T_1717 = or(T_1716, in[3].valid) + node T_1718 = or(T_1717, in[4].valid) + node T_1719 = or(T_1718, in[5].valid) + node T_1721 = eq(T_1719, UInt<1>("h00")) + node T_1723 = or(UInt<1>("h00"), T_1552) + node T_1724 = or(T_1723, T_1555) + node T_1725 = or(T_1724, T_1558) + node T_1726 = or(T_1725, T_1561) + node T_1727 = or(T_1726, T_1564) + node T_1728 = or(T_1727, T_1567) + node T_1729 = or(T_1728, T_1570) + node T_1730 = or(T_1729, T_1573) + node T_1731 = or(T_1730, in[0].valid) + node T_1732 = or(T_1731, in[1].valid) + node T_1733 = or(T_1732, in[2].valid) + node T_1734 = or(T_1733, in[3].valid) + node T_1735 = or(T_1734, in[4].valid) + node T_1736 = or(T_1735, in[5].valid) + node T_1737 = or(T_1736, in[6].valid) + node T_1739 = eq(T_1737, UInt<1>("h00")) + node T_1741 = gt(UInt<1>("h00"), last_grant) + node T_1742 = and(UInt<1>("h01"), T_1741) + node T_1743 = or(T_1742, T_1634) + node T_1745 = gt(UInt<1>("h01"), last_grant) + node T_1746 = and(T_1578, T_1745) + node T_1747 = or(T_1746, T_1646) + node T_1749 = gt(UInt<2>("h02"), last_grant) + node T_1750 = and(T_1583, T_1749) + node T_1751 = or(T_1750, T_1659) + node T_1753 = gt(UInt<2>("h03"), last_grant) + node T_1754 = and(T_1589, T_1753) + node T_1755 = or(T_1754, T_1673) + node T_1757 = gt(UInt<3>("h04"), last_grant) + node T_1758 = and(T_1596, T_1757) + node T_1759 = or(T_1758, T_1688) + node T_1761 = gt(UInt<3>("h05"), last_grant) + node T_1762 = and(T_1604, T_1761) + node T_1763 = or(T_1762, T_1704) + node T_1765 = gt(UInt<3>("h06"), last_grant) + node T_1766 = and(T_1613, T_1765) + node T_1767 = or(T_1766, T_1721) + node T_1769 = gt(UInt<3>("h07"), last_grant) + node T_1770 = and(T_1623, T_1769) + node T_1771 = or(T_1770, T_1739) + node T_1773 = eq(T_1366, UInt<1>("h00")) + node T_1774 = mux(T_1364, T_1773, T_1743) + node T_1775 = and(T_1774, out.ready) + in[0].ready := T_1775 + node T_1777 = eq(T_1366, UInt<1>("h01")) + node T_1778 = mux(T_1364, T_1777, T_1747) + node T_1779 = and(T_1778, out.ready) + in[1].ready := T_1779 + node T_1781 = eq(T_1366, UInt<2>("h02")) + node T_1782 = mux(T_1364, T_1781, T_1751) + node T_1783 = and(T_1782, out.ready) + in[2].ready := T_1783 + node T_1785 = eq(T_1366, UInt<2>("h03")) + node T_1786 = mux(T_1364, T_1785, T_1755) + node T_1787 = and(T_1786, out.ready) + in[3].ready := T_1787 + node T_1789 = eq(T_1366, UInt<3>("h04")) + node T_1790 = mux(T_1364, T_1789, T_1759) + node T_1791 = and(T_1790, out.ready) + in[4].ready := T_1791 + node T_1793 = eq(T_1366, UInt<3>("h05")) + node T_1794 = mux(T_1364, T_1793, T_1763) + node T_1795 = and(T_1794, out.ready) + in[5].ready := T_1795 + node T_1797 = eq(T_1366, UInt<3>("h06")) + node T_1798 = mux(T_1364, T_1797, T_1767) + node T_1799 = and(T_1798, out.ready) + in[6].ready := T_1799 + node T_1801 = eq(T_1366, UInt<3>("h07")) + node T_1802 = mux(T_1364, T_1801, T_1771) + node T_1803 = and(T_1802, out.ready) + in[7].ready := T_1803 + reg T_1805 : UInt<2>, clock, reset + onreset T_1805 := UInt<2>("h00") + node T_1807 = addw(T_1805, UInt<1>("h01")) + node T_1808 = and(out.ready, out.valid) + when T_1808 : + node T_1810 = and(UInt<1>("h01"), out.bits.is_builtin_type) + wire T_1813 : UInt<3>[1] + T_1813[0] := UInt<3>("h03") + node T_1816 = eq(T_1813[0], out.bits.a_type) + node T_1818 = or(UInt<1>("h00"), T_1816) + node T_1819 = and(T_1810, T_1818) + when T_1819 : + T_1805 := T_1807 + node T_1821 = eq(T_1364, UInt<1>("h00")) + when T_1821 : + T_1364 := UInt<1>("h01") + node T_1823 = and(in[0].ready, in[0].valid) + node T_1824 = and(in[1].ready, in[1].valid) + node T_1825 = and(in[2].ready, in[2].valid) + node T_1826 = and(in[3].ready, in[3].valid) + node T_1827 = and(in[4].ready, in[4].valid) + node T_1828 = and(in[5].ready, in[5].valid) + node T_1829 = and(in[6].ready, in[6].valid) + node T_1830 = and(in[7].ready, in[7].valid) + wire T_1832 : UInt<1>[8] + T_1832[0] := T_1823 + T_1832[1] := T_1824 + T_1832[2] := T_1825 + T_1832[3] := T_1826 + T_1832[4] := T_1827 + T_1832[5] := T_1828 + T_1832[6] := T_1829 + T_1832[7] := T_1830 + node T_1850 = mux(T_1832[6], UInt<3>("h06"), UInt<3>("h07")) + node T_1851 = mux(T_1832[5], UInt<3>("h05"), T_1850) + node T_1852 = mux(T_1832[4], UInt<3>("h04"), T_1851) + node T_1853 = mux(T_1832[3], UInt<2>("h03"), T_1852) + node T_1854 = mux(T_1832[2], UInt<2>("h02"), T_1853) + node T_1855 = mux(T_1832[1], UInt<1>("h01"), T_1854) + node T_1856 = mux(T_1832[0], UInt<1>("h00"), T_1855) + T_1366 := T_1856 + skip + skip + node T_1858 = eq(T_1807, UInt<1>("h00")) + when T_1858 : + T_1364 := UInt<1>("h00") + skip + skip + node T_1862 = mux(in[6].valid, UInt<3>("h06"), UInt<3>("h07")) + node T_1864 = mux(in[5].valid, UInt<3>("h05"), T_1862) + node T_1866 = mux(in[4].valid, UInt<3>("h04"), T_1864) + node T_1868 = mux(in[3].valid, UInt<2>("h03"), T_1866) + node T_1870 = mux(in[2].valid, UInt<2>("h02"), T_1868) + node T_1872 = mux(in[1].valid, UInt<1>("h01"), T_1870) + node T_1874 = mux(in[0].valid, UInt<1>("h00"), T_1872) + node T_1876 = gt(UInt<3>("h07"), last_grant) + node T_1877 = and(in[7].valid, T_1876) + node T_1879 = mux(T_1877, UInt<3>("h07"), T_1874) + node T_1881 = gt(UInt<3>("h06"), last_grant) + node T_1882 = and(in[6].valid, T_1881) + node T_1884 = mux(T_1882, UInt<3>("h06"), T_1879) + node T_1886 = gt(UInt<3>("h05"), last_grant) + node T_1887 = and(in[5].valid, T_1886) + node T_1889 = mux(T_1887, UInt<3>("h05"), T_1884) + node T_1891 = gt(UInt<3>("h04"), last_grant) + node T_1892 = and(in[4].valid, T_1891) + node T_1894 = mux(T_1892, UInt<3>("h04"), T_1889) + node T_1896 = gt(UInt<2>("h03"), last_grant) + node T_1897 = and(in[3].valid, T_1896) + node T_1899 = mux(T_1897, UInt<2>("h03"), T_1894) + node T_1901 = gt(UInt<2>("h02"), last_grant) + node T_1902 = and(in[2].valid, T_1901) + node T_1904 = mux(T_1902, UInt<2>("h02"), T_1899) + node T_1906 = gt(UInt<1>("h01"), last_grant) + node T_1907 = and(in[1].valid, T_1906) + node choose = mux(T_1907, UInt<1>("h01"), T_1904) + node T_1910 = mux(T_1364, T_1366, choose) + T_1368 := T_1910 + node T_1911 = and(out.ready, out.valid) + when T_1911 : + last_grant := T_1368 + skip + + module ClientUncachedTileLinkIOArbiter : + output out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<4>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<10>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<4>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}[8] + input clock : Clock + input reset : UInt<1> + + out.grant.ready := UInt<1>("h00") + out.acquire.bits.union := UInt<1>("h00") + out.acquire.bits.a_type := UInt<1>("h00") + out.acquire.bits.is_builtin_type := UInt<1>("h00") + out.acquire.bits.data := UInt<1>("h00") + out.acquire.bits.addr_beat := UInt<1>("h00") + out.acquire.bits.client_xact_id := UInt<1>("h00") + out.acquire.bits.addr_block := UInt<1>("h00") + out.acquire.valid := UInt<1>("h00") + in[0].grant.bits.g_type := UInt<1>("h00") + in[0].grant.bits.is_builtin_type := UInt<1>("h00") + in[0].grant.bits.manager_xact_id := UInt<1>("h00") + in[0].grant.bits.client_xact_id := UInt<1>("h00") + in[0].grant.bits.data := UInt<1>("h00") + in[0].grant.bits.addr_beat := UInt<1>("h00") + in[0].grant.valid := UInt<1>("h00") + in[0].acquire.ready := UInt<1>("h00") + in[1].grant.bits.g_type := UInt<1>("h00") + in[1].grant.bits.is_builtin_type := UInt<1>("h00") + in[1].grant.bits.manager_xact_id := UInt<1>("h00") + in[1].grant.bits.client_xact_id := UInt<1>("h00") + in[1].grant.bits.data := UInt<1>("h00") + in[1].grant.bits.addr_beat := UInt<1>("h00") + in[1].grant.valid := UInt<1>("h00") + in[1].acquire.ready := UInt<1>("h00") + in[2].grant.bits.g_type := UInt<1>("h00") + in[2].grant.bits.is_builtin_type := UInt<1>("h00") + in[2].grant.bits.manager_xact_id := UInt<1>("h00") + in[2].grant.bits.client_xact_id := UInt<1>("h00") + in[2].grant.bits.data := UInt<1>("h00") + in[2].grant.bits.addr_beat := UInt<1>("h00") + in[2].grant.valid := UInt<1>("h00") + in[2].acquire.ready := UInt<1>("h00") + in[3].grant.bits.g_type := UInt<1>("h00") + in[3].grant.bits.is_builtin_type := UInt<1>("h00") + in[3].grant.bits.manager_xact_id := UInt<1>("h00") + in[3].grant.bits.client_xact_id := UInt<1>("h00") + in[3].grant.bits.data := UInt<1>("h00") + in[3].grant.bits.addr_beat := UInt<1>("h00") + in[3].grant.valid := UInt<1>("h00") + in[3].acquire.ready := UInt<1>("h00") + in[4].grant.bits.g_type := UInt<1>("h00") + in[4].grant.bits.is_builtin_type := UInt<1>("h00") + in[4].grant.bits.manager_xact_id := UInt<1>("h00") + in[4].grant.bits.client_xact_id := UInt<1>("h00") + in[4].grant.bits.data := UInt<1>("h00") + in[4].grant.bits.addr_beat := UInt<1>("h00") + in[4].grant.valid := UInt<1>("h00") + in[4].acquire.ready := UInt<1>("h00") + in[5].grant.bits.g_type := UInt<1>("h00") + in[5].grant.bits.is_builtin_type := UInt<1>("h00") + in[5].grant.bits.manager_xact_id := UInt<1>("h00") + in[5].grant.bits.client_xact_id := UInt<1>("h00") + in[5].grant.bits.data := UInt<1>("h00") + in[5].grant.bits.addr_beat := UInt<1>("h00") + in[5].grant.valid := UInt<1>("h00") + in[5].acquire.ready := UInt<1>("h00") + in[6].grant.bits.g_type := UInt<1>("h00") + in[6].grant.bits.is_builtin_type := UInt<1>("h00") + in[6].grant.bits.manager_xact_id := UInt<1>("h00") + in[6].grant.bits.client_xact_id := UInt<1>("h00") + in[6].grant.bits.data := UInt<1>("h00") + in[6].grant.bits.addr_beat := UInt<1>("h00") + in[6].grant.valid := UInt<1>("h00") + in[6].acquire.ready := UInt<1>("h00") + in[7].grant.bits.g_type := UInt<1>("h00") + in[7].grant.bits.is_builtin_type := UInt<1>("h00") + in[7].grant.bits.manager_xact_id := UInt<1>("h00") + in[7].grant.bits.client_xact_id := UInt<1>("h00") + in[7].grant.bits.data := UInt<1>("h00") + in[7].grant.bits.addr_beat := UInt<1>("h00") + in[7].grant.valid := UInt<1>("h00") + in[7].acquire.ready := UInt<1>("h00") + inst T_5875 of LockingRRArbiter_35 + T_5875.out.ready := UInt<1>("h00") + T_5875.in[0].bits.union := UInt<1>("h00") + T_5875.in[0].bits.a_type := UInt<1>("h00") + T_5875.in[0].bits.is_builtin_type := UInt<1>("h00") + T_5875.in[0].bits.data := UInt<1>("h00") + T_5875.in[0].bits.addr_beat := UInt<1>("h00") + T_5875.in[0].bits.client_xact_id := UInt<1>("h00") + T_5875.in[0].bits.addr_block := UInt<1>("h00") + T_5875.in[0].valid := UInt<1>("h00") + T_5875.in[1].bits.union := UInt<1>("h00") + T_5875.in[1].bits.a_type := UInt<1>("h00") + T_5875.in[1].bits.is_builtin_type := UInt<1>("h00") + T_5875.in[1].bits.data := UInt<1>("h00") + T_5875.in[1].bits.addr_beat := UInt<1>("h00") + T_5875.in[1].bits.client_xact_id := UInt<1>("h00") + T_5875.in[1].bits.addr_block := UInt<1>("h00") + T_5875.in[1].valid := UInt<1>("h00") + T_5875.in[2].bits.union := UInt<1>("h00") + T_5875.in[2].bits.a_type := UInt<1>("h00") + T_5875.in[2].bits.is_builtin_type := UInt<1>("h00") + T_5875.in[2].bits.data := UInt<1>("h00") + T_5875.in[2].bits.addr_beat := UInt<1>("h00") + T_5875.in[2].bits.client_xact_id := UInt<1>("h00") + T_5875.in[2].bits.addr_block := UInt<1>("h00") + T_5875.in[2].valid := UInt<1>("h00") + T_5875.in[3].bits.union := UInt<1>("h00") + T_5875.in[3].bits.a_type := UInt<1>("h00") + T_5875.in[3].bits.is_builtin_type := UInt<1>("h00") + T_5875.in[3].bits.data := UInt<1>("h00") + T_5875.in[3].bits.addr_beat := UInt<1>("h00") + T_5875.in[3].bits.client_xact_id := UInt<1>("h00") + T_5875.in[3].bits.addr_block := UInt<1>("h00") + T_5875.in[3].valid := UInt<1>("h00") + T_5875.in[4].bits.union := UInt<1>("h00") + T_5875.in[4].bits.a_type := UInt<1>("h00") + T_5875.in[4].bits.is_builtin_type := UInt<1>("h00") + T_5875.in[4].bits.data := UInt<1>("h00") + T_5875.in[4].bits.addr_beat := UInt<1>("h00") + T_5875.in[4].bits.client_xact_id := UInt<1>("h00") + T_5875.in[4].bits.addr_block := UInt<1>("h00") + T_5875.in[4].valid := UInt<1>("h00") + T_5875.in[5].bits.union := UInt<1>("h00") + T_5875.in[5].bits.a_type := UInt<1>("h00") + T_5875.in[5].bits.is_builtin_type := UInt<1>("h00") + T_5875.in[5].bits.data := UInt<1>("h00") + T_5875.in[5].bits.addr_beat := UInt<1>("h00") + T_5875.in[5].bits.client_xact_id := UInt<1>("h00") + T_5875.in[5].bits.addr_block := UInt<1>("h00") + T_5875.in[5].valid := UInt<1>("h00") + T_5875.in[6].bits.union := UInt<1>("h00") + T_5875.in[6].bits.a_type := UInt<1>("h00") + T_5875.in[6].bits.is_builtin_type := UInt<1>("h00") + T_5875.in[6].bits.data := UInt<1>("h00") + T_5875.in[6].bits.addr_beat := UInt<1>("h00") + T_5875.in[6].bits.client_xact_id := UInt<1>("h00") + T_5875.in[6].bits.addr_block := UInt<1>("h00") + T_5875.in[6].valid := UInt<1>("h00") + T_5875.in[7].bits.union := UInt<1>("h00") + T_5875.in[7].bits.a_type := UInt<1>("h00") + T_5875.in[7].bits.is_builtin_type := UInt<1>("h00") + T_5875.in[7].bits.data := UInt<1>("h00") + T_5875.in[7].bits.addr_beat := UInt<1>("h00") + T_5875.in[7].bits.client_xact_id := UInt<1>("h00") + T_5875.in[7].bits.addr_block := UInt<1>("h00") + T_5875.in[7].valid := UInt<1>("h00") + T_5875.reset := UInt<1>("h00") + T_5875.clock := clock + T_5875.reset := reset + T_5875.in[0].valid := in[0].acquire.valid + T_5875.in[0].bits <> in[0].acquire.bits + node T_5819 = cat(in[0].acquire.bits.client_xact_id, UInt<3>("h00")) + T_5875.in[0].bits.client_xact_id := T_5819 + in[0].acquire.ready := T_5875.in[0].ready + T_5875.in[1].valid := in[1].acquire.valid + T_5875.in[1].bits <> in[1].acquire.bits + node T_5821 = cat(in[1].acquire.bits.client_xact_id, UInt<3>("h01")) + T_5875.in[1].bits.client_xact_id := T_5821 + in[1].acquire.ready := T_5875.in[1].ready + T_5875.in[2].valid := in[2].acquire.valid + T_5875.in[2].bits <> in[2].acquire.bits + node T_5823 = cat(in[2].acquire.bits.client_xact_id, UInt<3>("h02")) + T_5875.in[2].bits.client_xact_id := T_5823 + in[2].acquire.ready := T_5875.in[2].ready + T_5875.in[3].valid := in[3].acquire.valid + T_5875.in[3].bits <> in[3].acquire.bits + node T_5825 = cat(in[3].acquire.bits.client_xact_id, UInt<3>("h03")) + T_5875.in[3].bits.client_xact_id := T_5825 + in[3].acquire.ready := T_5875.in[3].ready + T_5875.in[4].valid := in[4].acquire.valid + T_5875.in[4].bits <> in[4].acquire.bits + node T_5827 = cat(in[4].acquire.bits.client_xact_id, UInt<3>("h04")) + T_5875.in[4].bits.client_xact_id := T_5827 + in[4].acquire.ready := T_5875.in[4].ready + T_5875.in[5].valid := in[5].acquire.valid + T_5875.in[5].bits <> in[5].acquire.bits + node T_5829 = cat(in[5].acquire.bits.client_xact_id, UInt<3>("h05")) + T_5875.in[5].bits.client_xact_id := T_5829 + in[5].acquire.ready := T_5875.in[5].ready + T_5875.in[6].valid := in[6].acquire.valid + T_5875.in[6].bits <> in[6].acquire.bits + node T_5831 = cat(in[6].acquire.bits.client_xact_id, UInt<3>("h06")) + T_5875.in[6].bits.client_xact_id := T_5831 + in[6].acquire.ready := T_5875.in[6].ready + T_5875.in[7].valid := in[7].acquire.valid + T_5875.in[7].bits <> in[7].acquire.bits + node T_5833 = cat(in[7].acquire.bits.client_xact_id, UInt<3>("h07")) + T_5875.in[7].bits.client_xact_id := T_5833 + in[7].acquire.ready := T_5875.in[7].ready + out.acquire <> T_5875.out + out.grant.ready := UInt<1>("h00") + in[0].grant.valid := UInt<1>("h00") + node T_5836 = bits(out.grant.bits.client_xact_id, 2, 0) + node T_5838 = eq(T_5836, UInt<1>("h00")) + when T_5838 : + in[0].grant.valid := out.grant.valid + out.grant.ready := in[0].grant.ready + skip + in[0].grant.bits <> out.grant.bits + node T_5839 = shr(out.grant.bits.client_xact_id, 3) + in[0].grant.bits.client_xact_id := T_5839 + in[1].grant.valid := UInt<1>("h00") + node T_5841 = bits(out.grant.bits.client_xact_id, 2, 0) + node T_5843 = eq(T_5841, UInt<1>("h01")) + when T_5843 : + in[1].grant.valid := out.grant.valid + out.grant.ready := in[1].grant.ready + skip + in[1].grant.bits <> out.grant.bits + node T_5844 = shr(out.grant.bits.client_xact_id, 3) + in[1].grant.bits.client_xact_id := T_5844 + in[2].grant.valid := UInt<1>("h00") + node T_5846 = bits(out.grant.bits.client_xact_id, 2, 0) + node T_5848 = eq(T_5846, UInt<2>("h02")) + when T_5848 : + in[2].grant.valid := out.grant.valid + out.grant.ready := in[2].grant.ready + skip + in[2].grant.bits <> out.grant.bits + node T_5849 = shr(out.grant.bits.client_xact_id, 3) + in[2].grant.bits.client_xact_id := T_5849 + in[3].grant.valid := UInt<1>("h00") + node T_5851 = bits(out.grant.bits.client_xact_id, 2, 0) + node T_5853 = eq(T_5851, UInt<2>("h03")) + when T_5853 : + in[3].grant.valid := out.grant.valid + out.grant.ready := in[3].grant.ready + skip + in[3].grant.bits <> out.grant.bits + node T_5854 = shr(out.grant.bits.client_xact_id, 3) + in[3].grant.bits.client_xact_id := T_5854 + in[4].grant.valid := UInt<1>("h00") + node T_5856 = bits(out.grant.bits.client_xact_id, 2, 0) + node T_5858 = eq(T_5856, UInt<3>("h04")) + when T_5858 : + in[4].grant.valid := out.grant.valid + out.grant.ready := in[4].grant.ready + skip + in[4].grant.bits <> out.grant.bits + node T_5859 = shr(out.grant.bits.client_xact_id, 3) + in[4].grant.bits.client_xact_id := T_5859 + in[5].grant.valid := UInt<1>("h00") + node T_5861 = bits(out.grant.bits.client_xact_id, 2, 0) + node T_5863 = eq(T_5861, UInt<3>("h05")) + when T_5863 : + in[5].grant.valid := out.grant.valid + out.grant.ready := in[5].grant.ready + skip + in[5].grant.bits <> out.grant.bits + node T_5864 = shr(out.grant.bits.client_xact_id, 3) + in[5].grant.bits.client_xact_id := T_5864 + in[6].grant.valid := UInt<1>("h00") + node T_5866 = bits(out.grant.bits.client_xact_id, 2, 0) + node T_5868 = eq(T_5866, UInt<3>("h06")) + when T_5868 : + in[6].grant.valid := out.grant.valid + out.grant.ready := in[6].grant.ready + skip + in[6].grant.bits <> out.grant.bits + node T_5869 = shr(out.grant.bits.client_xact_id, 3) + in[6].grant.bits.client_xact_id := T_5869 + in[7].grant.valid := UInt<1>("h00") + node T_5871 = bits(out.grant.bits.client_xact_id, 2, 0) + node T_5873 = eq(T_5871, UInt<3>("h07")) + when T_5873 : + in[7].grant.valid := out.grant.valid + out.grant.ready := in[7].grant.ready + skip + in[7].grant.bits <> out.grant.bits + node T_5874 = shr(out.grant.bits.client_xact_id, 3) + in[7].grant.bits.client_xact_id := T_5874 + + module L2BroadcastHub : + output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input incoherent : UInt<1>[1] + output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}} + input clock : Clock + input reset : UInt<1> + + outer.grant.ready := UInt<1>("h00") + outer.acquire.bits.union := UInt<1>("h00") + outer.acquire.bits.a_type := UInt<1>("h00") + outer.acquire.bits.is_builtin_type := UInt<1>("h00") + outer.acquire.bits.data := UInt<1>("h00") + outer.acquire.bits.addr_beat := UInt<1>("h00") + outer.acquire.bits.client_xact_id := UInt<1>("h00") + outer.acquire.bits.addr_block := UInt<1>("h00") + outer.acquire.valid := UInt<1>("h00") + inner.release.ready := UInt<1>("h00") + inner.probe.bits.client_id := UInt<1>("h00") + inner.probe.bits.p_type := UInt<1>("h00") + inner.probe.bits.addr_block := UInt<1>("h00") + inner.probe.valid := UInt<1>("h00") + inner.finish.ready := UInt<1>("h00") + inner.grant.bits.client_id := UInt<1>("h00") + inner.grant.bits.g_type := UInt<1>("h00") + inner.grant.bits.is_builtin_type := UInt<1>("h00") + inner.grant.bits.manager_xact_id := UInt<1>("h00") + inner.grant.bits.client_xact_id := UInt<1>("h00") + inner.grant.bits.data := UInt<1>("h00") + inner.grant.bits.addr_beat := UInt<1>("h00") + inner.grant.valid := UInt<1>("h00") + inner.acquire.ready := UInt<1>("h00") + inst T_2011 of BroadcastVoluntaryReleaseTracker + T_2011.outer.grant.bits.g_type := UInt<1>("h00") + T_2011.outer.grant.bits.is_builtin_type := UInt<1>("h00") + T_2011.outer.grant.bits.manager_xact_id := UInt<1>("h00") + T_2011.outer.grant.bits.client_xact_id := UInt<1>("h00") + T_2011.outer.grant.bits.data := UInt<1>("h00") + T_2011.outer.grant.bits.addr_beat := UInt<1>("h00") + T_2011.outer.grant.valid := UInt<1>("h00") + T_2011.outer.acquire.ready := UInt<1>("h00") + T_2011.incoherent[0] := UInt<1>("h00") + T_2011.inner.release.bits.client_id := UInt<1>("h00") + T_2011.inner.release.bits.voluntary := UInt<1>("h00") + T_2011.inner.release.bits.r_type := UInt<1>("h00") + T_2011.inner.release.bits.data := UInt<1>("h00") + T_2011.inner.release.bits.addr_beat := UInt<1>("h00") + T_2011.inner.release.bits.client_xact_id := UInt<1>("h00") + T_2011.inner.release.bits.addr_block := UInt<1>("h00") + T_2011.inner.release.valid := UInt<1>("h00") + T_2011.inner.probe.ready := UInt<1>("h00") + T_2011.inner.finish.bits.manager_xact_id := UInt<1>("h00") + T_2011.inner.finish.valid := UInt<1>("h00") + T_2011.inner.grant.ready := UInt<1>("h00") + T_2011.inner.acquire.bits.client_id := UInt<1>("h00") + T_2011.inner.acquire.bits.union := UInt<1>("h00") + T_2011.inner.acquire.bits.a_type := UInt<1>("h00") + T_2011.inner.acquire.bits.is_builtin_type := UInt<1>("h00") + T_2011.inner.acquire.bits.data := UInt<1>("h00") + T_2011.inner.acquire.bits.addr_beat := UInt<1>("h00") + T_2011.inner.acquire.bits.client_xact_id := UInt<1>("h00") + T_2011.inner.acquire.bits.addr_block := UInt<1>("h00") + T_2011.inner.acquire.valid := UInt<1>("h00") + T_2011.reset := UInt<1>("h00") + T_2011.clock := clock + T_2011.reset := reset + inst T_2012 of BroadcastAcquireTracker + T_2012.outer.grant.bits.g_type := UInt<1>("h00") + T_2012.outer.grant.bits.is_builtin_type := UInt<1>("h00") + T_2012.outer.grant.bits.manager_xact_id := UInt<1>("h00") + T_2012.outer.grant.bits.client_xact_id := UInt<1>("h00") + T_2012.outer.grant.bits.data := UInt<1>("h00") + T_2012.outer.grant.bits.addr_beat := UInt<1>("h00") + T_2012.outer.grant.valid := UInt<1>("h00") + T_2012.outer.acquire.ready := UInt<1>("h00") + T_2012.incoherent[0] := UInt<1>("h00") + T_2012.inner.release.bits.client_id := UInt<1>("h00") + T_2012.inner.release.bits.voluntary := UInt<1>("h00") + T_2012.inner.release.bits.r_type := UInt<1>("h00") + T_2012.inner.release.bits.data := UInt<1>("h00") + T_2012.inner.release.bits.addr_beat := UInt<1>("h00") + T_2012.inner.release.bits.client_xact_id := UInt<1>("h00") + T_2012.inner.release.bits.addr_block := UInt<1>("h00") + T_2012.inner.release.valid := UInt<1>("h00") + T_2012.inner.probe.ready := UInt<1>("h00") + T_2012.inner.finish.bits.manager_xact_id := UInt<1>("h00") + T_2012.inner.finish.valid := UInt<1>("h00") + T_2012.inner.grant.ready := UInt<1>("h00") + T_2012.inner.acquire.bits.client_id := UInt<1>("h00") + T_2012.inner.acquire.bits.union := UInt<1>("h00") + T_2012.inner.acquire.bits.a_type := UInt<1>("h00") + T_2012.inner.acquire.bits.is_builtin_type := UInt<1>("h00") + T_2012.inner.acquire.bits.data := UInt<1>("h00") + T_2012.inner.acquire.bits.addr_beat := UInt<1>("h00") + T_2012.inner.acquire.bits.client_xact_id := UInt<1>("h00") + T_2012.inner.acquire.bits.addr_block := UInt<1>("h00") + T_2012.inner.acquire.valid := UInt<1>("h00") + T_2012.reset := UInt<1>("h00") + T_2012.clock := clock + T_2012.reset := reset + inst T_2013 of BroadcastAcquireTracker_27 + T_2013.outer.grant.bits.g_type := UInt<1>("h00") + T_2013.outer.grant.bits.is_builtin_type := UInt<1>("h00") + T_2013.outer.grant.bits.manager_xact_id := UInt<1>("h00") + T_2013.outer.grant.bits.client_xact_id := UInt<1>("h00") + T_2013.outer.grant.bits.data := UInt<1>("h00") + T_2013.outer.grant.bits.addr_beat := UInt<1>("h00") + T_2013.outer.grant.valid := UInt<1>("h00") + T_2013.outer.acquire.ready := UInt<1>("h00") + T_2013.incoherent[0] := UInt<1>("h00") + T_2013.inner.release.bits.client_id := UInt<1>("h00") + T_2013.inner.release.bits.voluntary := UInt<1>("h00") + T_2013.inner.release.bits.r_type := UInt<1>("h00") + T_2013.inner.release.bits.data := UInt<1>("h00") + T_2013.inner.release.bits.addr_beat := UInt<1>("h00") + T_2013.inner.release.bits.client_xact_id := UInt<1>("h00") + T_2013.inner.release.bits.addr_block := UInt<1>("h00") + T_2013.inner.release.valid := UInt<1>("h00") + T_2013.inner.probe.ready := UInt<1>("h00") + T_2013.inner.finish.bits.manager_xact_id := UInt<1>("h00") + T_2013.inner.finish.valid := UInt<1>("h00") + T_2013.inner.grant.ready := UInt<1>("h00") + T_2013.inner.acquire.bits.client_id := UInt<1>("h00") + T_2013.inner.acquire.bits.union := UInt<1>("h00") + T_2013.inner.acquire.bits.a_type := UInt<1>("h00") + T_2013.inner.acquire.bits.is_builtin_type := UInt<1>("h00") + T_2013.inner.acquire.bits.data := UInt<1>("h00") + T_2013.inner.acquire.bits.addr_beat := UInt<1>("h00") + T_2013.inner.acquire.bits.client_xact_id := UInt<1>("h00") + T_2013.inner.acquire.bits.addr_block := UInt<1>("h00") + T_2013.inner.acquire.valid := UInt<1>("h00") + T_2013.reset := UInt<1>("h00") + T_2013.clock := clock + T_2013.reset := reset + inst T_2014 of BroadcastAcquireTracker_28 + T_2014.outer.grant.bits.g_type := UInt<1>("h00") + T_2014.outer.grant.bits.is_builtin_type := UInt<1>("h00") + T_2014.outer.grant.bits.manager_xact_id := UInt<1>("h00") + T_2014.outer.grant.bits.client_xact_id := UInt<1>("h00") + T_2014.outer.grant.bits.data := UInt<1>("h00") + T_2014.outer.grant.bits.addr_beat := UInt<1>("h00") + T_2014.outer.grant.valid := UInt<1>("h00") + T_2014.outer.acquire.ready := UInt<1>("h00") + T_2014.incoherent[0] := UInt<1>("h00") + T_2014.inner.release.bits.client_id := UInt<1>("h00") + T_2014.inner.release.bits.voluntary := UInt<1>("h00") + T_2014.inner.release.bits.r_type := UInt<1>("h00") + T_2014.inner.release.bits.data := UInt<1>("h00") + T_2014.inner.release.bits.addr_beat := UInt<1>("h00") + T_2014.inner.release.bits.client_xact_id := UInt<1>("h00") + T_2014.inner.release.bits.addr_block := UInt<1>("h00") + T_2014.inner.release.valid := UInt<1>("h00") + T_2014.inner.probe.ready := UInt<1>("h00") + T_2014.inner.finish.bits.manager_xact_id := UInt<1>("h00") + T_2014.inner.finish.valid := UInt<1>("h00") + T_2014.inner.grant.ready := UInt<1>("h00") + T_2014.inner.acquire.bits.client_id := UInt<1>("h00") + T_2014.inner.acquire.bits.union := UInt<1>("h00") + T_2014.inner.acquire.bits.a_type := UInt<1>("h00") + T_2014.inner.acquire.bits.is_builtin_type := UInt<1>("h00") + T_2014.inner.acquire.bits.data := UInt<1>("h00") + T_2014.inner.acquire.bits.addr_beat := UInt<1>("h00") + T_2014.inner.acquire.bits.client_xact_id := UInt<1>("h00") + T_2014.inner.acquire.bits.addr_block := UInt<1>("h00") + T_2014.inner.acquire.valid := UInt<1>("h00") + T_2014.reset := UInt<1>("h00") + T_2014.clock := clock + T_2014.reset := reset + inst T_2015 of BroadcastAcquireTracker_29 + T_2015.outer.grant.bits.g_type := UInt<1>("h00") + T_2015.outer.grant.bits.is_builtin_type := UInt<1>("h00") + T_2015.outer.grant.bits.manager_xact_id := UInt<1>("h00") + T_2015.outer.grant.bits.client_xact_id := UInt<1>("h00") + T_2015.outer.grant.bits.data := UInt<1>("h00") + T_2015.outer.grant.bits.addr_beat := UInt<1>("h00") + T_2015.outer.grant.valid := UInt<1>("h00") + T_2015.outer.acquire.ready := UInt<1>("h00") + T_2015.incoherent[0] := UInt<1>("h00") + T_2015.inner.release.bits.client_id := UInt<1>("h00") + T_2015.inner.release.bits.voluntary := UInt<1>("h00") + T_2015.inner.release.bits.r_type := UInt<1>("h00") + T_2015.inner.release.bits.data := UInt<1>("h00") + T_2015.inner.release.bits.addr_beat := UInt<1>("h00") + T_2015.inner.release.bits.client_xact_id := UInt<1>("h00") + T_2015.inner.release.bits.addr_block := UInt<1>("h00") + T_2015.inner.release.valid := UInt<1>("h00") + T_2015.inner.probe.ready := UInt<1>("h00") + T_2015.inner.finish.bits.manager_xact_id := UInt<1>("h00") + T_2015.inner.finish.valid := UInt<1>("h00") + T_2015.inner.grant.ready := UInt<1>("h00") + T_2015.inner.acquire.bits.client_id := UInt<1>("h00") + T_2015.inner.acquire.bits.union := UInt<1>("h00") + T_2015.inner.acquire.bits.a_type := UInt<1>("h00") + T_2015.inner.acquire.bits.is_builtin_type := UInt<1>("h00") + T_2015.inner.acquire.bits.data := UInt<1>("h00") + T_2015.inner.acquire.bits.addr_beat := UInt<1>("h00") + T_2015.inner.acquire.bits.client_xact_id := UInt<1>("h00") + T_2015.inner.acquire.bits.addr_block := UInt<1>("h00") + T_2015.inner.acquire.valid := UInt<1>("h00") + T_2015.reset := UInt<1>("h00") + T_2015.clock := clock + T_2015.reset := reset + inst T_2016 of BroadcastAcquireTracker_30 + T_2016.outer.grant.bits.g_type := UInt<1>("h00") + T_2016.outer.grant.bits.is_builtin_type := UInt<1>("h00") + T_2016.outer.grant.bits.manager_xact_id := UInt<1>("h00") + T_2016.outer.grant.bits.client_xact_id := UInt<1>("h00") + T_2016.outer.grant.bits.data := UInt<1>("h00") + T_2016.outer.grant.bits.addr_beat := UInt<1>("h00") + T_2016.outer.grant.valid := UInt<1>("h00") + T_2016.outer.acquire.ready := UInt<1>("h00") + T_2016.incoherent[0] := UInt<1>("h00") + T_2016.inner.release.bits.client_id := UInt<1>("h00") + T_2016.inner.release.bits.voluntary := UInt<1>("h00") + T_2016.inner.release.bits.r_type := UInt<1>("h00") + T_2016.inner.release.bits.data := UInt<1>("h00") + T_2016.inner.release.bits.addr_beat := UInt<1>("h00") + T_2016.inner.release.bits.client_xact_id := UInt<1>("h00") + T_2016.inner.release.bits.addr_block := UInt<1>("h00") + T_2016.inner.release.valid := UInt<1>("h00") + T_2016.inner.probe.ready := UInt<1>("h00") + T_2016.inner.finish.bits.manager_xact_id := UInt<1>("h00") + T_2016.inner.finish.valid := UInt<1>("h00") + T_2016.inner.grant.ready := UInt<1>("h00") + T_2016.inner.acquire.bits.client_id := UInt<1>("h00") + T_2016.inner.acquire.bits.union := UInt<1>("h00") + T_2016.inner.acquire.bits.a_type := UInt<1>("h00") + T_2016.inner.acquire.bits.is_builtin_type := UInt<1>("h00") + T_2016.inner.acquire.bits.data := UInt<1>("h00") + T_2016.inner.acquire.bits.addr_beat := UInt<1>("h00") + T_2016.inner.acquire.bits.client_xact_id := UInt<1>("h00") + T_2016.inner.acquire.bits.addr_block := UInt<1>("h00") + T_2016.inner.acquire.valid := UInt<1>("h00") + T_2016.reset := UInt<1>("h00") + T_2016.clock := clock + T_2016.reset := reset + inst T_2017 of BroadcastAcquireTracker_31 + T_2017.outer.grant.bits.g_type := UInt<1>("h00") + T_2017.outer.grant.bits.is_builtin_type := UInt<1>("h00") + T_2017.outer.grant.bits.manager_xact_id := UInt<1>("h00") + T_2017.outer.grant.bits.client_xact_id := UInt<1>("h00") + T_2017.outer.grant.bits.data := UInt<1>("h00") + T_2017.outer.grant.bits.addr_beat := UInt<1>("h00") + T_2017.outer.grant.valid := UInt<1>("h00") + T_2017.outer.acquire.ready := UInt<1>("h00") + T_2017.incoherent[0] := UInt<1>("h00") + T_2017.inner.release.bits.client_id := UInt<1>("h00") + T_2017.inner.release.bits.voluntary := UInt<1>("h00") + T_2017.inner.release.bits.r_type := UInt<1>("h00") + T_2017.inner.release.bits.data := UInt<1>("h00") + T_2017.inner.release.bits.addr_beat := UInt<1>("h00") + T_2017.inner.release.bits.client_xact_id := UInt<1>("h00") + T_2017.inner.release.bits.addr_block := UInt<1>("h00") + T_2017.inner.release.valid := UInt<1>("h00") + T_2017.inner.probe.ready := UInt<1>("h00") + T_2017.inner.finish.bits.manager_xact_id := UInt<1>("h00") + T_2017.inner.finish.valid := UInt<1>("h00") + T_2017.inner.grant.ready := UInt<1>("h00") + T_2017.inner.acquire.bits.client_id := UInt<1>("h00") + T_2017.inner.acquire.bits.union := UInt<1>("h00") + T_2017.inner.acquire.bits.a_type := UInt<1>("h00") + T_2017.inner.acquire.bits.is_builtin_type := UInt<1>("h00") + T_2017.inner.acquire.bits.data := UInt<1>("h00") + T_2017.inner.acquire.bits.addr_beat := UInt<1>("h00") + T_2017.inner.acquire.bits.client_xact_id := UInt<1>("h00") + T_2017.inner.acquire.bits.addr_block := UInt<1>("h00") + T_2017.inner.acquire.valid := UInt<1>("h00") + T_2017.reset := UInt<1>("h00") + T_2017.clock := clock + T_2017.reset := reset + inst T_2018 of BroadcastAcquireTracker_32 + T_2018.outer.grant.bits.g_type := UInt<1>("h00") + T_2018.outer.grant.bits.is_builtin_type := UInt<1>("h00") + T_2018.outer.grant.bits.manager_xact_id := UInt<1>("h00") + T_2018.outer.grant.bits.client_xact_id := UInt<1>("h00") + T_2018.outer.grant.bits.data := UInt<1>("h00") + T_2018.outer.grant.bits.addr_beat := UInt<1>("h00") + T_2018.outer.grant.valid := UInt<1>("h00") + T_2018.outer.acquire.ready := UInt<1>("h00") + T_2018.incoherent[0] := UInt<1>("h00") + T_2018.inner.release.bits.client_id := UInt<1>("h00") + T_2018.inner.release.bits.voluntary := UInt<1>("h00") + T_2018.inner.release.bits.r_type := UInt<1>("h00") + T_2018.inner.release.bits.data := UInt<1>("h00") + T_2018.inner.release.bits.addr_beat := UInt<1>("h00") + T_2018.inner.release.bits.client_xact_id := UInt<1>("h00") + T_2018.inner.release.bits.addr_block := UInt<1>("h00") + T_2018.inner.release.valid := UInt<1>("h00") + T_2018.inner.probe.ready := UInt<1>("h00") + T_2018.inner.finish.bits.manager_xact_id := UInt<1>("h00") + T_2018.inner.finish.valid := UInt<1>("h00") + T_2018.inner.grant.ready := UInt<1>("h00") + T_2018.inner.acquire.bits.client_id := UInt<1>("h00") + T_2018.inner.acquire.bits.union := UInt<1>("h00") + T_2018.inner.acquire.bits.a_type := UInt<1>("h00") + T_2018.inner.acquire.bits.is_builtin_type := UInt<1>("h00") + T_2018.inner.acquire.bits.data := UInt<1>("h00") + T_2018.inner.acquire.bits.addr_beat := UInt<1>("h00") + T_2018.inner.acquire.bits.client_xact_id := UInt<1>("h00") + T_2018.inner.acquire.bits.addr_block := UInt<1>("h00") + T_2018.inner.acquire.valid := UInt<1>("h00") + T_2018.reset := UInt<1>("h00") + T_2018.clock := clock + T_2018.reset := reset + T_2011.incoherent := incoherent + T_2012.incoherent := incoherent + T_2013.incoherent := incoherent + T_2014.incoherent := incoherent + T_2015.incoherent := incoherent + T_2016.incoherent := incoherent + T_2017.incoherent := incoherent + T_2018.incoherent := incoherent + reg sdq : UInt<128>[4], clock, reset + reg sdq_val : UInt<4>, clock, reset + onreset sdq_val := UInt<4>("h00") + node T_1196 = not(sdq_val) + node T_1197 = bit(T_1196, 0) + node T_1198 = bit(T_1196, 1) + node T_1199 = bit(T_1196, 2) + node T_1200 = bit(T_1196, 3) + wire T_1202 : UInt<1>[4] + T_1202[0] := T_1197 + T_1202[1] := T_1198 + T_1202[2] := T_1199 + T_1202[3] := T_1200 + node T_1212 = mux(T_1202[2], UInt<2>("h02"), UInt<2>("h03")) + node T_1213 = mux(T_1202[1], UInt<1>("h01"), T_1212) + node sdq_alloc_id = mux(T_1202[0], UInt<1>("h00"), T_1213) + node T_1215 = not(sdq_val) + node T_1217 = eq(T_1215, UInt<1>("h00")) + node sdq_rdy = eq(T_1217, UInt<1>("h00")) + node T_1220 = and(inner.acquire.ready, inner.acquire.valid) + wire T_1225 : UInt<3>[3] + T_1225[0] := UInt<3>("h02") + T_1225[1] := UInt<3>("h03") + T_1225[2] := UInt<3>("h04") + node T_1230 = eq(T_1225[0], inner.acquire.bits.a_type) + node T_1231 = eq(T_1225[1], inner.acquire.bits.a_type) + node T_1232 = eq(T_1225[2], inner.acquire.bits.a_type) + node T_1234 = or(UInt<1>("h00"), T_1230) + node T_1235 = or(T_1234, T_1231) + node T_1236 = or(T_1235, T_1232) + node T_1237 = and(inner.acquire.bits.is_builtin_type, T_1236) + node sdq_enq = and(T_1220, T_1237) + when sdq_enq : + infer accessor T_1239 = sdq[sdq_alloc_id] + T_1239 := inner.acquire.bits.data + skip + wire T_1241 : UInt<1>[8] + T_1241[0] := T_2011.has_acquire_conflict + T_1241[1] := T_2012.has_acquire_conflict + T_1241[2] := T_2013.has_acquire_conflict + T_1241[3] := T_2014.has_acquire_conflict + T_1241[4] := T_2015.has_acquire_conflict + T_1241[5] := T_2016.has_acquire_conflict + T_1241[6] := T_2017.has_acquire_conflict + T_1241[7] := T_2018.has_acquire_conflict + node T_1251 = cat(T_1241[7], T_1241[6]) + node T_1252 = cat(T_1241[5], T_1241[4]) + node T_1253 = cat(T_1251, T_1252) + node T_1254 = cat(T_1241[3], T_1241[2]) + node T_1255 = cat(T_1241[1], T_1241[0]) + node T_1256 = cat(T_1254, T_1255) + node acquireConflicts = cat(T_1253, T_1256) + wire T_1259 : UInt<1>[8] + T_1259[0] := T_2011.has_acquire_match + T_1259[1] := T_2012.has_acquire_match + T_1259[2] := T_2013.has_acquire_match + T_1259[3] := T_2014.has_acquire_match + T_1259[4] := T_2015.has_acquire_match + T_1259[5] := T_2016.has_acquire_match + T_1259[6] := T_2017.has_acquire_match + T_1259[7] := T_2018.has_acquire_match + node T_1269 = cat(T_1259[7], T_1259[6]) + node T_1270 = cat(T_1259[5], T_1259[4]) + node T_1271 = cat(T_1269, T_1270) + node T_1272 = cat(T_1259[3], T_1259[2]) + node T_1273 = cat(T_1259[1], T_1259[0]) + node T_1274 = cat(T_1272, T_1273) + node acquireMatches = cat(T_1271, T_1274) + wire T_1277 : UInt<1>[8] + T_1277[0] := T_2011.inner.acquire.ready + T_1277[1] := T_2012.inner.acquire.ready + T_1277[2] := T_2013.inner.acquire.ready + T_1277[3] := T_2014.inner.acquire.ready + T_1277[4] := T_2015.inner.acquire.ready + T_1277[5] := T_2016.inner.acquire.ready + T_1277[6] := T_2017.inner.acquire.ready + T_1277[7] := T_2018.inner.acquire.ready + node T_1287 = cat(T_1277[7], T_1277[6]) + node T_1288 = cat(T_1277[5], T_1277[4]) + node T_1289 = cat(T_1287, T_1288) + node T_1290 = cat(T_1277[3], T_1277[2]) + node T_1291 = cat(T_1277[1], T_1277[0]) + node T_1292 = cat(T_1290, T_1291) + node acquireReadys = cat(T_1289, T_1292) + node T_1295 = neq(acquireMatches, UInt<1>("h00")) + node T_1296 = bit(acquireMatches, 0) + node T_1297 = bit(acquireMatches, 1) + node T_1298 = bit(acquireMatches, 2) + node T_1299 = bit(acquireMatches, 3) + node T_1300 = bit(acquireMatches, 4) + node T_1301 = bit(acquireMatches, 5) + node T_1302 = bit(acquireMatches, 6) + node T_1303 = bit(acquireMatches, 7) + wire T_1305 : UInt<1>[8] + T_1305[0] := T_1296 + T_1305[1] := T_1297 + T_1305[2] := T_1298 + T_1305[3] := T_1299 + T_1305[4] := T_1300 + T_1305[5] := T_1301 + T_1305[6] := T_1302 + T_1305[7] := T_1303 + node T_1323 = mux(T_1305[6], UInt<3>("h06"), UInt<3>("h07")) + node T_1324 = mux(T_1305[5], UInt<3>("h05"), T_1323) + node T_1325 = mux(T_1305[4], UInt<3>("h04"), T_1324) + node T_1326 = mux(T_1305[3], UInt<2>("h03"), T_1325) + node T_1327 = mux(T_1305[2], UInt<2>("h02"), T_1326) + node T_1328 = mux(T_1305[1], UInt<1>("h01"), T_1327) + node T_1329 = mux(T_1305[0], UInt<1>("h00"), T_1328) + node T_1330 = bit(acquireReadys, 0) + node T_1331 = bit(acquireReadys, 1) + node T_1332 = bit(acquireReadys, 2) + node T_1333 = bit(acquireReadys, 3) + node T_1334 = bit(acquireReadys, 4) + node T_1335 = bit(acquireReadys, 5) + node T_1336 = bit(acquireReadys, 6) + node T_1337 = bit(acquireReadys, 7) + wire T_1339 : UInt<1>[8] + T_1339[0] := T_1330 + T_1339[1] := T_1331 + T_1339[2] := T_1332 + T_1339[3] := T_1333 + T_1339[4] := T_1334 + T_1339[5] := T_1335 + T_1339[6] := T_1336 + T_1339[7] := T_1337 + node T_1357 = mux(T_1339[6], UInt<3>("h06"), UInt<3>("h07")) + node T_1358 = mux(T_1339[5], UInt<3>("h05"), T_1357) + node T_1359 = mux(T_1339[4], UInt<3>("h04"), T_1358) + node T_1360 = mux(T_1339[3], UInt<2>("h03"), T_1359) + node T_1361 = mux(T_1339[2], UInt<2>("h02"), T_1360) + node T_1362 = mux(T_1339[1], UInt<1>("h01"), T_1361) + node T_1363 = mux(T_1339[0], UInt<1>("h00"), T_1362) + node acquire_idx = mux(T_1295, T_1329, T_1363) + node T_1366 = neq(acquireConflicts, UInt<1>("h00")) + node T_1368 = eq(sdq_rdy, UInt<1>("h00")) + node block_acquires = or(T_1366, T_1368) + node T_1371 = neq(acquireReadys, UInt<1>("h00")) + node T_1373 = eq(block_acquires, UInt<1>("h00")) + node T_1374 = and(T_1371, T_1373) + inner.acquire.ready := T_1374 + T_2011.inner.acquire.bits <> inner.acquire.bits + wire T_1378 : {idx : UInt<2>, loc : UInt<2>} + T_1378.loc := UInt<1>("h00") + T_1378.idx := UInt<1>("h00") + T_1378.idx := sdq_alloc_id + T_1378.loc := UInt<1>("h00") + node T_1383 = cat(T_1378.idx, T_1378.loc) + T_2011.inner.acquire.bits.data := T_1383 + node T_1385 = eq(block_acquires, UInt<1>("h00")) + node T_1386 = and(inner.acquire.valid, T_1385) + node T_1388 = eq(acquire_idx, UInt<1>("h00")) + node T_1389 = and(T_1386, T_1388) + T_2011.inner.acquire.valid := T_1389 + T_2012.inner.acquire.bits <> inner.acquire.bits + wire T_1393 : {idx : UInt<2>, loc : UInt<2>} + T_1393.loc := UInt<1>("h00") + T_1393.idx := UInt<1>("h00") + T_1393.idx := sdq_alloc_id + T_1393.loc := UInt<1>("h00") + node T_1398 = cat(T_1393.idx, T_1393.loc) + T_2012.inner.acquire.bits.data := T_1398 + node T_1400 = eq(block_acquires, UInt<1>("h00")) + node T_1401 = and(inner.acquire.valid, T_1400) + node T_1403 = eq(acquire_idx, UInt<1>("h01")) + node T_1404 = and(T_1401, T_1403) + T_2012.inner.acquire.valid := T_1404 + T_2013.inner.acquire.bits <> inner.acquire.bits + wire T_1408 : {idx : UInt<2>, loc : UInt<2>} + T_1408.loc := UInt<1>("h00") + T_1408.idx := UInt<1>("h00") + T_1408.idx := sdq_alloc_id + T_1408.loc := UInt<1>("h00") + node T_1413 = cat(T_1408.idx, T_1408.loc) + T_2013.inner.acquire.bits.data := T_1413 + node T_1415 = eq(block_acquires, UInt<1>("h00")) + node T_1416 = and(inner.acquire.valid, T_1415) + node T_1418 = eq(acquire_idx, UInt<2>("h02")) + node T_1419 = and(T_1416, T_1418) + T_2013.inner.acquire.valid := T_1419 + T_2014.inner.acquire.bits <> inner.acquire.bits + wire T_1423 : {idx : UInt<2>, loc : UInt<2>} + T_1423.loc := UInt<1>("h00") + T_1423.idx := UInt<1>("h00") + T_1423.idx := sdq_alloc_id + T_1423.loc := UInt<1>("h00") + node T_1428 = cat(T_1423.idx, T_1423.loc) + T_2014.inner.acquire.bits.data := T_1428 + node T_1430 = eq(block_acquires, UInt<1>("h00")) + node T_1431 = and(inner.acquire.valid, T_1430) + node T_1433 = eq(acquire_idx, UInt<2>("h03")) + node T_1434 = and(T_1431, T_1433) + T_2014.inner.acquire.valid := T_1434 + T_2015.inner.acquire.bits <> inner.acquire.bits + wire T_1438 : {idx : UInt<2>, loc : UInt<2>} + T_1438.loc := UInt<1>("h00") + T_1438.idx := UInt<1>("h00") + T_1438.idx := sdq_alloc_id + T_1438.loc := UInt<1>("h00") + node T_1443 = cat(T_1438.idx, T_1438.loc) + T_2015.inner.acquire.bits.data := T_1443 + node T_1445 = eq(block_acquires, UInt<1>("h00")) + node T_1446 = and(inner.acquire.valid, T_1445) + node T_1448 = eq(acquire_idx, UInt<3>("h04")) + node T_1449 = and(T_1446, T_1448) + T_2015.inner.acquire.valid := T_1449 + T_2016.inner.acquire.bits <> inner.acquire.bits + wire T_1453 : {idx : UInt<2>, loc : UInt<2>} + T_1453.loc := UInt<1>("h00") + T_1453.idx := UInt<1>("h00") + T_1453.idx := sdq_alloc_id + T_1453.loc := UInt<1>("h00") + node T_1458 = cat(T_1453.idx, T_1453.loc) + T_2016.inner.acquire.bits.data := T_1458 + node T_1460 = eq(block_acquires, UInt<1>("h00")) + node T_1461 = and(inner.acquire.valid, T_1460) + node T_1463 = eq(acquire_idx, UInt<3>("h05")) + node T_1464 = and(T_1461, T_1463) + T_2016.inner.acquire.valid := T_1464 + T_2017.inner.acquire.bits <> inner.acquire.bits + wire T_1468 : {idx : UInt<2>, loc : UInt<2>} + T_1468.loc := UInt<1>("h00") + T_1468.idx := UInt<1>("h00") + T_1468.idx := sdq_alloc_id + T_1468.loc := UInt<1>("h00") + node T_1473 = cat(T_1468.idx, T_1468.loc) + T_2017.inner.acquire.bits.data := T_1473 + node T_1475 = eq(block_acquires, UInt<1>("h00")) + node T_1476 = and(inner.acquire.valid, T_1475) + node T_1478 = eq(acquire_idx, UInt<3>("h06")) + node T_1479 = and(T_1476, T_1478) + T_2017.inner.acquire.valid := T_1479 + T_2018.inner.acquire.bits <> inner.acquire.bits + wire T_1483 : {idx : UInt<2>, loc : UInt<2>} + T_1483.loc := UInt<1>("h00") + T_1483.idx := UInt<1>("h00") + T_1483.idx := sdq_alloc_id + T_1483.loc := UInt<1>("h00") + node T_1488 = cat(T_1483.idx, T_1483.loc) + T_2018.inner.acquire.bits.data := T_1488 + node T_1490 = eq(block_acquires, UInt<1>("h00")) + node T_1491 = and(inner.acquire.valid, T_1490) + node T_1493 = eq(acquire_idx, UInt<3>("h07")) + node T_1494 = and(T_1491, T_1493) + T_2018.inner.acquire.valid := T_1494 + node T_1495 = and(inner.release.ready, inner.release.valid) + node T_1496 = and(T_1495, inner.release.bits.voluntary) + wire T_1498 : UInt<2>[3] + T_1498[0] := UInt<1>("h00") + T_1498[1] := UInt<1>("h01") + T_1498[2] := UInt<2>("h02") + node T_1503 = eq(T_1498[0], inner.release.bits.r_type) + node T_1504 = eq(T_1498[1], inner.release.bits.r_type) + node T_1505 = eq(T_1498[2], inner.release.bits.r_type) + node T_1507 = or(UInt<1>("h00"), T_1503) + node T_1508 = or(T_1507, T_1504) + node T_1509 = or(T_1508, T_1505) + node vwbdq_enq = and(T_1496, T_1509) + reg rel_data_cnt : UInt<2>, clock, reset + onreset rel_data_cnt := UInt<2>("h00") + when vwbdq_enq : + node T_1514 = eq(rel_data_cnt, UInt<2>("h03")) + node T_1516 = and(UInt<1>("h00"), T_1514) + node T_1519 = addw(rel_data_cnt, UInt<1>("h01")) + node T_1520 = mux(T_1516, UInt<1>("h00"), T_1519) + rel_data_cnt := T_1520 + skip + node rel_data_done = and(vwbdq_enq, T_1514) + reg vwbdq : UInt<128>[4], clock, reset + when vwbdq_enq : + infer accessor T_1537 = vwbdq[rel_data_cnt] + T_1537 := inner.release.bits.data + skip + wire T_1539 : UInt<1>[8] + T_1539[0] := T_2011.inner.release.ready + T_1539[1] := T_2012.inner.release.ready + T_1539[2] := T_2013.inner.release.ready + T_1539[3] := T_2014.inner.release.ready + T_1539[4] := T_2015.inner.release.ready + T_1539[5] := T_2016.inner.release.ready + T_1539[6] := T_2017.inner.release.ready + T_1539[7] := T_2018.inner.release.ready + node T_1549 = cat(T_1539[7], T_1539[6]) + node T_1550 = cat(T_1539[5], T_1539[4]) + node T_1551 = cat(T_1549, T_1550) + node T_1552 = cat(T_1539[3], T_1539[2]) + node T_1553 = cat(T_1539[1], T_1539[0]) + node T_1554 = cat(T_1552, T_1553) + node releaseReadys = cat(T_1551, T_1554) + wire T_1557 : UInt<1>[8] + T_1557[0] := T_2011.has_release_match + T_1557[1] := T_2012.has_release_match + T_1557[2] := T_2013.has_release_match + T_1557[3] := T_2014.has_release_match + T_1557[4] := T_2015.has_release_match + T_1557[5] := T_2016.has_release_match + T_1557[6] := T_2017.has_release_match + T_1557[7] := T_2018.has_release_match + node T_1567 = cat(T_1557[7], T_1557[6]) + node T_1568 = cat(T_1557[5], T_1557[4]) + node T_1569 = cat(T_1567, T_1568) + node T_1570 = cat(T_1557[3], T_1557[2]) + node T_1571 = cat(T_1557[1], T_1557[0]) + node T_1572 = cat(T_1570, T_1571) + node releaseMatches = cat(T_1569, T_1572) + node T_1574 = bit(releaseMatches, 0) + node T_1575 = bit(releaseMatches, 1) + node T_1576 = bit(releaseMatches, 2) + node T_1577 = bit(releaseMatches, 3) + node T_1578 = bit(releaseMatches, 4) + node T_1579 = bit(releaseMatches, 5) + node T_1580 = bit(releaseMatches, 6) + node T_1581 = bit(releaseMatches, 7) + wire T_1583 : UInt<1>[8] + T_1583[0] := T_1574 + T_1583[1] := T_1575 + T_1583[2] := T_1576 + T_1583[3] := T_1577 + T_1583[4] := T_1578 + T_1583[5] := T_1579 + T_1583[6] := T_1580 + T_1583[7] := T_1581 + node T_1601 = mux(T_1583[6], UInt<3>("h06"), UInt<3>("h07")) + node T_1602 = mux(T_1583[5], UInt<3>("h05"), T_1601) + node T_1603 = mux(T_1583[4], UInt<3>("h04"), T_1602) + node T_1604 = mux(T_1583[3], UInt<2>("h03"), T_1603) + node T_1605 = mux(T_1583[2], UInt<2>("h02"), T_1604) + node T_1606 = mux(T_1583[1], UInt<1>("h01"), T_1605) + node release_idx = mux(T_1583[0], UInt<1>("h00"), T_1606) + node T_1608 = dshr(releaseReadys, release_idx) + node T_1609 = bit(T_1608, 0) + inner.release.ready := T_1609 + node T_1611 = eq(release_idx, UInt<1>("h00")) + node T_1612 = and(inner.release.valid, T_1611) + T_2011.inner.release.valid := T_1612 + T_2011.inner.release.bits <> inner.release.bits + wire T_1616 : {idx : UInt<2>, loc : UInt<2>} + T_1616.loc := UInt<1>("h00") + T_1616.idx := UInt<1>("h00") + T_1616.idx := rel_data_cnt + T_1616.loc := UInt<1>("h01") + node T_1621 = cat(T_1616.idx, T_1616.loc) + T_2011.inner.release.bits.data := T_1621 + node T_1623 = eq(release_idx, UInt<1>("h01")) + node T_1624 = and(inner.release.valid, T_1623) + T_2012.inner.release.valid := T_1624 + T_2012.inner.release.bits <> inner.release.bits + wire T_1628 : {idx : UInt<2>, loc : UInt<2>} + T_1628.loc := UInt<1>("h00") + T_1628.idx := UInt<1>("h00") + T_1628.idx := rel_data_cnt + T_1628.loc := UInt<2>("h02") + node T_1633 = cat(T_1628.idx, T_1628.loc) + T_2012.inner.release.bits.data := T_1633 + node T_1635 = eq(release_idx, UInt<2>("h02")) + node T_1636 = and(inner.release.valid, T_1635) + T_2013.inner.release.valid := T_1636 + T_2013.inner.release.bits <> inner.release.bits + wire T_1640 : {idx : UInt<2>, loc : UInt<2>} + T_1640.loc := UInt<1>("h00") + T_1640.idx := UInt<1>("h00") + T_1640.idx := rel_data_cnt + T_1640.loc := UInt<2>("h02") + node T_1645 = cat(T_1640.idx, T_1640.loc) + T_2013.inner.release.bits.data := T_1645 + node T_1647 = eq(release_idx, UInt<2>("h03")) + node T_1648 = and(inner.release.valid, T_1647) + T_2014.inner.release.valid := T_1648 + T_2014.inner.release.bits <> inner.release.bits + wire T_1652 : {idx : UInt<2>, loc : UInt<2>} + T_1652.loc := UInt<1>("h00") + T_1652.idx := UInt<1>("h00") + T_1652.idx := rel_data_cnt + T_1652.loc := UInt<2>("h02") + node T_1657 = cat(T_1652.idx, T_1652.loc) + T_2014.inner.release.bits.data := T_1657 + node T_1659 = eq(release_idx, UInt<3>("h04")) + node T_1660 = and(inner.release.valid, T_1659) + T_2015.inner.release.valid := T_1660 + T_2015.inner.release.bits <> inner.release.bits + wire T_1664 : {idx : UInt<2>, loc : UInt<2>} + T_1664.loc := UInt<1>("h00") + T_1664.idx := UInt<1>("h00") + T_1664.idx := rel_data_cnt + T_1664.loc := UInt<2>("h02") + node T_1669 = cat(T_1664.idx, T_1664.loc) + T_2015.inner.release.bits.data := T_1669 + node T_1671 = eq(release_idx, UInt<3>("h05")) + node T_1672 = and(inner.release.valid, T_1671) + T_2016.inner.release.valid := T_1672 + T_2016.inner.release.bits <> inner.release.bits + wire T_1676 : {idx : UInt<2>, loc : UInt<2>} + T_1676.loc := UInt<1>("h00") + T_1676.idx := UInt<1>("h00") + T_1676.idx := rel_data_cnt + T_1676.loc := UInt<2>("h02") + node T_1681 = cat(T_1676.idx, T_1676.loc) + T_2016.inner.release.bits.data := T_1681 + node T_1683 = eq(release_idx, UInt<3>("h06")) + node T_1684 = and(inner.release.valid, T_1683) + T_2017.inner.release.valid := T_1684 + T_2017.inner.release.bits <> inner.release.bits + wire T_1688 : {idx : UInt<2>, loc : UInt<2>} + T_1688.loc := UInt<1>("h00") + T_1688.idx := UInt<1>("h00") + T_1688.idx := rel_data_cnt + T_1688.loc := UInt<2>("h02") + node T_1693 = cat(T_1688.idx, T_1688.loc) + T_2017.inner.release.bits.data := T_1693 + node T_1695 = eq(release_idx, UInt<3>("h07")) + node T_1696 = and(inner.release.valid, T_1695) + T_2018.inner.release.valid := T_1696 + T_2018.inner.release.bits <> inner.release.bits + wire T_1700 : {idx : UInt<2>, loc : UInt<2>} + T_1700.loc := UInt<1>("h00") + T_1700.idx := UInt<1>("h00") + T_1700.idx := rel_data_cnt + T_1700.loc := UInt<2>("h02") + node T_1705 = cat(T_1700.idx, T_1700.loc) + T_2018.inner.release.bits.data := T_1705 + node T_1707 = neq(releaseMatches, UInt<1>("h00")) + node T_1709 = eq(T_1707, UInt<1>("h00")) + node T_1710 = and(inner.release.valid, T_1709) + node T_1712 = eq(T_1710, UInt<1>("h00")) + inst T_2019 of LockingRRArbiter_33 + T_2019.out.ready := UInt<1>("h00") + T_2019.in[0].bits.client_id := UInt<1>("h00") + T_2019.in[0].bits.g_type := UInt<1>("h00") + T_2019.in[0].bits.is_builtin_type := UInt<1>("h00") + T_2019.in[0].bits.manager_xact_id := UInt<1>("h00") + T_2019.in[0].bits.client_xact_id := UInt<1>("h00") + T_2019.in[0].bits.data := UInt<1>("h00") + T_2019.in[0].bits.addr_beat := UInt<1>("h00") + T_2019.in[0].valid := UInt<1>("h00") + T_2019.in[1].bits.client_id := UInt<1>("h00") + T_2019.in[1].bits.g_type := UInt<1>("h00") + T_2019.in[1].bits.is_builtin_type := UInt<1>("h00") + T_2019.in[1].bits.manager_xact_id := UInt<1>("h00") + T_2019.in[1].bits.client_xact_id := UInt<1>("h00") + T_2019.in[1].bits.data := UInt<1>("h00") + T_2019.in[1].bits.addr_beat := UInt<1>("h00") + T_2019.in[1].valid := UInt<1>("h00") + T_2019.in[2].bits.client_id := UInt<1>("h00") + T_2019.in[2].bits.g_type := UInt<1>("h00") + T_2019.in[2].bits.is_builtin_type := UInt<1>("h00") + T_2019.in[2].bits.manager_xact_id := UInt<1>("h00") + T_2019.in[2].bits.client_xact_id := UInt<1>("h00") + T_2019.in[2].bits.data := UInt<1>("h00") + T_2019.in[2].bits.addr_beat := UInt<1>("h00") + T_2019.in[2].valid := UInt<1>("h00") + T_2019.in[3].bits.client_id := UInt<1>("h00") + T_2019.in[3].bits.g_type := UInt<1>("h00") + T_2019.in[3].bits.is_builtin_type := UInt<1>("h00") + T_2019.in[3].bits.manager_xact_id := UInt<1>("h00") + T_2019.in[3].bits.client_xact_id := UInt<1>("h00") + T_2019.in[3].bits.data := UInt<1>("h00") + T_2019.in[3].bits.addr_beat := UInt<1>("h00") + T_2019.in[3].valid := UInt<1>("h00") + T_2019.in[4].bits.client_id := UInt<1>("h00") + T_2019.in[4].bits.g_type := UInt<1>("h00") + T_2019.in[4].bits.is_builtin_type := UInt<1>("h00") + T_2019.in[4].bits.manager_xact_id := UInt<1>("h00") + T_2019.in[4].bits.client_xact_id := UInt<1>("h00") + T_2019.in[4].bits.data := UInt<1>("h00") + T_2019.in[4].bits.addr_beat := UInt<1>("h00") + T_2019.in[4].valid := UInt<1>("h00") + T_2019.in[5].bits.client_id := UInt<1>("h00") + T_2019.in[5].bits.g_type := UInt<1>("h00") + T_2019.in[5].bits.is_builtin_type := UInt<1>("h00") + T_2019.in[5].bits.manager_xact_id := UInt<1>("h00") + T_2019.in[5].bits.client_xact_id := UInt<1>("h00") + T_2019.in[5].bits.data := UInt<1>("h00") + T_2019.in[5].bits.addr_beat := UInt<1>("h00") + T_2019.in[5].valid := UInt<1>("h00") + T_2019.in[6].bits.client_id := UInt<1>("h00") + T_2019.in[6].bits.g_type := UInt<1>("h00") + T_2019.in[6].bits.is_builtin_type := UInt<1>("h00") + T_2019.in[6].bits.manager_xact_id := UInt<1>("h00") + T_2019.in[6].bits.client_xact_id := UInt<1>("h00") + T_2019.in[6].bits.data := UInt<1>("h00") + T_2019.in[6].bits.addr_beat := UInt<1>("h00") + T_2019.in[6].valid := UInt<1>("h00") + T_2019.in[7].bits.client_id := UInt<1>("h00") + T_2019.in[7].bits.g_type := UInt<1>("h00") + T_2019.in[7].bits.is_builtin_type := UInt<1>("h00") + T_2019.in[7].bits.manager_xact_id := UInt<1>("h00") + T_2019.in[7].bits.client_xact_id := UInt<1>("h00") + T_2019.in[7].bits.data := UInt<1>("h00") + T_2019.in[7].bits.addr_beat := UInt<1>("h00") + T_2019.in[7].valid := UInt<1>("h00") + T_2019.reset := UInt<1>("h00") + T_2019.clock := clock + T_2019.reset := reset + inner.grant <> T_2019.out + T_2019.in[0] <> T_2011.inner.grant + T_2019.in[1] <> T_2012.inner.grant + T_2019.in[2] <> T_2013.inner.grant + T_2019.in[3] <> T_2014.inner.grant + T_2019.in[4] <> T_2015.inner.grant + T_2019.in[5] <> T_2016.inner.grant + T_2019.in[6] <> T_2017.inner.grant + T_2019.in[7] <> T_2018.inner.grant + inner.grant.bits.data := outer.grant.bits.data + inner.grant.bits.addr_beat := outer.grant.bits.addr_beat + inst T_2020 of LockingRRArbiter_34 + T_2020.out.ready := UInt<1>("h00") + T_2020.in[0].bits.client_id := UInt<1>("h00") + T_2020.in[0].bits.p_type := UInt<1>("h00") + T_2020.in[0].bits.addr_block := UInt<1>("h00") + T_2020.in[0].valid := UInt<1>("h00") + T_2020.in[1].bits.client_id := UInt<1>("h00") + T_2020.in[1].bits.p_type := UInt<1>("h00") + T_2020.in[1].bits.addr_block := UInt<1>("h00") + T_2020.in[1].valid := UInt<1>("h00") + T_2020.in[2].bits.client_id := UInt<1>("h00") + T_2020.in[2].bits.p_type := UInt<1>("h00") + T_2020.in[2].bits.addr_block := UInt<1>("h00") + T_2020.in[2].valid := UInt<1>("h00") + T_2020.in[3].bits.client_id := UInt<1>("h00") + T_2020.in[3].bits.p_type := UInt<1>("h00") + T_2020.in[3].bits.addr_block := UInt<1>("h00") + T_2020.in[3].valid := UInt<1>("h00") + T_2020.in[4].bits.client_id := UInt<1>("h00") + T_2020.in[4].bits.p_type := UInt<1>("h00") + T_2020.in[4].bits.addr_block := UInt<1>("h00") + T_2020.in[4].valid := UInt<1>("h00") + T_2020.in[5].bits.client_id := UInt<1>("h00") + T_2020.in[5].bits.p_type := UInt<1>("h00") + T_2020.in[5].bits.addr_block := UInt<1>("h00") + T_2020.in[5].valid := UInt<1>("h00") + T_2020.in[6].bits.client_id := UInt<1>("h00") + T_2020.in[6].bits.p_type := UInt<1>("h00") + T_2020.in[6].bits.addr_block := UInt<1>("h00") + T_2020.in[6].valid := UInt<1>("h00") + T_2020.in[7].bits.client_id := UInt<1>("h00") + T_2020.in[7].bits.p_type := UInt<1>("h00") + T_2020.in[7].bits.addr_block := UInt<1>("h00") + T_2020.in[7].valid := UInt<1>("h00") + T_2020.reset := UInt<1>("h00") + T_2020.clock := clock + T_2020.reset := reset + inner.probe <> T_2020.out + T_2020.in[0] <> T_2011.inner.probe + T_2020.in[1] <> T_2012.inner.probe + T_2020.in[2] <> T_2013.inner.probe + T_2020.in[3] <> T_2014.inner.probe + T_2020.in[4] <> T_2015.inner.probe + T_2020.in[5] <> T_2016.inner.probe + T_2020.in[6] <> T_2017.inner.probe + T_2020.in[7] <> T_2018.inner.probe + T_2011.inner.finish.bits <> inner.finish.bits + T_2012.inner.finish.bits <> inner.finish.bits + T_2013.inner.finish.bits <> inner.finish.bits + T_2014.inner.finish.bits <> inner.finish.bits + T_2015.inner.finish.bits <> inner.finish.bits + T_2016.inner.finish.bits <> inner.finish.bits + T_2017.inner.finish.bits <> inner.finish.bits + T_2018.inner.finish.bits <> inner.finish.bits + node T_1814 = eq(inner.finish.bits.manager_xact_id, UInt<1>("h00")) + node T_1815 = and(inner.finish.valid, T_1814) + T_2011.inner.finish.valid := T_1815 + node T_1817 = eq(inner.finish.bits.manager_xact_id, UInt<1>("h01")) + node T_1818 = and(inner.finish.valid, T_1817) + T_2012.inner.finish.valid := T_1818 + node T_1820 = eq(inner.finish.bits.manager_xact_id, UInt<2>("h02")) + node T_1821 = and(inner.finish.valid, T_1820) + T_2013.inner.finish.valid := T_1821 + node T_1823 = eq(inner.finish.bits.manager_xact_id, UInt<2>("h03")) + node T_1824 = and(inner.finish.valid, T_1823) + T_2014.inner.finish.valid := T_1824 + node T_1826 = eq(inner.finish.bits.manager_xact_id, UInt<3>("h04")) + node T_1827 = and(inner.finish.valid, T_1826) + T_2015.inner.finish.valid := T_1827 + node T_1829 = eq(inner.finish.bits.manager_xact_id, UInt<3>("h05")) + node T_1830 = and(inner.finish.valid, T_1829) + T_2016.inner.finish.valid := T_1830 + node T_1832 = eq(inner.finish.bits.manager_xact_id, UInt<3>("h06")) + node T_1833 = and(inner.finish.valid, T_1832) + T_2017.inner.finish.valid := T_1833 + node T_1835 = eq(inner.finish.bits.manager_xact_id, UInt<3>("h07")) + node T_1836 = and(inner.finish.valid, T_1835) + T_2018.inner.finish.valid := T_1836 + wire T_1838 : UInt<1>[8] + T_1838[0] := T_2011.inner.finish.ready + T_1838[1] := T_2012.inner.finish.ready + T_1838[2] := T_2013.inner.finish.ready + T_1838[3] := T_2014.inner.finish.ready + T_1838[4] := T_2015.inner.finish.ready + T_1838[5] := T_2016.inner.finish.ready + T_1838[6] := T_2017.inner.finish.ready + T_1838[7] := T_2018.inner.finish.ready + infer accessor T_1848 = T_1838[inner.finish.bits.manager_xact_id] + inner.finish.ready := T_1848 + inst outer_arb of ClientUncachedTileLinkIOArbiter + outer_arb.out.grant.bits.g_type := UInt<1>("h00") + outer_arb.out.grant.bits.is_builtin_type := UInt<1>("h00") + outer_arb.out.grant.bits.manager_xact_id := UInt<1>("h00") + outer_arb.out.grant.bits.client_xact_id := UInt<1>("h00") + outer_arb.out.grant.bits.data := UInt<1>("h00") + outer_arb.out.grant.bits.addr_beat := UInt<1>("h00") + outer_arb.out.grant.valid := UInt<1>("h00") + outer_arb.out.acquire.ready := UInt<1>("h00") + outer_arb.in[0].grant.ready := UInt<1>("h00") + outer_arb.in[0].acquire.bits.union := UInt<1>("h00") + outer_arb.in[0].acquire.bits.a_type := UInt<1>("h00") + outer_arb.in[0].acquire.bits.is_builtin_type := UInt<1>("h00") + outer_arb.in[0].acquire.bits.data := UInt<1>("h00") + outer_arb.in[0].acquire.bits.addr_beat := UInt<1>("h00") + outer_arb.in[0].acquire.bits.client_xact_id := UInt<1>("h00") + outer_arb.in[0].acquire.bits.addr_block := UInt<1>("h00") + outer_arb.in[0].acquire.valid := UInt<1>("h00") + outer_arb.in[1].grant.ready := UInt<1>("h00") + outer_arb.in[1].acquire.bits.union := UInt<1>("h00") + outer_arb.in[1].acquire.bits.a_type := UInt<1>("h00") + outer_arb.in[1].acquire.bits.is_builtin_type := UInt<1>("h00") + outer_arb.in[1].acquire.bits.data := UInt<1>("h00") + outer_arb.in[1].acquire.bits.addr_beat := UInt<1>("h00") + outer_arb.in[1].acquire.bits.client_xact_id := UInt<1>("h00") + outer_arb.in[1].acquire.bits.addr_block := UInt<1>("h00") + outer_arb.in[1].acquire.valid := UInt<1>("h00") + outer_arb.in[2].grant.ready := UInt<1>("h00") + outer_arb.in[2].acquire.bits.union := UInt<1>("h00") + outer_arb.in[2].acquire.bits.a_type := UInt<1>("h00") + outer_arb.in[2].acquire.bits.is_builtin_type := UInt<1>("h00") + outer_arb.in[2].acquire.bits.data := UInt<1>("h00") + outer_arb.in[2].acquire.bits.addr_beat := UInt<1>("h00") + outer_arb.in[2].acquire.bits.client_xact_id := UInt<1>("h00") + outer_arb.in[2].acquire.bits.addr_block := UInt<1>("h00") + outer_arb.in[2].acquire.valid := UInt<1>("h00") + outer_arb.in[3].grant.ready := UInt<1>("h00") + outer_arb.in[3].acquire.bits.union := UInt<1>("h00") + outer_arb.in[3].acquire.bits.a_type := UInt<1>("h00") + outer_arb.in[3].acquire.bits.is_builtin_type := UInt<1>("h00") + outer_arb.in[3].acquire.bits.data := UInt<1>("h00") + outer_arb.in[3].acquire.bits.addr_beat := UInt<1>("h00") + outer_arb.in[3].acquire.bits.client_xact_id := UInt<1>("h00") + outer_arb.in[3].acquire.bits.addr_block := UInt<1>("h00") + outer_arb.in[3].acquire.valid := UInt<1>("h00") + outer_arb.in[4].grant.ready := UInt<1>("h00") + outer_arb.in[4].acquire.bits.union := UInt<1>("h00") + outer_arb.in[4].acquire.bits.a_type := UInt<1>("h00") + outer_arb.in[4].acquire.bits.is_builtin_type := UInt<1>("h00") + outer_arb.in[4].acquire.bits.data := UInt<1>("h00") + outer_arb.in[4].acquire.bits.addr_beat := UInt<1>("h00") + outer_arb.in[4].acquire.bits.client_xact_id := UInt<1>("h00") + outer_arb.in[4].acquire.bits.addr_block := UInt<1>("h00") + outer_arb.in[4].acquire.valid := UInt<1>("h00") + outer_arb.in[5].grant.ready := UInt<1>("h00") + outer_arb.in[5].acquire.bits.union := UInt<1>("h00") + outer_arb.in[5].acquire.bits.a_type := UInt<1>("h00") + outer_arb.in[5].acquire.bits.is_builtin_type := UInt<1>("h00") + outer_arb.in[5].acquire.bits.data := UInt<1>("h00") + outer_arb.in[5].acquire.bits.addr_beat := UInt<1>("h00") + outer_arb.in[5].acquire.bits.client_xact_id := UInt<1>("h00") + outer_arb.in[5].acquire.bits.addr_block := UInt<1>("h00") + outer_arb.in[5].acquire.valid := UInt<1>("h00") + outer_arb.in[6].grant.ready := UInt<1>("h00") + outer_arb.in[6].acquire.bits.union := UInt<1>("h00") + outer_arb.in[6].acquire.bits.a_type := UInt<1>("h00") + outer_arb.in[6].acquire.bits.is_builtin_type := UInt<1>("h00") + outer_arb.in[6].acquire.bits.data := UInt<1>("h00") + outer_arb.in[6].acquire.bits.addr_beat := UInt<1>("h00") + outer_arb.in[6].acquire.bits.client_xact_id := UInt<1>("h00") + outer_arb.in[6].acquire.bits.addr_block := UInt<1>("h00") + outer_arb.in[6].acquire.valid := UInt<1>("h00") + outer_arb.in[7].grant.ready := UInt<1>("h00") + outer_arb.in[7].acquire.bits.union := UInt<1>("h00") + outer_arb.in[7].acquire.bits.a_type := UInt<1>("h00") + outer_arb.in[7].acquire.bits.is_builtin_type := UInt<1>("h00") + outer_arb.in[7].acquire.bits.data := UInt<1>("h00") + outer_arb.in[7].acquire.bits.addr_beat := UInt<1>("h00") + outer_arb.in[7].acquire.bits.client_xact_id := UInt<1>("h00") + outer_arb.in[7].acquire.bits.addr_block := UInt<1>("h00") + outer_arb.in[7].acquire.valid := UInt<1>("h00") + outer_arb.reset := UInt<1>("h00") + outer_arb.clock := clock + outer_arb.reset := reset + outer_arb.in[0] <> T_2011.outer + outer_arb.in[1] <> T_2012.outer + outer_arb.in[2] <> T_2013.outer + outer_arb.in[3] <> T_2014.outer + outer_arb.in[4] <> T_2015.outer + outer_arb.in[5] <> T_2016.outer + outer_arb.in[6] <> T_2017.outer + outer_arb.in[7] <> T_2018.outer + wire outer_data_ptr : {idx : UInt<2>, loc : UInt<2>} + outer_data_ptr.loc := UInt<1>("h00") + outer_data_ptr.idx := UInt<1>("h00") + node T_1941 = bits(outer_arb.out.acquire.bits.data, 1, 0) + outer_data_ptr.loc := T_1941 + node T_1942 = bits(outer_arb.out.acquire.bits.data, 3, 2) + outer_data_ptr.idx := T_1942 + node is_in_sdq = eq(outer_data_ptr.loc, UInt<1>("h00")) + node T_1944 = and(outer.acquire.ready, outer.acquire.valid) + wire T_1949 : UInt<3>[3] + T_1949[0] := UInt<3>("h02") + T_1949[1] := UInt<3>("h03") + T_1949[2] := UInt<3>("h04") + node T_1954 = eq(T_1949[0], outer.acquire.bits.a_type) + node T_1955 = eq(T_1949[1], outer.acquire.bits.a_type) + node T_1956 = eq(T_1949[2], outer.acquire.bits.a_type) + node T_1958 = or(UInt<1>("h00"), T_1954) + node T_1959 = or(T_1958, T_1955) + node T_1960 = or(T_1959, T_1956) + node T_1961 = and(outer.acquire.bits.is_builtin_type, T_1960) + node T_1962 = and(T_1944, T_1961) + node T_1963 = eq(outer_data_ptr.loc, UInt<1>("h00")) + node free_sdq = and(T_1962, T_1963) + outer <> outer_arb.out + infer accessor T_1965 = sdq[outer_data_ptr.idx] + infer accessor T_1966 = vwbdq[outer_data_ptr.idx] + node T_1967 = eq(UInt<1>("h01"), outer_data_ptr.loc) + node T_1968 = mux(T_1967, T_1966, inner.release.bits.data) + node T_1969 = eq(UInt<1>("h00"), outer_data_ptr.loc) + node T_1970 = mux(T_1969, T_1965, T_1968) + outer.acquire.bits.data := T_1970 + node T_1971 = bit(outer_arb.out.acquire.bits.union, 1) + node T_1973 = subw(UInt<16>("h00"), T_1971) + node T_1974 = bit(outer_arb.out.acquire.bits.union, 0) + node T_1975 = cat(T_1973, T_1974) + outer.acquire.bits.union := T_1975 + node T_1976 = or(outer.acquire.valid, sdq_enq) + when T_1976 : + node T_1978 = dshl(UInt<1>("h01"), outer_data_ptr.idx) + node T_1980 = subw(UInt<4>("h00"), free_sdq) + node T_1981 = and(T_1978, T_1980) + node T_1982 = not(T_1981) + node T_1983 = and(sdq_val, T_1982) + node T_1984 = bits(sdq_val, 3, 0) + node T_1985 = not(T_1984) + node T_1986 = bit(T_1985, 0) + node T_1987 = bit(T_1985, 1) + node T_1988 = bit(T_1985, 2) + node T_1989 = bit(T_1985, 3) + wire T_1995 : UInt<4>[4] + T_1995[0] := UInt<4>("h01") + T_1995[1] := UInt<4>("h02") + T_1995[2] := UInt<4>("h04") + T_1995[3] := UInt<4>("h08") + node T_2003 = mux(T_1989, T_1995[3], UInt<4>("h00")) + node T_2004 = mux(T_1988, T_1995[2], T_2003) + node T_2005 = mux(T_1987, T_1995[1], T_2004) + node T_2006 = mux(T_1986, T_1995[0], T_2005) + node T_2008 = subw(UInt<4>("h00"), sdq_enq) + node T_2009 = and(T_2006, T_2008) + node T_2010 = or(T_1983, T_2009) + sdq_val := T_2010 + skip + + module FinishQueue_39 : + output count : UInt<2> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<1>}, dst : UInt<1>}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<1>}, dst : UInt<1>}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.dst := UInt<1>("h00") + deq.bits.fin.manager_xact_id := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem T_409 : {fin : {manager_xact_id : UInt<1>}, dst : UInt<1>}[2], clock + reg T_411 : UInt<1>, clock, reset + onreset T_411 := UInt<1>("h00") + reg T_413 : UInt<1>, clock, reset + onreset T_413 := UInt<1>("h00") + reg T_415 : UInt<1>, clock, reset + onreset T_415 := UInt<1>("h00") + node T_416 = eq(T_411, T_413) + node T_418 = eq(T_415, UInt<1>("h00")) + node T_419 = and(T_416, T_418) + node T_420 = and(T_416, T_415) + node T_422 = and(UInt<1>("h00"), T_419) + node T_423 = and(T_422, deq.ready) + node T_424 = and(enq.ready, enq.valid) + node T_426 = eq(T_423, UInt<1>("h00")) + node T_427 = and(T_424, T_426) + node T_428 = and(deq.ready, deq.valid) + node T_430 = eq(T_423, UInt<1>("h00")) + node T_431 = and(T_428, T_430) + when T_427 : + infer accessor T_432 = T_409[T_411] + T_432 <> enq.bits + node T_477 = eq(T_411, UInt<1>("h01")) + node T_479 = and(UInt<1>("h00"), T_477) + node T_482 = addw(T_411, UInt<1>("h01")) + node T_483 = mux(T_479, UInt<1>("h00"), T_482) + T_411 := T_483 + skip + when T_431 : + node T_485 = eq(T_413, UInt<1>("h01")) + node T_487 = and(UInt<1>("h00"), T_485) + node T_490 = addw(T_413, UInt<1>("h01")) + node T_491 = mux(T_487, UInt<1>("h00"), T_490) + T_413 := T_491 + skip + node T_492 = neq(T_427, T_431) + when T_492 : + T_415 := T_427 + skip + node T_494 = eq(T_419, UInt<1>("h00")) + node T_496 = and(UInt<1>("h00"), enq.valid) + node T_497 = or(T_494, T_496) + deq.valid := T_497 + node T_499 = eq(T_420, UInt<1>("h00")) + node T_501 = and(UInt<1>("h00"), deq.ready) + node T_502 = or(T_499, T_501) + enq.ready := T_502 + infer accessor T_503 = T_409[T_413] + wire T_591 : {fin : {manager_xact_id : UInt<1>}, dst : UInt<1>} + T_591 <> T_503 + when T_422 : + T_591 <> enq.bits + skip + deq.bits <> T_591 + node T_635 = subw(T_411, T_413) + node T_636 = and(T_415, T_416) + node T_637 = cat(T_636, T_635) + count := T_637 + + module FinishUnit_38 : + output ready : UInt<1> + output finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}} + output refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}} + input grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input clock : Clock + input reset : UInt<1> + + ready := UInt<1>("h00") + finish.bits.payload.manager_xact_id := UInt<1>("h00") + finish.bits.header.dst := UInt<1>("h00") + finish.bits.header.src := UInt<1>("h00") + finish.valid := UInt<1>("h00") + refill.bits.g_type := UInt<1>("h00") + refill.bits.is_builtin_type := UInt<1>("h00") + refill.bits.manager_xact_id := UInt<1>("h00") + refill.bits.client_xact_id := UInt<1>("h00") + refill.bits.data := UInt<1>("h00") + refill.bits.addr_beat := UInt<1>("h00") + refill.valid := UInt<1>("h00") + grant.ready := UInt<1>("h00") + node T_399 = and(grant.ready, grant.valid) + wire T_404 : UInt<3>[1] + T_404[0] := UInt<3>("h05") + node T_407 = eq(T_404[0], grant.bits.payload.g_type) + node T_409 = or(UInt<1>("h00"), T_407) + wire T_411 : UInt<1>[1] + T_411[0] := UInt<1>("h00") + node T_414 = eq(T_411[0], grant.bits.payload.g_type) + node T_416 = or(UInt<1>("h00"), T_414) + node T_417 = mux(grant.bits.payload.is_builtin_type, T_409, T_416) + node T_418 = and(UInt<1>("h01"), T_417) + node T_419 = and(T_399, T_418) + reg T_421 : UInt<2>, clock, reset + onreset T_421 := UInt<2>("h00") + when T_419 : + node T_423 = eq(T_421, UInt<2>("h03")) + node T_425 = and(UInt<1>("h00"), T_423) + node T_428 = addw(T_421, UInt<1>("h01")) + node T_429 = mux(T_425, UInt<1>("h00"), T_428) + T_421 := T_429 + skip + node T_430 = and(T_419, T_423) + node T_431 = mux(T_418, T_421, UInt<1>("h00")) + node T_432 = mux(T_418, T_430, T_399) + inst T_574 of FinishQueue_39 + T_574.deq.ready := UInt<1>("h00") + T_574.enq.bits.dst := UInt<1>("h00") + T_574.enq.bits.fin.manager_xact_id := UInt<1>("h00") + T_574.enq.valid := UInt<1>("h00") + T_574.reset := UInt<1>("h00") + T_574.clock := clock + T_574.reset := reset + node T_482 = and(grant.ready, grant.valid) + node T_485 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_487 = eq(grant.bits.payload.g_type, UInt<3>("h00")) + node T_488 = and(grant.bits.payload.is_builtin_type, T_487) + node T_490 = eq(T_488, UInt<1>("h00")) + node T_491 = and(T_485, T_490) + node T_492 = and(T_482, T_491) + wire T_496 : UInt<3>[1] + T_496[0] := UInt<3>("h05") + node T_499 = eq(T_496[0], grant.bits.payload.g_type) + node T_501 = or(UInt<1>("h00"), T_499) + wire T_503 : UInt<1>[1] + T_503[0] := UInt<1>("h00") + node T_506 = eq(T_503[0], grant.bits.payload.g_type) + node T_508 = or(UInt<1>("h00"), T_506) + node T_509 = mux(grant.bits.payload.is_builtin_type, T_501, T_508) + node T_510 = and(UInt<1>("h01"), T_509) + node T_512 = eq(T_510, UInt<1>("h00")) + node T_513 = or(T_512, T_432) + node T_514 = and(T_492, T_513) + T_574.enq.valid := T_514 + wire T_537 : {manager_xact_id : UInt<1>} + T_537.manager_xact_id := UInt<1>("h00") + T_537.manager_xact_id := grant.bits.payload.manager_xact_id + T_574.enq.bits.fin <> T_537 + T_574.enq.bits.dst := grant.bits.header.src + finish.bits.header.src := UInt<1>("h00") + finish.bits.header.dst := T_574.deq.bits.dst + finish.bits.payload <> T_574.deq.bits.fin + finish.valid := T_574.deq.valid + T_574.deq.ready := finish.ready + refill.valid := grant.valid + refill.bits <> grant.bits.payload + node T_563 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_565 = eq(grant.bits.payload.g_type, UInt<3>("h00")) + node T_566 = and(grant.bits.payload.is_builtin_type, T_565) + node T_568 = eq(T_566, UInt<1>("h00")) + node T_569 = and(T_563, T_568) + node T_571 = eq(T_569, UInt<1>("h00")) + node T_572 = or(T_574.enq.ready, T_571) + node T_573 = and(T_572, refill.ready) + grant.ready := T_573 + ready := T_574.enq.ready + + module ClientTileLinkNetworkPort_37 : + output network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} + input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + input clock : Clock + input reset : UInt<1> + + network.release.bits.payload.voluntary := UInt<1>("h00") + network.release.bits.payload.r_type := UInt<1>("h00") + network.release.bits.payload.data := UInt<1>("h00") + network.release.bits.payload.addr_beat := UInt<1>("h00") + network.release.bits.payload.client_xact_id := UInt<1>("h00") + network.release.bits.payload.addr_block := UInt<1>("h00") + network.release.bits.header.dst := UInt<1>("h00") + network.release.bits.header.src := UInt<1>("h00") + network.release.valid := UInt<1>("h00") + network.probe.ready := UInt<1>("h00") + network.finish.bits.payload.manager_xact_id := UInt<1>("h00") + network.finish.bits.header.dst := UInt<1>("h00") + network.finish.bits.header.src := UInt<1>("h00") + network.finish.valid := UInt<1>("h00") + network.grant.ready := UInt<1>("h00") + network.acquire.bits.payload.union := UInt<1>("h00") + network.acquire.bits.payload.a_type := UInt<1>("h00") + network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + network.acquire.bits.payload.data := UInt<1>("h00") + network.acquire.bits.payload.addr_beat := UInt<1>("h00") + network.acquire.bits.payload.client_xact_id := UInt<1>("h00") + network.acquire.bits.payload.addr_block := UInt<1>("h00") + network.acquire.bits.header.dst := UInt<1>("h00") + network.acquire.bits.header.src := UInt<1>("h00") + network.acquire.valid := UInt<1>("h00") + client.release.ready := UInt<1>("h00") + client.probe.bits.p_type := UInt<1>("h00") + client.probe.bits.addr_block := UInt<1>("h00") + client.probe.valid := UInt<1>("h00") + client.grant.bits.g_type := UInt<1>("h00") + client.grant.bits.is_builtin_type := UInt<1>("h00") + client.grant.bits.manager_xact_id := UInt<1>("h00") + client.grant.bits.client_xact_id := UInt<1>("h00") + client.grant.bits.data := UInt<1>("h00") + client.grant.bits.addr_beat := UInt<1>("h00") + client.grant.valid := UInt<1>("h00") + client.acquire.ready := UInt<1>("h00") + inst finisher of FinishUnit_38 + finisher.finish.ready := UInt<1>("h00") + finisher.refill.ready := UInt<1>("h00") + finisher.grant.bits.payload.g_type := UInt<1>("h00") + finisher.grant.bits.payload.is_builtin_type := UInt<1>("h00") + finisher.grant.bits.payload.manager_xact_id := UInt<1>("h00") + finisher.grant.bits.payload.client_xact_id := UInt<1>("h00") + finisher.grant.bits.payload.data := UInt<1>("h00") + finisher.grant.bits.payload.addr_beat := UInt<1>("h00") + finisher.grant.bits.header.dst := UInt<1>("h00") + finisher.grant.bits.header.src := UInt<1>("h00") + finisher.grant.valid := UInt<1>("h00") + finisher.reset := UInt<1>("h00") + finisher.clock := clock + finisher.reset := reset + finisher.grant <> network.grant + network.finish <> finisher.finish + wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}} + acq_with_header.bits.payload.union := UInt<1>("h00") + acq_with_header.bits.payload.a_type := UInt<1>("h00") + acq_with_header.bits.payload.is_builtin_type := UInt<1>("h00") + acq_with_header.bits.payload.data := UInt<1>("h00") + acq_with_header.bits.payload.addr_beat := UInt<1>("h00") + acq_with_header.bits.payload.client_xact_id := UInt<1>("h00") + acq_with_header.bits.payload.addr_block := UInt<1>("h00") + acq_with_header.bits.header.dst := UInt<1>("h00") + acq_with_header.bits.header.src := UInt<1>("h00") + acq_with_header.valid := UInt<1>("h00") + acq_with_header.ready := UInt<1>("h00") + acq_with_header.bits.payload <> client.acquire.bits + acq_with_header.bits.header.src := UInt<1>("h00") + acq_with_header.bits.header.dst := UInt<1>("h00") + acq_with_header.valid := client.acquire.valid + client.acquire.ready := acq_with_header.ready + wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + rel_with_header.bits.payload.voluntary := UInt<1>("h00") + rel_with_header.bits.payload.r_type := UInt<1>("h00") + rel_with_header.bits.payload.data := UInt<1>("h00") + rel_with_header.bits.payload.addr_beat := UInt<1>("h00") + rel_with_header.bits.payload.client_xact_id := UInt<1>("h00") + rel_with_header.bits.payload.addr_block := UInt<1>("h00") + rel_with_header.bits.header.dst := UInt<1>("h00") + rel_with_header.bits.header.src := UInt<1>("h00") + rel_with_header.valid := UInt<1>("h00") + rel_with_header.ready := UInt<1>("h00") + rel_with_header.bits.payload <> client.release.bits + rel_with_header.bits.header.src := UInt<1>("h00") + rel_with_header.bits.header.dst := UInt<1>("h00") + rel_with_header.valid := client.release.valid + client.release.ready := rel_with_header.ready + wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} + prb_without_header.bits.p_type := UInt<1>("h00") + prb_without_header.bits.addr_block := UInt<1>("h00") + prb_without_header.valid := UInt<1>("h00") + prb_without_header.ready := UInt<1>("h00") + prb_without_header.valid := network.probe.valid + prb_without_header.bits <> network.probe.bits.payload + network.probe.ready := prb_without_header.ready + network.acquire.bits <> acq_with_header.bits + node T_2123 = and(acq_with_header.valid, finisher.ready) + network.acquire.valid := T_2123 + node T_2124 = and(network.acquire.ready, finisher.ready) + acq_with_header.ready := T_2124 + network.release <> rel_with_header + client.probe <> prb_without_header + client.grant <> finisher.refill + + module TileLinkEnqueuer_40 : + output manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} + input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} + input clock : Clock + input reset : UInt<1> + + manager.release.bits.payload.voluntary := UInt<1>("h00") + manager.release.bits.payload.r_type := UInt<1>("h00") + manager.release.bits.payload.data := UInt<1>("h00") + manager.release.bits.payload.addr_beat := UInt<1>("h00") + manager.release.bits.payload.client_xact_id := UInt<1>("h00") + manager.release.bits.payload.addr_block := UInt<1>("h00") + manager.release.bits.header.dst := UInt<1>("h00") + manager.release.bits.header.src := UInt<1>("h00") + manager.release.valid := UInt<1>("h00") + manager.probe.ready := UInt<1>("h00") + manager.finish.bits.payload.manager_xact_id := UInt<1>("h00") + manager.finish.bits.header.dst := UInt<1>("h00") + manager.finish.bits.header.src := UInt<1>("h00") + manager.finish.valid := UInt<1>("h00") + manager.grant.ready := UInt<1>("h00") + manager.acquire.bits.payload.union := UInt<1>("h00") + manager.acquire.bits.payload.a_type := UInt<1>("h00") + manager.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + manager.acquire.bits.payload.data := UInt<1>("h00") + manager.acquire.bits.payload.addr_beat := UInt<1>("h00") + manager.acquire.bits.payload.client_xact_id := UInt<1>("h00") + manager.acquire.bits.payload.addr_block := UInt<1>("h00") + manager.acquire.bits.header.dst := UInt<1>("h00") + manager.acquire.bits.header.src := UInt<1>("h00") + manager.acquire.valid := UInt<1>("h00") + client.release.ready := UInt<1>("h00") + client.probe.bits.payload.p_type := UInt<1>("h00") + client.probe.bits.payload.addr_block := UInt<1>("h00") + client.probe.bits.header.dst := UInt<1>("h00") + client.probe.bits.header.src := UInt<1>("h00") + client.probe.valid := UInt<1>("h00") + client.finish.ready := UInt<1>("h00") + client.grant.bits.payload.g_type := UInt<1>("h00") + client.grant.bits.payload.is_builtin_type := UInt<1>("h00") + client.grant.bits.payload.manager_xact_id := UInt<1>("h00") + client.grant.bits.payload.client_xact_id := UInt<1>("h00") + client.grant.bits.payload.data := UInt<1>("h00") + client.grant.bits.payload.addr_beat := UInt<1>("h00") + client.grant.bits.header.dst := UInt<1>("h00") + client.grant.bits.header.src := UInt<1>("h00") + client.grant.valid := UInt<1>("h00") + client.acquire.ready := UInt<1>("h00") + manager.acquire <> client.acquire + client.probe <> manager.probe + manager.release <> client.release + client.grant <> manager.grant + manager.finish <> client.finish + + module ManagerTileLinkNetworkPort_41 : + input network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}} + input manager : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<1>}}} + input clock : Clock + input reset : UInt<1> + + network.release.ready := UInt<1>("h00") + network.probe.bits.payload.p_type := UInt<1>("h00") + network.probe.bits.payload.addr_block := UInt<1>("h00") + network.probe.bits.header.dst := UInt<1>("h00") + network.probe.bits.header.src := UInt<1>("h00") + network.probe.valid := UInt<1>("h00") + network.finish.ready := UInt<1>("h00") + network.grant.bits.payload.g_type := UInt<1>("h00") + network.grant.bits.payload.is_builtin_type := UInt<1>("h00") + network.grant.bits.payload.manager_xact_id := UInt<1>("h00") + network.grant.bits.payload.client_xact_id := UInt<1>("h00") + network.grant.bits.payload.data := UInt<1>("h00") + network.grant.bits.payload.addr_beat := UInt<1>("h00") + network.grant.bits.header.dst := UInt<1>("h00") + network.grant.bits.header.src := UInt<1>("h00") + network.grant.valid := UInt<1>("h00") + network.acquire.ready := UInt<1>("h00") + manager.release.bits.client_id := UInt<1>("h00") + manager.release.bits.voluntary := UInt<1>("h00") + manager.release.bits.r_type := UInt<1>("h00") + manager.release.bits.data := UInt<1>("h00") + manager.release.bits.addr_beat := UInt<1>("h00") + manager.release.bits.client_xact_id := UInt<1>("h00") + manager.release.bits.addr_block := UInt<1>("h00") + manager.release.valid := UInt<1>("h00") + manager.probe.ready := UInt<1>("h00") + manager.finish.bits.manager_xact_id := UInt<1>("h00") + manager.finish.valid := UInt<1>("h00") + manager.grant.ready := UInt<1>("h00") + manager.acquire.bits.client_id := UInt<1>("h00") + manager.acquire.bits.union := UInt<1>("h00") + manager.acquire.bits.a_type := UInt<1>("h00") + manager.acquire.bits.is_builtin_type := UInt<1>("h00") + manager.acquire.bits.data := UInt<1>("h00") + manager.acquire.bits.addr_beat := UInt<1>("h00") + manager.acquire.bits.client_xact_id := UInt<1>("h00") + manager.acquire.bits.addr_block := UInt<1>("h00") + manager.acquire.valid := UInt<1>("h00") + wire T_2766 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}} + T_2766.bits.payload.client_id := UInt<1>("h00") + T_2766.bits.payload.g_type := UInt<1>("h00") + T_2766.bits.payload.is_builtin_type := UInt<1>("h00") + T_2766.bits.payload.manager_xact_id := UInt<1>("h00") + T_2766.bits.payload.client_xact_id := UInt<1>("h00") + T_2766.bits.payload.data := UInt<1>("h00") + T_2766.bits.payload.addr_beat := UInt<1>("h00") + T_2766.bits.header.dst := UInt<1>("h00") + T_2766.bits.header.src := UInt<1>("h00") + T_2766.valid := UInt<1>("h00") + T_2766.ready := UInt<1>("h00") + T_2766.bits.payload <> manager.grant.bits + T_2766.bits.header.src := UInt<1>("h00") + T_2766.bits.header.dst := manager.grant.bits.client_id + T_2766.valid := manager.grant.valid + manager.grant.ready := T_2766.ready + network.grant <> T_2766 + wire T_2932 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}} + T_2932.bits.payload.client_id := UInt<1>("h00") + T_2932.bits.payload.p_type := UInt<1>("h00") + T_2932.bits.payload.addr_block := UInt<1>("h00") + T_2932.bits.header.dst := UInt<1>("h00") + T_2932.bits.header.src := UInt<1>("h00") + T_2932.valid := UInt<1>("h00") + T_2932.ready := UInt<1>("h00") + T_2932.bits.payload <> manager.probe.bits + T_2932.bits.header.src := UInt<1>("h00") + T_2932.bits.header.dst := manager.probe.bits.client_id + T_2932.valid := manager.probe.valid + manager.probe.ready := T_2932.ready + network.probe <> T_2932 + manager.acquire.bits.client_id := network.acquire.bits.header.src + wire T_3058 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} + T_3058.bits.union := UInt<1>("h00") + T_3058.bits.a_type := UInt<1>("h00") + T_3058.bits.is_builtin_type := UInt<1>("h00") + T_3058.bits.data := UInt<1>("h00") + T_3058.bits.addr_beat := UInt<1>("h00") + T_3058.bits.client_xact_id := UInt<1>("h00") + T_3058.bits.addr_block := UInt<1>("h00") + T_3058.valid := UInt<1>("h00") + T_3058.ready := UInt<1>("h00") + T_3058.valid := network.acquire.valid + T_3058.bits <> network.acquire.bits.payload + network.acquire.ready := T_3058.ready + manager.acquire <> T_3058 + manager.release.bits.client_id := network.release.bits.header.src + wire T_3183 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} + T_3183.bits.voluntary := UInt<1>("h00") + T_3183.bits.r_type := UInt<1>("h00") + T_3183.bits.data := UInt<1>("h00") + T_3183.bits.addr_beat := UInt<1>("h00") + T_3183.bits.client_xact_id := UInt<1>("h00") + T_3183.bits.addr_block := UInt<1>("h00") + T_3183.valid := UInt<1>("h00") + T_3183.ready := UInt<1>("h00") + T_3183.valid := network.release.valid + T_3183.bits <> network.release.bits.payload + network.release.ready := T_3183.ready + manager.release <> T_3183 + wire T_3295 : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}} + T_3295.bits.manager_xact_id := UInt<1>("h00") + T_3295.valid := UInt<1>("h00") + T_3295.ready := UInt<1>("h00") + T_3295.valid := network.finish.valid + T_3295.bits <> network.finish.bits.payload + network.finish.ready := T_3295.ready + manager.finish <> T_3295 + + module RocketChipTileLinkArbiter_36 : + input managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<1>}}}[1] + input clients : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[1] + input clock : Clock + input reset : UInt<1> + + managers[0].release.bits.client_id := UInt<1>("h00") + managers[0].release.bits.voluntary := UInt<1>("h00") + managers[0].release.bits.r_type := UInt<1>("h00") + managers[0].release.bits.data := UInt<1>("h00") + managers[0].release.bits.addr_beat := UInt<1>("h00") + managers[0].release.bits.client_xact_id := UInt<1>("h00") + managers[0].release.bits.addr_block := UInt<1>("h00") + managers[0].release.valid := UInt<1>("h00") + managers[0].probe.ready := UInt<1>("h00") + managers[0].finish.bits.manager_xact_id := UInt<1>("h00") + managers[0].finish.valid := UInt<1>("h00") + managers[0].grant.ready := UInt<1>("h00") + managers[0].acquire.bits.client_id := UInt<1>("h00") + managers[0].acquire.bits.union := UInt<1>("h00") + managers[0].acquire.bits.a_type := UInt<1>("h00") + managers[0].acquire.bits.is_builtin_type := UInt<1>("h00") + managers[0].acquire.bits.data := UInt<1>("h00") + managers[0].acquire.bits.addr_beat := UInt<1>("h00") + managers[0].acquire.bits.client_xact_id := UInt<1>("h00") + managers[0].acquire.bits.addr_block := UInt<1>("h00") + managers[0].acquire.valid := UInt<1>("h00") + clients[0].release.ready := UInt<1>("h00") + clients[0].probe.bits.p_type := UInt<1>("h00") + clients[0].probe.bits.addr_block := UInt<1>("h00") + clients[0].probe.valid := UInt<1>("h00") + clients[0].grant.bits.g_type := UInt<1>("h00") + clients[0].grant.bits.is_builtin_type := UInt<1>("h00") + clients[0].grant.bits.manager_xact_id := UInt<1>("h00") + clients[0].grant.bits.client_xact_id := UInt<1>("h00") + clients[0].grant.bits.data := UInt<1>("h00") + clients[0].grant.bits.addr_beat := UInt<1>("h00") + clients[0].grant.valid := UInt<1>("h00") + clients[0].acquire.ready := UInt<1>("h00") + inst T_8589 of ClientTileLinkNetworkPort_37 + T_8589.network.release.ready := UInt<1>("h00") + T_8589.network.probe.bits.payload.p_type := UInt<1>("h00") + T_8589.network.probe.bits.payload.addr_block := UInt<1>("h00") + T_8589.network.probe.bits.header.dst := UInt<1>("h00") + T_8589.network.probe.bits.header.src := UInt<1>("h00") + T_8589.network.probe.valid := UInt<1>("h00") + T_8589.network.finish.ready := UInt<1>("h00") + T_8589.network.grant.bits.payload.g_type := UInt<1>("h00") + T_8589.network.grant.bits.payload.is_builtin_type := UInt<1>("h00") + T_8589.network.grant.bits.payload.manager_xact_id := UInt<1>("h00") + T_8589.network.grant.bits.payload.client_xact_id := UInt<1>("h00") + T_8589.network.grant.bits.payload.data := UInt<1>("h00") + T_8589.network.grant.bits.payload.addr_beat := UInt<1>("h00") + T_8589.network.grant.bits.header.dst := UInt<1>("h00") + T_8589.network.grant.bits.header.src := UInt<1>("h00") + T_8589.network.grant.valid := UInt<1>("h00") + T_8589.network.acquire.ready := UInt<1>("h00") + T_8589.client.release.bits.voluntary := UInt<1>("h00") + T_8589.client.release.bits.r_type := UInt<1>("h00") + T_8589.client.release.bits.data := UInt<1>("h00") + T_8589.client.release.bits.addr_beat := UInt<1>("h00") + T_8589.client.release.bits.client_xact_id := UInt<1>("h00") + T_8589.client.release.bits.addr_block := UInt<1>("h00") + T_8589.client.release.valid := UInt<1>("h00") + T_8589.client.probe.ready := UInt<1>("h00") + T_8589.client.grant.ready := UInt<1>("h00") + T_8589.client.acquire.bits.union := UInt<1>("h00") + T_8589.client.acquire.bits.a_type := UInt<1>("h00") + T_8589.client.acquire.bits.is_builtin_type := UInt<1>("h00") + T_8589.client.acquire.bits.data := UInt<1>("h00") + T_8589.client.acquire.bits.addr_beat := UInt<1>("h00") + T_8589.client.acquire.bits.client_xact_id := UInt<1>("h00") + T_8589.client.acquire.bits.addr_block := UInt<1>("h00") + T_8589.client.acquire.valid := UInt<1>("h00") + T_8589.reset := UInt<1>("h00") + T_8589.clock := clock + T_8589.reset := reset + inst T_8590 of TileLinkEnqueuer_40 + T_8590.manager.release.ready := UInt<1>("h00") + T_8590.manager.probe.bits.payload.p_type := UInt<1>("h00") + T_8590.manager.probe.bits.payload.addr_block := UInt<1>("h00") + T_8590.manager.probe.bits.header.dst := UInt<1>("h00") + T_8590.manager.probe.bits.header.src := UInt<1>("h00") + T_8590.manager.probe.valid := UInt<1>("h00") + T_8590.manager.finish.ready := UInt<1>("h00") + T_8590.manager.grant.bits.payload.g_type := UInt<1>("h00") + T_8590.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") + T_8590.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") + T_8590.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") + T_8590.manager.grant.bits.payload.data := UInt<1>("h00") + T_8590.manager.grant.bits.payload.addr_beat := UInt<1>("h00") + T_8590.manager.grant.bits.header.dst := UInt<1>("h00") + T_8590.manager.grant.bits.header.src := UInt<1>("h00") + T_8590.manager.grant.valid := UInt<1>("h00") + T_8590.manager.acquire.ready := UInt<1>("h00") + T_8590.client.release.bits.payload.voluntary := UInt<1>("h00") + T_8590.client.release.bits.payload.r_type := UInt<1>("h00") + T_8590.client.release.bits.payload.data := UInt<1>("h00") + T_8590.client.release.bits.payload.addr_beat := UInt<1>("h00") + T_8590.client.release.bits.payload.client_xact_id := UInt<1>("h00") + T_8590.client.release.bits.payload.addr_block := UInt<1>("h00") + T_8590.client.release.bits.header.dst := UInt<1>("h00") + T_8590.client.release.bits.header.src := UInt<1>("h00") + T_8590.client.release.valid := UInt<1>("h00") + T_8590.client.probe.ready := UInt<1>("h00") + T_8590.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") + T_8590.client.finish.bits.header.dst := UInt<1>("h00") + T_8590.client.finish.bits.header.src := UInt<1>("h00") + T_8590.client.finish.valid := UInt<1>("h00") + T_8590.client.grant.ready := UInt<1>("h00") + T_8590.client.acquire.bits.payload.union := UInt<1>("h00") + T_8590.client.acquire.bits.payload.a_type := UInt<1>("h00") + T_8590.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + T_8590.client.acquire.bits.payload.data := UInt<1>("h00") + T_8590.client.acquire.bits.payload.addr_beat := UInt<1>("h00") + T_8590.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") + T_8590.client.acquire.bits.payload.addr_block := UInt<1>("h00") + T_8590.client.acquire.bits.header.dst := UInt<1>("h00") + T_8590.client.acquire.bits.header.src := UInt<1>("h00") + T_8590.client.acquire.valid := UInt<1>("h00") + T_8590.reset := UInt<1>("h00") + T_8590.clock := clock + T_8590.reset := reset + T_8589.client <> clients[0] + T_8590.client <> T_8589.network + inst T_8591 of ManagerTileLinkNetworkPort_41 + T_8591.network.release.bits.payload.voluntary := UInt<1>("h00") + T_8591.network.release.bits.payload.r_type := UInt<1>("h00") + T_8591.network.release.bits.payload.data := UInt<1>("h00") + T_8591.network.release.bits.payload.addr_beat := UInt<1>("h00") + T_8591.network.release.bits.payload.client_xact_id := UInt<1>("h00") + T_8591.network.release.bits.payload.addr_block := UInt<1>("h00") + T_8591.network.release.bits.header.dst := UInt<1>("h00") + T_8591.network.release.bits.header.src := UInt<1>("h00") + T_8591.network.release.valid := UInt<1>("h00") + T_8591.network.probe.ready := UInt<1>("h00") + T_8591.network.finish.bits.payload.manager_xact_id := UInt<1>("h00") + T_8591.network.finish.bits.header.dst := UInt<1>("h00") + T_8591.network.finish.bits.header.src := UInt<1>("h00") + T_8591.network.finish.valid := UInt<1>("h00") + T_8591.network.grant.ready := UInt<1>("h00") + T_8591.network.acquire.bits.payload.union := UInt<1>("h00") + T_8591.network.acquire.bits.payload.a_type := UInt<1>("h00") + T_8591.network.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + T_8591.network.acquire.bits.payload.data := UInt<1>("h00") + T_8591.network.acquire.bits.payload.addr_beat := UInt<1>("h00") + T_8591.network.acquire.bits.payload.client_xact_id := UInt<1>("h00") + T_8591.network.acquire.bits.payload.addr_block := UInt<1>("h00") + T_8591.network.acquire.bits.header.dst := UInt<1>("h00") + T_8591.network.acquire.bits.header.src := UInt<1>("h00") + T_8591.network.acquire.valid := UInt<1>("h00") + T_8591.manager.release.ready := UInt<1>("h00") + T_8591.manager.probe.bits.client_id := UInt<1>("h00") + T_8591.manager.probe.bits.p_type := UInt<1>("h00") + T_8591.manager.probe.bits.addr_block := UInt<1>("h00") + T_8591.manager.probe.valid := UInt<1>("h00") + T_8591.manager.finish.ready := UInt<1>("h00") + T_8591.manager.grant.bits.client_id := UInt<1>("h00") + T_8591.manager.grant.bits.g_type := UInt<1>("h00") + T_8591.manager.grant.bits.is_builtin_type := UInt<1>("h00") + T_8591.manager.grant.bits.manager_xact_id := UInt<1>("h00") + T_8591.manager.grant.bits.client_xact_id := UInt<1>("h00") + T_8591.manager.grant.bits.data := UInt<1>("h00") + T_8591.manager.grant.bits.addr_beat := UInt<1>("h00") + T_8591.manager.grant.valid := UInt<1>("h00") + T_8591.manager.acquire.ready := UInt<1>("h00") + T_8591.reset := UInt<1>("h00") + T_8591.clock := clock + T_8591.reset := reset + inst T_8592 of TileLinkEnqueuer_40 + T_8592.manager.release.ready := UInt<1>("h00") + T_8592.manager.probe.bits.payload.p_type := UInt<1>("h00") + T_8592.manager.probe.bits.payload.addr_block := UInt<1>("h00") + T_8592.manager.probe.bits.header.dst := UInt<1>("h00") + T_8592.manager.probe.bits.header.src := UInt<1>("h00") + T_8592.manager.probe.valid := UInt<1>("h00") + T_8592.manager.finish.ready := UInt<1>("h00") + T_8592.manager.grant.bits.payload.g_type := UInt<1>("h00") + T_8592.manager.grant.bits.payload.is_builtin_type := UInt<1>("h00") + T_8592.manager.grant.bits.payload.manager_xact_id := UInt<1>("h00") + T_8592.manager.grant.bits.payload.client_xact_id := UInt<1>("h00") + T_8592.manager.grant.bits.payload.data := UInt<1>("h00") + T_8592.manager.grant.bits.payload.addr_beat := UInt<1>("h00") + T_8592.manager.grant.bits.header.dst := UInt<1>("h00") + T_8592.manager.grant.bits.header.src := UInt<1>("h00") + T_8592.manager.grant.valid := UInt<1>("h00") + T_8592.manager.acquire.ready := UInt<1>("h00") + T_8592.client.release.bits.payload.voluntary := UInt<1>("h00") + T_8592.client.release.bits.payload.r_type := UInt<1>("h00") + T_8592.client.release.bits.payload.data := UInt<1>("h00") + T_8592.client.release.bits.payload.addr_beat := UInt<1>("h00") + T_8592.client.release.bits.payload.client_xact_id := UInt<1>("h00") + T_8592.client.release.bits.payload.addr_block := UInt<1>("h00") + T_8592.client.release.bits.header.dst := UInt<1>("h00") + T_8592.client.release.bits.header.src := UInt<1>("h00") + T_8592.client.release.valid := UInt<1>("h00") + T_8592.client.probe.ready := UInt<1>("h00") + T_8592.client.finish.bits.payload.manager_xact_id := UInt<1>("h00") + T_8592.client.finish.bits.header.dst := UInt<1>("h00") + T_8592.client.finish.bits.header.src := UInt<1>("h00") + T_8592.client.finish.valid := UInt<1>("h00") + T_8592.client.grant.ready := UInt<1>("h00") + T_8592.client.acquire.bits.payload.union := UInt<1>("h00") + T_8592.client.acquire.bits.payload.a_type := UInt<1>("h00") + T_8592.client.acquire.bits.payload.is_builtin_type := UInt<1>("h00") + T_8592.client.acquire.bits.payload.data := UInt<1>("h00") + T_8592.client.acquire.bits.payload.addr_beat := UInt<1>("h00") + T_8592.client.acquire.bits.payload.client_xact_id := UInt<1>("h00") + T_8592.client.acquire.bits.payload.addr_block := UInt<1>("h00") + T_8592.client.acquire.bits.header.dst := UInt<1>("h00") + T_8592.client.acquire.bits.header.src := UInt<1>("h00") + T_8592.client.acquire.valid := UInt<1>("h00") + T_8592.reset := UInt<1>("h00") + T_8592.clock := clock + T_8592.reset := reset + T_8591.manager <> managers[0] + T_8591.network <> T_8592.manager + T_8592.client <> T_8590.manager + + module Arbiter : + output chosen : UInt<1> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}[2] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.client_id := UInt<1>("h00") + out.bits.g_type := UInt<1>("h00") + out.bits.is_builtin_type := UInt<1>("h00") + out.bits.manager_xact_id := UInt<1>("h00") + out.bits.client_xact_id := UInt<1>("h00") + out.bits.data := UInt<1>("h00") + out.bits.addr_beat := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + wire T_658 : UInt<1> + T_658 := UInt<1>("h00") + infer accessor T_660 = in[T_658] + out.valid := T_660.valid + infer accessor T_719 = in[T_658] + out.bits <> T_719.bits + chosen := T_658 + infer accessor T_778 = in[T_658] + T_778.ready := UInt<1>("h00") + node T_840 = or(UInt<1>("h00"), in[0].valid) + node T_842 = eq(T_840, UInt<1>("h00")) + node T_844 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_845 = mux(UInt<1>("h00"), T_844, UInt<1>("h01")) + node T_846 = and(T_845, out.ready) + in[0].ready := T_846 + node T_848 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_849 = mux(UInt<1>("h00"), T_848, T_842) + node T_850 = and(T_849, out.ready) + in[1].ready := T_850 + node T_853 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_854 = mux(UInt<1>("h00"), UInt<1>("h01"), T_853) + T_658 := T_854 + + module MemIOTileLinkIOConverter : + output mem_1 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} + output tl : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<1>}}} + input clock : Clock + input reset : UInt<1> + + mem_1.resp.ready := UInt<1>("h00") + mem_1.req_data.bits.data := UInt<1>("h00") + mem_1.req_data.valid := UInt<1>("h00") + mem_1.req_cmd.bits.rw := UInt<1>("h00") + mem_1.req_cmd.bits.tag := UInt<1>("h00") + mem_1.req_cmd.bits.addr := UInt<1>("h00") + mem_1.req_cmd.valid := UInt<1>("h00") + tl.release.ready := UInt<1>("h00") + tl.probe.bits.client_id := UInt<1>("h00") + tl.probe.bits.p_type := UInt<1>("h00") + tl.probe.bits.addr_block := UInt<1>("h00") + tl.probe.valid := UInt<1>("h00") + tl.finish.ready := UInt<1>("h00") + tl.grant.bits.client_id := UInt<1>("h00") + tl.grant.bits.g_type := UInt<1>("h00") + tl.grant.bits.is_builtin_type := UInt<1>("h00") + tl.grant.bits.manager_xact_id := UInt<1>("h00") + tl.grant.bits.client_xact_id := UInt<1>("h00") + tl.grant.bits.data := UInt<1>("h00") + tl.grant.bits.addr_beat := UInt<1>("h00") + tl.grant.valid := UInt<1>("h00") + tl.acquire.ready := UInt<1>("h00") + tl.acquire.ready := UInt<1>("h00") + tl.probe.valid := UInt<1>("h00") + tl.release.ready := UInt<1>("h00") + tl.finish.ready := UInt<1>("h01") + mem_1.resp.ready := UInt<1>("h00") + inst gnt_arb of Arbiter + gnt_arb.out.ready := UInt<1>("h00") + gnt_arb.in[0].bits.client_id := UInt<1>("h00") + gnt_arb.in[0].bits.g_type := UInt<1>("h00") + gnt_arb.in[0].bits.is_builtin_type := UInt<1>("h00") + gnt_arb.in[0].bits.manager_xact_id := UInt<1>("h00") + gnt_arb.in[0].bits.client_xact_id := UInt<1>("h00") + gnt_arb.in[0].bits.data := UInt<1>("h00") + gnt_arb.in[0].bits.addr_beat := UInt<1>("h00") + gnt_arb.in[0].valid := UInt<1>("h00") + gnt_arb.in[1].bits.client_id := UInt<1>("h00") + gnt_arb.in[1].bits.g_type := UInt<1>("h00") + gnt_arb.in[1].bits.is_builtin_type := UInt<1>("h00") + gnt_arb.in[1].bits.manager_xact_id := UInt<1>("h00") + gnt_arb.in[1].bits.client_xact_id := UInt<1>("h00") + gnt_arb.in[1].bits.data := UInt<1>("h00") + gnt_arb.in[1].bits.addr_beat := UInt<1>("h00") + gnt_arb.in[1].valid := UInt<1>("h00") + gnt_arb.reset := UInt<1>("h00") + gnt_arb.clock := clock + gnt_arb.reset := reset + tl.grant <> gnt_arb.out + wire T_721 : UInt<3>[3] + T_721[0] := UInt<3>("h02") + T_721[1] := UInt<3>("h03") + T_721[2] := UInt<3>("h04") + node T_726 = eq(T_721[0], tl.acquire.bits.a_type) + node T_727 = eq(T_721[1], tl.acquire.bits.a_type) + node T_728 = eq(T_721[2], tl.acquire.bits.a_type) + node T_730 = or(UInt<1>("h00"), T_726) + node T_731 = or(T_730, T_727) + node T_732 = or(T_731, T_728) + node acq_has_data = and(tl.acquire.bits.is_builtin_type, T_732) + wire T_735 : UInt<2>[3] + T_735[0] := UInt<1>("h00") + T_735[1] := UInt<1>("h01") + T_735[2] := UInt<2>("h02") + node T_740 = eq(T_735[0], tl.release.bits.r_type) + node T_741 = eq(T_735[1], tl.release.bits.r_type) + node T_742 = eq(T_735[2], tl.release.bits.r_type) + node T_744 = or(UInt<1>("h00"), T_740) + node T_745 = or(T_744, T_741) + node rel_has_data = or(T_745, T_742) + reg active_out : UInt<1>, clock, reset + onreset active_out := UInt<1>("h00") + reg cmd_sent_out : UInt<1>, clock, reset + onreset cmd_sent_out := UInt<1>("h00") + reg tag_out : UInt<7>, clock, reset + reg addr_out : UInt<26>, clock, reset + reg has_data : UInt<1>, clock, reset + onreset has_data := UInt<1>("h00") + reg data_from_rel : UInt<1>, clock, reset + onreset data_from_rel := UInt<1>("h00") + node T_759 = and(tl.acquire.ready, tl.acquire.valid) + node T_760 = and(T_759, acq_has_data) + node T_761 = and(tl.release.ready, tl.release.valid) + node T_762 = and(T_761, rel_has_data) + node T_763 = or(T_760, T_762) + reg tl_cnt_out : UInt<2>, clock, reset + onreset tl_cnt_out := UInt<2>("h00") + when T_763 : + node T_767 = eq(tl_cnt_out, UInt<2>("h03")) + node T_769 = and(UInt<1>("h00"), T_767) + node T_772 = addw(tl_cnt_out, UInt<1>("h01")) + node T_773 = mux(T_769, UInt<1>("h00"), T_772) + tl_cnt_out := T_773 + skip + node tl_wrap_out = and(T_763, T_767) + reg tl_done_out : UInt<1>, clock, reset + onreset tl_done_out := UInt<1>("h00") + reg make_grant_ack : UInt<1>, clock, reset + onreset make_grant_ack := UInt<1>("h00") + gnt_arb.in[1].valid := UInt<1>("h00") + node T_780 = bits(tag_out, 5, 5) + node T_784 = mux(data_from_rel, UInt<3>("h00"), UInt<3>("h03")) + node T_785 = shr(tag_out, 1) + wire T_817 : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>} + T_817.client_id := UInt<1>("h00") + T_817.g_type := UInt<1>("h00") + T_817.is_builtin_type := UInt<1>("h00") + T_817.manager_xact_id := UInt<1>("h00") + T_817.client_xact_id := UInt<1>("h00") + T_817.data := UInt<1>("h00") + T_817.addr_beat := UInt<1>("h00") + T_817.client_id := T_780 + T_817.is_builtin_type := UInt<1>("h01") + T_817.g_type := T_784 + T_817.client_xact_id := T_785 + T_817.manager_xact_id := UInt<1>("h00") + T_817.addr_beat := UInt<1>("h00") + T_817.data := UInt<1>("h00") + gnt_arb.in[1].bits <> T_817 + mem_1.req_cmd.valid := UInt<1>("h00") + mem_1.req_data.valid := UInt<1>("h00") + mem_1.req_cmd.bits.rw := has_data + mem_1.req_cmd.bits.tag := tag_out + mem_1.req_cmd.bits.addr := addr_out + node T_854 = mux(data_from_rel, tl.release.bits.data, tl.acquire.bits.data) + mem_1.req_data.bits.data := T_854 + node T_856 = eq(active_out, UInt<1>("h00")) + when T_856 : + tl.release.ready := mem_1.req_data.ready + node T_858 = eq(tl.release.valid, UInt<1>("h00")) + node T_859 = and(mem_1.req_data.ready, T_858) + tl.acquire.ready := T_859 + node T_860 = and(tl.release.valid, rel_has_data) + node T_861 = and(tl.acquire.valid, acq_has_data) + node T_862 = or(T_860, T_861) + mem_1.req_data.valid := T_862 + node T_863 = or(tl.release.valid, tl.acquire.valid) + node T_864 = and(mem_1.req_data.ready, T_863) + when T_864 : + node T_866 = eq(mem_1.req_cmd.ready, UInt<1>("h00")) + node T_867 = or(T_866, mem_1.req_data.valid) + active_out := T_867 + mem_1.req_cmd.valid := UInt<1>("h01") + cmd_sent_out := mem_1.req_cmd.ready + tl_done_out := tl_wrap_out + when tl.release.valid : + data_from_rel := UInt<1>("h01") + node T_872 = eq(UInt<1>("h00"), UInt<1>("h00")) + make_grant_ack := T_872 + mem_1.req_data.bits.data := tl.release.bits.data + node T_873 = cat(tl.release.bits.client_xact_id, tl.release.bits.voluntary) + node T_874 = cat(tl.release.bits.client_id, T_873) + mem_1.req_cmd.bits.tag := T_874 + mem_1.req_cmd.bits.addr := tl.release.bits.addr_block + mem_1.req_cmd.bits.rw := rel_has_data + tag_out := T_874 + addr_out := tl.release.bits.addr_block + has_data := rel_has_data + skip + else : + when tl.acquire.valid : + data_from_rel := UInt<1>("h00") + make_grant_ack := acq_has_data + mem_1.req_data.bits.data := tl.acquire.bits.data + mem_1.req_cmd.bits.rw := acq_has_data + node T_876 = cat(tl.acquire.bits.client_xact_id, tl.acquire.bits.is_builtin_type) + node T_877 = cat(tl.acquire.bits.client_id, T_876) + mem_1.req_cmd.bits.tag := T_877 + mem_1.req_cmd.bits.addr := tl.acquire.bits.addr_block + mem_1.req_cmd.bits.rw := acq_has_data + tag_out := T_877 + addr_out := tl.acquire.bits.addr_block + has_data := acq_has_data + skip + skip + skip + skip + when active_out : + node T_879 = eq(cmd_sent_out, UInt<1>("h00")) + mem_1.req_cmd.valid := T_879 + node T_880 = and(mem_1.req_cmd.ready, mem_1.req_cmd.valid) + node T_881 = or(cmd_sent_out, T_880) + cmd_sent_out := T_881 + node T_883 = eq(tl_done_out, UInt<1>("h00")) + node T_884 = and(has_data, T_883) + when T_884 : + when data_from_rel : + tl.release.ready := mem_1.req_data.ready + mem_1.req_data.valid := tl.release.valid + skip + else : + tl.acquire.ready := mem_1.req_data.ready + mem_1.req_data.valid := tl.acquire.valid + skip + skip + when tl_wrap_out : + tl_done_out := UInt<1>("h01") + skip + node T_886 = and(tl_done_out, make_grant_ack) + when T_886 : + gnt_arb.in[1].valid := UInt<1>("h01") + when gnt_arb.in[1].ready : + make_grant_ack := UInt<1>("h00") + skip + skip + node T_890 = eq(has_data, UInt<1>("h00")) + node T_891 = or(T_890, tl_done_out) + node T_892 = and(cmd_sent_out, T_891) + node T_894 = eq(make_grant_ack, UInt<1>("h00")) + node T_895 = and(T_892, T_894) + when T_895 : + active_out := UInt<1>("h00") + skip + skip + reg active_in : UInt<1>, clock, reset + onreset active_in := UInt<1>("h00") + node T_899 = and(tl.grant.ready, tl.grant.valid) + wire T_903 : UInt<3>[1] + T_903[0] := UInt<3>("h05") + node T_906 = eq(T_903[0], tl.grant.bits.g_type) + node T_908 = or(UInt<1>("h00"), T_906) + wire T_910 : UInt<1>[1] + T_910[0] := UInt<1>("h00") + node T_913 = eq(T_910[0], tl.grant.bits.g_type) + node T_915 = or(UInt<1>("h00"), T_913) + node T_916 = mux(tl.grant.bits.is_builtin_type, T_908, T_915) + node T_917 = and(UInt<1>("h01"), T_916) + node T_918 = and(T_899, T_917) + reg tl_cnt_in : UInt<2>, clock, reset + onreset tl_cnt_in := UInt<2>("h00") + when T_918 : + node T_922 = eq(tl_cnt_in, UInt<2>("h03")) + node T_924 = and(UInt<1>("h00"), T_922) + node T_927 = addw(tl_cnt_in, UInt<1>("h01")) + node T_928 = mux(T_924, UInt<1>("h00"), T_927) + tl_cnt_in := T_928 + skip + node tl_wrap_in = and(T_918, T_922) + reg tag_in : UInt<7>, clock, reset + gnt_arb.in[0].valid := mem_1.resp.valid + mem_1.resp.ready := gnt_arb.in[0].ready + node T_932 = bits(mem_1.resp.bits.tag, 5, 5) + node T_933 = bit(mem_1.resp.bits.tag, 0) + node T_934 = bit(mem_1.resp.bits.tag, 0) + node T_937 = mux(T_934, UInt<3>("h05"), UInt<1>("h00")) + node T_938 = shr(mem_1.resp.bits.tag, 1) + wire T_968 : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>} + T_968.client_id := UInt<1>("h00") + T_968.g_type := UInt<1>("h00") + T_968.is_builtin_type := UInt<1>("h00") + T_968.manager_xact_id := UInt<1>("h00") + T_968.client_xact_id := UInt<1>("h00") + T_968.data := UInt<1>("h00") + T_968.addr_beat := UInt<1>("h00") + T_968.client_id := T_932 + T_968.is_builtin_type := T_933 + T_968.g_type := T_937 + T_968.client_xact_id := T_938 + T_968.manager_xact_id := UInt<1>("h00") + T_968.addr_beat := tl_cnt_in + T_968.data := mem_1.resp.bits.data + gnt_arb.in[0].bits <> T_968 + + module HellaFlowQueue : + output count : UInt<6> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.data := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + wire do_flow : UInt<1> + do_flow := UInt<1>("h00") + node T_35 = and(enq.ready, enq.valid) + node T_37 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_35, T_37) + node T_39 = and(deq.ready, deq.valid) + node T_41 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_39, T_41) + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + reg enq_ptr : UInt<6>, clock, reset + onreset enq_ptr := UInt<6>("h00") + when do_enq : + node T_48 = eq(enq_ptr, UInt<6>("h023")) + node T_50 = and(UInt<1>("h01"), T_48) + node T_53 = addw(enq_ptr, UInt<1>("h01")) + node T_54 = mux(T_50, UInt<1>("h00"), T_53) + enq_ptr := T_54 + skip + node T_55 = and(do_enq, T_48) + reg deq_ptr : UInt<6>, clock, reset + onreset deq_ptr := UInt<6>("h00") + when do_deq : + node T_59 = eq(deq_ptr, UInt<6>("h023")) + node T_61 = and(UInt<1>("h01"), T_59) + node T_64 = addw(deq_ptr, UInt<1>("h01")) + node T_65 = mux(T_61, UInt<1>("h00"), T_64) + deq_ptr := T_65 + skip + node deq_done = and(do_deq, T_59) + node T_67 = neq(do_enq, do_deq) + when T_67 : + maybe_full := do_enq + skip + node ptr_match = eq(enq_ptr, deq_ptr) + node T_70 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_70) + node full = and(ptr_match, maybe_full) + node T_73 = subw(enq_ptr, deq_ptr) + node T_75 = geq(T_73, UInt<2>("h02")) + node atLeastTwo = or(full, T_75) + node T_77 = and(empty, deq.ready) + do_flow := T_77 + cmem T_82 : {data : UInt<128>}[36], clock + when do_enq : + infer accessor T_83 = T_82[enq_ptr] + T_83 <> enq.bits + skip + node T_86 = eq(deq.valid, UInt<1>("h00")) + node T_88 = eq(empty, UInt<1>("h00")) + node T_89 = and(T_86, T_88) + node T_90 = or(atLeastTwo, T_89) + node ren = and(deq.ready, T_90) + node T_94 = addw(deq_ptr, UInt<1>("h01")) + node T_95 = mux(deq_done, UInt<1>("h00"), T_94) + node raddr = mux(deq.valid, T_95, deq_ptr) + reg ram_out_valid : UInt<1>, clock, reset + ram_out_valid := ren + node T_98 = mux(empty, enq.valid, ram_out_valid) + deq.valid := T_98 + node T_100 = eq(full, UInt<1>("h00")) + enq.ready := T_100 + reg T_101 : UInt<6>, clock, reset + when ren : + T_101 := raddr + skip + infer accessor T_102 = T_82[T_101] + wire T_106 : {data : UInt<128>} + T_106 <> T_102 + when empty : + T_106 <> enq.bits + skip + deq.bits <> T_106 + + module Queue_43 : + output count : UInt<1> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.data := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : {data : UInt<128>}[1], clock + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_39 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_39) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_45 = and(enq.ready, enq.valid) + node T_47 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_45, T_47) + node T_49 = and(deq.ready, deq.valid) + node T_51 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_49, T_51) + when do_enq : + infer accessor T_53 = ram[UInt<1>("h00")] + T_53 <> enq.bits + skip + when do_deq : + skip + node T_57 = neq(do_enq, do_deq) + when T_57 : + maybe_full := do_enq + skip + node T_59 = eq(empty, UInt<1>("h00")) + node T_61 = and(UInt<1>("h00"), enq.valid) + node T_62 = or(T_59, T_61) + deq.valid := T_62 + node T_64 = eq(full, UInt<1>("h00")) + node T_66 = and(UInt<1>("h01"), deq.ready) + node T_67 = or(T_64, T_66) + enq.ready := T_67 + infer accessor T_68 = ram[UInt<1>("h00")] + wire T_72 : {data : UInt<128>} + T_72 <> T_68 + when maybe_flow : + T_72 <> enq.bits + skip + deq.bits <> T_72 + node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) + node T_75 = and(maybe_full, ptr_match) + node T_76 = cat(T_75, ptr_diff) + count := T_76 + + module HellaQueue : + output count : UInt<6> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.data := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + inst fq of HellaFlowQueue + fq.deq.ready := UInt<1>("h00") + fq.enq.bits.data := UInt<1>("h00") + fq.enq.valid := UInt<1>("h00") + fq.reset := UInt<1>("h00") + fq.clock := clock + fq.reset := reset + fq.enq <> enq + inst T_43 of Queue_43 + T_43.deq.ready := UInt<1>("h00") + T_43.enq.bits.data := UInt<1>("h00") + T_43.enq.valid := UInt<1>("h00") + T_43.reset := UInt<1>("h00") + T_43.clock := clock + T_43.reset := reset + T_43.enq.valid := fq.deq.valid + T_43.enq.bits <> fq.deq.bits + fq.deq.ready := T_43.enq.ready + deq <> T_43.deq + + module HellaFlowQueue_45 : + output count : UInt<6> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<7>}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<7>}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.tag := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + wire do_flow : UInt<1> + do_flow := UInt<1>("h00") + node T_35 = and(enq.ready, enq.valid) + node T_37 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_35, T_37) + node T_39 = and(deq.ready, deq.valid) + node T_41 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_39, T_41) + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + reg enq_ptr : UInt<6>, clock, reset + onreset enq_ptr := UInt<6>("h00") + when do_enq : + node T_48 = eq(enq_ptr, UInt<6>("h023")) + node T_50 = and(UInt<1>("h01"), T_48) + node T_53 = addw(enq_ptr, UInt<1>("h01")) + node T_54 = mux(T_50, UInt<1>("h00"), T_53) + enq_ptr := T_54 + skip + node T_55 = and(do_enq, T_48) + reg deq_ptr : UInt<6>, clock, reset + onreset deq_ptr := UInt<6>("h00") + when do_deq : + node T_59 = eq(deq_ptr, UInt<6>("h023")) + node T_61 = and(UInt<1>("h01"), T_59) + node T_64 = addw(deq_ptr, UInt<1>("h01")) + node T_65 = mux(T_61, UInt<1>("h00"), T_64) + deq_ptr := T_65 + skip + node deq_done = and(do_deq, T_59) + node T_67 = neq(do_enq, do_deq) + when T_67 : + maybe_full := do_enq + skip + node ptr_match = eq(enq_ptr, deq_ptr) + node T_70 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_70) + node full = and(ptr_match, maybe_full) + node T_73 = subw(enq_ptr, deq_ptr) + node T_75 = geq(T_73, UInt<2>("h02")) + node atLeastTwo = or(full, T_75) + node T_77 = and(empty, deq.ready) + do_flow := T_77 + cmem T_82 : {tag : UInt<7>}[36], clock + when do_enq : + infer accessor T_83 = T_82[enq_ptr] + T_83 <> enq.bits + skip + node T_86 = eq(deq.valid, UInt<1>("h00")) + node T_88 = eq(empty, UInt<1>("h00")) + node T_89 = and(T_86, T_88) + node T_90 = or(atLeastTwo, T_89) + node ren = and(deq.ready, T_90) + node T_94 = addw(deq_ptr, UInt<1>("h01")) + node T_95 = mux(deq_done, UInt<1>("h00"), T_94) + node raddr = mux(deq.valid, T_95, deq_ptr) + reg ram_out_valid : UInt<1>, clock, reset + ram_out_valid := ren + node T_98 = mux(empty, enq.valid, ram_out_valid) + deq.valid := T_98 + node T_100 = eq(full, UInt<1>("h00")) + enq.ready := T_100 + reg T_101 : UInt<6>, clock, reset + when ren : + T_101 := raddr + skip + infer accessor T_102 = T_82[T_101] + wire T_106 : {tag : UInt<7>} + T_106 <> T_102 + when empty : + T_106 <> enq.bits + skip + deq.bits <> T_106 + + module Queue_46 : + output count : UInt<1> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<7>}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<7>}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.tag := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : {tag : UInt<7>}[1], clock + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_39 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_39) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_45 = and(enq.ready, enq.valid) + node T_47 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_45, T_47) + node T_49 = and(deq.ready, deq.valid) + node T_51 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_49, T_51) + when do_enq : + infer accessor T_53 = ram[UInt<1>("h00")] + T_53 <> enq.bits + skip + when do_deq : + skip + node T_57 = neq(do_enq, do_deq) + when T_57 : + maybe_full := do_enq + skip + node T_59 = eq(empty, UInt<1>("h00")) + node T_61 = and(UInt<1>("h00"), enq.valid) + node T_62 = or(T_59, T_61) + deq.valid := T_62 + node T_64 = eq(full, UInt<1>("h00")) + node T_66 = and(UInt<1>("h01"), deq.ready) + node T_67 = or(T_64, T_66) + enq.ready := T_67 + infer accessor T_68 = ram[UInt<1>("h00")] + wire T_72 : {tag : UInt<7>} + T_72 <> T_68 + when maybe_flow : + T_72 <> enq.bits + skip + deq.bits <> T_72 + node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) + node T_75 = and(maybe_full, ptr_match) + node T_76 = cat(T_75, ptr_diff) + count := T_76 + + module HellaQueue_44 : + output count : UInt<6> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<7>}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<7>}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.tag := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + inst fq of HellaFlowQueue_45 + fq.deq.ready := UInt<1>("h00") + fq.enq.bits.tag := UInt<1>("h00") + fq.enq.valid := UInt<1>("h00") + fq.reset := UInt<1>("h00") + fq.clock := clock + fq.reset := reset + fq.enq <> enq + inst T_43 of Queue_46 + T_43.deq.ready := UInt<1>("h00") + T_43.enq.bits.tag := UInt<1>("h00") + T_43.enq.valid := UInt<1>("h00") + T_43.reset := UInt<1>("h00") + T_43.clock := clock + T_43.reset := reset + T_43.enq.valid := fq.deq.valid + T_43.enq.bits <> fq.deq.bits + fq.deq.ready := T_43.enq.ready + deq <> T_43.deq + + module MemPipeIOMemIOConverter : + output mem_1 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} + input cpu : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} + input clock : Clock + input reset : UInt<1> + + mem_1.req_data.bits.data := UInt<1>("h00") + mem_1.req_data.valid := UInt<1>("h00") + mem_1.req_cmd.bits.rw := UInt<1>("h00") + mem_1.req_cmd.bits.tag := UInt<1>("h00") + mem_1.req_cmd.bits.addr := UInt<1>("h00") + mem_1.req_cmd.valid := UInt<1>("h00") + cpu.resp.bits.tag := UInt<1>("h00") + cpu.resp.bits.data := UInt<1>("h00") + cpu.resp.valid := UInt<1>("h00") + cpu.req_data.ready := UInt<1>("h00") + cpu.req_cmd.ready := UInt<1>("h00") + wire inc : UInt<1> + inc := UInt<1>("h00") + wire dec : UInt<1> + dec := UInt<1>("h00") + reg count : UInt<6>, clock, reset + onreset count := UInt<6>("h024") + node watermark = geq(count, UInt<3>("h04")) + node T_151 = eq(dec, UInt<1>("h00")) + node T_152 = and(inc, T_151) + when T_152 : + node T_154 = addw(count, UInt<1>("h01")) + count := T_154 + skip + node T_156 = eq(inc, UInt<1>("h00")) + node T_157 = and(T_156, dec) + when T_157 : + node T_159 = subw(count, UInt<3>("h04")) + count := T_159 + skip + node T_160 = and(inc, dec) + when T_160 : + node T_162 = subw(count, UInt<2>("h03")) + count := T_162 + skip + node cmdq_mask = or(cpu.req_cmd.bits.rw, watermark) + node T_164 = and(cpu.req_cmd.valid, cmdq_mask) + mem_1.req_cmd.valid := T_164 + node T_165 = and(mem_1.req_cmd.ready, cmdq_mask) + cpu.req_cmd.ready := T_165 + mem_1.req_cmd.bits <> cpu.req_cmd.bits + mem_1.req_data <> cpu.req_data + inst resp_data_q of HellaQueue + resp_data_q.deq.ready := UInt<1>("h00") + resp_data_q.enq.bits.data := UInt<1>("h00") + resp_data_q.enq.valid := UInt<1>("h00") + resp_data_q.reset := UInt<1>("h00") + resp_data_q.clock := clock + resp_data_q.reset := reset + resp_data_q.enq.valid := mem_1.resp.valid + resp_data_q.enq.bits.data := mem_1.resp.bits.data + inst resp_tag_q of HellaQueue_44 + resp_tag_q.deq.ready := UInt<1>("h00") + resp_tag_q.enq.bits.tag := UInt<1>("h00") + resp_tag_q.enq.valid := UInt<1>("h00") + resp_tag_q.reset := UInt<1>("h00") + resp_tag_q.clock := clock + resp_tag_q.reset := reset + resp_tag_q.enq.valid := mem_1.resp.valid + resp_tag_q.enq.bits.tag := mem_1.resp.bits.tag + node T_174 = and(resp_data_q.deq.valid, resp_tag_q.deq.valid) + cpu.resp.valid := T_174 + cpu.resp.bits.data := resp_data_q.deq.bits.data + cpu.resp.bits.tag := resp_tag_q.deq.bits.tag + resp_data_q.deq.ready := cpu.resp.ready + resp_tag_q.deq.ready := cpu.resp.ready + node T_175 = and(resp_data_q.deq.ready, resp_data_q.deq.valid) + node T_176 = and(resp_tag_q.deq.ready, resp_tag_q.deq.valid) + node T_177 = and(T_175, T_176) + inc := T_177 + node T_178 = and(mem_1.req_cmd.ready, mem_1.req_cmd.valid) + node T_180 = eq(mem_1.req_cmd.bits.rw, UInt<1>("h00")) + node T_181 = and(T_178, T_180) + dec := T_181 + + module Queue_47 : + output count : UInt<2> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.rw := UInt<1>("h00") + deq.bits.tag := UInt<1>("h00") + deq.bits.addr := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}[2], clock + reg T_52 : UInt<1>, clock, reset + onreset T_52 := UInt<1>("h00") + reg T_54 : UInt<1>, clock, reset + onreset T_54 := UInt<1>("h00") + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(T_52, T_54) + node T_59 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_59) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_65 = and(enq.ready, enq.valid) + node T_67 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_65, T_67) + node T_69 = and(deq.ready, deq.valid) + node T_71 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_69, T_71) + when do_enq : + infer accessor T_73 = ram[T_52] + T_73 <> enq.bits + node T_78 = eq(T_52, UInt<1>("h01")) + node T_80 = and(UInt<1>("h00"), T_78) + node T_83 = addw(T_52, UInt<1>("h01")) + node T_84 = mux(T_80, UInt<1>("h00"), T_83) + T_52 := T_84 + skip + when do_deq : + node T_86 = eq(T_54, UInt<1>("h01")) + node T_88 = and(UInt<1>("h00"), T_86) + node T_91 = addw(T_54, UInt<1>("h01")) + node T_92 = mux(T_88, UInt<1>("h00"), T_91) + T_54 := T_92 + skip + node T_93 = neq(do_enq, do_deq) + when T_93 : + maybe_full := do_enq + skip + node T_95 = eq(empty, UInt<1>("h00")) + node T_97 = and(UInt<1>("h00"), enq.valid) + node T_98 = or(T_95, T_97) + deq.valid := T_98 + node T_100 = eq(full, UInt<1>("h00")) + node T_102 = and(UInt<1>("h01"), deq.ready) + node T_103 = or(T_100, T_102) + enq.ready := T_103 + infer accessor T_104 = ram[T_54] + wire T_112 : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>} + T_112 <> T_104 + when maybe_flow : + T_112 <> enq.bits + skip + deq.bits <> T_112 + node ptr_diff = subw(T_52, T_54) + node T_117 = and(maybe_full, ptr_match) + node T_118 = cat(T_117, ptr_diff) + count := T_118 + + module Queue_48 : + output count : UInt<3> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.data := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : {data : UInt<128>}[4], clock + reg T_34 : UInt<2>, clock, reset + onreset T_34 := UInt<2>("h00") + reg T_36 : UInt<2>, clock, reset + onreset T_36 := UInt<2>("h00") + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(T_34, T_36) + node T_41 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_41) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_47 = and(enq.ready, enq.valid) + node T_49 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_47, T_49) + node T_51 = and(deq.ready, deq.valid) + node T_53 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_51, T_53) + when do_enq : + infer accessor T_55 = ram[T_34] + T_55 <> enq.bits + node T_58 = eq(T_34, UInt<2>("h03")) + node T_60 = and(UInt<1>("h00"), T_58) + node T_63 = addw(T_34, UInt<1>("h01")) + node T_64 = mux(T_60, UInt<1>("h00"), T_63) + T_34 := T_64 + skip + when do_deq : + node T_66 = eq(T_36, UInt<2>("h03")) + node T_68 = and(UInt<1>("h00"), T_66) + node T_71 = addw(T_36, UInt<1>("h01")) + node T_72 = mux(T_68, UInt<1>("h00"), T_71) + T_36 := T_72 + skip + node T_73 = neq(do_enq, do_deq) + when T_73 : + maybe_full := do_enq + skip + node T_75 = eq(empty, UInt<1>("h00")) + node T_77 = and(UInt<1>("h00"), enq.valid) + node T_78 = or(T_75, T_77) + deq.valid := T_78 + node T_80 = eq(full, UInt<1>("h00")) + node T_82 = and(UInt<1>("h01"), deq.ready) + node T_83 = or(T_80, T_82) + enq.ready := T_83 + infer accessor T_84 = ram[T_36] + wire T_88 : {data : UInt<128>} + T_88 <> T_84 + when maybe_flow : + T_88 <> enq.bits + skip + deq.bits <> T_88 + node ptr_diff = subw(T_34, T_36) + node T_91 = and(maybe_full, ptr_match) + node T_92 = cat(T_91, ptr_diff) + count := T_92 + + module MemPipeIOTileLinkIOConverter : + output mem_1 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} + output tl : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<1>}}} + input clock : Clock + input reset : UInt<1> + + mem_1.req_data.bits.data := UInt<1>("h00") + mem_1.req_data.valid := UInt<1>("h00") + mem_1.req_cmd.bits.rw := UInt<1>("h00") + mem_1.req_cmd.bits.tag := UInt<1>("h00") + mem_1.req_cmd.bits.addr := UInt<1>("h00") + mem_1.req_cmd.valid := UInt<1>("h00") + tl.release.ready := UInt<1>("h00") + tl.probe.bits.client_id := UInt<1>("h00") + tl.probe.bits.p_type := UInt<1>("h00") + tl.probe.bits.addr_block := UInt<1>("h00") + tl.probe.valid := UInt<1>("h00") + tl.finish.ready := UInt<1>("h00") + tl.grant.bits.client_id := UInt<1>("h00") + tl.grant.bits.g_type := UInt<1>("h00") + tl.grant.bits.is_builtin_type := UInt<1>("h00") + tl.grant.bits.manager_xact_id := UInt<1>("h00") + tl.grant.bits.client_xact_id := UInt<1>("h00") + tl.grant.bits.data := UInt<1>("h00") + tl.grant.bits.addr_beat := UInt<1>("h00") + tl.grant.valid := UInt<1>("h00") + tl.acquire.ready := UInt<1>("h00") + inst a of MemIOTileLinkIOConverter + a.mem_1.resp.bits.tag := UInt<1>("h00") + a.mem_1.resp.bits.data := UInt<1>("h00") + a.mem_1.resp.valid := UInt<1>("h00") + a.mem_1.req_data.ready := UInt<1>("h00") + a.mem_1.req_cmd.ready := UInt<1>("h00") + a.tl.release.bits.client_id := UInt<1>("h00") + a.tl.release.bits.voluntary := UInt<1>("h00") + a.tl.release.bits.r_type := UInt<1>("h00") + a.tl.release.bits.data := UInt<1>("h00") + a.tl.release.bits.addr_beat := UInt<1>("h00") + a.tl.release.bits.client_xact_id := UInt<1>("h00") + a.tl.release.bits.addr_block := UInt<1>("h00") + a.tl.release.valid := UInt<1>("h00") + a.tl.probe.ready := UInt<1>("h00") + a.tl.finish.bits.manager_xact_id := UInt<1>("h00") + a.tl.finish.valid := UInt<1>("h00") + a.tl.grant.ready := UInt<1>("h00") + a.tl.acquire.bits.client_id := UInt<1>("h00") + a.tl.acquire.bits.union := UInt<1>("h00") + a.tl.acquire.bits.a_type := UInt<1>("h00") + a.tl.acquire.bits.is_builtin_type := UInt<1>("h00") + a.tl.acquire.bits.data := UInt<1>("h00") + a.tl.acquire.bits.addr_beat := UInt<1>("h00") + a.tl.acquire.bits.client_xact_id := UInt<1>("h00") + a.tl.acquire.bits.addr_block := UInt<1>("h00") + a.tl.acquire.valid := UInt<1>("h00") + a.reset := UInt<1>("h00") + a.clock := clock + a.reset := reset + inst b of MemPipeIOMemIOConverter + b.mem_1.resp.bits.tag := UInt<1>("h00") + b.mem_1.resp.bits.data := UInt<1>("h00") + b.mem_1.resp.valid := UInt<1>("h00") + b.mem_1.req_data.ready := UInt<1>("h00") + b.mem_1.req_cmd.ready := UInt<1>("h00") + b.cpu.resp.ready := UInt<1>("h00") + b.cpu.req_data.bits.data := UInt<1>("h00") + b.cpu.req_data.valid := UInt<1>("h00") + b.cpu.req_cmd.bits.rw := UInt<1>("h00") + b.cpu.req_cmd.bits.tag := UInt<1>("h00") + b.cpu.req_cmd.bits.addr := UInt<1>("h00") + b.cpu.req_cmd.valid := UInt<1>("h00") + b.reset := UInt<1>("h00") + b.clock := clock + b.reset := reset + tl <> a.tl + inst T_702 of Queue_47 + T_702.deq.ready := UInt<1>("h00") + T_702.enq.bits.rw := UInt<1>("h00") + T_702.enq.bits.tag := UInt<1>("h00") + T_702.enq.bits.addr := UInt<1>("h00") + T_702.enq.valid := UInt<1>("h00") + T_702.reset := UInt<1>("h00") + T_702.clock := clock + T_702.reset := reset + T_702.enq.valid := a.mem_1.req_cmd.valid + T_702.enq.bits <> a.mem_1.req_cmd.bits + a.mem_1.req_cmd.ready := T_702.enq.ready + b.cpu.req_cmd <> T_702.deq + inst T_703 of Queue_48 + T_703.deq.ready := UInt<1>("h00") + T_703.enq.bits.data := UInt<1>("h00") + T_703.enq.valid := UInt<1>("h00") + T_703.reset := UInt<1>("h00") + T_703.clock := clock + T_703.reset := reset + T_703.enq.valid := a.mem_1.req_data.valid + T_703.enq.bits <> a.mem_1.req_data.bits + a.mem_1.req_data.ready := T_703.enq.ready + b.cpu.req_data <> T_703.deq + a.mem_1.resp <> b.cpu.resp + mem_1 <> b.mem_1 + + module ClientTileLinkIOWrapper_49 : + output out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + input in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input clock : Clock + input reset : UInt<1> + + out.release.bits.voluntary := UInt<1>("h00") + out.release.bits.r_type := UInt<1>("h00") + out.release.bits.data := UInt<1>("h00") + out.release.bits.addr_beat := UInt<1>("h00") + out.release.bits.client_xact_id := UInt<1>("h00") + out.release.bits.addr_block := UInt<1>("h00") + out.release.valid := UInt<1>("h00") + out.probe.ready := UInt<1>("h00") + out.grant.ready := UInt<1>("h00") + out.acquire.bits.union := UInt<1>("h00") + out.acquire.bits.a_type := UInt<1>("h00") + out.acquire.bits.is_builtin_type := UInt<1>("h00") + out.acquire.bits.data := UInt<1>("h00") + out.acquire.bits.addr_beat := UInt<1>("h00") + out.acquire.bits.client_xact_id := UInt<1>("h00") + out.acquire.bits.addr_block := UInt<1>("h00") + out.acquire.valid := UInt<1>("h00") + in.grant.bits.g_type := UInt<1>("h00") + in.grant.bits.is_builtin_type := UInt<1>("h00") + in.grant.bits.manager_xact_id := UInt<1>("h00") + in.grant.bits.client_xact_id := UInt<1>("h00") + in.grant.bits.data := UInt<1>("h00") + in.grant.bits.addr_beat := UInt<1>("h00") + in.grant.valid := UInt<1>("h00") + in.acquire.ready := UInt<1>("h00") + out.acquire <> in.acquire + in.grant <> out.grant + out.probe.ready := UInt<1>("h01") + out.release.valid := UInt<1>("h00") + + module MemIOArbiter : + output outer : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} + input inner : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}}[1] + input clock : Clock + input reset : UInt<1> + + outer.resp.ready := UInt<1>("h00") + outer.req_data.bits.data := UInt<1>("h00") + outer.req_data.valid := UInt<1>("h00") + outer.req_cmd.bits.rw := UInt<1>("h00") + outer.req_cmd.bits.tag := UInt<1>("h00") + outer.req_cmd.bits.addr := UInt<1>("h00") + outer.req_cmd.valid := UInt<1>("h00") + inner[0].resp.bits.tag := UInt<1>("h00") + inner[0].resp.bits.data := UInt<1>("h00") + inner[0].resp.valid := UInt<1>("h00") + inner[0].req_data.ready := UInt<1>("h00") + inner[0].req_cmd.ready := UInt<1>("h00") + outer <> inner[0] + + module MemSerdes : + output narrow : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}} + input wide : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} + input clock : Clock + input reset : UInt<1> + + narrow.req.bits := UInt<1>("h00") + narrow.req.valid := UInt<1>("h00") + wide.resp.bits.tag := UInt<1>("h00") + wide.resp.bits.data := UInt<1>("h00") + wide.resp.valid := UInt<1>("h00") + wide.req_data.ready := UInt<1>("h00") + wide.req_cmd.ready := UInt<1>("h00") + node T_111 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw) + node T_112 = cat(wide.req_cmd.bits.addr, T_111) + reg out_buf : UInt<?>, clock, reset + reg in_buf : UInt<?>, clock, reset + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg send_cnt : UInt<3>, clock, reset + onreset send_cnt := UInt<3>("h00") + reg data_send_cnt : UInt<2>, clock, reset + onreset data_send_cnt := UInt<2>("h00") + node T_129 = eq(send_cnt, UInt<2>("h02")) + node adone = and(narrow.req.ready, T_129) + node T_132 = eq(send_cnt, UInt<3>("h07")) + node ddone = and(narrow.req.ready, T_132) + node T_134 = and(narrow.req.valid, narrow.req.ready) + when T_134 : + node T_136 = addw(send_cnt, UInt<1>("h01")) + send_cnt := T_136 + node T_138 = dshr(out_buf, UInt<5>("h010")) + out_buf := T_138 + skip + node T_139 = and(wide.req_cmd.valid, wide.req_cmd.ready) + when T_139 : + node T_140 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw) + node T_141 = cat(wide.req_cmd.bits.addr, T_140) + out_buf := T_141 + skip + node T_142 = and(wide.req_data.valid, wide.req_data.ready) + when T_142 : + out_buf := wide.req_data.bits.data + skip + node T_143 = eq(state, UInt<1>("h00")) + wide.req_cmd.ready := T_143 + node T_144 = eq(state, UInt<2>("h03")) + wide.req_data.ready := T_144 + node T_145 = eq(state, UInt<1>("h01")) + node T_146 = eq(state, UInt<2>("h02")) + node T_147 = or(T_145, T_146) + node T_148 = eq(state, UInt<3>("h04")) + node T_149 = or(T_147, T_148) + narrow.req.valid := T_149 + narrow.req.bits := out_buf + node T_150 = eq(state, UInt<1>("h00")) + node T_151 = and(T_150, wide.req_cmd.valid) + when T_151 : + node T_152 = mux(wide.req_cmd.bits.rw, UInt<2>("h02"), UInt<1>("h01")) + state := T_152 + skip + node T_153 = eq(state, UInt<1>("h01")) + node T_154 = and(T_153, adone) + when T_154 : + state := UInt<1>("h00") + send_cnt := UInt<1>("h00") + skip + node T_156 = eq(state, UInt<2>("h02")) + node T_157 = and(T_156, adone) + when T_157 : + state := UInt<2>("h03") + send_cnt := UInt<1>("h00") + skip + node T_159 = eq(state, UInt<2>("h03")) + node T_160 = and(T_159, wide.req_data.valid) + when T_160 : + state := UInt<3>("h04") + skip + node T_161 = eq(state, UInt<3>("h04")) + node T_162 = and(T_161, ddone) + when T_162 : + node T_164 = addw(data_send_cnt, UInt<1>("h01")) + data_send_cnt := T_164 + node T_166 = eq(data_send_cnt, UInt<2>("h03")) + node T_167 = mux(T_166, UInt<1>("h00"), UInt<2>("h03")) + state := T_167 + send_cnt := UInt<1>("h00") + skip + reg recv_cnt : UInt<4>, clock, reset + onreset recv_cnt := UInt<4>("h00") + reg data_recv_cnt : UInt<2>, clock, reset + onreset data_recv_cnt := UInt<2>("h00") + reg resp_val : UInt<1>, clock, reset + onreset resp_val := UInt<1>("h00") + resp_val := UInt<1>("h00") + when narrow.resp.valid : + node T_177 = addw(recv_cnt, UInt<1>("h01")) + recv_cnt := T_177 + node T_179 = eq(recv_cnt, UInt<4>("h08")) + when T_179 : + recv_cnt := UInt<1>("h00") + node T_182 = addw(data_recv_cnt, UInt<1>("h01")) + data_recv_cnt := T_182 + resp_val := UInt<1>("h01") + skip + node T_184 = bits(in_buf, 143, 16) + node T_185 = cat(narrow.resp.bits, T_184) + in_buf := T_185 + skip + wide.resp.valid := resp_val + wire T_189 : {data : UInt<128>, tag : UInt<7>} + T_189.tag := UInt<1>("h00") + T_189.data := UInt<1>("h00") + node T_194 = bits(in_buf, 6, 0) + T_189.tag := T_194 + node T_195 = bits(in_buf, 134, 7) + T_189.data := T_195 + wide.resp.bits <> T_189 + + module OuterMemorySystem : + input mem_backup_en : UInt<1> + output mem_backup : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}} + output mem_1 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}}[1] + input incoherent : UInt<1>[1] + input htif_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}[1] + input tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[1] + input clock : Clock + input reset : UInt<1> + + mem_backup.req.bits := UInt<1>("h00") + mem_backup.req.valid := UInt<1>("h00") + mem_1[0].resp.ready := UInt<1>("h00") + mem_1[0].req_data.bits.data := UInt<1>("h00") + mem_1[0].req_data.valid := UInt<1>("h00") + mem_1[0].req_cmd.bits.rw := UInt<1>("h00") + mem_1[0].req_cmd.bits.tag := UInt<1>("h00") + mem_1[0].req_cmd.bits.addr := UInt<1>("h00") + mem_1[0].req_cmd.valid := UInt<1>("h00") + htif_uncached.grant.bits.g_type := UInt<1>("h00") + htif_uncached.grant.bits.is_builtin_type := UInt<1>("h00") + htif_uncached.grant.bits.manager_xact_id := UInt<1>("h00") + htif_uncached.grant.bits.client_xact_id := UInt<1>("h00") + htif_uncached.grant.bits.data := UInt<1>("h00") + htif_uncached.grant.bits.addr_beat := UInt<1>("h00") + htif_uncached.grant.valid := UInt<1>("h00") + htif_uncached.acquire.ready := UInt<1>("h00") + tiles_uncached[0].grant.bits.g_type := UInt<1>("h00") + tiles_uncached[0].grant.bits.is_builtin_type := UInt<1>("h00") + tiles_uncached[0].grant.bits.manager_xact_id := UInt<1>("h00") + tiles_uncached[0].grant.bits.client_xact_id := UInt<1>("h00") + tiles_uncached[0].grant.bits.data := UInt<1>("h00") + tiles_uncached[0].grant.bits.addr_beat := UInt<1>("h00") + tiles_uncached[0].grant.valid := UInt<1>("h00") + tiles_uncached[0].acquire.ready := UInt<1>("h00") + tiles_cached[0].release.ready := UInt<1>("h00") + tiles_cached[0].probe.bits.p_type := UInt<1>("h00") + tiles_cached[0].probe.bits.addr_block := UInt<1>("h00") + tiles_cached[0].probe.valid := UInt<1>("h00") + tiles_cached[0].grant.bits.g_type := UInt<1>("h00") + tiles_cached[0].grant.bits.is_builtin_type := UInt<1>("h00") + tiles_cached[0].grant.bits.manager_xact_id := UInt<1>("h00") + tiles_cached[0].grant.bits.client_xact_id := UInt<1>("h00") + tiles_cached[0].grant.bits.data := UInt<1>("h00") + tiles_cached[0].grant.bits.addr_beat := UInt<1>("h00") + tiles_cached[0].grant.valid := UInt<1>("h00") + tiles_cached[0].acquire.ready := UInt<1>("h00") + inst T_7394 of ClientTileLinkIOWrapper + T_7394.out.release.ready := UInt<1>("h00") + T_7394.out.probe.bits.p_type := UInt<1>("h00") + T_7394.out.probe.bits.addr_block := UInt<1>("h00") + T_7394.out.probe.valid := UInt<1>("h00") + T_7394.out.grant.bits.g_type := UInt<1>("h00") + T_7394.out.grant.bits.is_builtin_type := UInt<1>("h00") + T_7394.out.grant.bits.manager_xact_id := UInt<1>("h00") + T_7394.out.grant.bits.client_xact_id := UInt<1>("h00") + T_7394.out.grant.bits.data := UInt<1>("h00") + T_7394.out.grant.bits.addr_beat := UInt<1>("h00") + T_7394.out.grant.valid := UInt<1>("h00") + T_7394.out.acquire.ready := UInt<1>("h00") + T_7394.in.grant.ready := UInt<1>("h00") + T_7394.in.acquire.bits.union := UInt<1>("h00") + T_7394.in.acquire.bits.a_type := UInt<1>("h00") + T_7394.in.acquire.bits.is_builtin_type := UInt<1>("h00") + T_7394.in.acquire.bits.data := UInt<1>("h00") + T_7394.in.acquire.bits.addr_beat := UInt<1>("h00") + T_7394.in.acquire.bits.client_xact_id := UInt<1>("h00") + T_7394.in.acquire.bits.addr_block := UInt<1>("h00") + T_7394.in.acquire.valid := UInt<1>("h00") + T_7394.reset := UInt<1>("h00") + T_7394.clock := clock + T_7394.reset := reset + T_7394.in <> tiles_uncached[0] + inst T_7395 of ClientTileLinkIOWrapper + T_7395.out.release.ready := UInt<1>("h00") + T_7395.out.probe.bits.p_type := UInt<1>("h00") + T_7395.out.probe.bits.addr_block := UInt<1>("h00") + T_7395.out.probe.valid := UInt<1>("h00") + T_7395.out.grant.bits.g_type := UInt<1>("h00") + T_7395.out.grant.bits.is_builtin_type := UInt<1>("h00") + T_7395.out.grant.bits.manager_xact_id := UInt<1>("h00") + T_7395.out.grant.bits.client_xact_id := UInt<1>("h00") + T_7395.out.grant.bits.data := UInt<1>("h00") + T_7395.out.grant.bits.addr_beat := UInt<1>("h00") + T_7395.out.grant.valid := UInt<1>("h00") + T_7395.out.acquire.ready := UInt<1>("h00") + T_7395.in.grant.ready := UInt<1>("h00") + T_7395.in.acquire.bits.union := UInt<1>("h00") + T_7395.in.acquire.bits.a_type := UInt<1>("h00") + T_7395.in.acquire.bits.is_builtin_type := UInt<1>("h00") + T_7395.in.acquire.bits.data := UInt<1>("h00") + T_7395.in.acquire.bits.addr_beat := UInt<1>("h00") + T_7395.in.acquire.bits.client_xact_id := UInt<1>("h00") + T_7395.in.acquire.bits.addr_block := UInt<1>("h00") + T_7395.in.acquire.valid := UInt<1>("h00") + T_7395.reset := UInt<1>("h00") + T_7395.clock := clock + T_7395.reset := reset + T_7395.in <> htif_uncached + inst l1tol2net of RocketChipTileLinkArbiter + l1tol2net.managers[0].release.ready := UInt<1>("h00") + l1tol2net.managers[0].probe.bits.client_id := UInt<1>("h00") + l1tol2net.managers[0].probe.bits.p_type := UInt<1>("h00") + l1tol2net.managers[0].probe.bits.addr_block := UInt<1>("h00") + l1tol2net.managers[0].probe.valid := UInt<1>("h00") + l1tol2net.managers[0].finish.ready := UInt<1>("h00") + l1tol2net.managers[0].grant.bits.client_id := UInt<1>("h00") + l1tol2net.managers[0].grant.bits.g_type := UInt<1>("h00") + l1tol2net.managers[0].grant.bits.is_builtin_type := UInt<1>("h00") + l1tol2net.managers[0].grant.bits.manager_xact_id := UInt<1>("h00") + l1tol2net.managers[0].grant.bits.client_xact_id := UInt<1>("h00") + l1tol2net.managers[0].grant.bits.data := UInt<1>("h00") + l1tol2net.managers[0].grant.bits.addr_beat := UInt<1>("h00") + l1tol2net.managers[0].grant.valid := UInt<1>("h00") + l1tol2net.managers[0].acquire.ready := UInt<1>("h00") + l1tol2net.clients[0].release.bits.voluntary := UInt<1>("h00") + l1tol2net.clients[0].release.bits.r_type := UInt<1>("h00") + l1tol2net.clients[0].release.bits.data := UInt<1>("h00") + l1tol2net.clients[0].release.bits.addr_beat := UInt<1>("h00") + l1tol2net.clients[0].release.bits.client_xact_id := UInt<1>("h00") + l1tol2net.clients[0].release.bits.addr_block := UInt<1>("h00") + l1tol2net.clients[0].release.valid := UInt<1>("h00") + l1tol2net.clients[0].probe.ready := UInt<1>("h00") + l1tol2net.clients[0].grant.ready := UInt<1>("h00") + l1tol2net.clients[0].acquire.bits.union := UInt<1>("h00") + l1tol2net.clients[0].acquire.bits.a_type := UInt<1>("h00") + l1tol2net.clients[0].acquire.bits.is_builtin_type := UInt<1>("h00") + l1tol2net.clients[0].acquire.bits.data := UInt<1>("h00") + l1tol2net.clients[0].acquire.bits.addr_beat := UInt<1>("h00") + l1tol2net.clients[0].acquire.bits.client_xact_id := UInt<1>("h00") + l1tol2net.clients[0].acquire.bits.addr_block := UInt<1>("h00") + l1tol2net.clients[0].acquire.valid := UInt<1>("h00") + l1tol2net.clients[1].release.bits.voluntary := UInt<1>("h00") + l1tol2net.clients[1].release.bits.r_type := UInt<1>("h00") + l1tol2net.clients[1].release.bits.data := UInt<1>("h00") + l1tol2net.clients[1].release.bits.addr_beat := UInt<1>("h00") + l1tol2net.clients[1].release.bits.client_xact_id := UInt<1>("h00") + l1tol2net.clients[1].release.bits.addr_block := UInt<1>("h00") + l1tol2net.clients[1].release.valid := UInt<1>("h00") + l1tol2net.clients[1].probe.ready := UInt<1>("h00") + l1tol2net.clients[1].grant.ready := UInt<1>("h00") + l1tol2net.clients[1].acquire.bits.union := UInt<1>("h00") + l1tol2net.clients[1].acquire.bits.a_type := UInt<1>("h00") + l1tol2net.clients[1].acquire.bits.is_builtin_type := UInt<1>("h00") + l1tol2net.clients[1].acquire.bits.data := UInt<1>("h00") + l1tol2net.clients[1].acquire.bits.addr_beat := UInt<1>("h00") + l1tol2net.clients[1].acquire.bits.client_xact_id := UInt<1>("h00") + l1tol2net.clients[1].acquire.bits.addr_block := UInt<1>("h00") + l1tol2net.clients[1].acquire.valid := UInt<1>("h00") + l1tol2net.clients[2].release.bits.voluntary := UInt<1>("h00") + l1tol2net.clients[2].release.bits.r_type := UInt<1>("h00") + l1tol2net.clients[2].release.bits.data := UInt<1>("h00") + l1tol2net.clients[2].release.bits.addr_beat := UInt<1>("h00") + l1tol2net.clients[2].release.bits.client_xact_id := UInt<1>("h00") + l1tol2net.clients[2].release.bits.addr_block := UInt<1>("h00") + l1tol2net.clients[2].release.valid := UInt<1>("h00") + l1tol2net.clients[2].probe.ready := UInt<1>("h00") + l1tol2net.clients[2].grant.ready := UInt<1>("h00") + l1tol2net.clients[2].acquire.bits.union := UInt<1>("h00") + l1tol2net.clients[2].acquire.bits.a_type := UInt<1>("h00") + l1tol2net.clients[2].acquire.bits.is_builtin_type := UInt<1>("h00") + l1tol2net.clients[2].acquire.bits.data := UInt<1>("h00") + l1tol2net.clients[2].acquire.bits.addr_beat := UInt<1>("h00") + l1tol2net.clients[2].acquire.bits.client_xact_id := UInt<1>("h00") + l1tol2net.clients[2].acquire.bits.addr_block := UInt<1>("h00") + l1tol2net.clients[2].acquire.valid := UInt<1>("h00") + l1tol2net.reset := UInt<1>("h00") + l1tol2net.clock := clock + l1tol2net.reset := reset + inst T_7397 of L2BroadcastHub + T_7397.outer.grant.bits.g_type := UInt<1>("h00") + T_7397.outer.grant.bits.is_builtin_type := UInt<1>("h00") + T_7397.outer.grant.bits.manager_xact_id := UInt<1>("h00") + T_7397.outer.grant.bits.client_xact_id := UInt<1>("h00") + T_7397.outer.grant.bits.data := UInt<1>("h00") + T_7397.outer.grant.bits.addr_beat := UInt<1>("h00") + T_7397.outer.grant.valid := UInt<1>("h00") + T_7397.outer.acquire.ready := UInt<1>("h00") + T_7397.incoherent[0] := UInt<1>("h00") + T_7397.inner.release.bits.client_id := UInt<1>("h00") + T_7397.inner.release.bits.voluntary := UInt<1>("h00") + T_7397.inner.release.bits.r_type := UInt<1>("h00") + T_7397.inner.release.bits.data := UInt<1>("h00") + T_7397.inner.release.bits.addr_beat := UInt<1>("h00") + T_7397.inner.release.bits.client_xact_id := UInt<1>("h00") + T_7397.inner.release.bits.addr_block := UInt<1>("h00") + T_7397.inner.release.valid := UInt<1>("h00") + T_7397.inner.probe.ready := UInt<1>("h00") + T_7397.inner.finish.bits.manager_xact_id := UInt<1>("h00") + T_7397.inner.finish.valid := UInt<1>("h00") + T_7397.inner.grant.ready := UInt<1>("h00") + T_7397.inner.acquire.bits.client_id := UInt<1>("h00") + T_7397.inner.acquire.bits.union := UInt<1>("h00") + T_7397.inner.acquire.bits.a_type := UInt<1>("h00") + T_7397.inner.acquire.bits.is_builtin_type := UInt<1>("h00") + T_7397.inner.acquire.bits.data := UInt<1>("h00") + T_7397.inner.acquire.bits.addr_beat := UInt<1>("h00") + T_7397.inner.acquire.bits.client_xact_id := UInt<1>("h00") + T_7397.inner.acquire.bits.addr_block := UInt<1>("h00") + T_7397.inner.acquire.valid := UInt<1>("h00") + T_7397.reset := UInt<1>("h00") + T_7397.clock := clock + T_7397.reset := reset + T_7397.incoherent := incoherent + l1tol2net.clients[0] <> tiles_cached[0] + l1tol2net.clients[1] <> T_7394.out + l1tol2net.clients[2] <> T_7395.out + l1tol2net.managers[0] <> T_7397.inner + inst T_7398 of RocketChipTileLinkArbiter_36 + T_7398.managers[0].release.ready := UInt<1>("h00") + T_7398.managers[0].probe.bits.client_id := UInt<1>("h00") + T_7398.managers[0].probe.bits.p_type := UInt<1>("h00") + T_7398.managers[0].probe.bits.addr_block := UInt<1>("h00") + T_7398.managers[0].probe.valid := UInt<1>("h00") + T_7398.managers[0].finish.ready := UInt<1>("h00") + T_7398.managers[0].grant.bits.client_id := UInt<1>("h00") + T_7398.managers[0].grant.bits.g_type := UInt<1>("h00") + T_7398.managers[0].grant.bits.is_builtin_type := UInt<1>("h00") + T_7398.managers[0].grant.bits.manager_xact_id := UInt<1>("h00") + T_7398.managers[0].grant.bits.client_xact_id := UInt<1>("h00") + T_7398.managers[0].grant.bits.data := UInt<1>("h00") + T_7398.managers[0].grant.bits.addr_beat := UInt<1>("h00") + T_7398.managers[0].grant.valid := UInt<1>("h00") + T_7398.managers[0].acquire.ready := UInt<1>("h00") + T_7398.clients[0].release.bits.voluntary := UInt<1>("h00") + T_7398.clients[0].release.bits.r_type := UInt<1>("h00") + T_7398.clients[0].release.bits.data := UInt<1>("h00") + T_7398.clients[0].release.bits.addr_beat := UInt<1>("h00") + T_7398.clients[0].release.bits.client_xact_id := UInt<1>("h00") + T_7398.clients[0].release.bits.addr_block := UInt<1>("h00") + T_7398.clients[0].release.valid := UInt<1>("h00") + T_7398.clients[0].probe.ready := UInt<1>("h00") + T_7398.clients[0].grant.ready := UInt<1>("h00") + T_7398.clients[0].acquire.bits.union := UInt<1>("h00") + T_7398.clients[0].acquire.bits.a_type := UInt<1>("h00") + T_7398.clients[0].acquire.bits.is_builtin_type := UInt<1>("h00") + T_7398.clients[0].acquire.bits.data := UInt<1>("h00") + T_7398.clients[0].acquire.bits.addr_beat := UInt<1>("h00") + T_7398.clients[0].acquire.bits.client_xact_id := UInt<1>("h00") + T_7398.clients[0].acquire.bits.addr_block := UInt<1>("h00") + T_7398.clients[0].acquire.valid := UInt<1>("h00") + T_7398.reset := UInt<1>("h00") + T_7398.clock := clock + T_7398.reset := reset + inst T_7399 of MemPipeIOTileLinkIOConverter + T_7399.mem_1.resp.bits.tag := UInt<1>("h00") + T_7399.mem_1.resp.bits.data := UInt<1>("h00") + T_7399.mem_1.resp.valid := UInt<1>("h00") + T_7399.mem_1.req_data.ready := UInt<1>("h00") + T_7399.mem_1.req_cmd.ready := UInt<1>("h00") + T_7399.tl.release.bits.client_id := UInt<1>("h00") + T_7399.tl.release.bits.voluntary := UInt<1>("h00") + T_7399.tl.release.bits.r_type := UInt<1>("h00") + T_7399.tl.release.bits.data := UInt<1>("h00") + T_7399.tl.release.bits.addr_beat := UInt<1>("h00") + T_7399.tl.release.bits.client_xact_id := UInt<1>("h00") + T_7399.tl.release.bits.addr_block := UInt<1>("h00") + T_7399.tl.release.valid := UInt<1>("h00") + T_7399.tl.probe.ready := UInt<1>("h00") + T_7399.tl.finish.bits.manager_xact_id := UInt<1>("h00") + T_7399.tl.finish.valid := UInt<1>("h00") + T_7399.tl.grant.ready := UInt<1>("h00") + T_7399.tl.acquire.bits.client_id := UInt<1>("h00") + T_7399.tl.acquire.bits.union := UInt<1>("h00") + T_7399.tl.acquire.bits.a_type := UInt<1>("h00") + T_7399.tl.acquire.bits.is_builtin_type := UInt<1>("h00") + T_7399.tl.acquire.bits.data := UInt<1>("h00") + T_7399.tl.acquire.bits.addr_beat := UInt<1>("h00") + T_7399.tl.acquire.bits.client_xact_id := UInt<1>("h00") + T_7399.tl.acquire.bits.addr_block := UInt<1>("h00") + T_7399.tl.acquire.valid := UInt<1>("h00") + T_7399.reset := UInt<1>("h00") + T_7399.clock := clock + T_7399.reset := reset + inst T_7400 of ClientTileLinkIOWrapper_49 + T_7400.out.release.ready := UInt<1>("h00") + T_7400.out.probe.bits.p_type := UInt<1>("h00") + T_7400.out.probe.bits.addr_block := UInt<1>("h00") + T_7400.out.probe.valid := UInt<1>("h00") + T_7400.out.grant.bits.g_type := UInt<1>("h00") + T_7400.out.grant.bits.is_builtin_type := UInt<1>("h00") + T_7400.out.grant.bits.manager_xact_id := UInt<1>("h00") + T_7400.out.grant.bits.client_xact_id := UInt<1>("h00") + T_7400.out.grant.bits.data := UInt<1>("h00") + T_7400.out.grant.bits.addr_beat := UInt<1>("h00") + T_7400.out.grant.valid := UInt<1>("h00") + T_7400.out.acquire.ready := UInt<1>("h00") + T_7400.in.grant.ready := UInt<1>("h00") + T_7400.in.acquire.bits.union := UInt<1>("h00") + T_7400.in.acquire.bits.a_type := UInt<1>("h00") + T_7400.in.acquire.bits.is_builtin_type := UInt<1>("h00") + T_7400.in.acquire.bits.data := UInt<1>("h00") + T_7400.in.acquire.bits.addr_beat := UInt<1>("h00") + T_7400.in.acquire.bits.client_xact_id := UInt<1>("h00") + T_7400.in.acquire.bits.addr_block := UInt<1>("h00") + T_7400.in.acquire.valid := UInt<1>("h00") + T_7400.reset := UInt<1>("h00") + T_7400.clock := clock + T_7400.reset := reset + T_7400.in <> T_7397.outer + T_7398.clients[0] <> T_7400.out + T_7398.managers[0] <> T_7399.tl + wire T_7290 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} + T_7290.resp.bits.tag := UInt<1>("h00") + T_7290.resp.bits.data := UInt<1>("h00") + T_7290.resp.valid := UInt<1>("h00") + T_7290.resp.ready := UInt<1>("h00") + T_7290.req_data.bits.data := UInt<1>("h00") + T_7290.req_data.valid := UInt<1>("h00") + T_7290.req_data.ready := UInt<1>("h00") + T_7290.req_cmd.bits.rw := UInt<1>("h00") + T_7290.req_cmd.bits.tag := UInt<1>("h00") + T_7290.req_cmd.bits.addr := UInt<1>("h00") + T_7290.req_cmd.valid := UInt<1>("h00") + T_7290.req_cmd.ready := UInt<1>("h00") + T_7399.mem_1.resp.valid := T_7290.resp.valid + T_7399.mem_1.resp.bits <> T_7290.resp.bits + T_7290.resp.ready := UInt<1>("h01") + T_7290.req_cmd.valid := T_7399.mem_1.req_cmd.valid + T_7290.req_cmd.bits <> T_7399.mem_1.req_cmd.bits + T_7399.mem_1.req_cmd.ready := T_7290.req_cmd.ready + T_7290.req_data.valid := T_7399.mem_1.req_data.valid + T_7290.req_data.bits <> T_7399.mem_1.req_data.bits + T_7399.mem_1.req_data.ready := T_7290.req_data.ready + inst T_7401 of MemIOArbiter + T_7401.outer.resp.bits.tag := UInt<1>("h00") + T_7401.outer.resp.bits.data := UInt<1>("h00") + T_7401.outer.resp.valid := UInt<1>("h00") + T_7401.outer.req_data.ready := UInt<1>("h00") + T_7401.outer.req_cmd.ready := UInt<1>("h00") + T_7401.inner[0].resp.ready := UInt<1>("h00") + T_7401.inner[0].req_data.bits.data := UInt<1>("h00") + T_7401.inner[0].req_data.valid := UInt<1>("h00") + T_7401.inner[0].req_cmd.bits.rw := UInt<1>("h00") + T_7401.inner[0].req_cmd.bits.tag := UInt<1>("h00") + T_7401.inner[0].req_cmd.bits.addr := UInt<1>("h00") + T_7401.inner[0].req_cmd.valid := UInt<1>("h00") + T_7401.reset := UInt<1>("h00") + T_7401.clock := clock + T_7401.reset := reset + inst T_7402 of MemSerdes + T_7402.narrow.resp.bits := UInt<1>("h00") + T_7402.narrow.resp.valid := UInt<1>("h00") + T_7402.narrow.req.ready := UInt<1>("h00") + T_7402.wide.resp.ready := UInt<1>("h00") + T_7402.wide.req_data.bits.data := UInt<1>("h00") + T_7402.wide.req_data.valid := UInt<1>("h00") + T_7402.wide.req_cmd.bits.rw := UInt<1>("h00") + T_7402.wide.req_cmd.bits.tag := UInt<1>("h00") + T_7402.wide.req_cmd.bits.addr := UInt<1>("h00") + T_7402.wide.req_cmd.valid := UInt<1>("h00") + T_7402.reset := UInt<1>("h00") + T_7402.clock := clock + T_7402.reset := reset + T_7402.wide <> T_7401.outer + mem_backup <> T_7402.narrow + node T_7373 = mux(mem_backup_en, T_7401.inner[0].req_cmd.ready, mem_1[0].req_cmd.ready) + T_7290.req_cmd.ready := T_7373 + node T_7375 = eq(mem_backup_en, UInt<1>("h00")) + node T_7376 = and(T_7290.req_cmd.valid, T_7375) + mem_1[0].req_cmd.valid := T_7376 + mem_1[0].req_cmd.bits <> T_7290.req_cmd.bits + node T_7377 = and(T_7290.req_cmd.valid, mem_backup_en) + T_7401.inner[0].req_cmd.valid := T_7377 + T_7401.inner[0].req_cmd.bits <> T_7290.req_cmd.bits + node T_7378 = mux(mem_backup_en, T_7401.inner[0].req_data.ready, mem_1[0].req_data.ready) + T_7290.req_data.ready := T_7378 + node T_7380 = eq(mem_backup_en, UInt<1>("h00")) + node T_7381 = and(T_7290.req_data.valid, T_7380) + mem_1[0].req_data.valid := T_7381 + mem_1[0].req_data.bits <> T_7290.req_data.bits + node T_7382 = and(T_7290.req_data.valid, mem_backup_en) + T_7401.inner[0].req_data.valid := T_7382 + T_7401.inner[0].req_data.bits <> T_7290.req_data.bits + node T_7383 = mux(mem_backup_en, T_7401.inner[0].resp.valid, mem_1[0].resp.valid) + T_7290.resp.valid := T_7383 + wire T_7387 : {data : UInt<128>, tag : UInt<7>} + T_7387 <> mem_1[0].resp.bits + when mem_backup_en : + T_7387 <> T_7401.inner[0].resp.bits + skip + T_7290.resp.bits <> T_7387 + node T_7391 = eq(mem_backup_en, UInt<1>("h00")) + node T_7392 = and(T_7290.resp.ready, T_7391) + mem_1[0].resp.ready := T_7392 + node T_7393 = and(T_7290.resp.ready, mem_backup_en) + T_7401.inner[0].resp.ready := T_7393 + + module Queue_50 : + output count : UInt<1> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : UInt<17>[1], clock + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_30 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_30) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_36 = and(enq.ready, enq.valid) + node T_38 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_36, T_38) + node T_40 = and(deq.ready, deq.valid) + node T_42 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_40, T_42) + when do_enq : + infer accessor T_44 = ram[UInt<1>("h00")] + T_44 := enq.bits + skip + when do_deq : + skip + node T_47 = neq(do_enq, do_deq) + when T_47 : + maybe_full := do_enq + skip + node T_49 = eq(empty, UInt<1>("h00")) + node T_51 = and(UInt<1>("h00"), enq.valid) + node T_52 = or(T_49, T_51) + deq.valid := T_52 + node T_54 = eq(full, UInt<1>("h00")) + node T_56 = and(UInt<1>("h00"), deq.ready) + node T_57 = or(T_54, T_56) + enq.ready := T_57 + infer accessor T_58 = ram[UInt<1>("h00")] + node T_59 = mux(maybe_flow, enq.bits, T_58) + deq.bits := T_59 + node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) + node T_61 = and(maybe_full, ptr_match) + node T_62 = cat(T_61, ptr_diff) + count := T_62 + + module SlowIO : + output divisor : UInt<32> + input set_divisor : {valid : UInt<1>, bits : UInt<32>} + output clk_slow : UInt<1> + input in_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} + output in_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} + output out_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} + input out_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} + input clock : Clock + input reset : UInt<1> + + divisor := UInt<1>("h00") + clk_slow := UInt<1>("h00") + in_slow.ready := UInt<1>("h00") + in_fast.bits := UInt<1>("h00") + in_fast.valid := UInt<1>("h00") + out_slow.bits := UInt<1>("h00") + out_slow.valid := UInt<1>("h00") + out_fast.ready := UInt<1>("h00") + reg divisor_1 : UInt<?>, clock, reset + onreset divisor_1 := UInt<9>("h01ff") + reg d_shadow : UInt<?>, clock, reset + onreset d_shadow := UInt<9>("h01ff") + reg hold : UInt<?>, clock, reset + onreset hold := UInt<7>("h07f") + reg h_shadow : UInt<?>, clock, reset + onreset h_shadow := UInt<7>("h07f") + when set_divisor.valid : + node T_57 = bits(set_divisor.bits, 8, 0) + d_shadow := T_57 + node T_58 = bits(set_divisor.bits, 24, 16) + h_shadow := T_58 + skip + node T_59 = shl(hold, 16) + node T_60 = or(T_59, divisor_1) + divisor := T_60 + reg count : UInt<9>, clock, reset + reg myclock : UInt<1>, clock, reset + node T_66 = addw(count, UInt<1>("h01")) + count := T_66 + node T_67 = shr(divisor_1, 1) + node rising = eq(count, T_67) + node falling = eq(count, divisor_1) + node T_70 = shr(divisor_1, 1) + node T_71 = addw(T_70, hold) + node held = eq(count, T_71) + when falling : + divisor_1 := d_shadow + hold := h_shadow + count := UInt<1>("h00") + myclock := UInt<1>("h00") + skip + when rising : + myclock := UInt<1>("h01") + skip + reg in_slow_rdy : UInt<1>, clock, reset + onreset in_slow_rdy := UInt<1>("h00") + reg out_slow_val : UInt<1>, clock, reset + onreset out_slow_val := UInt<1>("h00") + reg out_slow_bits : UInt<17>, clock, reset + inst fromhost_q of Queue_50 + fromhost_q.deq.ready := UInt<1>("h00") + fromhost_q.enq.bits := UInt<1>("h00") + fromhost_q.enq.valid := UInt<1>("h00") + fromhost_q.reset := UInt<1>("h00") + fromhost_q.clock := clock + fromhost_q.reset := reset + node T_87 = and(in_slow.valid, in_slow_rdy) + node T_88 = or(T_87, reset) + node T_89 = and(rising, T_88) + fromhost_q.enq.valid := T_89 + fromhost_q.enq.bits := in_slow.bits + in_fast <> fromhost_q.deq + inst tohost_q of Queue_50 + tohost_q.deq.ready := UInt<1>("h00") + tohost_q.enq.bits := UInt<1>("h00") + tohost_q.enq.valid := UInt<1>("h00") + tohost_q.reset := UInt<1>("h00") + tohost_q.clock := clock + tohost_q.reset := reset + tohost_q.enq <> out_fast + node T_95 = and(rising, out_slow.ready) + node T_96 = and(T_95, out_slow_val) + tohost_q.deq.ready := T_96 + when held : + in_slow_rdy := fromhost_q.enq.ready + out_slow_val := tohost_q.deq.valid + node T_97 = mux(reset, fromhost_q.deq.bits, tohost_q.deq.bits) + out_slow_bits := T_97 + skip + in_slow.ready := in_slow_rdy + out_slow.valid := out_slow_val + out_slow.bits := out_slow_bits + clk_slow := myclock + + module Uncore : + output mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>} + input htif : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}[1] + input tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}[1] + input tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[1] + output mem_1 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}}[1] + output host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>} + input clock : Clock + input reset : UInt<1> + + mem_backup_ctrl.out_valid := UInt<1>("h00") + htif[0].ipi_rep.bits := UInt<1>("h00") + htif[0].ipi_rep.valid := UInt<1>("h00") + htif[0].ipi_req.ready := UInt<1>("h00") + htif[0].pcr_rep.ready := UInt<1>("h00") + htif[0].pcr_req.bits.data := UInt<1>("h00") + htif[0].pcr_req.bits.addr := UInt<1>("h00") + htif[0].pcr_req.bits.rw := UInt<1>("h00") + htif[0].pcr_req.valid := UInt<1>("h00") + htif[0].id := UInt<1>("h00") + htif[0].reset := UInt<1>("h00") + tiles_uncached[0].grant.bits.g_type := UInt<1>("h00") + tiles_uncached[0].grant.bits.is_builtin_type := UInt<1>("h00") + tiles_uncached[0].grant.bits.manager_xact_id := UInt<1>("h00") + tiles_uncached[0].grant.bits.client_xact_id := UInt<1>("h00") + tiles_uncached[0].grant.bits.data := UInt<1>("h00") + tiles_uncached[0].grant.bits.addr_beat := UInt<1>("h00") + tiles_uncached[0].grant.valid := UInt<1>("h00") + tiles_uncached[0].acquire.ready := UInt<1>("h00") + tiles_cached[0].release.ready := UInt<1>("h00") + tiles_cached[0].probe.bits.p_type := UInt<1>("h00") + tiles_cached[0].probe.bits.addr_block := UInt<1>("h00") + tiles_cached[0].probe.valid := UInt<1>("h00") + tiles_cached[0].grant.bits.g_type := UInt<1>("h00") + tiles_cached[0].grant.bits.is_builtin_type := UInt<1>("h00") + tiles_cached[0].grant.bits.manager_xact_id := UInt<1>("h00") + tiles_cached[0].grant.bits.client_xact_id := UInt<1>("h00") + tiles_cached[0].grant.bits.data := UInt<1>("h00") + tiles_cached[0].grant.bits.addr_beat := UInt<1>("h00") + tiles_cached[0].grant.valid := UInt<1>("h00") + tiles_cached[0].acquire.ready := UInt<1>("h00") + mem_1[0].resp.ready := UInt<1>("h00") + mem_1[0].req_data.bits.data := UInt<1>("h00") + mem_1[0].req_data.valid := UInt<1>("h00") + mem_1[0].req_cmd.bits.rw := UInt<1>("h00") + mem_1[0].req_cmd.bits.tag := UInt<1>("h00") + mem_1[0].req_cmd.bits.addr := UInt<1>("h00") + mem_1[0].req_cmd.valid := UInt<1>("h00") + host.debug_stats_pcr := UInt<1>("h00") + host.out.bits := UInt<1>("h00") + host.out.valid := UInt<1>("h00") + host.in.ready := UInt<1>("h00") + host.clk_edge := UInt<1>("h00") + host.clk := UInt<1>("h00") + inst htif_2 of HTIF + htif_2.scr.rdata[0] := UInt<1>("h00") + htif_2.scr.rdata[1] := UInt<1>("h00") + htif_2.scr.rdata[2] := UInt<1>("h00") + htif_2.scr.rdata[3] := UInt<1>("h00") + htif_2.scr.rdata[4] := UInt<1>("h00") + htif_2.scr.rdata[5] := UInt<1>("h00") + htif_2.scr.rdata[6] := UInt<1>("h00") + htif_2.scr.rdata[7] := UInt<1>("h00") + htif_2.scr.rdata[8] := UInt<1>("h00") + htif_2.scr.rdata[9] := UInt<1>("h00") + htif_2.scr.rdata[10] := UInt<1>("h00") + htif_2.scr.rdata[11] := UInt<1>("h00") + htif_2.scr.rdata[12] := UInt<1>("h00") + htif_2.scr.rdata[13] := UInt<1>("h00") + htif_2.scr.rdata[14] := UInt<1>("h00") + htif_2.scr.rdata[15] := UInt<1>("h00") + htif_2.scr.rdata[16] := UInt<1>("h00") + htif_2.scr.rdata[17] := UInt<1>("h00") + htif_2.scr.rdata[18] := UInt<1>("h00") + htif_2.scr.rdata[19] := UInt<1>("h00") + htif_2.scr.rdata[20] := UInt<1>("h00") + htif_2.scr.rdata[21] := UInt<1>("h00") + htif_2.scr.rdata[22] := UInt<1>("h00") + htif_2.scr.rdata[23] := UInt<1>("h00") + htif_2.scr.rdata[24] := UInt<1>("h00") + htif_2.scr.rdata[25] := UInt<1>("h00") + htif_2.scr.rdata[26] := UInt<1>("h00") + htif_2.scr.rdata[27] := UInt<1>("h00") + htif_2.scr.rdata[28] := UInt<1>("h00") + htif_2.scr.rdata[29] := UInt<1>("h00") + htif_2.scr.rdata[30] := UInt<1>("h00") + htif_2.scr.rdata[31] := UInt<1>("h00") + htif_2.scr.rdata[32] := UInt<1>("h00") + htif_2.scr.rdata[33] := UInt<1>("h00") + htif_2.scr.rdata[34] := UInt<1>("h00") + htif_2.scr.rdata[35] := UInt<1>("h00") + htif_2.scr.rdata[36] := UInt<1>("h00") + htif_2.scr.rdata[37] := UInt<1>("h00") + htif_2.scr.rdata[38] := UInt<1>("h00") + htif_2.scr.rdata[39] := UInt<1>("h00") + htif_2.scr.rdata[40] := UInt<1>("h00") + htif_2.scr.rdata[41] := UInt<1>("h00") + htif_2.scr.rdata[42] := UInt<1>("h00") + htif_2.scr.rdata[43] := UInt<1>("h00") + htif_2.scr.rdata[44] := UInt<1>("h00") + htif_2.scr.rdata[45] := UInt<1>("h00") + htif_2.scr.rdata[46] := UInt<1>("h00") + htif_2.scr.rdata[47] := UInt<1>("h00") + htif_2.scr.rdata[48] := UInt<1>("h00") + htif_2.scr.rdata[49] := UInt<1>("h00") + htif_2.scr.rdata[50] := UInt<1>("h00") + htif_2.scr.rdata[51] := UInt<1>("h00") + htif_2.scr.rdata[52] := UInt<1>("h00") + htif_2.scr.rdata[53] := UInt<1>("h00") + htif_2.scr.rdata[54] := UInt<1>("h00") + htif_2.scr.rdata[55] := UInt<1>("h00") + htif_2.scr.rdata[56] := UInt<1>("h00") + htif_2.scr.rdata[57] := UInt<1>("h00") + htif_2.scr.rdata[58] := UInt<1>("h00") + htif_2.scr.rdata[59] := UInt<1>("h00") + htif_2.scr.rdata[60] := UInt<1>("h00") + htif_2.scr.rdata[61] := UInt<1>("h00") + htif_2.scr.rdata[62] := UInt<1>("h00") + htif_2.scr.rdata[63] := UInt<1>("h00") + htif_2.mem_1.grant.bits.g_type := UInt<1>("h00") + htif_2.mem_1.grant.bits.is_builtin_type := UInt<1>("h00") + htif_2.mem_1.grant.bits.manager_xact_id := UInt<1>("h00") + htif_2.mem_1.grant.bits.client_xact_id := UInt<1>("h00") + htif_2.mem_1.grant.bits.data := UInt<1>("h00") + htif_2.mem_1.grant.bits.addr_beat := UInt<1>("h00") + htif_2.mem_1.grant.valid := UInt<1>("h00") + htif_2.mem_1.acquire.ready := UInt<1>("h00") + htif_2.cpu[0].debug_stats_pcr := UInt<1>("h00") + htif_2.cpu[0].ipi_rep.ready := UInt<1>("h00") + htif_2.cpu[0].ipi_req.bits := UInt<1>("h00") + htif_2.cpu[0].ipi_req.valid := UInt<1>("h00") + htif_2.cpu[0].pcr_rep.bits := UInt<1>("h00") + htif_2.cpu[0].pcr_rep.valid := UInt<1>("h00") + htif_2.cpu[0].pcr_req.ready := UInt<1>("h00") + htif_2.host.out.ready := UInt<1>("h00") + htif_2.host.in.bits := UInt<1>("h00") + htif_2.host.in.valid := UInt<1>("h00") + htif_2.reset := UInt<1>("h00") + htif_2.clock := clock + htif_2.reset := reset + inst outmemsys of OuterMemorySystem + outmemsys.mem_backup_en := UInt<1>("h00") + outmemsys.mem_backup.resp.bits := UInt<1>("h00") + outmemsys.mem_backup.resp.valid := UInt<1>("h00") + outmemsys.mem_backup.req.ready := UInt<1>("h00") + outmemsys.mem_1[0].resp.bits.tag := UInt<1>("h00") + outmemsys.mem_1[0].resp.bits.data := UInt<1>("h00") + outmemsys.mem_1[0].resp.valid := UInt<1>("h00") + outmemsys.mem_1[0].req_data.ready := UInt<1>("h00") + outmemsys.mem_1[0].req_cmd.ready := UInt<1>("h00") + outmemsys.incoherent[0] := UInt<1>("h00") + outmemsys.htif_uncached.grant.ready := UInt<1>("h00") + outmemsys.htif_uncached.acquire.bits.union := UInt<1>("h00") + outmemsys.htif_uncached.acquire.bits.a_type := UInt<1>("h00") + outmemsys.htif_uncached.acquire.bits.is_builtin_type := UInt<1>("h00") + outmemsys.htif_uncached.acquire.bits.data := UInt<1>("h00") + outmemsys.htif_uncached.acquire.bits.addr_beat := UInt<1>("h00") + outmemsys.htif_uncached.acquire.bits.client_xact_id := UInt<1>("h00") + outmemsys.htif_uncached.acquire.bits.addr_block := UInt<1>("h00") + outmemsys.htif_uncached.acquire.valid := UInt<1>("h00") + outmemsys.tiles_uncached[0].grant.ready := UInt<1>("h00") + outmemsys.tiles_uncached[0].acquire.bits.union := UInt<1>("h00") + outmemsys.tiles_uncached[0].acquire.bits.a_type := UInt<1>("h00") + outmemsys.tiles_uncached[0].acquire.bits.is_builtin_type := UInt<1>("h00") + outmemsys.tiles_uncached[0].acquire.bits.data := UInt<1>("h00") + outmemsys.tiles_uncached[0].acquire.bits.addr_beat := UInt<1>("h00") + outmemsys.tiles_uncached[0].acquire.bits.client_xact_id := UInt<1>("h00") + outmemsys.tiles_uncached[0].acquire.bits.addr_block := UInt<1>("h00") + outmemsys.tiles_uncached[0].acquire.valid := UInt<1>("h00") + outmemsys.tiles_cached[0].release.bits.voluntary := UInt<1>("h00") + outmemsys.tiles_cached[0].release.bits.r_type := UInt<1>("h00") + outmemsys.tiles_cached[0].release.bits.data := UInt<1>("h00") + outmemsys.tiles_cached[0].release.bits.addr_beat := UInt<1>("h00") + outmemsys.tiles_cached[0].release.bits.client_xact_id := UInt<1>("h00") + outmemsys.tiles_cached[0].release.bits.addr_block := UInt<1>("h00") + outmemsys.tiles_cached[0].release.valid := UInt<1>("h00") + outmemsys.tiles_cached[0].probe.ready := UInt<1>("h00") + outmemsys.tiles_cached[0].grant.ready := UInt<1>("h00") + outmemsys.tiles_cached[0].acquire.bits.union := UInt<1>("h00") + outmemsys.tiles_cached[0].acquire.bits.a_type := UInt<1>("h00") + outmemsys.tiles_cached[0].acquire.bits.is_builtin_type := UInt<1>("h00") + outmemsys.tiles_cached[0].acquire.bits.data := UInt<1>("h00") + outmemsys.tiles_cached[0].acquire.bits.addr_beat := UInt<1>("h00") + outmemsys.tiles_cached[0].acquire.bits.client_xact_id := UInt<1>("h00") + outmemsys.tiles_cached[0].acquire.bits.addr_block := UInt<1>("h00") + outmemsys.tiles_cached[0].acquire.valid := UInt<1>("h00") + outmemsys.reset := UInt<1>("h00") + outmemsys.clock := clock + outmemsys.reset := reset + outmemsys.incoherent[0] := htif_2.cpu[0].reset + outmemsys.htif_uncached <> htif_2.mem_1 + outmemsys.tiles_uncached <> tiles_uncached + outmemsys.tiles_cached <> tiles_cached + host.debug_stats_pcr := htif_2.host.debug_stats_pcr + htif_2.cpu <> htif + mem_1 <> outmemsys.mem_1 + outmemsys.mem_backup_en := mem_backup_ctrl.en + inst T_7095 of SlowIO + T_7095.set_divisor.bits := UInt<1>("h00") + T_7095.set_divisor.valid := UInt<1>("h00") + T_7095.in_slow.bits := UInt<1>("h00") + T_7095.in_slow.valid := UInt<1>("h00") + T_7095.in_fast.ready := UInt<1>("h00") + T_7095.out_slow.ready := UInt<1>("h00") + T_7095.out_fast.bits := UInt<1>("h00") + T_7095.out_fast.valid := UInt<1>("h00") + T_7095.reset := UInt<1>("h00") + T_7095.clock := clock + T_7095.reset := reset + node T_7060 = eq(htif_2.scr.waddr, UInt<6>("h03f")) + node T_7061 = and(htif_2.scr.wen, T_7060) + T_7095.set_divisor.valid := T_7061 + T_7095.set_divisor.bits := htif_2.scr.wdata + htif_2.scr.rdata[63] := T_7095.divisor + node T_7062 = or(htif_2.host.out.valid, outmemsys.mem_backup.req.valid) + T_7095.out_fast.valid := T_7062 + node T_7063 = mux(htif_2.host.out.valid, htif_2.host.out.bits, outmemsys.mem_backup.req.bits) + node T_7064 = cat(htif_2.host.out.valid, T_7063) + T_7095.out_fast.bits := T_7064 + htif_2.host.out.ready := T_7095.out_fast.ready + node T_7066 = eq(htif_2.host.out.valid, UInt<1>("h00")) + node T_7067 = and(T_7095.out_fast.ready, T_7066) + outmemsys.mem_backup.req.ready := T_7067 + node T_7068 = bit(T_7095.out_slow.bits, 16) + node T_7069 = and(T_7095.out_slow.valid, T_7068) + host.out.valid := T_7069 + host.out.bits := T_7095.out_slow.bits + node T_7070 = bit(T_7095.out_slow.bits, 16) + node T_7072 = eq(T_7070, UInt<1>("h00")) + node T_7073 = and(T_7095.out_slow.valid, T_7072) + mem_backup_ctrl.out_valid := T_7073 + node T_7074 = bit(T_7095.out_slow.bits, 16) + node T_7075 = mux(T_7074, host.out.ready, mem_backup_ctrl.out_ready) + T_7095.out_slow.ready := T_7075 + node T_7076 = and(mem_backup_ctrl.en, mem_backup_ctrl.in_valid) + node T_7077 = or(T_7076, host.in.valid) + T_7095.in_slow.valid := T_7077 + node T_7078 = cat(T_7076, host.in.bits) + T_7095.in_slow.bits := T_7078 + host.in.ready := T_7095.in_slow.ready + node T_7079 = bit(T_7095.in_fast.bits, 16) + node T_7080 = and(T_7095.in_fast.valid, T_7079) + outmemsys.mem_backup.resp.valid := T_7080 + outmemsys.mem_backup.resp.bits := T_7095.in_fast.bits + node T_7081 = bit(T_7095.in_fast.bits, 16) + node T_7083 = eq(T_7081, UInt<1>("h00")) + node T_7084 = and(T_7095.in_fast.valid, T_7083) + htif_2.host.in.valid := T_7084 + htif_2.host.in.bits := T_7095.in_fast.bits + node T_7085 = bit(T_7095.in_fast.bits, 16) + node T_7087 = mux(T_7085, UInt<1>("h01"), htif_2.host.in.ready) + T_7095.in_fast.ready := T_7087 + host.clk := T_7095.clk_slow + reg T_7088 : UInt<1>, clock, reset + T_7088 := host.clk + node T_7090 = eq(T_7088, UInt<1>("h00")) + node T_7091 = and(host.clk, T_7090) + reg T_7092 : UInt<1>, clock, reset + T_7092 := T_7091 + host.clk_edge := T_7092 + + module BTB : + input invalidate : UInt<1> + input ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}} + input bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}} + input btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}} + output resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}} + input req : {valid : UInt<1>, bits : {addr : UInt<39>}} + input clock : Clock + input reset : UInt<1> + + resp.bits.bht.value := UInt<1>("h00") + resp.bits.bht.history := UInt<1>("h00") + resp.bits.entry := UInt<1>("h00") + resp.bits.target := UInt<1>("h00") + resp.bits.bridx := UInt<1>("h00") + resp.bits.mask := UInt<1>("h00") + resp.bits.taken := UInt<1>("h00") + resp.valid := UInt<1>("h00") + reg idxValid : UInt<62>, clock, reset + onreset idxValid := UInt<62>("h00") + cmem idxs : UInt<12>[62], clock + cmem idxPages : UInt<3>[62], clock + cmem tgts : UInt<12>[62], clock + cmem tgtPages : UInt<3>[62], clock + cmem pages : UInt<27>[6], clock + reg pageValid : UInt<6>, clock, reset + onreset pageValid := UInt<6>("h00") + infer accessor T_589 = idxPages[UInt<1>("h00")] + node T_591 = dshl(UInt<1>("h01"), T_589) + node T_592 = bits(T_591, 5, 0) + infer accessor T_594 = idxPages[UInt<1>("h01")] + node T_596 = dshl(UInt<1>("h01"), T_594) + node T_597 = bits(T_596, 5, 0) + infer accessor T_599 = idxPages[UInt<2>("h02")] + node T_601 = dshl(UInt<1>("h01"), T_599) + node T_602 = bits(T_601, 5, 0) + infer accessor T_604 = idxPages[UInt<2>("h03")] + node T_606 = dshl(UInt<1>("h01"), T_604) + node T_607 = bits(T_606, 5, 0) + infer accessor T_609 = idxPages[UInt<3>("h04")] + node T_611 = dshl(UInt<1>("h01"), T_609) + node T_612 = bits(T_611, 5, 0) + infer accessor T_614 = idxPages[UInt<3>("h05")] + node T_616 = dshl(UInt<1>("h01"), T_614) + node T_617 = bits(T_616, 5, 0) + infer accessor T_619 = idxPages[UInt<3>("h06")] + node T_621 = dshl(UInt<1>("h01"), T_619) + node T_622 = bits(T_621, 5, 0) + infer accessor T_624 = idxPages[UInt<3>("h07")] + node T_626 = dshl(UInt<1>("h01"), T_624) + node T_627 = bits(T_626, 5, 0) + infer accessor T_629 = idxPages[UInt<4>("h08")] + node T_631 = dshl(UInt<1>("h01"), T_629) + node T_632 = bits(T_631, 5, 0) + infer accessor T_634 = idxPages[UInt<4>("h09")] + node T_636 = dshl(UInt<1>("h01"), T_634) + node T_637 = bits(T_636, 5, 0) + infer accessor T_639 = idxPages[UInt<4>("h0a")] + node T_641 = dshl(UInt<1>("h01"), T_639) + node T_642 = bits(T_641, 5, 0) + infer accessor T_644 = idxPages[UInt<4>("h0b")] + node T_646 = dshl(UInt<1>("h01"), T_644) + node T_647 = bits(T_646, 5, 0) + infer accessor T_649 = idxPages[UInt<4>("h0c")] + node T_651 = dshl(UInt<1>("h01"), T_649) + node T_652 = bits(T_651, 5, 0) + infer accessor T_654 = idxPages[UInt<4>("h0d")] + node T_656 = dshl(UInt<1>("h01"), T_654) + node T_657 = bits(T_656, 5, 0) + infer accessor T_659 = idxPages[UInt<4>("h0e")] + node T_661 = dshl(UInt<1>("h01"), T_659) + node T_662 = bits(T_661, 5, 0) + infer accessor T_664 = idxPages[UInt<4>("h0f")] + node T_666 = dshl(UInt<1>("h01"), T_664) + node T_667 = bits(T_666, 5, 0) + infer accessor T_669 = idxPages[UInt<5>("h010")] + node T_671 = dshl(UInt<1>("h01"), T_669) + node T_672 = bits(T_671, 5, 0) + infer accessor T_674 = idxPages[UInt<5>("h011")] + node T_676 = dshl(UInt<1>("h01"), T_674) + node T_677 = bits(T_676, 5, 0) + infer accessor T_679 = idxPages[UInt<5>("h012")] + node T_681 = dshl(UInt<1>("h01"), T_679) + node T_682 = bits(T_681, 5, 0) + infer accessor T_684 = idxPages[UInt<5>("h013")] + node T_686 = dshl(UInt<1>("h01"), T_684) + node T_687 = bits(T_686, 5, 0) + infer accessor T_689 = idxPages[UInt<5>("h014")] + node T_691 = dshl(UInt<1>("h01"), T_689) + node T_692 = bits(T_691, 5, 0) + infer accessor T_694 = idxPages[UInt<5>("h015")] + node T_696 = dshl(UInt<1>("h01"), T_694) + node T_697 = bits(T_696, 5, 0) + infer accessor T_699 = idxPages[UInt<5>("h016")] + node T_701 = dshl(UInt<1>("h01"), T_699) + node T_702 = bits(T_701, 5, 0) + infer accessor T_704 = idxPages[UInt<5>("h017")] + node T_706 = dshl(UInt<1>("h01"), T_704) + node T_707 = bits(T_706, 5, 0) + infer accessor T_709 = idxPages[UInt<5>("h018")] + node T_711 = dshl(UInt<1>("h01"), T_709) + node T_712 = bits(T_711, 5, 0) + infer accessor T_714 = idxPages[UInt<5>("h019")] + node T_716 = dshl(UInt<1>("h01"), T_714) + node T_717 = bits(T_716, 5, 0) + infer accessor T_719 = idxPages[UInt<5>("h01a")] + node T_721 = dshl(UInt<1>("h01"), T_719) + node T_722 = bits(T_721, 5, 0) + infer accessor T_724 = idxPages[UInt<5>("h01b")] + node T_726 = dshl(UInt<1>("h01"), T_724) + node T_727 = bits(T_726, 5, 0) + infer accessor T_729 = idxPages[UInt<5>("h01c")] + node T_731 = dshl(UInt<1>("h01"), T_729) + node T_732 = bits(T_731, 5, 0) + infer accessor T_734 = idxPages[UInt<5>("h01d")] + node T_736 = dshl(UInt<1>("h01"), T_734) + node T_737 = bits(T_736, 5, 0) + infer accessor T_739 = idxPages[UInt<5>("h01e")] + node T_741 = dshl(UInt<1>("h01"), T_739) + node T_742 = bits(T_741, 5, 0) + infer accessor T_744 = idxPages[UInt<5>("h01f")] + node T_746 = dshl(UInt<1>("h01"), T_744) + node T_747 = bits(T_746, 5, 0) + infer accessor T_749 = idxPages[UInt<6>("h020")] + node T_751 = dshl(UInt<1>("h01"), T_749) + node T_752 = bits(T_751, 5, 0) + infer accessor T_754 = idxPages[UInt<6>("h021")] + node T_756 = dshl(UInt<1>("h01"), T_754) + node T_757 = bits(T_756, 5, 0) + infer accessor T_759 = idxPages[UInt<6>("h022")] + node T_761 = dshl(UInt<1>("h01"), T_759) + node T_762 = bits(T_761, 5, 0) + infer accessor T_764 = idxPages[UInt<6>("h023")] + node T_766 = dshl(UInt<1>("h01"), T_764) + node T_767 = bits(T_766, 5, 0) + infer accessor T_769 = idxPages[UInt<6>("h024")] + node T_771 = dshl(UInt<1>("h01"), T_769) + node T_772 = bits(T_771, 5, 0) + infer accessor T_774 = idxPages[UInt<6>("h025")] + node T_776 = dshl(UInt<1>("h01"), T_774) + node T_777 = bits(T_776, 5, 0) + infer accessor T_779 = idxPages[UInt<6>("h026")] + node T_781 = dshl(UInt<1>("h01"), T_779) + node T_782 = bits(T_781, 5, 0) + infer accessor T_784 = idxPages[UInt<6>("h027")] + node T_786 = dshl(UInt<1>("h01"), T_784) + node T_787 = bits(T_786, 5, 0) + infer accessor T_789 = idxPages[UInt<6>("h028")] + node T_791 = dshl(UInt<1>("h01"), T_789) + node T_792 = bits(T_791, 5, 0) + infer accessor T_794 = idxPages[UInt<6>("h029")] + node T_796 = dshl(UInt<1>("h01"), T_794) + node T_797 = bits(T_796, 5, 0) + infer accessor T_799 = idxPages[UInt<6>("h02a")] + node T_801 = dshl(UInt<1>("h01"), T_799) + node T_802 = bits(T_801, 5, 0) + infer accessor T_804 = idxPages[UInt<6>("h02b")] + node T_806 = dshl(UInt<1>("h01"), T_804) + node T_807 = bits(T_806, 5, 0) + infer accessor T_809 = idxPages[UInt<6>("h02c")] + node T_811 = dshl(UInt<1>("h01"), T_809) + node T_812 = bits(T_811, 5, 0) + infer accessor T_814 = idxPages[UInt<6>("h02d")] + node T_816 = dshl(UInt<1>("h01"), T_814) + node T_817 = bits(T_816, 5, 0) + infer accessor T_819 = idxPages[UInt<6>("h02e")] + node T_821 = dshl(UInt<1>("h01"), T_819) + node T_822 = bits(T_821, 5, 0) + infer accessor T_824 = idxPages[UInt<6>("h02f")] + node T_826 = dshl(UInt<1>("h01"), T_824) + node T_827 = bits(T_826, 5, 0) + infer accessor T_829 = idxPages[UInt<6>("h030")] + node T_831 = dshl(UInt<1>("h01"), T_829) + node T_832 = bits(T_831, 5, 0) + infer accessor T_834 = idxPages[UInt<6>("h031")] + node T_836 = dshl(UInt<1>("h01"), T_834) + node T_837 = bits(T_836, 5, 0) + infer accessor T_839 = idxPages[UInt<6>("h032")] + node T_841 = dshl(UInt<1>("h01"), T_839) + node T_842 = bits(T_841, 5, 0) + infer accessor T_844 = idxPages[UInt<6>("h033")] + node T_846 = dshl(UInt<1>("h01"), T_844) + node T_847 = bits(T_846, 5, 0) + infer accessor T_849 = idxPages[UInt<6>("h034")] + node T_851 = dshl(UInt<1>("h01"), T_849) + node T_852 = bits(T_851, 5, 0) + infer accessor T_854 = idxPages[UInt<6>("h035")] + node T_856 = dshl(UInt<1>("h01"), T_854) + node T_857 = bits(T_856, 5, 0) + infer accessor T_859 = idxPages[UInt<6>("h036")] + node T_861 = dshl(UInt<1>("h01"), T_859) + node T_862 = bits(T_861, 5, 0) + infer accessor T_864 = idxPages[UInt<6>("h037")] + node T_866 = dshl(UInt<1>("h01"), T_864) + node T_867 = bits(T_866, 5, 0) + infer accessor T_869 = idxPages[UInt<6>("h038")] + node T_871 = dshl(UInt<1>("h01"), T_869) + node T_872 = bits(T_871, 5, 0) + infer accessor T_874 = idxPages[UInt<6>("h039")] + node T_876 = dshl(UInt<1>("h01"), T_874) + node T_877 = bits(T_876, 5, 0) + infer accessor T_879 = idxPages[UInt<6>("h03a")] + node T_881 = dshl(UInt<1>("h01"), T_879) + node T_882 = bits(T_881, 5, 0) + infer accessor T_884 = idxPages[UInt<6>("h03b")] + node T_886 = dshl(UInt<1>("h01"), T_884) + node T_887 = bits(T_886, 5, 0) + infer accessor T_889 = idxPages[UInt<6>("h03c")] + node T_891 = dshl(UInt<1>("h01"), T_889) + node T_892 = bits(T_891, 5, 0) + infer accessor T_894 = idxPages[UInt<6>("h03d")] + node T_896 = dshl(UInt<1>("h01"), T_894) + node T_897 = bits(T_896, 5, 0) + infer accessor T_899 = tgtPages[UInt<1>("h00")] + node T_901 = dshl(UInt<1>("h01"), T_899) + node T_902 = bits(T_901, 5, 0) + infer accessor T_904 = tgtPages[UInt<1>("h01")] + node T_906 = dshl(UInt<1>("h01"), T_904) + node T_907 = bits(T_906, 5, 0) + infer accessor T_909 = tgtPages[UInt<2>("h02")] + node T_911 = dshl(UInt<1>("h01"), T_909) + node T_912 = bits(T_911, 5, 0) + infer accessor T_914 = tgtPages[UInt<2>("h03")] + node T_916 = dshl(UInt<1>("h01"), T_914) + node T_917 = bits(T_916, 5, 0) + infer accessor T_919 = tgtPages[UInt<3>("h04")] + node T_921 = dshl(UInt<1>("h01"), T_919) + node T_922 = bits(T_921, 5, 0) + infer accessor T_924 = tgtPages[UInt<3>("h05")] + node T_926 = dshl(UInt<1>("h01"), T_924) + node T_927 = bits(T_926, 5, 0) + infer accessor T_929 = tgtPages[UInt<3>("h06")] + node T_931 = dshl(UInt<1>("h01"), T_929) + node T_932 = bits(T_931, 5, 0) + infer accessor T_934 = tgtPages[UInt<3>("h07")] + node T_936 = dshl(UInt<1>("h01"), T_934) + node T_937 = bits(T_936, 5, 0) + infer accessor T_939 = tgtPages[UInt<4>("h08")] + node T_941 = dshl(UInt<1>("h01"), T_939) + node T_942 = bits(T_941, 5, 0) + infer accessor T_944 = tgtPages[UInt<4>("h09")] + node T_946 = dshl(UInt<1>("h01"), T_944) + node T_947 = bits(T_946, 5, 0) + infer accessor T_949 = tgtPages[UInt<4>("h0a")] + node T_951 = dshl(UInt<1>("h01"), T_949) + node T_952 = bits(T_951, 5, 0) + infer accessor T_954 = tgtPages[UInt<4>("h0b")] + node T_956 = dshl(UInt<1>("h01"), T_954) + node T_957 = bits(T_956, 5, 0) + infer accessor T_959 = tgtPages[UInt<4>("h0c")] + node T_961 = dshl(UInt<1>("h01"), T_959) + node T_962 = bits(T_961, 5, 0) + infer accessor T_964 = tgtPages[UInt<4>("h0d")] + node T_966 = dshl(UInt<1>("h01"), T_964) + node T_967 = bits(T_966, 5, 0) + infer accessor T_969 = tgtPages[UInt<4>("h0e")] + node T_971 = dshl(UInt<1>("h01"), T_969) + node T_972 = bits(T_971, 5, 0) + infer accessor T_974 = tgtPages[UInt<4>("h0f")] + node T_976 = dshl(UInt<1>("h01"), T_974) + node T_977 = bits(T_976, 5, 0) + infer accessor T_979 = tgtPages[UInt<5>("h010")] + node T_981 = dshl(UInt<1>("h01"), T_979) + node T_982 = bits(T_981, 5, 0) + infer accessor T_984 = tgtPages[UInt<5>("h011")] + node T_986 = dshl(UInt<1>("h01"), T_984) + node T_987 = bits(T_986, 5, 0) + infer accessor T_989 = tgtPages[UInt<5>("h012")] + node T_991 = dshl(UInt<1>("h01"), T_989) + node T_992 = bits(T_991, 5, 0) + infer accessor T_994 = tgtPages[UInt<5>("h013")] + node T_996 = dshl(UInt<1>("h01"), T_994) + node T_997 = bits(T_996, 5, 0) + infer accessor T_999 = tgtPages[UInt<5>("h014")] + node T_1001 = dshl(UInt<1>("h01"), T_999) + node T_1002 = bits(T_1001, 5, 0) + infer accessor T_1004 = tgtPages[UInt<5>("h015")] + node T_1006 = dshl(UInt<1>("h01"), T_1004) + node T_1007 = bits(T_1006, 5, 0) + infer accessor T_1009 = tgtPages[UInt<5>("h016")] + node T_1011 = dshl(UInt<1>("h01"), T_1009) + node T_1012 = bits(T_1011, 5, 0) + infer accessor T_1014 = tgtPages[UInt<5>("h017")] + node T_1016 = dshl(UInt<1>("h01"), T_1014) + node T_1017 = bits(T_1016, 5, 0) + infer accessor T_1019 = tgtPages[UInt<5>("h018")] + node T_1021 = dshl(UInt<1>("h01"), T_1019) + node T_1022 = bits(T_1021, 5, 0) + infer accessor T_1024 = tgtPages[UInt<5>("h019")] + node T_1026 = dshl(UInt<1>("h01"), T_1024) + node T_1027 = bits(T_1026, 5, 0) + infer accessor T_1029 = tgtPages[UInt<5>("h01a")] + node T_1031 = dshl(UInt<1>("h01"), T_1029) + node T_1032 = bits(T_1031, 5, 0) + infer accessor T_1034 = tgtPages[UInt<5>("h01b")] + node T_1036 = dshl(UInt<1>("h01"), T_1034) + node T_1037 = bits(T_1036, 5, 0) + infer accessor T_1039 = tgtPages[UInt<5>("h01c")] + node T_1041 = dshl(UInt<1>("h01"), T_1039) + node T_1042 = bits(T_1041, 5, 0) + infer accessor T_1044 = tgtPages[UInt<5>("h01d")] + node T_1046 = dshl(UInt<1>("h01"), T_1044) + node T_1047 = bits(T_1046, 5, 0) + infer accessor T_1049 = tgtPages[UInt<5>("h01e")] + node T_1051 = dshl(UInt<1>("h01"), T_1049) + node T_1052 = bits(T_1051, 5, 0) + infer accessor T_1054 = tgtPages[UInt<5>("h01f")] + node T_1056 = dshl(UInt<1>("h01"), T_1054) + node T_1057 = bits(T_1056, 5, 0) + infer accessor T_1059 = tgtPages[UInt<6>("h020")] + node T_1061 = dshl(UInt<1>("h01"), T_1059) + node T_1062 = bits(T_1061, 5, 0) + infer accessor T_1064 = tgtPages[UInt<6>("h021")] + node T_1066 = dshl(UInt<1>("h01"), T_1064) + node T_1067 = bits(T_1066, 5, 0) + infer accessor T_1069 = tgtPages[UInt<6>("h022")] + node T_1071 = dshl(UInt<1>("h01"), T_1069) + node T_1072 = bits(T_1071, 5, 0) + infer accessor T_1074 = tgtPages[UInt<6>("h023")] + node T_1076 = dshl(UInt<1>("h01"), T_1074) + node T_1077 = bits(T_1076, 5, 0) + infer accessor T_1079 = tgtPages[UInt<6>("h024")] + node T_1081 = dshl(UInt<1>("h01"), T_1079) + node T_1082 = bits(T_1081, 5, 0) + infer accessor T_1084 = tgtPages[UInt<6>("h025")] + node T_1086 = dshl(UInt<1>("h01"), T_1084) + node T_1087 = bits(T_1086, 5, 0) + infer accessor T_1089 = tgtPages[UInt<6>("h026")] + node T_1091 = dshl(UInt<1>("h01"), T_1089) + node T_1092 = bits(T_1091, 5, 0) + infer accessor T_1094 = tgtPages[UInt<6>("h027")] + node T_1096 = dshl(UInt<1>("h01"), T_1094) + node T_1097 = bits(T_1096, 5, 0) + infer accessor T_1099 = tgtPages[UInt<6>("h028")] + node T_1101 = dshl(UInt<1>("h01"), T_1099) + node T_1102 = bits(T_1101, 5, 0) + infer accessor T_1104 = tgtPages[UInt<6>("h029")] + node T_1106 = dshl(UInt<1>("h01"), T_1104) + node T_1107 = bits(T_1106, 5, 0) + infer accessor T_1109 = tgtPages[UInt<6>("h02a")] + node T_1111 = dshl(UInt<1>("h01"), T_1109) + node T_1112 = bits(T_1111, 5, 0) + infer accessor T_1114 = tgtPages[UInt<6>("h02b")] + node T_1116 = dshl(UInt<1>("h01"), T_1114) + node T_1117 = bits(T_1116, 5, 0) + infer accessor T_1119 = tgtPages[UInt<6>("h02c")] + node T_1121 = dshl(UInt<1>("h01"), T_1119) + node T_1122 = bits(T_1121, 5, 0) + infer accessor T_1124 = tgtPages[UInt<6>("h02d")] + node T_1126 = dshl(UInt<1>("h01"), T_1124) + node T_1127 = bits(T_1126, 5, 0) + infer accessor T_1129 = tgtPages[UInt<6>("h02e")] + node T_1131 = dshl(UInt<1>("h01"), T_1129) + node T_1132 = bits(T_1131, 5, 0) + infer accessor T_1134 = tgtPages[UInt<6>("h02f")] + node T_1136 = dshl(UInt<1>("h01"), T_1134) + node T_1137 = bits(T_1136, 5, 0) + infer accessor T_1139 = tgtPages[UInt<6>("h030")] + node T_1141 = dshl(UInt<1>("h01"), T_1139) + node T_1142 = bits(T_1141, 5, 0) + infer accessor T_1144 = tgtPages[UInt<6>("h031")] + node T_1146 = dshl(UInt<1>("h01"), T_1144) + node T_1147 = bits(T_1146, 5, 0) + infer accessor T_1149 = tgtPages[UInt<6>("h032")] + node T_1151 = dshl(UInt<1>("h01"), T_1149) + node T_1152 = bits(T_1151, 5, 0) + infer accessor T_1154 = tgtPages[UInt<6>("h033")] + node T_1156 = dshl(UInt<1>("h01"), T_1154) + node T_1157 = bits(T_1156, 5, 0) + infer accessor T_1159 = tgtPages[UInt<6>("h034")] + node T_1161 = dshl(UInt<1>("h01"), T_1159) + node T_1162 = bits(T_1161, 5, 0) + infer accessor T_1164 = tgtPages[UInt<6>("h035")] + node T_1166 = dshl(UInt<1>("h01"), T_1164) + node T_1167 = bits(T_1166, 5, 0) + infer accessor T_1169 = tgtPages[UInt<6>("h036")] + node T_1171 = dshl(UInt<1>("h01"), T_1169) + node T_1172 = bits(T_1171, 5, 0) + infer accessor T_1174 = tgtPages[UInt<6>("h037")] + node T_1176 = dshl(UInt<1>("h01"), T_1174) + node T_1177 = bits(T_1176, 5, 0) + infer accessor T_1179 = tgtPages[UInt<6>("h038")] + node T_1181 = dshl(UInt<1>("h01"), T_1179) + node T_1182 = bits(T_1181, 5, 0) + infer accessor T_1184 = tgtPages[UInt<6>("h039")] + node T_1186 = dshl(UInt<1>("h01"), T_1184) + node T_1187 = bits(T_1186, 5, 0) + infer accessor T_1189 = tgtPages[UInt<6>("h03a")] + node T_1191 = dshl(UInt<1>("h01"), T_1189) + node T_1192 = bits(T_1191, 5, 0) + infer accessor T_1194 = tgtPages[UInt<6>("h03b")] + node T_1196 = dshl(UInt<1>("h01"), T_1194) + node T_1197 = bits(T_1196, 5, 0) + infer accessor T_1199 = tgtPages[UInt<6>("h03c")] + node T_1201 = dshl(UInt<1>("h01"), T_1199) + node T_1202 = bits(T_1201, 5, 0) + infer accessor T_1204 = tgtPages[UInt<6>("h03d")] + node T_1206 = dshl(UInt<1>("h01"), T_1204) + node T_1207 = bits(T_1206, 5, 0) + reg useRAS : UInt<1>[62], clock, reset + reg isJump : UInt<1>[62], clock, reset + cmem brIdx : UInt<1>[62], clock + reg T_1477 : UInt<1>, clock, reset + onreset T_1477 := UInt<1>("h00") + T_1477 := btb_update.valid + reg T_1478 : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}, clock, reset + when btb_update.valid : + T_1478 <> btb_update.bits + skip + wire r_btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}} + r_btb_update.bits.br_pc := UInt<1>("h00") + r_btb_update.bits.isReturn := UInt<1>("h00") + r_btb_update.bits.isJump := UInt<1>("h00") + r_btb_update.bits.taken := UInt<1>("h00") + r_btb_update.bits.target := UInt<1>("h00") + r_btb_update.bits.pc := UInt<1>("h00") + r_btb_update.bits.prediction.bits.bht.value := UInt<1>("h00") + r_btb_update.bits.prediction.bits.bht.history := UInt<1>("h00") + r_btb_update.bits.prediction.bits.entry := UInt<1>("h00") + r_btb_update.bits.prediction.bits.target := UInt<1>("h00") + r_btb_update.bits.prediction.bits.bridx := UInt<1>("h00") + r_btb_update.bits.prediction.bits.mask := UInt<1>("h00") + r_btb_update.bits.prediction.bits.taken := UInt<1>("h00") + r_btb_update.bits.prediction.valid := UInt<1>("h00") + r_btb_update.valid := UInt<1>("h00") + r_btb_update.valid := T_1477 + r_btb_update.bits <> T_1478 + node T_1677 = shr(req.bits.addr, 12) + infer accessor T_1679 = pages[UInt<1>("h00")] + node T_1680 = eq(T_1679, T_1677) + infer accessor T_1682 = pages[UInt<1>("h01")] + node T_1683 = eq(T_1682, T_1677) + infer accessor T_1685 = pages[UInt<2>("h02")] + node T_1686 = eq(T_1685, T_1677) + infer accessor T_1688 = pages[UInt<2>("h03")] + node T_1689 = eq(T_1688, T_1677) + infer accessor T_1691 = pages[UInt<3>("h04")] + node T_1692 = eq(T_1691, T_1677) + infer accessor T_1694 = pages[UInt<3>("h05")] + node T_1695 = eq(T_1694, T_1677) + wire T_1697 : UInt<1>[6] + T_1697[0] := T_1680 + T_1697[1] := T_1683 + T_1697[2] := T_1686 + T_1697[3] := T_1689 + T_1697[4] := T_1692 + T_1697[5] := T_1695 + node T_1705 = cat(T_1697[4], T_1697[3]) + node T_1706 = cat(T_1697[5], T_1705) + node T_1707 = cat(T_1697[1], T_1697[0]) + node T_1708 = cat(T_1697[2], T_1707) + node T_1709 = cat(T_1706, T_1708) + node pageHit = and(T_1709, pageValid) + node T_1711 = bits(req.bits.addr, 11, 0) + infer accessor T_1713 = idxs[UInt<1>("h00")] + node T_1714 = eq(T_1713, T_1711) + infer accessor T_1716 = idxs[UInt<1>("h01")] + node T_1717 = eq(T_1716, T_1711) + infer accessor T_1719 = idxs[UInt<2>("h02")] + node T_1720 = eq(T_1719, T_1711) + infer accessor T_1722 = idxs[UInt<2>("h03")] + node T_1723 = eq(T_1722, T_1711) + infer accessor T_1725 = idxs[UInt<3>("h04")] + node T_1726 = eq(T_1725, T_1711) + infer accessor T_1728 = idxs[UInt<3>("h05")] + node T_1729 = eq(T_1728, T_1711) + infer accessor T_1731 = idxs[UInt<3>("h06")] + node T_1732 = eq(T_1731, T_1711) + infer accessor T_1734 = idxs[UInt<3>("h07")] + node T_1735 = eq(T_1734, T_1711) + infer accessor T_1737 = idxs[UInt<4>("h08")] + node T_1738 = eq(T_1737, T_1711) + infer accessor T_1740 = idxs[UInt<4>("h09")] + node T_1741 = eq(T_1740, T_1711) + infer accessor T_1743 = idxs[UInt<4>("h0a")] + node T_1744 = eq(T_1743, T_1711) + infer accessor T_1746 = idxs[UInt<4>("h0b")] + node T_1747 = eq(T_1746, T_1711) + infer accessor T_1749 = idxs[UInt<4>("h0c")] + node T_1750 = eq(T_1749, T_1711) + infer accessor T_1752 = idxs[UInt<4>("h0d")] + node T_1753 = eq(T_1752, T_1711) + infer accessor T_1755 = idxs[UInt<4>("h0e")] + node T_1756 = eq(T_1755, T_1711) + infer accessor T_1758 = idxs[UInt<4>("h0f")] + node T_1759 = eq(T_1758, T_1711) + infer accessor T_1761 = idxs[UInt<5>("h010")] + node T_1762 = eq(T_1761, T_1711) + infer accessor T_1764 = idxs[UInt<5>("h011")] + node T_1765 = eq(T_1764, T_1711) + infer accessor T_1767 = idxs[UInt<5>("h012")] + node T_1768 = eq(T_1767, T_1711) + infer accessor T_1770 = idxs[UInt<5>("h013")] + node T_1771 = eq(T_1770, T_1711) + infer accessor T_1773 = idxs[UInt<5>("h014")] + node T_1774 = eq(T_1773, T_1711) + infer accessor T_1776 = idxs[UInt<5>("h015")] + node T_1777 = eq(T_1776, T_1711) + infer accessor T_1779 = idxs[UInt<5>("h016")] + node T_1780 = eq(T_1779, T_1711) + infer accessor T_1782 = idxs[UInt<5>("h017")] + node T_1783 = eq(T_1782, T_1711) + infer accessor T_1785 = idxs[UInt<5>("h018")] + node T_1786 = eq(T_1785, T_1711) + infer accessor T_1788 = idxs[UInt<5>("h019")] + node T_1789 = eq(T_1788, T_1711) + infer accessor T_1791 = idxs[UInt<5>("h01a")] + node T_1792 = eq(T_1791, T_1711) + infer accessor T_1794 = idxs[UInt<5>("h01b")] + node T_1795 = eq(T_1794, T_1711) + infer accessor T_1797 = idxs[UInt<5>("h01c")] + node T_1798 = eq(T_1797, T_1711) + infer accessor T_1800 = idxs[UInt<5>("h01d")] + node T_1801 = eq(T_1800, T_1711) + infer accessor T_1803 = idxs[UInt<5>("h01e")] + node T_1804 = eq(T_1803, T_1711) + infer accessor T_1806 = idxs[UInt<5>("h01f")] + node T_1807 = eq(T_1806, T_1711) + infer accessor T_1809 = idxs[UInt<6>("h020")] + node T_1810 = eq(T_1809, T_1711) + infer accessor T_1812 = idxs[UInt<6>("h021")] + node T_1813 = eq(T_1812, T_1711) + infer accessor T_1815 = idxs[UInt<6>("h022")] + node T_1816 = eq(T_1815, T_1711) + infer accessor T_1818 = idxs[UInt<6>("h023")] + node T_1819 = eq(T_1818, T_1711) + infer accessor T_1821 = idxs[UInt<6>("h024")] + node T_1822 = eq(T_1821, T_1711) + infer accessor T_1824 = idxs[UInt<6>("h025")] + node T_1825 = eq(T_1824, T_1711) + infer accessor T_1827 = idxs[UInt<6>("h026")] + node T_1828 = eq(T_1827, T_1711) + infer accessor T_1830 = idxs[UInt<6>("h027")] + node T_1831 = eq(T_1830, T_1711) + infer accessor T_1833 = idxs[UInt<6>("h028")] + node T_1834 = eq(T_1833, T_1711) + infer accessor T_1836 = idxs[UInt<6>("h029")] + node T_1837 = eq(T_1836, T_1711) + infer accessor T_1839 = idxs[UInt<6>("h02a")] + node T_1840 = eq(T_1839, T_1711) + infer accessor T_1842 = idxs[UInt<6>("h02b")] + node T_1843 = eq(T_1842, T_1711) + infer accessor T_1845 = idxs[UInt<6>("h02c")] + node T_1846 = eq(T_1845, T_1711) + infer accessor T_1848 = idxs[UInt<6>("h02d")] + node T_1849 = eq(T_1848, T_1711) + infer accessor T_1851 = idxs[UInt<6>("h02e")] + node T_1852 = eq(T_1851, T_1711) + infer accessor T_1854 = idxs[UInt<6>("h02f")] + node T_1855 = eq(T_1854, T_1711) + infer accessor T_1857 = idxs[UInt<6>("h030")] + node T_1858 = eq(T_1857, T_1711) + infer accessor T_1860 = idxs[UInt<6>("h031")] + node T_1861 = eq(T_1860, T_1711) + infer accessor T_1863 = idxs[UInt<6>("h032")] + node T_1864 = eq(T_1863, T_1711) + infer accessor T_1866 = idxs[UInt<6>("h033")] + node T_1867 = eq(T_1866, T_1711) + infer accessor T_1869 = idxs[UInt<6>("h034")] + node T_1870 = eq(T_1869, T_1711) + infer accessor T_1872 = idxs[UInt<6>("h035")] + node T_1873 = eq(T_1872, T_1711) + infer accessor T_1875 = idxs[UInt<6>("h036")] + node T_1876 = eq(T_1875, T_1711) + infer accessor T_1878 = idxs[UInt<6>("h037")] + node T_1879 = eq(T_1878, T_1711) + infer accessor T_1881 = idxs[UInt<6>("h038")] + node T_1882 = eq(T_1881, T_1711) + infer accessor T_1884 = idxs[UInt<6>("h039")] + node T_1885 = eq(T_1884, T_1711) + infer accessor T_1887 = idxs[UInt<6>("h03a")] + node T_1888 = eq(T_1887, T_1711) + infer accessor T_1890 = idxs[UInt<6>("h03b")] + node T_1891 = eq(T_1890, T_1711) + infer accessor T_1893 = idxs[UInt<6>("h03c")] + node T_1894 = eq(T_1893, T_1711) + infer accessor T_1896 = idxs[UInt<6>("h03d")] + node T_1897 = eq(T_1896, T_1711) + wire T_1899 : UInt<1>[62] + T_1899[0] := T_1714 + T_1899[1] := T_1717 + T_1899[2] := T_1720 + T_1899[3] := T_1723 + T_1899[4] := T_1726 + T_1899[5] := T_1729 + T_1899[6] := T_1732 + T_1899[7] := T_1735 + T_1899[8] := T_1738 + T_1899[9] := T_1741 + T_1899[10] := T_1744 + T_1899[11] := T_1747 + T_1899[12] := T_1750 + T_1899[13] := T_1753 + T_1899[14] := T_1756 + T_1899[15] := T_1759 + T_1899[16] := T_1762 + T_1899[17] := T_1765 + T_1899[18] := T_1768 + T_1899[19] := T_1771 + T_1899[20] := T_1774 + T_1899[21] := T_1777 + T_1899[22] := T_1780 + T_1899[23] := T_1783 + T_1899[24] := T_1786 + T_1899[25] := T_1789 + T_1899[26] := T_1792 + T_1899[27] := T_1795 + T_1899[28] := T_1798 + T_1899[29] := T_1801 + T_1899[30] := T_1804 + T_1899[31] := T_1807 + T_1899[32] := T_1810 + T_1899[33] := T_1813 + T_1899[34] := T_1816 + T_1899[35] := T_1819 + T_1899[36] := T_1822 + T_1899[37] := T_1825 + T_1899[38] := T_1828 + T_1899[39] := T_1831 + T_1899[40] := T_1834 + T_1899[41] := T_1837 + T_1899[42] := T_1840 + T_1899[43] := T_1843 + T_1899[44] := T_1846 + T_1899[45] := T_1849 + T_1899[46] := T_1852 + T_1899[47] := T_1855 + T_1899[48] := T_1858 + T_1899[49] := T_1861 + T_1899[50] := T_1864 + T_1899[51] := T_1867 + T_1899[52] := T_1870 + T_1899[53] := T_1873 + T_1899[54] := T_1876 + T_1899[55] := T_1879 + T_1899[56] := T_1882 + T_1899[57] := T_1885 + T_1899[58] := T_1888 + T_1899[59] := T_1891 + T_1899[60] := T_1894 + T_1899[61] := T_1897 + node T_1963 = cat(T_1899[60], T_1899[59]) + node T_1964 = cat(T_1899[61], T_1963) + node T_1965 = cat(T_1899[58], T_1899[57]) + node T_1966 = cat(T_1899[56], T_1899[55]) + node T_1967 = cat(T_1965, T_1966) + node T_1968 = cat(T_1964, T_1967) + node T_1969 = cat(T_1899[54], T_1899[53]) + node T_1970 = cat(T_1899[52], T_1899[51]) + node T_1971 = cat(T_1969, T_1970) + node T_1972 = cat(T_1899[50], T_1899[49]) + node T_1973 = cat(T_1899[48], T_1899[47]) + node T_1974 = cat(T_1972, T_1973) + node T_1975 = cat(T_1971, T_1974) + node T_1976 = cat(T_1968, T_1975) + node T_1977 = cat(T_1899[46], T_1899[45]) + node T_1978 = cat(T_1899[44], T_1899[43]) + node T_1979 = cat(T_1977, T_1978) + node T_1980 = cat(T_1899[42], T_1899[41]) + node T_1981 = cat(T_1899[40], T_1899[39]) + node T_1982 = cat(T_1980, T_1981) + node T_1983 = cat(T_1979, T_1982) + node T_1984 = cat(T_1899[38], T_1899[37]) + node T_1985 = cat(T_1899[36], T_1899[35]) + node T_1986 = cat(T_1984, T_1985) + node T_1987 = cat(T_1899[34], T_1899[33]) + node T_1988 = cat(T_1899[32], T_1899[31]) + node T_1989 = cat(T_1987, T_1988) + node T_1990 = cat(T_1986, T_1989) + node T_1991 = cat(T_1983, T_1990) + node T_1992 = cat(T_1976, T_1991) + node T_1993 = cat(T_1899[29], T_1899[28]) + node T_1994 = cat(T_1899[30], T_1993) + node T_1995 = cat(T_1899[27], T_1899[26]) + node T_1996 = cat(T_1899[25], T_1899[24]) + node T_1997 = cat(T_1995, T_1996) + node T_1998 = cat(T_1994, T_1997) + node T_1999 = cat(T_1899[23], T_1899[22]) + node T_2000 = cat(T_1899[21], T_1899[20]) + node T_2001 = cat(T_1999, T_2000) + node T_2002 = cat(T_1899[19], T_1899[18]) + node T_2003 = cat(T_1899[17], T_1899[16]) + node T_2004 = cat(T_2002, T_2003) + node T_2005 = cat(T_2001, T_2004) + node T_2006 = cat(T_1998, T_2005) + node T_2007 = cat(T_1899[15], T_1899[14]) + node T_2008 = cat(T_1899[13], T_1899[12]) + node T_2009 = cat(T_2007, T_2008) + node T_2010 = cat(T_1899[11], T_1899[10]) + node T_2011 = cat(T_1899[9], T_1899[8]) + node T_2012 = cat(T_2010, T_2011) + node T_2013 = cat(T_2009, T_2012) + node T_2014 = cat(T_1899[7], T_1899[6]) + node T_2015 = cat(T_1899[5], T_1899[4]) + node T_2016 = cat(T_2014, T_2015) + node T_2017 = cat(T_1899[3], T_1899[2]) + node T_2018 = cat(T_1899[1], T_1899[0]) + node T_2019 = cat(T_2017, T_2018) + node T_2020 = cat(T_2016, T_2019) + node T_2021 = cat(T_2013, T_2020) + node T_2022 = cat(T_2006, T_2021) + node T_2023 = cat(T_1992, T_2022) + node T_2024 = and(T_592, pageHit) + node T_2025 = and(T_597, pageHit) + node T_2026 = and(T_602, pageHit) + node T_2027 = and(T_607, pageHit) + node T_2028 = and(T_612, pageHit) + node T_2029 = and(T_617, pageHit) + node T_2030 = and(T_622, pageHit) + node T_2031 = and(T_627, pageHit) + node T_2032 = and(T_632, pageHit) + node T_2033 = and(T_637, pageHit) + node T_2034 = and(T_642, pageHit) + node T_2035 = and(T_647, pageHit) + node T_2036 = and(T_652, pageHit) + node T_2037 = and(T_657, pageHit) + node T_2038 = and(T_662, pageHit) + node T_2039 = and(T_667, pageHit) + node T_2040 = and(T_672, pageHit) + node T_2041 = and(T_677, pageHit) + node T_2042 = and(T_682, pageHit) + node T_2043 = and(T_687, pageHit) + node T_2044 = and(T_692, pageHit) + node T_2045 = and(T_697, pageHit) + node T_2046 = and(T_702, pageHit) + node T_2047 = and(T_707, pageHit) + node T_2048 = and(T_712, pageHit) + node T_2049 = and(T_717, pageHit) + node T_2050 = and(T_722, pageHit) + node T_2051 = and(T_727, pageHit) + node T_2052 = and(T_732, pageHit) + node T_2053 = and(T_737, pageHit) + node T_2054 = and(T_742, pageHit) + node T_2055 = and(T_747, pageHit) + node T_2056 = and(T_752, pageHit) + node T_2057 = and(T_757, pageHit) + node T_2058 = and(T_762, pageHit) + node T_2059 = and(T_767, pageHit) + node T_2060 = and(T_772, pageHit) + node T_2061 = and(T_777, pageHit) + node T_2062 = and(T_782, pageHit) + node T_2063 = and(T_787, pageHit) + node T_2064 = and(T_792, pageHit) + node T_2065 = and(T_797, pageHit) + node T_2066 = and(T_802, pageHit) + node T_2067 = and(T_807, pageHit) + node T_2068 = and(T_812, pageHit) + node T_2069 = and(T_817, pageHit) + node T_2070 = and(T_822, pageHit) + node T_2071 = and(T_827, pageHit) + node T_2072 = and(T_832, pageHit) + node T_2073 = and(T_837, pageHit) + node T_2074 = and(T_842, pageHit) + node T_2075 = and(T_847, pageHit) + node T_2076 = and(T_852, pageHit) + node T_2077 = and(T_857, pageHit) + node T_2078 = and(T_862, pageHit) + node T_2079 = and(T_867, pageHit) + node T_2080 = and(T_872, pageHit) + node T_2081 = and(T_877, pageHit) + node T_2082 = and(T_882, pageHit) + node T_2083 = and(T_887, pageHit) + node T_2084 = and(T_892, pageHit) + node T_2085 = and(T_897, pageHit) + node T_2087 = neq(T_2024, UInt<1>("h00")) + node T_2089 = neq(T_2025, UInt<1>("h00")) + node T_2091 = neq(T_2026, UInt<1>("h00")) + node T_2093 = neq(T_2027, UInt<1>("h00")) + node T_2095 = neq(T_2028, UInt<1>("h00")) + node T_2097 = neq(T_2029, UInt<1>("h00")) + node T_2099 = neq(T_2030, UInt<1>("h00")) + node T_2101 = neq(T_2031, UInt<1>("h00")) + node T_2103 = neq(T_2032, UInt<1>("h00")) + node T_2105 = neq(T_2033, UInt<1>("h00")) + node T_2107 = neq(T_2034, UInt<1>("h00")) + node T_2109 = neq(T_2035, UInt<1>("h00")) + node T_2111 = neq(T_2036, UInt<1>("h00")) + node T_2113 = neq(T_2037, UInt<1>("h00")) + node T_2115 = neq(T_2038, UInt<1>("h00")) + node T_2117 = neq(T_2039, UInt<1>("h00")) + node T_2119 = neq(T_2040, UInt<1>("h00")) + node T_2121 = neq(T_2041, UInt<1>("h00")) + node T_2123 = neq(T_2042, UInt<1>("h00")) + node T_2125 = neq(T_2043, UInt<1>("h00")) + node T_2127 = neq(T_2044, UInt<1>("h00")) + node T_2129 = neq(T_2045, UInt<1>("h00")) + node T_2131 = neq(T_2046, UInt<1>("h00")) + node T_2133 = neq(T_2047, UInt<1>("h00")) + node T_2135 = neq(T_2048, UInt<1>("h00")) + node T_2137 = neq(T_2049, UInt<1>("h00")) + node T_2139 = neq(T_2050, UInt<1>("h00")) + node T_2141 = neq(T_2051, UInt<1>("h00")) + node T_2143 = neq(T_2052, UInt<1>("h00")) + node T_2145 = neq(T_2053, UInt<1>("h00")) + node T_2147 = neq(T_2054, UInt<1>("h00")) + node T_2149 = neq(T_2055, UInt<1>("h00")) + node T_2151 = neq(T_2056, UInt<1>("h00")) + node T_2153 = neq(T_2057, UInt<1>("h00")) + node T_2155 = neq(T_2058, UInt<1>("h00")) + node T_2157 = neq(T_2059, UInt<1>("h00")) + node T_2159 = neq(T_2060, UInt<1>("h00")) + node T_2161 = neq(T_2061, UInt<1>("h00")) + node T_2163 = neq(T_2062, UInt<1>("h00")) + node T_2165 = neq(T_2063, UInt<1>("h00")) + node T_2167 = neq(T_2064, UInt<1>("h00")) + node T_2169 = neq(T_2065, UInt<1>("h00")) + node T_2171 = neq(T_2066, UInt<1>("h00")) + node T_2173 = neq(T_2067, UInt<1>("h00")) + node T_2175 = neq(T_2068, UInt<1>("h00")) + node T_2177 = neq(T_2069, UInt<1>("h00")) + node T_2179 = neq(T_2070, UInt<1>("h00")) + node T_2181 = neq(T_2071, UInt<1>("h00")) + node T_2183 = neq(T_2072, UInt<1>("h00")) + node T_2185 = neq(T_2073, UInt<1>("h00")) + node T_2187 = neq(T_2074, UInt<1>("h00")) + node T_2189 = neq(T_2075, UInt<1>("h00")) + node T_2191 = neq(T_2076, UInt<1>("h00")) + node T_2193 = neq(T_2077, UInt<1>("h00")) + node T_2195 = neq(T_2078, UInt<1>("h00")) + node T_2197 = neq(T_2079, UInt<1>("h00")) + node T_2199 = neq(T_2080, UInt<1>("h00")) + node T_2201 = neq(T_2081, UInt<1>("h00")) + node T_2203 = neq(T_2082, UInt<1>("h00")) + node T_2205 = neq(T_2083, UInt<1>("h00")) + node T_2207 = neq(T_2084, UInt<1>("h00")) + node T_2209 = neq(T_2085, UInt<1>("h00")) + wire T_2211 : UInt<1>[62] + T_2211[0] := T_2087 + T_2211[1] := T_2089 + T_2211[2] := T_2091 + T_2211[3] := T_2093 + T_2211[4] := T_2095 + T_2211[5] := T_2097 + T_2211[6] := T_2099 + T_2211[7] := T_2101 + T_2211[8] := T_2103 + T_2211[9] := T_2105 + T_2211[10] := T_2107 + T_2211[11] := T_2109 + T_2211[12] := T_2111 + T_2211[13] := T_2113 + T_2211[14] := T_2115 + T_2211[15] := T_2117 + T_2211[16] := T_2119 + T_2211[17] := T_2121 + T_2211[18] := T_2123 + T_2211[19] := T_2125 + T_2211[20] := T_2127 + T_2211[21] := T_2129 + T_2211[22] := T_2131 + T_2211[23] := T_2133 + T_2211[24] := T_2135 + T_2211[25] := T_2137 + T_2211[26] := T_2139 + T_2211[27] := T_2141 + T_2211[28] := T_2143 + T_2211[29] := T_2145 + T_2211[30] := T_2147 + T_2211[31] := T_2149 + T_2211[32] := T_2151 + T_2211[33] := T_2153 + T_2211[34] := T_2155 + T_2211[35] := T_2157 + T_2211[36] := T_2159 + T_2211[37] := T_2161 + T_2211[38] := T_2163 + T_2211[39] := T_2165 + T_2211[40] := T_2167 + T_2211[41] := T_2169 + T_2211[42] := T_2171 + T_2211[43] := T_2173 + T_2211[44] := T_2175 + T_2211[45] := T_2177 + T_2211[46] := T_2179 + T_2211[47] := T_2181 + T_2211[48] := T_2183 + T_2211[49] := T_2185 + T_2211[50] := T_2187 + T_2211[51] := T_2189 + T_2211[52] := T_2191 + T_2211[53] := T_2193 + T_2211[54] := T_2195 + T_2211[55] := T_2197 + T_2211[56] := T_2199 + T_2211[57] := T_2201 + T_2211[58] := T_2203 + T_2211[59] := T_2205 + T_2211[60] := T_2207 + T_2211[61] := T_2209 + node T_2275 = cat(T_2211[60], T_2211[59]) + node T_2276 = cat(T_2211[61], T_2275) + node T_2277 = cat(T_2211[58], T_2211[57]) + node T_2278 = cat(T_2211[56], T_2211[55]) + node T_2279 = cat(T_2277, T_2278) + node T_2280 = cat(T_2276, T_2279) + node T_2281 = cat(T_2211[54], T_2211[53]) + node T_2282 = cat(T_2211[52], T_2211[51]) + node T_2283 = cat(T_2281, T_2282) + node T_2284 = cat(T_2211[50], T_2211[49]) + node T_2285 = cat(T_2211[48], T_2211[47]) + node T_2286 = cat(T_2284, T_2285) + node T_2287 = cat(T_2283, T_2286) + node T_2288 = cat(T_2280, T_2287) + node T_2289 = cat(T_2211[46], T_2211[45]) + node T_2290 = cat(T_2211[44], T_2211[43]) + node T_2291 = cat(T_2289, T_2290) + node T_2292 = cat(T_2211[42], T_2211[41]) + node T_2293 = cat(T_2211[40], T_2211[39]) + node T_2294 = cat(T_2292, T_2293) + node T_2295 = cat(T_2291, T_2294) + node T_2296 = cat(T_2211[38], T_2211[37]) + node T_2297 = cat(T_2211[36], T_2211[35]) + node T_2298 = cat(T_2296, T_2297) + node T_2299 = cat(T_2211[34], T_2211[33]) + node T_2300 = cat(T_2211[32], T_2211[31]) + node T_2301 = cat(T_2299, T_2300) + node T_2302 = cat(T_2298, T_2301) + node T_2303 = cat(T_2295, T_2302) + node T_2304 = cat(T_2288, T_2303) + node T_2305 = cat(T_2211[29], T_2211[28]) + node T_2306 = cat(T_2211[30], T_2305) + node T_2307 = cat(T_2211[27], T_2211[26]) + node T_2308 = cat(T_2211[25], T_2211[24]) + node T_2309 = cat(T_2307, T_2308) + node T_2310 = cat(T_2306, T_2309) + node T_2311 = cat(T_2211[23], T_2211[22]) + node T_2312 = cat(T_2211[21], T_2211[20]) + node T_2313 = cat(T_2311, T_2312) + node T_2314 = cat(T_2211[19], T_2211[18]) + node T_2315 = cat(T_2211[17], T_2211[16]) + node T_2316 = cat(T_2314, T_2315) + node T_2317 = cat(T_2313, T_2316) + node T_2318 = cat(T_2310, T_2317) + node T_2319 = cat(T_2211[15], T_2211[14]) + node T_2320 = cat(T_2211[13], T_2211[12]) + node T_2321 = cat(T_2319, T_2320) + node T_2322 = cat(T_2211[11], T_2211[10]) + node T_2323 = cat(T_2211[9], T_2211[8]) + node T_2324 = cat(T_2322, T_2323) + node T_2325 = cat(T_2321, T_2324) + node T_2326 = cat(T_2211[7], T_2211[6]) + node T_2327 = cat(T_2211[5], T_2211[4]) + node T_2328 = cat(T_2326, T_2327) + node T_2329 = cat(T_2211[3], T_2211[2]) + node T_2330 = cat(T_2211[1], T_2211[0]) + node T_2331 = cat(T_2329, T_2330) + node T_2332 = cat(T_2328, T_2331) + node T_2333 = cat(T_2325, T_2332) + node T_2334 = cat(T_2318, T_2333) + node T_2335 = cat(T_2304, T_2334) + node T_2336 = and(idxValid, T_2023) + node hits = and(T_2336, T_2335) + node T_2338 = shr(r_btb_update.bits.pc, 12) + infer accessor T_2340 = pages[UInt<1>("h00")] + node T_2341 = eq(T_2340, T_2338) + infer accessor T_2343 = pages[UInt<1>("h01")] + node T_2344 = eq(T_2343, T_2338) + infer accessor T_2346 = pages[UInt<2>("h02")] + node T_2347 = eq(T_2346, T_2338) + infer accessor T_2349 = pages[UInt<2>("h03")] + node T_2350 = eq(T_2349, T_2338) + infer accessor T_2352 = pages[UInt<3>("h04")] + node T_2353 = eq(T_2352, T_2338) + infer accessor T_2355 = pages[UInt<3>("h05")] + node T_2356 = eq(T_2355, T_2338) + wire T_2358 : UInt<1>[6] + T_2358[0] := T_2341 + T_2358[1] := T_2344 + T_2358[2] := T_2347 + T_2358[3] := T_2350 + T_2358[4] := T_2353 + T_2358[5] := T_2356 + node T_2366 = cat(T_2358[4], T_2358[3]) + node T_2367 = cat(T_2358[5], T_2366) + node T_2368 = cat(T_2358[1], T_2358[0]) + node T_2369 = cat(T_2358[2], T_2368) + node T_2370 = cat(T_2367, T_2369) + node updatePageHit = and(T_2370, pageValid) + node T_2372 = bits(r_btb_update.bits.pc, 11, 0) + infer accessor T_2374 = idxs[UInt<1>("h00")] + node T_2375 = eq(T_2374, T_2372) + infer accessor T_2377 = idxs[UInt<1>("h01")] + node T_2378 = eq(T_2377, T_2372) + infer accessor T_2380 = idxs[UInt<2>("h02")] + node T_2381 = eq(T_2380, T_2372) + infer accessor T_2383 = idxs[UInt<2>("h03")] + node T_2384 = eq(T_2383, T_2372) + infer accessor T_2386 = idxs[UInt<3>("h04")] + node T_2387 = eq(T_2386, T_2372) + infer accessor T_2389 = idxs[UInt<3>("h05")] + node T_2390 = eq(T_2389, T_2372) + infer accessor T_2392 = idxs[UInt<3>("h06")] + node T_2393 = eq(T_2392, T_2372) + infer accessor T_2395 = idxs[UInt<3>("h07")] + node T_2396 = eq(T_2395, T_2372) + infer accessor T_2398 = idxs[UInt<4>("h08")] + node T_2399 = eq(T_2398, T_2372) + infer accessor T_2401 = idxs[UInt<4>("h09")] + node T_2402 = eq(T_2401, T_2372) + infer accessor T_2404 = idxs[UInt<4>("h0a")] + node T_2405 = eq(T_2404, T_2372) + infer accessor T_2407 = idxs[UInt<4>("h0b")] + node T_2408 = eq(T_2407, T_2372) + infer accessor T_2410 = idxs[UInt<4>("h0c")] + node T_2411 = eq(T_2410, T_2372) + infer accessor T_2413 = idxs[UInt<4>("h0d")] + node T_2414 = eq(T_2413, T_2372) + infer accessor T_2416 = idxs[UInt<4>("h0e")] + node T_2417 = eq(T_2416, T_2372) + infer accessor T_2419 = idxs[UInt<4>("h0f")] + node T_2420 = eq(T_2419, T_2372) + infer accessor T_2422 = idxs[UInt<5>("h010")] + node T_2423 = eq(T_2422, T_2372) + infer accessor T_2425 = idxs[UInt<5>("h011")] + node T_2426 = eq(T_2425, T_2372) + infer accessor T_2428 = idxs[UInt<5>("h012")] + node T_2429 = eq(T_2428, T_2372) + infer accessor T_2431 = idxs[UInt<5>("h013")] + node T_2432 = eq(T_2431, T_2372) + infer accessor T_2434 = idxs[UInt<5>("h014")] + node T_2435 = eq(T_2434, T_2372) + infer accessor T_2437 = idxs[UInt<5>("h015")] + node T_2438 = eq(T_2437, T_2372) + infer accessor T_2440 = idxs[UInt<5>("h016")] + node T_2441 = eq(T_2440, T_2372) + infer accessor T_2443 = idxs[UInt<5>("h017")] + node T_2444 = eq(T_2443, T_2372) + infer accessor T_2446 = idxs[UInt<5>("h018")] + node T_2447 = eq(T_2446, T_2372) + infer accessor T_2449 = idxs[UInt<5>("h019")] + node T_2450 = eq(T_2449, T_2372) + infer accessor T_2452 = idxs[UInt<5>("h01a")] + node T_2453 = eq(T_2452, T_2372) + infer accessor T_2455 = idxs[UInt<5>("h01b")] + node T_2456 = eq(T_2455, T_2372) + infer accessor T_2458 = idxs[UInt<5>("h01c")] + node T_2459 = eq(T_2458, T_2372) + infer accessor T_2461 = idxs[UInt<5>("h01d")] + node T_2462 = eq(T_2461, T_2372) + infer accessor T_2464 = idxs[UInt<5>("h01e")] + node T_2465 = eq(T_2464, T_2372) + infer accessor T_2467 = idxs[UInt<5>("h01f")] + node T_2468 = eq(T_2467, T_2372) + infer accessor T_2470 = idxs[UInt<6>("h020")] + node T_2471 = eq(T_2470, T_2372) + infer accessor T_2473 = idxs[UInt<6>("h021")] + node T_2474 = eq(T_2473, T_2372) + infer accessor T_2476 = idxs[UInt<6>("h022")] + node T_2477 = eq(T_2476, T_2372) + infer accessor T_2479 = idxs[UInt<6>("h023")] + node T_2480 = eq(T_2479, T_2372) + infer accessor T_2482 = idxs[UInt<6>("h024")] + node T_2483 = eq(T_2482, T_2372) + infer accessor T_2485 = idxs[UInt<6>("h025")] + node T_2486 = eq(T_2485, T_2372) + infer accessor T_2488 = idxs[UInt<6>("h026")] + node T_2489 = eq(T_2488, T_2372) + infer accessor T_2491 = idxs[UInt<6>("h027")] + node T_2492 = eq(T_2491, T_2372) + infer accessor T_2494 = idxs[UInt<6>("h028")] + node T_2495 = eq(T_2494, T_2372) + infer accessor T_2497 = idxs[UInt<6>("h029")] + node T_2498 = eq(T_2497, T_2372) + infer accessor T_2500 = idxs[UInt<6>("h02a")] + node T_2501 = eq(T_2500, T_2372) + infer accessor T_2503 = idxs[UInt<6>("h02b")] + node T_2504 = eq(T_2503, T_2372) + infer accessor T_2506 = idxs[UInt<6>("h02c")] + node T_2507 = eq(T_2506, T_2372) + infer accessor T_2509 = idxs[UInt<6>("h02d")] + node T_2510 = eq(T_2509, T_2372) + infer accessor T_2512 = idxs[UInt<6>("h02e")] + node T_2513 = eq(T_2512, T_2372) + infer accessor T_2515 = idxs[UInt<6>("h02f")] + node T_2516 = eq(T_2515, T_2372) + infer accessor T_2518 = idxs[UInt<6>("h030")] + node T_2519 = eq(T_2518, T_2372) + infer accessor T_2521 = idxs[UInt<6>("h031")] + node T_2522 = eq(T_2521, T_2372) + infer accessor T_2524 = idxs[UInt<6>("h032")] + node T_2525 = eq(T_2524, T_2372) + infer accessor T_2527 = idxs[UInt<6>("h033")] + node T_2528 = eq(T_2527, T_2372) + infer accessor T_2530 = idxs[UInt<6>("h034")] + node T_2531 = eq(T_2530, T_2372) + infer accessor T_2533 = idxs[UInt<6>("h035")] + node T_2534 = eq(T_2533, T_2372) + infer accessor T_2536 = idxs[UInt<6>("h036")] + node T_2537 = eq(T_2536, T_2372) + infer accessor T_2539 = idxs[UInt<6>("h037")] + node T_2540 = eq(T_2539, T_2372) + infer accessor T_2542 = idxs[UInt<6>("h038")] + node T_2543 = eq(T_2542, T_2372) + infer accessor T_2545 = idxs[UInt<6>("h039")] + node T_2546 = eq(T_2545, T_2372) + infer accessor T_2548 = idxs[UInt<6>("h03a")] + node T_2549 = eq(T_2548, T_2372) + infer accessor T_2551 = idxs[UInt<6>("h03b")] + node T_2552 = eq(T_2551, T_2372) + infer accessor T_2554 = idxs[UInt<6>("h03c")] + node T_2555 = eq(T_2554, T_2372) + infer accessor T_2557 = idxs[UInt<6>("h03d")] + node T_2558 = eq(T_2557, T_2372) + wire T_2560 : UInt<1>[62] + T_2560[0] := T_2375 + T_2560[1] := T_2378 + T_2560[2] := T_2381 + T_2560[3] := T_2384 + T_2560[4] := T_2387 + T_2560[5] := T_2390 + T_2560[6] := T_2393 + T_2560[7] := T_2396 + T_2560[8] := T_2399 + T_2560[9] := T_2402 + T_2560[10] := T_2405 + T_2560[11] := T_2408 + T_2560[12] := T_2411 + T_2560[13] := T_2414 + T_2560[14] := T_2417 + T_2560[15] := T_2420 + T_2560[16] := T_2423 + T_2560[17] := T_2426 + T_2560[18] := T_2429 + T_2560[19] := T_2432 + T_2560[20] := T_2435 + T_2560[21] := T_2438 + T_2560[22] := T_2441 + T_2560[23] := T_2444 + T_2560[24] := T_2447 + T_2560[25] := T_2450 + T_2560[26] := T_2453 + T_2560[27] := T_2456 + T_2560[28] := T_2459 + T_2560[29] := T_2462 + T_2560[30] := T_2465 + T_2560[31] := T_2468 + T_2560[32] := T_2471 + T_2560[33] := T_2474 + T_2560[34] := T_2477 + T_2560[35] := T_2480 + T_2560[36] := T_2483 + T_2560[37] := T_2486 + T_2560[38] := T_2489 + T_2560[39] := T_2492 + T_2560[40] := T_2495 + T_2560[41] := T_2498 + T_2560[42] := T_2501 + T_2560[43] := T_2504 + T_2560[44] := T_2507 + T_2560[45] := T_2510 + T_2560[46] := T_2513 + T_2560[47] := T_2516 + T_2560[48] := T_2519 + T_2560[49] := T_2522 + T_2560[50] := T_2525 + T_2560[51] := T_2528 + T_2560[52] := T_2531 + T_2560[53] := T_2534 + T_2560[54] := T_2537 + T_2560[55] := T_2540 + T_2560[56] := T_2543 + T_2560[57] := T_2546 + T_2560[58] := T_2549 + T_2560[59] := T_2552 + T_2560[60] := T_2555 + T_2560[61] := T_2558 + node T_2624 = cat(T_2560[60], T_2560[59]) + node T_2625 = cat(T_2560[61], T_2624) + node T_2626 = cat(T_2560[58], T_2560[57]) + node T_2627 = cat(T_2560[56], T_2560[55]) + node T_2628 = cat(T_2626, T_2627) + node T_2629 = cat(T_2625, T_2628) + node T_2630 = cat(T_2560[54], T_2560[53]) + node T_2631 = cat(T_2560[52], T_2560[51]) + node T_2632 = cat(T_2630, T_2631) + node T_2633 = cat(T_2560[50], T_2560[49]) + node T_2634 = cat(T_2560[48], T_2560[47]) + node T_2635 = cat(T_2633, T_2634) + node T_2636 = cat(T_2632, T_2635) + node T_2637 = cat(T_2629, T_2636) + node T_2638 = cat(T_2560[46], T_2560[45]) + node T_2639 = cat(T_2560[44], T_2560[43]) + node T_2640 = cat(T_2638, T_2639) + node T_2641 = cat(T_2560[42], T_2560[41]) + node T_2642 = cat(T_2560[40], T_2560[39]) + node T_2643 = cat(T_2641, T_2642) + node T_2644 = cat(T_2640, T_2643) + node T_2645 = cat(T_2560[38], T_2560[37]) + node T_2646 = cat(T_2560[36], T_2560[35]) + node T_2647 = cat(T_2645, T_2646) + node T_2648 = cat(T_2560[34], T_2560[33]) + node T_2649 = cat(T_2560[32], T_2560[31]) + node T_2650 = cat(T_2648, T_2649) + node T_2651 = cat(T_2647, T_2650) + node T_2652 = cat(T_2644, T_2651) + node T_2653 = cat(T_2637, T_2652) + node T_2654 = cat(T_2560[29], T_2560[28]) + node T_2655 = cat(T_2560[30], T_2654) + node T_2656 = cat(T_2560[27], T_2560[26]) + node T_2657 = cat(T_2560[25], T_2560[24]) + node T_2658 = cat(T_2656, T_2657) + node T_2659 = cat(T_2655, T_2658) + node T_2660 = cat(T_2560[23], T_2560[22]) + node T_2661 = cat(T_2560[21], T_2560[20]) + node T_2662 = cat(T_2660, T_2661) + node T_2663 = cat(T_2560[19], T_2560[18]) + node T_2664 = cat(T_2560[17], T_2560[16]) + node T_2665 = cat(T_2663, T_2664) + node T_2666 = cat(T_2662, T_2665) + node T_2667 = cat(T_2659, T_2666) + node T_2668 = cat(T_2560[15], T_2560[14]) + node T_2669 = cat(T_2560[13], T_2560[12]) + node T_2670 = cat(T_2668, T_2669) + node T_2671 = cat(T_2560[11], T_2560[10]) + node T_2672 = cat(T_2560[9], T_2560[8]) + node T_2673 = cat(T_2671, T_2672) + node T_2674 = cat(T_2670, T_2673) + node T_2675 = cat(T_2560[7], T_2560[6]) + node T_2676 = cat(T_2560[5], T_2560[4]) + node T_2677 = cat(T_2675, T_2676) + node T_2678 = cat(T_2560[3], T_2560[2]) + node T_2679 = cat(T_2560[1], T_2560[0]) + node T_2680 = cat(T_2678, T_2679) + node T_2681 = cat(T_2677, T_2680) + node T_2682 = cat(T_2674, T_2681) + node T_2683 = cat(T_2667, T_2682) + node T_2684 = cat(T_2653, T_2683) + node T_2685 = and(T_592, updatePageHit) + node T_2686 = and(T_597, updatePageHit) + node T_2687 = and(T_602, updatePageHit) + node T_2688 = and(T_607, updatePageHit) + node T_2689 = and(T_612, updatePageHit) + node T_2690 = and(T_617, updatePageHit) + node T_2691 = and(T_622, updatePageHit) + node T_2692 = and(T_627, updatePageHit) + node T_2693 = and(T_632, updatePageHit) + node T_2694 = and(T_637, updatePageHit) + node T_2695 = and(T_642, updatePageHit) + node T_2696 = and(T_647, updatePageHit) + node T_2697 = and(T_652, updatePageHit) + node T_2698 = and(T_657, updatePageHit) + node T_2699 = and(T_662, updatePageHit) + node T_2700 = and(T_667, updatePageHit) + node T_2701 = and(T_672, updatePageHit) + node T_2702 = and(T_677, updatePageHit) + node T_2703 = and(T_682, updatePageHit) + node T_2704 = and(T_687, updatePageHit) + node T_2705 = and(T_692, updatePageHit) + node T_2706 = and(T_697, updatePageHit) + node T_2707 = and(T_702, updatePageHit) + node T_2708 = and(T_707, updatePageHit) + node T_2709 = and(T_712, updatePageHit) + node T_2710 = and(T_717, updatePageHit) + node T_2711 = and(T_722, updatePageHit) + node T_2712 = and(T_727, updatePageHit) + node T_2713 = and(T_732, updatePageHit) + node T_2714 = and(T_737, updatePageHit) + node T_2715 = and(T_742, updatePageHit) + node T_2716 = and(T_747, updatePageHit) + node T_2717 = and(T_752, updatePageHit) + node T_2718 = and(T_757, updatePageHit) + node T_2719 = and(T_762, updatePageHit) + node T_2720 = and(T_767, updatePageHit) + node T_2721 = and(T_772, updatePageHit) + node T_2722 = and(T_777, updatePageHit) + node T_2723 = and(T_782, updatePageHit) + node T_2724 = and(T_787, updatePageHit) + node T_2725 = and(T_792, updatePageHit) + node T_2726 = and(T_797, updatePageHit) + node T_2727 = and(T_802, updatePageHit) + node T_2728 = and(T_807, updatePageHit) + node T_2729 = and(T_812, updatePageHit) + node T_2730 = and(T_817, updatePageHit) + node T_2731 = and(T_822, updatePageHit) + node T_2732 = and(T_827, updatePageHit) + node T_2733 = and(T_832, updatePageHit) + node T_2734 = and(T_837, updatePageHit) + node T_2735 = and(T_842, updatePageHit) + node T_2736 = and(T_847, updatePageHit) + node T_2737 = and(T_852, updatePageHit) + node T_2738 = and(T_857, updatePageHit) + node T_2739 = and(T_862, updatePageHit) + node T_2740 = and(T_867, updatePageHit) + node T_2741 = and(T_872, updatePageHit) + node T_2742 = and(T_877, updatePageHit) + node T_2743 = and(T_882, updatePageHit) + node T_2744 = and(T_887, updatePageHit) + node T_2745 = and(T_892, updatePageHit) + node T_2746 = and(T_897, updatePageHit) + node T_2748 = neq(T_2685, UInt<1>("h00")) + node T_2750 = neq(T_2686, UInt<1>("h00")) + node T_2752 = neq(T_2687, UInt<1>("h00")) + node T_2754 = neq(T_2688, UInt<1>("h00")) + node T_2756 = neq(T_2689, UInt<1>("h00")) + node T_2758 = neq(T_2690, UInt<1>("h00")) + node T_2760 = neq(T_2691, UInt<1>("h00")) + node T_2762 = neq(T_2692, UInt<1>("h00")) + node T_2764 = neq(T_2693, UInt<1>("h00")) + node T_2766 = neq(T_2694, UInt<1>("h00")) + node T_2768 = neq(T_2695, UInt<1>("h00")) + node T_2770 = neq(T_2696, UInt<1>("h00")) + node T_2772 = neq(T_2697, UInt<1>("h00")) + node T_2774 = neq(T_2698, UInt<1>("h00")) + node T_2776 = neq(T_2699, UInt<1>("h00")) + node T_2778 = neq(T_2700, UInt<1>("h00")) + node T_2780 = neq(T_2701, UInt<1>("h00")) + node T_2782 = neq(T_2702, UInt<1>("h00")) + node T_2784 = neq(T_2703, UInt<1>("h00")) + node T_2786 = neq(T_2704, UInt<1>("h00")) + node T_2788 = neq(T_2705, UInt<1>("h00")) + node T_2790 = neq(T_2706, UInt<1>("h00")) + node T_2792 = neq(T_2707, UInt<1>("h00")) + node T_2794 = neq(T_2708, UInt<1>("h00")) + node T_2796 = neq(T_2709, UInt<1>("h00")) + node T_2798 = neq(T_2710, UInt<1>("h00")) + node T_2800 = neq(T_2711, UInt<1>("h00")) + node T_2802 = neq(T_2712, UInt<1>("h00")) + node T_2804 = neq(T_2713, UInt<1>("h00")) + node T_2806 = neq(T_2714, UInt<1>("h00")) + node T_2808 = neq(T_2715, UInt<1>("h00")) + node T_2810 = neq(T_2716, UInt<1>("h00")) + node T_2812 = neq(T_2717, UInt<1>("h00")) + node T_2814 = neq(T_2718, UInt<1>("h00")) + node T_2816 = neq(T_2719, UInt<1>("h00")) + node T_2818 = neq(T_2720, UInt<1>("h00")) + node T_2820 = neq(T_2721, UInt<1>("h00")) + node T_2822 = neq(T_2722, UInt<1>("h00")) + node T_2824 = neq(T_2723, UInt<1>("h00")) + node T_2826 = neq(T_2724, UInt<1>("h00")) + node T_2828 = neq(T_2725, UInt<1>("h00")) + node T_2830 = neq(T_2726, UInt<1>("h00")) + node T_2832 = neq(T_2727, UInt<1>("h00")) + node T_2834 = neq(T_2728, UInt<1>("h00")) + node T_2836 = neq(T_2729, UInt<1>("h00")) + node T_2838 = neq(T_2730, UInt<1>("h00")) + node T_2840 = neq(T_2731, UInt<1>("h00")) + node T_2842 = neq(T_2732, UInt<1>("h00")) + node T_2844 = neq(T_2733, UInt<1>("h00")) + node T_2846 = neq(T_2734, UInt<1>("h00")) + node T_2848 = neq(T_2735, UInt<1>("h00")) + node T_2850 = neq(T_2736, UInt<1>("h00")) + node T_2852 = neq(T_2737, UInt<1>("h00")) + node T_2854 = neq(T_2738, UInt<1>("h00")) + node T_2856 = neq(T_2739, UInt<1>("h00")) + node T_2858 = neq(T_2740, UInt<1>("h00")) + node T_2860 = neq(T_2741, UInt<1>("h00")) + node T_2862 = neq(T_2742, UInt<1>("h00")) + node T_2864 = neq(T_2743, UInt<1>("h00")) + node T_2866 = neq(T_2744, UInt<1>("h00")) + node T_2868 = neq(T_2745, UInt<1>("h00")) + node T_2870 = neq(T_2746, UInt<1>("h00")) + wire T_2872 : UInt<1>[62] + T_2872[0] := T_2748 + T_2872[1] := T_2750 + T_2872[2] := T_2752 + T_2872[3] := T_2754 + T_2872[4] := T_2756 + T_2872[5] := T_2758 + T_2872[6] := T_2760 + T_2872[7] := T_2762 + T_2872[8] := T_2764 + T_2872[9] := T_2766 + T_2872[10] := T_2768 + T_2872[11] := T_2770 + T_2872[12] := T_2772 + T_2872[13] := T_2774 + T_2872[14] := T_2776 + T_2872[15] := T_2778 + T_2872[16] := T_2780 + T_2872[17] := T_2782 + T_2872[18] := T_2784 + T_2872[19] := T_2786 + T_2872[20] := T_2788 + T_2872[21] := T_2790 + T_2872[22] := T_2792 + T_2872[23] := T_2794 + T_2872[24] := T_2796 + T_2872[25] := T_2798 + T_2872[26] := T_2800 + T_2872[27] := T_2802 + T_2872[28] := T_2804 + T_2872[29] := T_2806 + T_2872[30] := T_2808 + T_2872[31] := T_2810 + T_2872[32] := T_2812 + T_2872[33] := T_2814 + T_2872[34] := T_2816 + T_2872[35] := T_2818 + T_2872[36] := T_2820 + T_2872[37] := T_2822 + T_2872[38] := T_2824 + T_2872[39] := T_2826 + T_2872[40] := T_2828 + T_2872[41] := T_2830 + T_2872[42] := T_2832 + T_2872[43] := T_2834 + T_2872[44] := T_2836 + T_2872[45] := T_2838 + T_2872[46] := T_2840 + T_2872[47] := T_2842 + T_2872[48] := T_2844 + T_2872[49] := T_2846 + T_2872[50] := T_2848 + T_2872[51] := T_2850 + T_2872[52] := T_2852 + T_2872[53] := T_2854 + T_2872[54] := T_2856 + T_2872[55] := T_2858 + T_2872[56] := T_2860 + T_2872[57] := T_2862 + T_2872[58] := T_2864 + T_2872[59] := T_2866 + T_2872[60] := T_2868 + T_2872[61] := T_2870 + node T_2936 = cat(T_2872[60], T_2872[59]) + node T_2937 = cat(T_2872[61], T_2936) + node T_2938 = cat(T_2872[58], T_2872[57]) + node T_2939 = cat(T_2872[56], T_2872[55]) + node T_2940 = cat(T_2938, T_2939) + node T_2941 = cat(T_2937, T_2940) + node T_2942 = cat(T_2872[54], T_2872[53]) + node T_2943 = cat(T_2872[52], T_2872[51]) + node T_2944 = cat(T_2942, T_2943) + node T_2945 = cat(T_2872[50], T_2872[49]) + node T_2946 = cat(T_2872[48], T_2872[47]) + node T_2947 = cat(T_2945, T_2946) + node T_2948 = cat(T_2944, T_2947) + node T_2949 = cat(T_2941, T_2948) + node T_2950 = cat(T_2872[46], T_2872[45]) + node T_2951 = cat(T_2872[44], T_2872[43]) + node T_2952 = cat(T_2950, T_2951) + node T_2953 = cat(T_2872[42], T_2872[41]) + node T_2954 = cat(T_2872[40], T_2872[39]) + node T_2955 = cat(T_2953, T_2954) + node T_2956 = cat(T_2952, T_2955) + node T_2957 = cat(T_2872[38], T_2872[37]) + node T_2958 = cat(T_2872[36], T_2872[35]) + node T_2959 = cat(T_2957, T_2958) + node T_2960 = cat(T_2872[34], T_2872[33]) + node T_2961 = cat(T_2872[32], T_2872[31]) + node T_2962 = cat(T_2960, T_2961) + node T_2963 = cat(T_2959, T_2962) + node T_2964 = cat(T_2956, T_2963) + node T_2965 = cat(T_2949, T_2964) + node T_2966 = cat(T_2872[29], T_2872[28]) + node T_2967 = cat(T_2872[30], T_2966) + node T_2968 = cat(T_2872[27], T_2872[26]) + node T_2969 = cat(T_2872[25], T_2872[24]) + node T_2970 = cat(T_2968, T_2969) + node T_2971 = cat(T_2967, T_2970) + node T_2972 = cat(T_2872[23], T_2872[22]) + node T_2973 = cat(T_2872[21], T_2872[20]) + node T_2974 = cat(T_2972, T_2973) + node T_2975 = cat(T_2872[19], T_2872[18]) + node T_2976 = cat(T_2872[17], T_2872[16]) + node T_2977 = cat(T_2975, T_2976) + node T_2978 = cat(T_2974, T_2977) + node T_2979 = cat(T_2971, T_2978) + node T_2980 = cat(T_2872[15], T_2872[14]) + node T_2981 = cat(T_2872[13], T_2872[12]) + node T_2982 = cat(T_2980, T_2981) + node T_2983 = cat(T_2872[11], T_2872[10]) + node T_2984 = cat(T_2872[9], T_2872[8]) + node T_2985 = cat(T_2983, T_2984) + node T_2986 = cat(T_2982, T_2985) + node T_2987 = cat(T_2872[7], T_2872[6]) + node T_2988 = cat(T_2872[5], T_2872[4]) + node T_2989 = cat(T_2987, T_2988) + node T_2990 = cat(T_2872[3], T_2872[2]) + node T_2991 = cat(T_2872[1], T_2872[0]) + node T_2992 = cat(T_2990, T_2991) + node T_2993 = cat(T_2989, T_2992) + node T_2994 = cat(T_2986, T_2993) + node T_2995 = cat(T_2979, T_2994) + node T_2996 = cat(T_2965, T_2995) + node T_2997 = and(idxValid, T_2684) + node updateHits = and(T_2997, T_2996) + reg T_3000 : UInt<16>, clock, reset + onreset T_3000 := UInt<16>("h01") + when r_btb_update.valid : + node T_3001 = bit(T_3000, 0) + node T_3002 = bit(T_3000, 2) + node T_3003 = xor(T_3001, T_3002) + node T_3004 = bit(T_3000, 3) + node T_3005 = xor(T_3003, T_3004) + node T_3006 = bit(T_3000, 5) + node T_3007 = xor(T_3005, T_3006) + node T_3008 = bits(T_3000, 15, 1) + node T_3009 = cat(T_3007, T_3008) + T_3000 := T_3009 + skip + node useUpdatePageHit = neq(updatePageHit, UInt<1>("h00")) + node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>("h00")) + wire idxPageRepl : UInt<6> + idxPageRepl := UInt<1>("h00") + node idxPageUpdateOH = mux(useUpdatePageHit, updatePageHit, idxPageRepl) + node T_3018 = bits(idxPageUpdateOH, 5, 4) + node T_3019 = bits(idxPageUpdateOH, 3, 0) + node T_3021 = neq(T_3018, UInt<1>("h00")) + node T_3022 = or(T_3018, T_3019) + node T_3023 = bits(T_3022, 3, 2) + node T_3024 = bits(T_3022, 1, 0) + node T_3026 = neq(T_3023, UInt<1>("h00")) + node T_3027 = or(T_3023, T_3024) + node T_3028 = bit(T_3027, 1) + node T_3029 = cat(T_3026, T_3028) + node idxPageUpdate = cat(T_3021, T_3029) + node idxPageReplEn = mux(doIdxPageRepl, idxPageRepl, UInt<1>("h00")) + node T_3033 = shr(r_btb_update.bits.pc, 12) + node T_3034 = shr(req.bits.addr, 12) + node samePage = eq(T_3033, T_3034) + node T_3036 = not(idxPageReplEn) + node T_3037 = and(pageHit, T_3036) + node usePageHit = neq(T_3037, UInt<1>("h00")) + node T_3041 = eq(samePage, UInt<1>("h00")) + node T_3043 = eq(usePageHit, UInt<1>("h00")) + node doTgtPageRepl = and(T_3041, T_3043) + node T_3045 = bits(idxPageUpdateOH, 4, 0) + node T_3046 = shl(T_3045, 1) + node T_3047 = bit(idxPageUpdateOH, 5) + node T_3048 = or(T_3046, T_3047) + node tgtPageRepl = mux(samePage, idxPageUpdateOH, T_3048) + node T_3050 = mux(usePageHit, pageHit, tgtPageRepl) + node T_3051 = bits(T_3050, 5, 4) + node T_3052 = bits(T_3050, 3, 0) + node T_3054 = neq(T_3051, UInt<1>("h00")) + node T_3055 = or(T_3051, T_3052) + node T_3056 = bits(T_3055, 3, 2) + node T_3057 = bits(T_3055, 1, 0) + node T_3059 = neq(T_3056, UInt<1>("h00")) + node T_3060 = or(T_3056, T_3057) + node T_3061 = bit(T_3060, 1) + node T_3062 = cat(T_3059, T_3061) + node tgtPageUpdate = cat(T_3054, T_3062) + node tgtPageReplEn = mux(doTgtPageRepl, tgtPageRepl, UInt<1>("h00")) + node doPageRepl = or(doIdxPageRepl, doTgtPageRepl) + node pageReplEn = or(idxPageReplEn, tgtPageReplEn) + node T_3068 = and(r_btb_update.valid, doPageRepl) + reg T_3070 : UInt<3>, clock, reset + onreset T_3070 := UInt<3>("h00") + when T_3068 : + node T_3072 = eq(T_3070, UInt<3>("h05")) + node T_3074 = and(UInt<1>("h01"), T_3072) + node T_3077 = addw(T_3070, UInt<1>("h01")) + node T_3078 = mux(T_3074, UInt<1>("h00"), T_3077) + T_3070 := T_3078 + skip + node T_3079 = and(T_3068, T_3072) + node T_3081 = dshl(UInt<1>("h01"), T_3070) + idxPageRepl := T_3081 + when r_btb_update.valid : + node T_3082 = eq(req.bits.addr, r_btb_update.bits.target) + node T_3084 = eq(r_btb_update.bits.prediction.valid, UInt<1>("h00")) + reg T_3086 : UInt<6>, clock, reset + onreset T_3086 := UInt<6>("h00") + when T_3084 : + node T_3088 = eq(T_3086, UInt<6>("h03d")) + node T_3090 = and(UInt<1>("h01"), T_3088) + node T_3093 = addw(T_3086, UInt<1>("h01")) + node T_3094 = mux(T_3090, UInt<1>("h00"), T_3093) + T_3086 := T_3094 + skip + node T_3095 = and(T_3084, T_3088) + node T_3096 = mux(r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry, T_3086) + node T_3097 = or(T_592, T_902) + node T_3098 = and(pageReplEn, T_3097) + node T_3100 = neq(T_3098, UInt<1>("h00")) + node T_3101 = or(T_597, T_907) + node T_3102 = and(pageReplEn, T_3101) + node T_3104 = neq(T_3102, UInt<1>("h00")) + node T_3105 = or(T_602, T_912) + node T_3106 = and(pageReplEn, T_3105) + node T_3108 = neq(T_3106, UInt<1>("h00")) + node T_3109 = or(T_607, T_917) + node T_3110 = and(pageReplEn, T_3109) + node T_3112 = neq(T_3110, UInt<1>("h00")) + node T_3113 = or(T_612, T_922) + node T_3114 = and(pageReplEn, T_3113) + node T_3116 = neq(T_3114, UInt<1>("h00")) + node T_3117 = or(T_617, T_927) + node T_3118 = and(pageReplEn, T_3117) + node T_3120 = neq(T_3118, UInt<1>("h00")) + node T_3121 = or(T_622, T_932) + node T_3122 = and(pageReplEn, T_3121) + node T_3124 = neq(T_3122, UInt<1>("h00")) + node T_3125 = or(T_627, T_937) + node T_3126 = and(pageReplEn, T_3125) + node T_3128 = neq(T_3126, UInt<1>("h00")) + node T_3129 = or(T_632, T_942) + node T_3130 = and(pageReplEn, T_3129) + node T_3132 = neq(T_3130, UInt<1>("h00")) + node T_3133 = or(T_637, T_947) + node T_3134 = and(pageReplEn, T_3133) + node T_3136 = neq(T_3134, UInt<1>("h00")) + node T_3137 = or(T_642, T_952) + node T_3138 = and(pageReplEn, T_3137) + node T_3140 = neq(T_3138, UInt<1>("h00")) + node T_3141 = or(T_647, T_957) + node T_3142 = and(pageReplEn, T_3141) + node T_3144 = neq(T_3142, UInt<1>("h00")) + node T_3145 = or(T_652, T_962) + node T_3146 = and(pageReplEn, T_3145) + node T_3148 = neq(T_3146, UInt<1>("h00")) + node T_3149 = or(T_657, T_967) + node T_3150 = and(pageReplEn, T_3149) + node T_3152 = neq(T_3150, UInt<1>("h00")) + node T_3153 = or(T_662, T_972) + node T_3154 = and(pageReplEn, T_3153) + node T_3156 = neq(T_3154, UInt<1>("h00")) + node T_3157 = or(T_667, T_977) + node T_3158 = and(pageReplEn, T_3157) + node T_3160 = neq(T_3158, UInt<1>("h00")) + node T_3161 = or(T_672, T_982) + node T_3162 = and(pageReplEn, T_3161) + node T_3164 = neq(T_3162, UInt<1>("h00")) + node T_3165 = or(T_677, T_987) + node T_3166 = and(pageReplEn, T_3165) + node T_3168 = neq(T_3166, UInt<1>("h00")) + node T_3169 = or(T_682, T_992) + node T_3170 = and(pageReplEn, T_3169) + node T_3172 = neq(T_3170, UInt<1>("h00")) + node T_3173 = or(T_687, T_997) + node T_3174 = and(pageReplEn, T_3173) + node T_3176 = neq(T_3174, UInt<1>("h00")) + node T_3177 = or(T_692, T_1002) + node T_3178 = and(pageReplEn, T_3177) + node T_3180 = neq(T_3178, UInt<1>("h00")) + node T_3181 = or(T_697, T_1007) + node T_3182 = and(pageReplEn, T_3181) + node T_3184 = neq(T_3182, UInt<1>("h00")) + node T_3185 = or(T_702, T_1012) + node T_3186 = and(pageReplEn, T_3185) + node T_3188 = neq(T_3186, UInt<1>("h00")) + node T_3189 = or(T_707, T_1017) + node T_3190 = and(pageReplEn, T_3189) + node T_3192 = neq(T_3190, UInt<1>("h00")) + node T_3193 = or(T_712, T_1022) + node T_3194 = and(pageReplEn, T_3193) + node T_3196 = neq(T_3194, UInt<1>("h00")) + node T_3197 = or(T_717, T_1027) + node T_3198 = and(pageReplEn, T_3197) + node T_3200 = neq(T_3198, UInt<1>("h00")) + node T_3201 = or(T_722, T_1032) + node T_3202 = and(pageReplEn, T_3201) + node T_3204 = neq(T_3202, UInt<1>("h00")) + node T_3205 = or(T_727, T_1037) + node T_3206 = and(pageReplEn, T_3205) + node T_3208 = neq(T_3206, UInt<1>("h00")) + node T_3209 = or(T_732, T_1042) + node T_3210 = and(pageReplEn, T_3209) + node T_3212 = neq(T_3210, UInt<1>("h00")) + node T_3213 = or(T_737, T_1047) + node T_3214 = and(pageReplEn, T_3213) + node T_3216 = neq(T_3214, UInt<1>("h00")) + node T_3217 = or(T_742, T_1052) + node T_3218 = and(pageReplEn, T_3217) + node T_3220 = neq(T_3218, UInt<1>("h00")) + node T_3221 = or(T_747, T_1057) + node T_3222 = and(pageReplEn, T_3221) + node T_3224 = neq(T_3222, UInt<1>("h00")) + node T_3225 = or(T_752, T_1062) + node T_3226 = and(pageReplEn, T_3225) + node T_3228 = neq(T_3226, UInt<1>("h00")) + node T_3229 = or(T_757, T_1067) + node T_3230 = and(pageReplEn, T_3229) + node T_3232 = neq(T_3230, UInt<1>("h00")) + node T_3233 = or(T_762, T_1072) + node T_3234 = and(pageReplEn, T_3233) + node T_3236 = neq(T_3234, UInt<1>("h00")) + node T_3237 = or(T_767, T_1077) + node T_3238 = and(pageReplEn, T_3237) + node T_3240 = neq(T_3238, UInt<1>("h00")) + node T_3241 = or(T_772, T_1082) + node T_3242 = and(pageReplEn, T_3241) + node T_3244 = neq(T_3242, UInt<1>("h00")) + node T_3245 = or(T_777, T_1087) + node T_3246 = and(pageReplEn, T_3245) + node T_3248 = neq(T_3246, UInt<1>("h00")) + node T_3249 = or(T_782, T_1092) + node T_3250 = and(pageReplEn, T_3249) + node T_3252 = neq(T_3250, UInt<1>("h00")) + node T_3253 = or(T_787, T_1097) + node T_3254 = and(pageReplEn, T_3253) + node T_3256 = neq(T_3254, UInt<1>("h00")) + node T_3257 = or(T_792, T_1102) + node T_3258 = and(pageReplEn, T_3257) + node T_3260 = neq(T_3258, UInt<1>("h00")) + node T_3261 = or(T_797, T_1107) + node T_3262 = and(pageReplEn, T_3261) + node T_3264 = neq(T_3262, UInt<1>("h00")) + node T_3265 = or(T_802, T_1112) + node T_3266 = and(pageReplEn, T_3265) + node T_3268 = neq(T_3266, UInt<1>("h00")) + node T_3269 = or(T_807, T_1117) + node T_3270 = and(pageReplEn, T_3269) + node T_3272 = neq(T_3270, UInt<1>("h00")) + node T_3273 = or(T_812, T_1122) + node T_3274 = and(pageReplEn, T_3273) + node T_3276 = neq(T_3274, UInt<1>("h00")) + node T_3277 = or(T_817, T_1127) + node T_3278 = and(pageReplEn, T_3277) + node T_3280 = neq(T_3278, UInt<1>("h00")) + node T_3281 = or(T_822, T_1132) + node T_3282 = and(pageReplEn, T_3281) + node T_3284 = neq(T_3282, UInt<1>("h00")) + node T_3285 = or(T_827, T_1137) + node T_3286 = and(pageReplEn, T_3285) + node T_3288 = neq(T_3286, UInt<1>("h00")) + node T_3289 = or(T_832, T_1142) + node T_3290 = and(pageReplEn, T_3289) + node T_3292 = neq(T_3290, UInt<1>("h00")) + node T_3293 = or(T_837, T_1147) + node T_3294 = and(pageReplEn, T_3293) + node T_3296 = neq(T_3294, UInt<1>("h00")) + node T_3297 = or(T_842, T_1152) + node T_3298 = and(pageReplEn, T_3297) + node T_3300 = neq(T_3298, UInt<1>("h00")) + node T_3301 = or(T_847, T_1157) + node T_3302 = and(pageReplEn, T_3301) + node T_3304 = neq(T_3302, UInt<1>("h00")) + node T_3305 = or(T_852, T_1162) + node T_3306 = and(pageReplEn, T_3305) + node T_3308 = neq(T_3306, UInt<1>("h00")) + node T_3309 = or(T_857, T_1167) + node T_3310 = and(pageReplEn, T_3309) + node T_3312 = neq(T_3310, UInt<1>("h00")) + node T_3313 = or(T_862, T_1172) + node T_3314 = and(pageReplEn, T_3313) + node T_3316 = neq(T_3314, UInt<1>("h00")) + node T_3317 = or(T_867, T_1177) + node T_3318 = and(pageReplEn, T_3317) + node T_3320 = neq(T_3318, UInt<1>("h00")) + node T_3321 = or(T_872, T_1182) + node T_3322 = and(pageReplEn, T_3321) + node T_3324 = neq(T_3322, UInt<1>("h00")) + node T_3325 = or(T_877, T_1187) + node T_3326 = and(pageReplEn, T_3325) + node T_3328 = neq(T_3326, UInt<1>("h00")) + node T_3329 = or(T_882, T_1192) + node T_3330 = and(pageReplEn, T_3329) + node T_3332 = neq(T_3330, UInt<1>("h00")) + node T_3333 = or(T_887, T_1197) + node T_3334 = and(pageReplEn, T_3333) + node T_3336 = neq(T_3334, UInt<1>("h00")) + node T_3337 = or(T_892, T_1202) + node T_3338 = and(pageReplEn, T_3337) + node T_3340 = neq(T_3338, UInt<1>("h00")) + node T_3341 = or(T_897, T_1207) + node T_3342 = and(pageReplEn, T_3341) + node T_3344 = neq(T_3342, UInt<1>("h00")) + wire T_3346 : UInt<1>[62] + T_3346[0] := T_3100 + T_3346[1] := T_3104 + T_3346[2] := T_3108 + T_3346[3] := T_3112 + T_3346[4] := T_3116 + T_3346[5] := T_3120 + T_3346[6] := T_3124 + T_3346[7] := T_3128 + T_3346[8] := T_3132 + T_3346[9] := T_3136 + T_3346[10] := T_3140 + T_3346[11] := T_3144 + T_3346[12] := T_3148 + T_3346[13] := T_3152 + T_3346[14] := T_3156 + T_3346[15] := T_3160 + T_3346[16] := T_3164 + T_3346[17] := T_3168 + T_3346[18] := T_3172 + T_3346[19] := T_3176 + T_3346[20] := T_3180 + T_3346[21] := T_3184 + T_3346[22] := T_3188 + T_3346[23] := T_3192 + T_3346[24] := T_3196 + T_3346[25] := T_3200 + T_3346[26] := T_3204 + T_3346[27] := T_3208 + T_3346[28] := T_3212 + T_3346[29] := T_3216 + T_3346[30] := T_3220 + T_3346[31] := T_3224 + T_3346[32] := T_3228 + T_3346[33] := T_3232 + T_3346[34] := T_3236 + T_3346[35] := T_3240 + T_3346[36] := T_3244 + T_3346[37] := T_3248 + T_3346[38] := T_3252 + T_3346[39] := T_3256 + T_3346[40] := T_3260 + T_3346[41] := T_3264 + T_3346[42] := T_3268 + T_3346[43] := T_3272 + T_3346[44] := T_3276 + T_3346[45] := T_3280 + T_3346[46] := T_3284 + T_3346[47] := T_3288 + T_3346[48] := T_3292 + T_3346[49] := T_3296 + T_3346[50] := T_3300 + T_3346[51] := T_3304 + T_3346[52] := T_3308 + T_3346[53] := T_3312 + T_3346[54] := T_3316 + T_3346[55] := T_3320 + T_3346[56] := T_3324 + T_3346[57] := T_3328 + T_3346[58] := T_3332 + T_3346[59] := T_3336 + T_3346[60] := T_3340 + T_3346[61] := T_3344 + node T_3410 = cat(T_3346[60], T_3346[59]) + node T_3411 = cat(T_3346[61], T_3410) + node T_3412 = cat(T_3346[58], T_3346[57]) + node T_3413 = cat(T_3346[56], T_3346[55]) + node T_3414 = cat(T_3412, T_3413) + node T_3415 = cat(T_3411, T_3414) + node T_3416 = cat(T_3346[54], T_3346[53]) + node T_3417 = cat(T_3346[52], T_3346[51]) + node T_3418 = cat(T_3416, T_3417) + node T_3419 = cat(T_3346[50], T_3346[49]) + node T_3420 = cat(T_3346[48], T_3346[47]) + node T_3421 = cat(T_3419, T_3420) + node T_3422 = cat(T_3418, T_3421) + node T_3423 = cat(T_3415, T_3422) + node T_3424 = cat(T_3346[46], T_3346[45]) + node T_3425 = cat(T_3346[44], T_3346[43]) + node T_3426 = cat(T_3424, T_3425) + node T_3427 = cat(T_3346[42], T_3346[41]) + node T_3428 = cat(T_3346[40], T_3346[39]) + node T_3429 = cat(T_3427, T_3428) + node T_3430 = cat(T_3426, T_3429) + node T_3431 = cat(T_3346[38], T_3346[37]) + node T_3432 = cat(T_3346[36], T_3346[35]) + node T_3433 = cat(T_3431, T_3432) + node T_3434 = cat(T_3346[34], T_3346[33]) + node T_3435 = cat(T_3346[32], T_3346[31]) + node T_3436 = cat(T_3434, T_3435) + node T_3437 = cat(T_3433, T_3436) + node T_3438 = cat(T_3430, T_3437) + node T_3439 = cat(T_3423, T_3438) + node T_3440 = cat(T_3346[29], T_3346[28]) + node T_3441 = cat(T_3346[30], T_3440) + node T_3442 = cat(T_3346[27], T_3346[26]) + node T_3443 = cat(T_3346[25], T_3346[24]) + node T_3444 = cat(T_3442, T_3443) + node T_3445 = cat(T_3441, T_3444) + node T_3446 = cat(T_3346[23], T_3346[22]) + node T_3447 = cat(T_3346[21], T_3346[20]) + node T_3448 = cat(T_3446, T_3447) + node T_3449 = cat(T_3346[19], T_3346[18]) + node T_3450 = cat(T_3346[17], T_3346[16]) + node T_3451 = cat(T_3449, T_3450) + node T_3452 = cat(T_3448, T_3451) + node T_3453 = cat(T_3445, T_3452) + node T_3454 = cat(T_3346[15], T_3346[14]) + node T_3455 = cat(T_3346[13], T_3346[12]) + node T_3456 = cat(T_3454, T_3455) + node T_3457 = cat(T_3346[11], T_3346[10]) + node T_3458 = cat(T_3346[9], T_3346[8]) + node T_3459 = cat(T_3457, T_3458) + node T_3460 = cat(T_3456, T_3459) + node T_3461 = cat(T_3346[7], T_3346[6]) + node T_3462 = cat(T_3346[5], T_3346[4]) + node T_3463 = cat(T_3461, T_3462) + node T_3464 = cat(T_3346[3], T_3346[2]) + node T_3465 = cat(T_3346[1], T_3346[0]) + node T_3466 = cat(T_3464, T_3465) + node T_3467 = cat(T_3463, T_3466) + node T_3468 = cat(T_3460, T_3467) + node T_3469 = cat(T_3453, T_3468) + node T_3470 = cat(T_3439, T_3469) + node T_3472 = dshl(UInt<1>("h01"), T_3096) + node T_3473 = not(T_3470) + node T_3474 = and(idxValid, T_3473) + node T_3475 = or(T_3474, T_3472) + idxValid := T_3475 + infer accessor T_3476 = idxs[T_3096] + T_3476 := r_btb_update.bits.pc + infer accessor T_3477 = tgts[T_3096] + T_3477 := req.bits.addr + infer accessor T_3478 = idxPages[T_3096] + T_3478 := idxPageUpdate + infer accessor T_3479 = tgtPages[T_3096] + T_3479 := tgtPageUpdate + infer accessor T_3480 = useRAS[T_3096] + T_3480 := r_btb_update.bits.isReturn + infer accessor T_3481 = isJump[T_3096] + T_3481 := r_btb_update.bits.isJump + infer accessor T_3482 = brIdx[T_3096] + T_3482 := UInt<1>("h00") + node T_3485 = cat(UInt<2>("h01"), UInt<2>("h01")) + node T_3486 = cat(UInt<2>("h01"), T_3485) + node T_3487 = and(idxPageUpdateOH, T_3486) + node T_3489 = neq(T_3487, UInt<1>("h00")) + node T_3490 = mux(T_3489, doIdxPageRepl, doTgtPageRepl) + node T_3491 = shr(r_btb_update.bits.pc, 12) + node T_3492 = shr(req.bits.addr, 12) + node T_3493 = mux(T_3489, T_3491, T_3492) + node T_3494 = bit(pageReplEn, 0) + node T_3495 = and(T_3490, T_3494) + when T_3495 : + infer accessor T_3497 = pages[UInt<1>("h00")] + T_3497 := T_3493 + skip + node T_3498 = bit(pageReplEn, 2) + node T_3499 = and(T_3490, T_3498) + when T_3499 : + infer accessor T_3501 = pages[UInt<2>("h02")] + T_3501 := T_3493 + skip + node T_3502 = bit(pageReplEn, 4) + node T_3503 = and(T_3490, T_3502) + when T_3503 : + infer accessor T_3505 = pages[UInt<3>("h04")] + T_3505 := T_3493 + skip + node T_3506 = mux(T_3489, doTgtPageRepl, doIdxPageRepl) + node T_3507 = shr(req.bits.addr, 12) + node T_3508 = shr(r_btb_update.bits.pc, 12) + node T_3509 = mux(T_3489, T_3507, T_3508) + node T_3510 = bit(pageReplEn, 1) + node T_3511 = and(T_3506, T_3510) + when T_3511 : + infer accessor T_3513 = pages[UInt<1>("h01")] + T_3513 := T_3509 + skip + node T_3514 = bit(pageReplEn, 3) + node T_3515 = and(T_3506, T_3514) + when T_3515 : + infer accessor T_3517 = pages[UInt<2>("h03")] + T_3517 := T_3509 + skip + node T_3518 = bit(pageReplEn, 5) + node T_3519 = and(T_3506, T_3518) + when T_3519 : + infer accessor T_3521 = pages[UInt<3>("h05")] + T_3521 := T_3509 + skip + when doPageRepl : + node T_3522 = or(pageValid, pageReplEn) + pageValid := T_3522 + skip + skip + when invalidate : + idxValid := UInt<1>("h00") + pageValid := UInt<1>("h00") + skip + node T_3526 = neq(hits, UInt<1>("h00")) + resp.valid := T_3526 + resp.bits.taken := resp.valid + node T_3527 = bit(hits, 0) + node T_3528 = bit(hits, 1) + node T_3529 = bit(hits, 2) + node T_3530 = bit(hits, 3) + node T_3531 = bit(hits, 4) + node T_3532 = bit(hits, 5) + node T_3533 = bit(hits, 6) + node T_3534 = bit(hits, 7) + node T_3535 = bit(hits, 8) + node T_3536 = bit(hits, 9) + node T_3537 = bit(hits, 10) + node T_3538 = bit(hits, 11) + node T_3539 = bit(hits, 12) + node T_3540 = bit(hits, 13) + node T_3541 = bit(hits, 14) + node T_3542 = bit(hits, 15) + node T_3543 = bit(hits, 16) + node T_3544 = bit(hits, 17) + node T_3545 = bit(hits, 18) + node T_3546 = bit(hits, 19) + node T_3547 = bit(hits, 20) + node T_3548 = bit(hits, 21) + node T_3549 = bit(hits, 22) + node T_3550 = bit(hits, 23) + node T_3551 = bit(hits, 24) + node T_3552 = bit(hits, 25) + node T_3553 = bit(hits, 26) + node T_3554 = bit(hits, 27) + node T_3555 = bit(hits, 28) + node T_3556 = bit(hits, 29) + node T_3557 = bit(hits, 30) + node T_3558 = bit(hits, 31) + node T_3559 = bit(hits, 32) + node T_3560 = bit(hits, 33) + node T_3561 = bit(hits, 34) + node T_3562 = bit(hits, 35) + node T_3563 = bit(hits, 36) + node T_3564 = bit(hits, 37) + node T_3565 = bit(hits, 38) + node T_3566 = bit(hits, 39) + node T_3567 = bit(hits, 40) + node T_3568 = bit(hits, 41) + node T_3569 = bit(hits, 42) + node T_3570 = bit(hits, 43) + node T_3571 = bit(hits, 44) + node T_3572 = bit(hits, 45) + node T_3573 = bit(hits, 46) + node T_3574 = bit(hits, 47) + node T_3575 = bit(hits, 48) + node T_3576 = bit(hits, 49) + node T_3577 = bit(hits, 50) + node T_3578 = bit(hits, 51) + node T_3579 = bit(hits, 52) + node T_3580 = bit(hits, 53) + node T_3581 = bit(hits, 54) + node T_3582 = bit(hits, 55) + node T_3583 = bit(hits, 56) + node T_3584 = bit(hits, 57) + node T_3585 = bit(hits, 58) + node T_3586 = bit(hits, 59) + node T_3587 = bit(hits, 60) + node T_3588 = bit(hits, 61) + node T_3590 = mux(T_3527, T_902, UInt<1>("h00")) + node T_3592 = mux(T_3528, T_907, UInt<1>("h00")) + node T_3594 = mux(T_3529, T_912, UInt<1>("h00")) + node T_3596 = mux(T_3530, T_917, UInt<1>("h00")) + node T_3598 = mux(T_3531, T_922, UInt<1>("h00")) + node T_3600 = mux(T_3532, T_927, UInt<1>("h00")) + node T_3602 = mux(T_3533, T_932, UInt<1>("h00")) + node T_3604 = mux(T_3534, T_937, UInt<1>("h00")) + node T_3606 = mux(T_3535, T_942, UInt<1>("h00")) + node T_3608 = mux(T_3536, T_947, UInt<1>("h00")) + node T_3610 = mux(T_3537, T_952, UInt<1>("h00")) + node T_3612 = mux(T_3538, T_957, UInt<1>("h00")) + node T_3614 = mux(T_3539, T_962, UInt<1>("h00")) + node T_3616 = mux(T_3540, T_967, UInt<1>("h00")) + node T_3618 = mux(T_3541, T_972, UInt<1>("h00")) + node T_3620 = mux(T_3542, T_977, UInt<1>("h00")) + node T_3622 = mux(T_3543, T_982, UInt<1>("h00")) + node T_3624 = mux(T_3544, T_987, UInt<1>("h00")) + node T_3626 = mux(T_3545, T_992, UInt<1>("h00")) + node T_3628 = mux(T_3546, T_997, UInt<1>("h00")) + node T_3630 = mux(T_3547, T_1002, UInt<1>("h00")) + node T_3632 = mux(T_3548, T_1007, UInt<1>("h00")) + node T_3634 = mux(T_3549, T_1012, UInt<1>("h00")) + node T_3636 = mux(T_3550, T_1017, UInt<1>("h00")) + node T_3638 = mux(T_3551, T_1022, UInt<1>("h00")) + node T_3640 = mux(T_3552, T_1027, UInt<1>("h00")) + node T_3642 = mux(T_3553, T_1032, UInt<1>("h00")) + node T_3644 = mux(T_3554, T_1037, UInt<1>("h00")) + node T_3646 = mux(T_3555, T_1042, UInt<1>("h00")) + node T_3648 = mux(T_3556, T_1047, UInt<1>("h00")) + node T_3650 = mux(T_3557, T_1052, UInt<1>("h00")) + node T_3652 = mux(T_3558, T_1057, UInt<1>("h00")) + node T_3654 = mux(T_3559, T_1062, UInt<1>("h00")) + node T_3656 = mux(T_3560, T_1067, UInt<1>("h00")) + node T_3658 = mux(T_3561, T_1072, UInt<1>("h00")) + node T_3660 = mux(T_3562, T_1077, UInt<1>("h00")) + node T_3662 = mux(T_3563, T_1082, UInt<1>("h00")) + node T_3664 = mux(T_3564, T_1087, UInt<1>("h00")) + node T_3666 = mux(T_3565, T_1092, UInt<1>("h00")) + node T_3668 = mux(T_3566, T_1097, UInt<1>("h00")) + node T_3670 = mux(T_3567, T_1102, UInt<1>("h00")) + node T_3672 = mux(T_3568, T_1107, UInt<1>("h00")) + node T_3674 = mux(T_3569, T_1112, UInt<1>("h00")) + node T_3676 = mux(T_3570, T_1117, UInt<1>("h00")) + node T_3678 = mux(T_3571, T_1122, UInt<1>("h00")) + node T_3680 = mux(T_3572, T_1127, UInt<1>("h00")) + node T_3682 = mux(T_3573, T_1132, UInt<1>("h00")) + node T_3684 = mux(T_3574, T_1137, UInt<1>("h00")) + node T_3686 = mux(T_3575, T_1142, UInt<1>("h00")) + node T_3688 = mux(T_3576, T_1147, UInt<1>("h00")) + node T_3690 = mux(T_3577, T_1152, UInt<1>("h00")) + node T_3692 = mux(T_3578, T_1157, UInt<1>("h00")) + node T_3694 = mux(T_3579, T_1162, UInt<1>("h00")) + node T_3696 = mux(T_3580, T_1167, UInt<1>("h00")) + node T_3698 = mux(T_3581, T_1172, UInt<1>("h00")) + node T_3700 = mux(T_3582, T_1177, UInt<1>("h00")) + node T_3702 = mux(T_3583, T_1182, UInt<1>("h00")) + node T_3704 = mux(T_3584, T_1187, UInt<1>("h00")) + node T_3706 = mux(T_3585, T_1192, UInt<1>("h00")) + node T_3708 = mux(T_3586, T_1197, UInt<1>("h00")) + node T_3710 = mux(T_3587, T_1202, UInt<1>("h00")) + node T_3712 = mux(T_3588, T_1207, UInt<1>("h00")) + node T_3714 = or(T_3590, T_3592) + node T_3715 = or(T_3714, T_3594) + node T_3716 = or(T_3715, T_3596) + node T_3717 = or(T_3716, T_3598) + node T_3718 = or(T_3717, T_3600) + node T_3719 = or(T_3718, T_3602) + node T_3720 = or(T_3719, T_3604) + node T_3721 = or(T_3720, T_3606) + node T_3722 = or(T_3721, T_3608) + node T_3723 = or(T_3722, T_3610) + node T_3724 = or(T_3723, T_3612) + node T_3725 = or(T_3724, T_3614) + node T_3726 = or(T_3725, T_3616) + node T_3727 = or(T_3726, T_3618) + node T_3728 = or(T_3727, T_3620) + node T_3729 = or(T_3728, T_3622) + node T_3730 = or(T_3729, T_3624) + node T_3731 = or(T_3730, T_3626) + node T_3732 = or(T_3731, T_3628) + node T_3733 = or(T_3732, T_3630) + node T_3734 = or(T_3733, T_3632) + node T_3735 = or(T_3734, T_3634) + node T_3736 = or(T_3735, T_3636) + node T_3737 = or(T_3736, T_3638) + node T_3738 = or(T_3737, T_3640) + node T_3739 = or(T_3738, T_3642) + node T_3740 = or(T_3739, T_3644) + node T_3741 = or(T_3740, T_3646) + node T_3742 = or(T_3741, T_3648) + node T_3743 = or(T_3742, T_3650) + node T_3744 = or(T_3743, T_3652) + node T_3745 = or(T_3744, T_3654) + node T_3746 = or(T_3745, T_3656) + node T_3747 = or(T_3746, T_3658) + node T_3748 = or(T_3747, T_3660) + node T_3749 = or(T_3748, T_3662) + node T_3750 = or(T_3749, T_3664) + node T_3751 = or(T_3750, T_3666) + node T_3752 = or(T_3751, T_3668) + node T_3753 = or(T_3752, T_3670) + node T_3754 = or(T_3753, T_3672) + node T_3755 = or(T_3754, T_3674) + node T_3756 = or(T_3755, T_3676) + node T_3757 = or(T_3756, T_3678) + node T_3758 = or(T_3757, T_3680) + node T_3759 = or(T_3758, T_3682) + node T_3760 = or(T_3759, T_3684) + node T_3761 = or(T_3760, T_3686) + node T_3762 = or(T_3761, T_3688) + node T_3763 = or(T_3762, T_3690) + node T_3764 = or(T_3763, T_3692) + node T_3765 = or(T_3764, T_3694) + node T_3766 = or(T_3765, T_3696) + node T_3767 = or(T_3766, T_3698) + node T_3768 = or(T_3767, T_3700) + node T_3769 = or(T_3768, T_3702) + node T_3770 = or(T_3769, T_3704) + node T_3771 = or(T_3770, T_3706) + node T_3772 = or(T_3771, T_3708) + node T_3773 = or(T_3772, T_3710) + node T_3774 = or(T_3773, T_3712) + wire T_3775 : UInt<6> + T_3775 := UInt<1>("h00") + T_3775 := T_3774 + node T_3777 = bit(T_3775, 0) + node T_3778 = bit(T_3775, 1) + node T_3779 = bit(T_3775, 2) + node T_3780 = bit(T_3775, 3) + node T_3781 = bit(T_3775, 4) + node T_3782 = bit(T_3775, 5) + infer accessor T_3784 = pages[UInt<1>("h00")] + infer accessor T_3786 = pages[UInt<1>("h01")] + infer accessor T_3788 = pages[UInt<2>("h02")] + infer accessor T_3790 = pages[UInt<2>("h03")] + infer accessor T_3792 = pages[UInt<3>("h04")] + infer accessor T_3794 = pages[UInt<3>("h05")] + node T_3796 = mux(T_3777, T_3784, UInt<1>("h00")) + node T_3798 = mux(T_3778, T_3786, UInt<1>("h00")) + node T_3800 = mux(T_3779, T_3788, UInt<1>("h00")) + node T_3802 = mux(T_3780, T_3790, UInt<1>("h00")) + node T_3804 = mux(T_3781, T_3792, UInt<1>("h00")) + node T_3806 = mux(T_3782, T_3794, UInt<1>("h00")) + node T_3808 = or(T_3796, T_3798) + node T_3809 = or(T_3808, T_3800) + node T_3810 = or(T_3809, T_3802) + node T_3811 = or(T_3810, T_3804) + node T_3812 = or(T_3811, T_3806) + wire T_3813 : UInt<27> + T_3813 := UInt<1>("h00") + T_3813 := T_3812 + node T_3815 = bit(hits, 0) + node T_3816 = bit(hits, 1) + node T_3817 = bit(hits, 2) + node T_3818 = bit(hits, 3) + node T_3819 = bit(hits, 4) + node T_3820 = bit(hits, 5) + node T_3821 = bit(hits, 6) + node T_3822 = bit(hits, 7) + node T_3823 = bit(hits, 8) + node T_3824 = bit(hits, 9) + node T_3825 = bit(hits, 10) + node T_3826 = bit(hits, 11) + node T_3827 = bit(hits, 12) + node T_3828 = bit(hits, 13) + node T_3829 = bit(hits, 14) + node T_3830 = bit(hits, 15) + node T_3831 = bit(hits, 16) + node T_3832 = bit(hits, 17) + node T_3833 = bit(hits, 18) + node T_3834 = bit(hits, 19) + node T_3835 = bit(hits, 20) + node T_3836 = bit(hits, 21) + node T_3837 = bit(hits, 22) + node T_3838 = bit(hits, 23) + node T_3839 = bit(hits, 24) + node T_3840 = bit(hits, 25) + node T_3841 = bit(hits, 26) + node T_3842 = bit(hits, 27) + node T_3843 = bit(hits, 28) + node T_3844 = bit(hits, 29) + node T_3845 = bit(hits, 30) + node T_3846 = bit(hits, 31) + node T_3847 = bit(hits, 32) + node T_3848 = bit(hits, 33) + node T_3849 = bit(hits, 34) + node T_3850 = bit(hits, 35) + node T_3851 = bit(hits, 36) + node T_3852 = bit(hits, 37) + node T_3853 = bit(hits, 38) + node T_3854 = bit(hits, 39) + node T_3855 = bit(hits, 40) + node T_3856 = bit(hits, 41) + node T_3857 = bit(hits, 42) + node T_3858 = bit(hits, 43) + node T_3859 = bit(hits, 44) + node T_3860 = bit(hits, 45) + node T_3861 = bit(hits, 46) + node T_3862 = bit(hits, 47) + node T_3863 = bit(hits, 48) + node T_3864 = bit(hits, 49) + node T_3865 = bit(hits, 50) + node T_3866 = bit(hits, 51) + node T_3867 = bit(hits, 52) + node T_3868 = bit(hits, 53) + node T_3869 = bit(hits, 54) + node T_3870 = bit(hits, 55) + node T_3871 = bit(hits, 56) + node T_3872 = bit(hits, 57) + node T_3873 = bit(hits, 58) + node T_3874 = bit(hits, 59) + node T_3875 = bit(hits, 60) + node T_3876 = bit(hits, 61) + infer accessor T_3878 = tgts[UInt<1>("h00")] + infer accessor T_3880 = tgts[UInt<1>("h01")] + infer accessor T_3882 = tgts[UInt<2>("h02")] + infer accessor T_3884 = tgts[UInt<2>("h03")] + infer accessor T_3886 = tgts[UInt<3>("h04")] + infer accessor T_3888 = tgts[UInt<3>("h05")] + infer accessor T_3890 = tgts[UInt<3>("h06")] + infer accessor T_3892 = tgts[UInt<3>("h07")] + infer accessor T_3894 = tgts[UInt<4>("h08")] + infer accessor T_3896 = tgts[UInt<4>("h09")] + infer accessor T_3898 = tgts[UInt<4>("h0a")] + infer accessor T_3900 = tgts[UInt<4>("h0b")] + infer accessor T_3902 = tgts[UInt<4>("h0c")] + infer accessor T_3904 = tgts[UInt<4>("h0d")] + infer accessor T_3906 = tgts[UInt<4>("h0e")] + infer accessor T_3908 = tgts[UInt<4>("h0f")] + infer accessor T_3910 = tgts[UInt<5>("h010")] + infer accessor T_3912 = tgts[UInt<5>("h011")] + infer accessor T_3914 = tgts[UInt<5>("h012")] + infer accessor T_3916 = tgts[UInt<5>("h013")] + infer accessor T_3918 = tgts[UInt<5>("h014")] + infer accessor T_3920 = tgts[UInt<5>("h015")] + infer accessor T_3922 = tgts[UInt<5>("h016")] + infer accessor T_3924 = tgts[UInt<5>("h017")] + infer accessor T_3926 = tgts[UInt<5>("h018")] + infer accessor T_3928 = tgts[UInt<5>("h019")] + infer accessor T_3930 = tgts[UInt<5>("h01a")] + infer accessor T_3932 = tgts[UInt<5>("h01b")] + infer accessor T_3934 = tgts[UInt<5>("h01c")] + infer accessor T_3936 = tgts[UInt<5>("h01d")] + infer accessor T_3938 = tgts[UInt<5>("h01e")] + infer accessor T_3940 = tgts[UInt<5>("h01f")] + infer accessor T_3942 = tgts[UInt<6>("h020")] + infer accessor T_3944 = tgts[UInt<6>("h021")] + infer accessor T_3946 = tgts[UInt<6>("h022")] + infer accessor T_3948 = tgts[UInt<6>("h023")] + infer accessor T_3950 = tgts[UInt<6>("h024")] + infer accessor T_3952 = tgts[UInt<6>("h025")] + infer accessor T_3954 = tgts[UInt<6>("h026")] + infer accessor T_3956 = tgts[UInt<6>("h027")] + infer accessor T_3958 = tgts[UInt<6>("h028")] + infer accessor T_3960 = tgts[UInt<6>("h029")] + infer accessor T_3962 = tgts[UInt<6>("h02a")] + infer accessor T_3964 = tgts[UInt<6>("h02b")] + infer accessor T_3966 = tgts[UInt<6>("h02c")] + infer accessor T_3968 = tgts[UInt<6>("h02d")] + infer accessor T_3970 = tgts[UInt<6>("h02e")] + infer accessor T_3972 = tgts[UInt<6>("h02f")] + infer accessor T_3974 = tgts[UInt<6>("h030")] + infer accessor T_3976 = tgts[UInt<6>("h031")] + infer accessor T_3978 = tgts[UInt<6>("h032")] + infer accessor T_3980 = tgts[UInt<6>("h033")] + infer accessor T_3982 = tgts[UInt<6>("h034")] + infer accessor T_3984 = tgts[UInt<6>("h035")] + infer accessor T_3986 = tgts[UInt<6>("h036")] + infer accessor T_3988 = tgts[UInt<6>("h037")] + infer accessor T_3990 = tgts[UInt<6>("h038")] + infer accessor T_3992 = tgts[UInt<6>("h039")] + infer accessor T_3994 = tgts[UInt<6>("h03a")] + infer accessor T_3996 = tgts[UInt<6>("h03b")] + infer accessor T_3998 = tgts[UInt<6>("h03c")] + infer accessor T_4000 = tgts[UInt<6>("h03d")] + node T_4002 = mux(T_3815, T_3878, UInt<1>("h00")) + node T_4004 = mux(T_3816, T_3880, UInt<1>("h00")) + node T_4006 = mux(T_3817, T_3882, UInt<1>("h00")) + node T_4008 = mux(T_3818, T_3884, UInt<1>("h00")) + node T_4010 = mux(T_3819, T_3886, UInt<1>("h00")) + node T_4012 = mux(T_3820, T_3888, UInt<1>("h00")) + node T_4014 = mux(T_3821, T_3890, UInt<1>("h00")) + node T_4016 = mux(T_3822, T_3892, UInt<1>("h00")) + node T_4018 = mux(T_3823, T_3894, UInt<1>("h00")) + node T_4020 = mux(T_3824, T_3896, UInt<1>("h00")) + node T_4022 = mux(T_3825, T_3898, UInt<1>("h00")) + node T_4024 = mux(T_3826, T_3900, UInt<1>("h00")) + node T_4026 = mux(T_3827, T_3902, UInt<1>("h00")) + node T_4028 = mux(T_3828, T_3904, UInt<1>("h00")) + node T_4030 = mux(T_3829, T_3906, UInt<1>("h00")) + node T_4032 = mux(T_3830, T_3908, UInt<1>("h00")) + node T_4034 = mux(T_3831, T_3910, UInt<1>("h00")) + node T_4036 = mux(T_3832, T_3912, UInt<1>("h00")) + node T_4038 = mux(T_3833, T_3914, UInt<1>("h00")) + node T_4040 = mux(T_3834, T_3916, UInt<1>("h00")) + node T_4042 = mux(T_3835, T_3918, UInt<1>("h00")) + node T_4044 = mux(T_3836, T_3920, UInt<1>("h00")) + node T_4046 = mux(T_3837, T_3922, UInt<1>("h00")) + node T_4048 = mux(T_3838, T_3924, UInt<1>("h00")) + node T_4050 = mux(T_3839, T_3926, UInt<1>("h00")) + node T_4052 = mux(T_3840, T_3928, UInt<1>("h00")) + node T_4054 = mux(T_3841, T_3930, UInt<1>("h00")) + node T_4056 = mux(T_3842, T_3932, UInt<1>("h00")) + node T_4058 = mux(T_3843, T_3934, UInt<1>("h00")) + node T_4060 = mux(T_3844, T_3936, UInt<1>("h00")) + node T_4062 = mux(T_3845, T_3938, UInt<1>("h00")) + node T_4064 = mux(T_3846, T_3940, UInt<1>("h00")) + node T_4066 = mux(T_3847, T_3942, UInt<1>("h00")) + node T_4068 = mux(T_3848, T_3944, UInt<1>("h00")) + node T_4070 = mux(T_3849, T_3946, UInt<1>("h00")) + node T_4072 = mux(T_3850, T_3948, UInt<1>("h00")) + node T_4074 = mux(T_3851, T_3950, UInt<1>("h00")) + node T_4076 = mux(T_3852, T_3952, UInt<1>("h00")) + node T_4078 = mux(T_3853, T_3954, UInt<1>("h00")) + node T_4080 = mux(T_3854, T_3956, UInt<1>("h00")) + node T_4082 = mux(T_3855, T_3958, UInt<1>("h00")) + node T_4084 = mux(T_3856, T_3960, UInt<1>("h00")) + node T_4086 = mux(T_3857, T_3962, UInt<1>("h00")) + node T_4088 = mux(T_3858, T_3964, UInt<1>("h00")) + node T_4090 = mux(T_3859, T_3966, UInt<1>("h00")) + node T_4092 = mux(T_3860, T_3968, UInt<1>("h00")) + node T_4094 = mux(T_3861, T_3970, UInt<1>("h00")) + node T_4096 = mux(T_3862, T_3972, UInt<1>("h00")) + node T_4098 = mux(T_3863, T_3974, UInt<1>("h00")) + node T_4100 = mux(T_3864, T_3976, UInt<1>("h00")) + node T_4102 = mux(T_3865, T_3978, UInt<1>("h00")) + node T_4104 = mux(T_3866, T_3980, UInt<1>("h00")) + node T_4106 = mux(T_3867, T_3982, UInt<1>("h00")) + node T_4108 = mux(T_3868, T_3984, UInt<1>("h00")) + node T_4110 = mux(T_3869, T_3986, UInt<1>("h00")) + node T_4112 = mux(T_3870, T_3988, UInt<1>("h00")) + node T_4114 = mux(T_3871, T_3990, UInt<1>("h00")) + node T_4116 = mux(T_3872, T_3992, UInt<1>("h00")) + node T_4118 = mux(T_3873, T_3994, UInt<1>("h00")) + node T_4120 = mux(T_3874, T_3996, UInt<1>("h00")) + node T_4122 = mux(T_3875, T_3998, UInt<1>("h00")) + node T_4124 = mux(T_3876, T_4000, UInt<1>("h00")) + node T_4126 = or(T_4002, T_4004) + node T_4127 = or(T_4126, T_4006) + node T_4128 = or(T_4127, T_4008) + node T_4129 = or(T_4128, T_4010) + node T_4130 = or(T_4129, T_4012) + node T_4131 = or(T_4130, T_4014) + node T_4132 = or(T_4131, T_4016) + node T_4133 = or(T_4132, T_4018) + node T_4134 = or(T_4133, T_4020) + node T_4135 = or(T_4134, T_4022) + node T_4136 = or(T_4135, T_4024) + node T_4137 = or(T_4136, T_4026) + node T_4138 = or(T_4137, T_4028) + node T_4139 = or(T_4138, T_4030) + node T_4140 = or(T_4139, T_4032) + node T_4141 = or(T_4140, T_4034) + node T_4142 = or(T_4141, T_4036) + node T_4143 = or(T_4142, T_4038) + node T_4144 = or(T_4143, T_4040) + node T_4145 = or(T_4144, T_4042) + node T_4146 = or(T_4145, T_4044) + node T_4147 = or(T_4146, T_4046) + node T_4148 = or(T_4147, T_4048) + node T_4149 = or(T_4148, T_4050) + node T_4150 = or(T_4149, T_4052) + node T_4151 = or(T_4150, T_4054) + node T_4152 = or(T_4151, T_4056) + node T_4153 = or(T_4152, T_4058) + node T_4154 = or(T_4153, T_4060) + node T_4155 = or(T_4154, T_4062) + node T_4156 = or(T_4155, T_4064) + node T_4157 = or(T_4156, T_4066) + node T_4158 = or(T_4157, T_4068) + node T_4159 = or(T_4158, T_4070) + node T_4160 = or(T_4159, T_4072) + node T_4161 = or(T_4160, T_4074) + node T_4162 = or(T_4161, T_4076) + node T_4163 = or(T_4162, T_4078) + node T_4164 = or(T_4163, T_4080) + node T_4165 = or(T_4164, T_4082) + node T_4166 = or(T_4165, T_4084) + node T_4167 = or(T_4166, T_4086) + node T_4168 = or(T_4167, T_4088) + node T_4169 = or(T_4168, T_4090) + node T_4170 = or(T_4169, T_4092) + node T_4171 = or(T_4170, T_4094) + node T_4172 = or(T_4171, T_4096) + node T_4173 = or(T_4172, T_4098) + node T_4174 = or(T_4173, T_4100) + node T_4175 = or(T_4174, T_4102) + node T_4176 = or(T_4175, T_4104) + node T_4177 = or(T_4176, T_4106) + node T_4178 = or(T_4177, T_4108) + node T_4179 = or(T_4178, T_4110) + node T_4180 = or(T_4179, T_4112) + node T_4181 = or(T_4180, T_4114) + node T_4182 = or(T_4181, T_4116) + node T_4183 = or(T_4182, T_4118) + node T_4184 = or(T_4183, T_4120) + node T_4185 = or(T_4184, T_4122) + node T_4186 = or(T_4185, T_4124) + wire T_4187 : UInt<12> + T_4187 := UInt<1>("h00") + T_4187 := T_4186 + node T_4189 = cat(T_3813, T_4187) + resp.bits.target := T_4189 + node T_4190 = bits(hits, 61, 32) + node T_4191 = bits(hits, 31, 0) + node T_4193 = neq(T_4190, UInt<1>("h00")) + node T_4194 = or(T_4190, T_4191) + node T_4195 = bits(T_4194, 31, 16) + node T_4196 = bits(T_4194, 15, 0) + node T_4198 = neq(T_4195, UInt<1>("h00")) + node T_4199 = or(T_4195, T_4196) + node T_4200 = bits(T_4199, 15, 8) + node T_4201 = bits(T_4199, 7, 0) + node T_4203 = neq(T_4200, UInt<1>("h00")) + node T_4204 = or(T_4200, T_4201) + node T_4205 = bits(T_4204, 7, 4) + node T_4206 = bits(T_4204, 3, 0) + node T_4208 = neq(T_4205, UInt<1>("h00")) + node T_4209 = or(T_4205, T_4206) + node T_4210 = bits(T_4209, 3, 2) + node T_4211 = bits(T_4209, 1, 0) + node T_4213 = neq(T_4210, UInt<1>("h00")) + node T_4214 = or(T_4210, T_4211) + node T_4215 = bit(T_4214, 1) + node T_4216 = cat(T_4213, T_4215) + node T_4217 = cat(T_4208, T_4216) + node T_4218 = cat(T_4203, T_4217) + node T_4219 = cat(T_4198, T_4218) + node T_4220 = cat(T_4193, T_4219) + resp.bits.entry := T_4220 + infer accessor T_4221 = brIdx[resp.bits.entry] + resp.bits.bridx := T_4221 + resp.bits.mask := UInt<1>("h01") + cmem T_4225 : UInt<2>[128], clock + reg T_4227 : UInt<7>, clock, reset + node T_4228 = bit(hits, 0) + node T_4229 = bit(hits, 1) + node T_4230 = bit(hits, 2) + node T_4231 = bit(hits, 3) + node T_4232 = bit(hits, 4) + node T_4233 = bit(hits, 5) + node T_4234 = bit(hits, 6) + node T_4235 = bit(hits, 7) + node T_4236 = bit(hits, 8) + node T_4237 = bit(hits, 9) + node T_4238 = bit(hits, 10) + node T_4239 = bit(hits, 11) + node T_4240 = bit(hits, 12) + node T_4241 = bit(hits, 13) + node T_4242 = bit(hits, 14) + node T_4243 = bit(hits, 15) + node T_4244 = bit(hits, 16) + node T_4245 = bit(hits, 17) + node T_4246 = bit(hits, 18) + node T_4247 = bit(hits, 19) + node T_4248 = bit(hits, 20) + node T_4249 = bit(hits, 21) + node T_4250 = bit(hits, 22) + node T_4251 = bit(hits, 23) + node T_4252 = bit(hits, 24) + node T_4253 = bit(hits, 25) + node T_4254 = bit(hits, 26) + node T_4255 = bit(hits, 27) + node T_4256 = bit(hits, 28) + node T_4257 = bit(hits, 29) + node T_4258 = bit(hits, 30) + node T_4259 = bit(hits, 31) + node T_4260 = bit(hits, 32) + node T_4261 = bit(hits, 33) + node T_4262 = bit(hits, 34) + node T_4263 = bit(hits, 35) + node T_4264 = bit(hits, 36) + node T_4265 = bit(hits, 37) + node T_4266 = bit(hits, 38) + node T_4267 = bit(hits, 39) + node T_4268 = bit(hits, 40) + node T_4269 = bit(hits, 41) + node T_4270 = bit(hits, 42) + node T_4271 = bit(hits, 43) + node T_4272 = bit(hits, 44) + node T_4273 = bit(hits, 45) + node T_4274 = bit(hits, 46) + node T_4275 = bit(hits, 47) + node T_4276 = bit(hits, 48) + node T_4277 = bit(hits, 49) + node T_4278 = bit(hits, 50) + node T_4279 = bit(hits, 51) + node T_4280 = bit(hits, 52) + node T_4281 = bit(hits, 53) + node T_4282 = bit(hits, 54) + node T_4283 = bit(hits, 55) + node T_4284 = bit(hits, 56) + node T_4285 = bit(hits, 57) + node T_4286 = bit(hits, 58) + node T_4287 = bit(hits, 59) + node T_4288 = bit(hits, 60) + node T_4289 = bit(hits, 61) + node T_4291 = shl(isJump[0], 0) + node T_4292 = mux(T_4228, T_4291, UInt<1>("h00")) + node T_4294 = shl(isJump[1], 0) + node T_4295 = mux(T_4229, T_4294, UInt<1>("h00")) + node T_4297 = shl(isJump[2], 0) + node T_4298 = mux(T_4230, T_4297, UInt<1>("h00")) + node T_4300 = shl(isJump[3], 0) + node T_4301 = mux(T_4231, T_4300, UInt<1>("h00")) + node T_4303 = shl(isJump[4], 0) + node T_4304 = mux(T_4232, T_4303, UInt<1>("h00")) + node T_4306 = shl(isJump[5], 0) + node T_4307 = mux(T_4233, T_4306, UInt<1>("h00")) + node T_4309 = shl(isJump[6], 0) + node T_4310 = mux(T_4234, T_4309, UInt<1>("h00")) + node T_4312 = shl(isJump[7], 0) + node T_4313 = mux(T_4235, T_4312, UInt<1>("h00")) + node T_4315 = shl(isJump[8], 0) + node T_4316 = mux(T_4236, T_4315, UInt<1>("h00")) + node T_4318 = shl(isJump[9], 0) + node T_4319 = mux(T_4237, T_4318, UInt<1>("h00")) + node T_4321 = shl(isJump[10], 0) + node T_4322 = mux(T_4238, T_4321, UInt<1>("h00")) + node T_4324 = shl(isJump[11], 0) + node T_4325 = mux(T_4239, T_4324, UInt<1>("h00")) + node T_4327 = shl(isJump[12], 0) + node T_4328 = mux(T_4240, T_4327, UInt<1>("h00")) + node T_4330 = shl(isJump[13], 0) + node T_4331 = mux(T_4241, T_4330, UInt<1>("h00")) + node T_4333 = shl(isJump[14], 0) + node T_4334 = mux(T_4242, T_4333, UInt<1>("h00")) + node T_4336 = shl(isJump[15], 0) + node T_4337 = mux(T_4243, T_4336, UInt<1>("h00")) + node T_4339 = shl(isJump[16], 0) + node T_4340 = mux(T_4244, T_4339, UInt<1>("h00")) + node T_4342 = shl(isJump[17], 0) + node T_4343 = mux(T_4245, T_4342, UInt<1>("h00")) + node T_4345 = shl(isJump[18], 0) + node T_4346 = mux(T_4246, T_4345, UInt<1>("h00")) + node T_4348 = shl(isJump[19], 0) + node T_4349 = mux(T_4247, T_4348, UInt<1>("h00")) + node T_4351 = shl(isJump[20], 0) + node T_4352 = mux(T_4248, T_4351, UInt<1>("h00")) + node T_4354 = shl(isJump[21], 0) + node T_4355 = mux(T_4249, T_4354, UInt<1>("h00")) + node T_4357 = shl(isJump[22], 0) + node T_4358 = mux(T_4250, T_4357, UInt<1>("h00")) + node T_4360 = shl(isJump[23], 0) + node T_4361 = mux(T_4251, T_4360, UInt<1>("h00")) + node T_4363 = shl(isJump[24], 0) + node T_4364 = mux(T_4252, T_4363, UInt<1>("h00")) + node T_4366 = shl(isJump[25], 0) + node T_4367 = mux(T_4253, T_4366, UInt<1>("h00")) + node T_4369 = shl(isJump[26], 0) + node T_4370 = mux(T_4254, T_4369, UInt<1>("h00")) + node T_4372 = shl(isJump[27], 0) + node T_4373 = mux(T_4255, T_4372, UInt<1>("h00")) + node T_4375 = shl(isJump[28], 0) + node T_4376 = mux(T_4256, T_4375, UInt<1>("h00")) + node T_4378 = shl(isJump[29], 0) + node T_4379 = mux(T_4257, T_4378, UInt<1>("h00")) + node T_4381 = shl(isJump[30], 0) + node T_4382 = mux(T_4258, T_4381, UInt<1>("h00")) + node T_4384 = shl(isJump[31], 0) + node T_4385 = mux(T_4259, T_4384, UInt<1>("h00")) + node T_4387 = shl(isJump[32], 0) + node T_4388 = mux(T_4260, T_4387, UInt<1>("h00")) + node T_4390 = shl(isJump[33], 0) + node T_4391 = mux(T_4261, T_4390, UInt<1>("h00")) + node T_4393 = shl(isJump[34], 0) + node T_4394 = mux(T_4262, T_4393, UInt<1>("h00")) + node T_4396 = shl(isJump[35], 0) + node T_4397 = mux(T_4263, T_4396, UInt<1>("h00")) + node T_4399 = shl(isJump[36], 0) + node T_4400 = mux(T_4264, T_4399, UInt<1>("h00")) + node T_4402 = shl(isJump[37], 0) + node T_4403 = mux(T_4265, T_4402, UInt<1>("h00")) + node T_4405 = shl(isJump[38], 0) + node T_4406 = mux(T_4266, T_4405, UInt<1>("h00")) + node T_4408 = shl(isJump[39], 0) + node T_4409 = mux(T_4267, T_4408, UInt<1>("h00")) + node T_4411 = shl(isJump[40], 0) + node T_4412 = mux(T_4268, T_4411, UInt<1>("h00")) + node T_4414 = shl(isJump[41], 0) + node T_4415 = mux(T_4269, T_4414, UInt<1>("h00")) + node T_4417 = shl(isJump[42], 0) + node T_4418 = mux(T_4270, T_4417, UInt<1>("h00")) + node T_4420 = shl(isJump[43], 0) + node T_4421 = mux(T_4271, T_4420, UInt<1>("h00")) + node T_4423 = shl(isJump[44], 0) + node T_4424 = mux(T_4272, T_4423, UInt<1>("h00")) + node T_4426 = shl(isJump[45], 0) + node T_4427 = mux(T_4273, T_4426, UInt<1>("h00")) + node T_4429 = shl(isJump[46], 0) + node T_4430 = mux(T_4274, T_4429, UInt<1>("h00")) + node T_4432 = shl(isJump[47], 0) + node T_4433 = mux(T_4275, T_4432, UInt<1>("h00")) + node T_4435 = shl(isJump[48], 0) + node T_4436 = mux(T_4276, T_4435, UInt<1>("h00")) + node T_4438 = shl(isJump[49], 0) + node T_4439 = mux(T_4277, T_4438, UInt<1>("h00")) + node T_4441 = shl(isJump[50], 0) + node T_4442 = mux(T_4278, T_4441, UInt<1>("h00")) + node T_4444 = shl(isJump[51], 0) + node T_4445 = mux(T_4279, T_4444, UInt<1>("h00")) + node T_4447 = shl(isJump[52], 0) + node T_4448 = mux(T_4280, T_4447, UInt<1>("h00")) + node T_4450 = shl(isJump[53], 0) + node T_4451 = mux(T_4281, T_4450, UInt<1>("h00")) + node T_4453 = shl(isJump[54], 0) + node T_4454 = mux(T_4282, T_4453, UInt<1>("h00")) + node T_4456 = shl(isJump[55], 0) + node T_4457 = mux(T_4283, T_4456, UInt<1>("h00")) + node T_4459 = shl(isJump[56], 0) + node T_4460 = mux(T_4284, T_4459, UInt<1>("h00")) + node T_4462 = shl(isJump[57], 0) + node T_4463 = mux(T_4285, T_4462, UInt<1>("h00")) + node T_4465 = shl(isJump[58], 0) + node T_4466 = mux(T_4286, T_4465, UInt<1>("h00")) + node T_4468 = shl(isJump[59], 0) + node T_4469 = mux(T_4287, T_4468, UInt<1>("h00")) + node T_4471 = shl(isJump[60], 0) + node T_4472 = mux(T_4288, T_4471, UInt<1>("h00")) + node T_4474 = shl(isJump[61], 0) + node T_4475 = mux(T_4289, T_4474, UInt<1>("h00")) + node T_4477 = or(T_4292, T_4295) + node T_4478 = or(T_4477, T_4298) + node T_4479 = or(T_4478, T_4301) + node T_4480 = or(T_4479, T_4304) + node T_4481 = or(T_4480, T_4307) + node T_4482 = or(T_4481, T_4310) + node T_4483 = or(T_4482, T_4313) + node T_4484 = or(T_4483, T_4316) + node T_4485 = or(T_4484, T_4319) + node T_4486 = or(T_4485, T_4322) + node T_4487 = or(T_4486, T_4325) + node T_4488 = or(T_4487, T_4328) + node T_4489 = or(T_4488, T_4331) + node T_4490 = or(T_4489, T_4334) + node T_4491 = or(T_4490, T_4337) + node T_4492 = or(T_4491, T_4340) + node T_4493 = or(T_4492, T_4343) + node T_4494 = or(T_4493, T_4346) + node T_4495 = or(T_4494, T_4349) + node T_4496 = or(T_4495, T_4352) + node T_4497 = or(T_4496, T_4355) + node T_4498 = or(T_4497, T_4358) + node T_4499 = or(T_4498, T_4361) + node T_4500 = or(T_4499, T_4364) + node T_4501 = or(T_4500, T_4367) + node T_4502 = or(T_4501, T_4370) + node T_4503 = or(T_4502, T_4373) + node T_4504 = or(T_4503, T_4376) + node T_4505 = or(T_4504, T_4379) + node T_4506 = or(T_4505, T_4382) + node T_4507 = or(T_4506, T_4385) + node T_4508 = or(T_4507, T_4388) + node T_4509 = or(T_4508, T_4391) + node T_4510 = or(T_4509, T_4394) + node T_4511 = or(T_4510, T_4397) + node T_4512 = or(T_4511, T_4400) + node T_4513 = or(T_4512, T_4403) + node T_4514 = or(T_4513, T_4406) + node T_4515 = or(T_4514, T_4409) + node T_4516 = or(T_4515, T_4412) + node T_4517 = or(T_4516, T_4415) + node T_4518 = or(T_4517, T_4418) + node T_4519 = or(T_4518, T_4421) + node T_4520 = or(T_4519, T_4424) + node T_4521 = or(T_4520, T_4427) + node T_4522 = or(T_4521, T_4430) + node T_4523 = or(T_4522, T_4433) + node T_4524 = or(T_4523, T_4436) + node T_4525 = or(T_4524, T_4439) + node T_4526 = or(T_4525, T_4442) + node T_4527 = or(T_4526, T_4445) + node T_4528 = or(T_4527, T_4448) + node T_4529 = or(T_4528, T_4451) + node T_4530 = or(T_4529, T_4454) + node T_4531 = or(T_4530, T_4457) + node T_4532 = or(T_4531, T_4460) + node T_4533 = or(T_4532, T_4463) + node T_4534 = or(T_4533, T_4466) + node T_4535 = or(T_4534, T_4469) + node T_4536 = or(T_4535, T_4472) + node T_4537 = or(T_4536, T_4475) + wire T_4538 : UInt<1> + T_4538 := UInt<1>("h00") + T_4538 := T_4537 + node T_4541 = eq(T_4538, UInt<1>("h00")) + node T_4542 = and(req.valid, resp.valid) + node T_4543 = and(T_4542, T_4541) + wire T_4547 : {history : UInt<7>, value : UInt<2>} + T_4547.value := UInt<1>("h00") + T_4547.history := UInt<1>("h00") + node T_4552 = bits(req.bits.addr, 8, 2) + node T_4553 = xor(T_4552, T_4227) + infer accessor T_4554 = T_4225[T_4553] + T_4547.value := T_4554 + T_4547.history := T_4227 + node T_4555 = bit(T_4547.value, 0) + when T_4543 : + node T_4556 = bits(T_4227, 6, 1) + node T_4557 = cat(T_4555, T_4556) + T_4227 := T_4557 + skip + node T_4558 = and(bht_update.valid, bht_update.bits.prediction.valid) + when T_4558 : + node T_4559 = bits(bht_update.bits.pc, 8, 2) + node T_4560 = xor(T_4559, bht_update.bits.prediction.bits.bht.history) + infer accessor T_4561 = T_4225[T_4560] + node T_4562 = bit(bht_update.bits.prediction.bits.bht.value, 1) + node T_4563 = bit(bht_update.bits.prediction.bits.bht.value, 0) + node T_4564 = and(T_4562, T_4563) + node T_4565 = bit(bht_update.bits.prediction.bits.bht.value, 1) + node T_4566 = bit(bht_update.bits.prediction.bits.bht.value, 0) + node T_4567 = or(T_4565, T_4566) + node T_4568 = and(T_4567, bht_update.bits.taken) + node T_4569 = or(T_4564, T_4568) + node T_4570 = cat(bht_update.bits.taken, T_4569) + T_4561 := T_4570 + when bht_update.bits.mispredict : + node T_4571 = bits(bht_update.bits.prediction.bits.bht.history, 6, 1) + node T_4572 = cat(bht_update.bits.taken, T_4571) + T_4227 := T_4572 + skip + skip + node T_4573 = bit(T_4547.value, 0) + node T_4575 = eq(T_4573, UInt<1>("h00")) + node T_4576 = and(T_4575, T_4541) + when T_4576 : + resp.bits.taken := UInt<1>("h00") + skip + resp.bits.bht <> T_4547 + reg T_4579 : UInt<2>, clock, reset + onreset T_4579 := UInt<2>("h00") + reg T_4581 : UInt<1>, clock, reset + onreset T_4581 := UInt<1>("h00") + reg T_4590 : UInt<?>[2], clock, reset + node T_4594 = bit(hits, 0) + node T_4595 = bit(hits, 1) + node T_4596 = bit(hits, 2) + node T_4597 = bit(hits, 3) + node T_4598 = bit(hits, 4) + node T_4599 = bit(hits, 5) + node T_4600 = bit(hits, 6) + node T_4601 = bit(hits, 7) + node T_4602 = bit(hits, 8) + node T_4603 = bit(hits, 9) + node T_4604 = bit(hits, 10) + node T_4605 = bit(hits, 11) + node T_4606 = bit(hits, 12) + node T_4607 = bit(hits, 13) + node T_4608 = bit(hits, 14) + node T_4609 = bit(hits, 15) + node T_4610 = bit(hits, 16) + node T_4611 = bit(hits, 17) + node T_4612 = bit(hits, 18) + node T_4613 = bit(hits, 19) + node T_4614 = bit(hits, 20) + node T_4615 = bit(hits, 21) + node T_4616 = bit(hits, 22) + node T_4617 = bit(hits, 23) + node T_4618 = bit(hits, 24) + node T_4619 = bit(hits, 25) + node T_4620 = bit(hits, 26) + node T_4621 = bit(hits, 27) + node T_4622 = bit(hits, 28) + node T_4623 = bit(hits, 29) + node T_4624 = bit(hits, 30) + node T_4625 = bit(hits, 31) + node T_4626 = bit(hits, 32) + node T_4627 = bit(hits, 33) + node T_4628 = bit(hits, 34) + node T_4629 = bit(hits, 35) + node T_4630 = bit(hits, 36) + node T_4631 = bit(hits, 37) + node T_4632 = bit(hits, 38) + node T_4633 = bit(hits, 39) + node T_4634 = bit(hits, 40) + node T_4635 = bit(hits, 41) + node T_4636 = bit(hits, 42) + node T_4637 = bit(hits, 43) + node T_4638 = bit(hits, 44) + node T_4639 = bit(hits, 45) + node T_4640 = bit(hits, 46) + node T_4641 = bit(hits, 47) + node T_4642 = bit(hits, 48) + node T_4643 = bit(hits, 49) + node T_4644 = bit(hits, 50) + node T_4645 = bit(hits, 51) + node T_4646 = bit(hits, 52) + node T_4647 = bit(hits, 53) + node T_4648 = bit(hits, 54) + node T_4649 = bit(hits, 55) + node T_4650 = bit(hits, 56) + node T_4651 = bit(hits, 57) + node T_4652 = bit(hits, 58) + node T_4653 = bit(hits, 59) + node T_4654 = bit(hits, 60) + node T_4655 = bit(hits, 61) + node T_4657 = shl(useRAS[0], 0) + node T_4658 = mux(T_4594, T_4657, UInt<1>("h00")) + node T_4660 = shl(useRAS[1], 0) + node T_4661 = mux(T_4595, T_4660, UInt<1>("h00")) + node T_4663 = shl(useRAS[2], 0) + node T_4664 = mux(T_4596, T_4663, UInt<1>("h00")) + node T_4666 = shl(useRAS[3], 0) + node T_4667 = mux(T_4597, T_4666, UInt<1>("h00")) + node T_4669 = shl(useRAS[4], 0) + node T_4670 = mux(T_4598, T_4669, UInt<1>("h00")) + node T_4672 = shl(useRAS[5], 0) + node T_4673 = mux(T_4599, T_4672, UInt<1>("h00")) + node T_4675 = shl(useRAS[6], 0) + node T_4676 = mux(T_4600, T_4675, UInt<1>("h00")) + node T_4678 = shl(useRAS[7], 0) + node T_4679 = mux(T_4601, T_4678, UInt<1>("h00")) + node T_4681 = shl(useRAS[8], 0) + node T_4682 = mux(T_4602, T_4681, UInt<1>("h00")) + node T_4684 = shl(useRAS[9], 0) + node T_4685 = mux(T_4603, T_4684, UInt<1>("h00")) + node T_4687 = shl(useRAS[10], 0) + node T_4688 = mux(T_4604, T_4687, UInt<1>("h00")) + node T_4690 = shl(useRAS[11], 0) + node T_4691 = mux(T_4605, T_4690, UInt<1>("h00")) + node T_4693 = shl(useRAS[12], 0) + node T_4694 = mux(T_4606, T_4693, UInt<1>("h00")) + node T_4696 = shl(useRAS[13], 0) + node T_4697 = mux(T_4607, T_4696, UInt<1>("h00")) + node T_4699 = shl(useRAS[14], 0) + node T_4700 = mux(T_4608, T_4699, UInt<1>("h00")) + node T_4702 = shl(useRAS[15], 0) + node T_4703 = mux(T_4609, T_4702, UInt<1>("h00")) + node T_4705 = shl(useRAS[16], 0) + node T_4706 = mux(T_4610, T_4705, UInt<1>("h00")) + node T_4708 = shl(useRAS[17], 0) + node T_4709 = mux(T_4611, T_4708, UInt<1>("h00")) + node T_4711 = shl(useRAS[18], 0) + node T_4712 = mux(T_4612, T_4711, UInt<1>("h00")) + node T_4714 = shl(useRAS[19], 0) + node T_4715 = mux(T_4613, T_4714, UInt<1>("h00")) + node T_4717 = shl(useRAS[20], 0) + node T_4718 = mux(T_4614, T_4717, UInt<1>("h00")) + node T_4720 = shl(useRAS[21], 0) + node T_4721 = mux(T_4615, T_4720, UInt<1>("h00")) + node T_4723 = shl(useRAS[22], 0) + node T_4724 = mux(T_4616, T_4723, UInt<1>("h00")) + node T_4726 = shl(useRAS[23], 0) + node T_4727 = mux(T_4617, T_4726, UInt<1>("h00")) + node T_4729 = shl(useRAS[24], 0) + node T_4730 = mux(T_4618, T_4729, UInt<1>("h00")) + node T_4732 = shl(useRAS[25], 0) + node T_4733 = mux(T_4619, T_4732, UInt<1>("h00")) + node T_4735 = shl(useRAS[26], 0) + node T_4736 = mux(T_4620, T_4735, UInt<1>("h00")) + node T_4738 = shl(useRAS[27], 0) + node T_4739 = mux(T_4621, T_4738, UInt<1>("h00")) + node T_4741 = shl(useRAS[28], 0) + node T_4742 = mux(T_4622, T_4741, UInt<1>("h00")) + node T_4744 = shl(useRAS[29], 0) + node T_4745 = mux(T_4623, T_4744, UInt<1>("h00")) + node T_4747 = shl(useRAS[30], 0) + node T_4748 = mux(T_4624, T_4747, UInt<1>("h00")) + node T_4750 = shl(useRAS[31], 0) + node T_4751 = mux(T_4625, T_4750, UInt<1>("h00")) + node T_4753 = shl(useRAS[32], 0) + node T_4754 = mux(T_4626, T_4753, UInt<1>("h00")) + node T_4756 = shl(useRAS[33], 0) + node T_4757 = mux(T_4627, T_4756, UInt<1>("h00")) + node T_4759 = shl(useRAS[34], 0) + node T_4760 = mux(T_4628, T_4759, UInt<1>("h00")) + node T_4762 = shl(useRAS[35], 0) + node T_4763 = mux(T_4629, T_4762, UInt<1>("h00")) + node T_4765 = shl(useRAS[36], 0) + node T_4766 = mux(T_4630, T_4765, UInt<1>("h00")) + node T_4768 = shl(useRAS[37], 0) + node T_4769 = mux(T_4631, T_4768, UInt<1>("h00")) + node T_4771 = shl(useRAS[38], 0) + node T_4772 = mux(T_4632, T_4771, UInt<1>("h00")) + node T_4774 = shl(useRAS[39], 0) + node T_4775 = mux(T_4633, T_4774, UInt<1>("h00")) + node T_4777 = shl(useRAS[40], 0) + node T_4778 = mux(T_4634, T_4777, UInt<1>("h00")) + node T_4780 = shl(useRAS[41], 0) + node T_4781 = mux(T_4635, T_4780, UInt<1>("h00")) + node T_4783 = shl(useRAS[42], 0) + node T_4784 = mux(T_4636, T_4783, UInt<1>("h00")) + node T_4786 = shl(useRAS[43], 0) + node T_4787 = mux(T_4637, T_4786, UInt<1>("h00")) + node T_4789 = shl(useRAS[44], 0) + node T_4790 = mux(T_4638, T_4789, UInt<1>("h00")) + node T_4792 = shl(useRAS[45], 0) + node T_4793 = mux(T_4639, T_4792, UInt<1>("h00")) + node T_4795 = shl(useRAS[46], 0) + node T_4796 = mux(T_4640, T_4795, UInt<1>("h00")) + node T_4798 = shl(useRAS[47], 0) + node T_4799 = mux(T_4641, T_4798, UInt<1>("h00")) + node T_4801 = shl(useRAS[48], 0) + node T_4802 = mux(T_4642, T_4801, UInt<1>("h00")) + node T_4804 = shl(useRAS[49], 0) + node T_4805 = mux(T_4643, T_4804, UInt<1>("h00")) + node T_4807 = shl(useRAS[50], 0) + node T_4808 = mux(T_4644, T_4807, UInt<1>("h00")) + node T_4810 = shl(useRAS[51], 0) + node T_4811 = mux(T_4645, T_4810, UInt<1>("h00")) + node T_4813 = shl(useRAS[52], 0) + node T_4814 = mux(T_4646, T_4813, UInt<1>("h00")) + node T_4816 = shl(useRAS[53], 0) + node T_4817 = mux(T_4647, T_4816, UInt<1>("h00")) + node T_4819 = shl(useRAS[54], 0) + node T_4820 = mux(T_4648, T_4819, UInt<1>("h00")) + node T_4822 = shl(useRAS[55], 0) + node T_4823 = mux(T_4649, T_4822, UInt<1>("h00")) + node T_4825 = shl(useRAS[56], 0) + node T_4826 = mux(T_4650, T_4825, UInt<1>("h00")) + node T_4828 = shl(useRAS[57], 0) + node T_4829 = mux(T_4651, T_4828, UInt<1>("h00")) + node T_4831 = shl(useRAS[58], 0) + node T_4832 = mux(T_4652, T_4831, UInt<1>("h00")) + node T_4834 = shl(useRAS[59], 0) + node T_4835 = mux(T_4653, T_4834, UInt<1>("h00")) + node T_4837 = shl(useRAS[60], 0) + node T_4838 = mux(T_4654, T_4837, UInt<1>("h00")) + node T_4840 = shl(useRAS[61], 0) + node T_4841 = mux(T_4655, T_4840, UInt<1>("h00")) + node T_4843 = or(T_4658, T_4661) + node T_4844 = or(T_4843, T_4664) + node T_4845 = or(T_4844, T_4667) + node T_4846 = or(T_4845, T_4670) + node T_4847 = or(T_4846, T_4673) + node T_4848 = or(T_4847, T_4676) + node T_4849 = or(T_4848, T_4679) + node T_4850 = or(T_4849, T_4682) + node T_4851 = or(T_4850, T_4685) + node T_4852 = or(T_4851, T_4688) + node T_4853 = or(T_4852, T_4691) + node T_4854 = or(T_4853, T_4694) + node T_4855 = or(T_4854, T_4697) + node T_4856 = or(T_4855, T_4700) + node T_4857 = or(T_4856, T_4703) + node T_4858 = or(T_4857, T_4706) + node T_4859 = or(T_4858, T_4709) + node T_4860 = or(T_4859, T_4712) + node T_4861 = or(T_4860, T_4715) + node T_4862 = or(T_4861, T_4718) + node T_4863 = or(T_4862, T_4721) + node T_4864 = or(T_4863, T_4724) + node T_4865 = or(T_4864, T_4727) + node T_4866 = or(T_4865, T_4730) + node T_4867 = or(T_4866, T_4733) + node T_4868 = or(T_4867, T_4736) + node T_4869 = or(T_4868, T_4739) + node T_4870 = or(T_4869, T_4742) + node T_4871 = or(T_4870, T_4745) + node T_4872 = or(T_4871, T_4748) + node T_4873 = or(T_4872, T_4751) + node T_4874 = or(T_4873, T_4754) + node T_4875 = or(T_4874, T_4757) + node T_4876 = or(T_4875, T_4760) + node T_4877 = or(T_4876, T_4763) + node T_4878 = or(T_4877, T_4766) + node T_4879 = or(T_4878, T_4769) + node T_4880 = or(T_4879, T_4772) + node T_4881 = or(T_4880, T_4775) + node T_4882 = or(T_4881, T_4778) + node T_4883 = or(T_4882, T_4781) + node T_4884 = or(T_4883, T_4784) + node T_4885 = or(T_4884, T_4787) + node T_4886 = or(T_4885, T_4790) + node T_4887 = or(T_4886, T_4793) + node T_4888 = or(T_4887, T_4796) + node T_4889 = or(T_4888, T_4799) + node T_4890 = or(T_4889, T_4802) + node T_4891 = or(T_4890, T_4805) + node T_4892 = or(T_4891, T_4808) + node T_4893 = or(T_4892, T_4811) + node T_4894 = or(T_4893, T_4814) + node T_4895 = or(T_4894, T_4817) + node T_4896 = or(T_4895, T_4820) + node T_4897 = or(T_4896, T_4823) + node T_4898 = or(T_4897, T_4826) + node T_4899 = or(T_4898, T_4829) + node T_4900 = or(T_4899, T_4832) + node T_4901 = or(T_4900, T_4835) + node T_4902 = or(T_4901, T_4838) + node T_4903 = or(T_4902, T_4841) + wire T_4904 : UInt<1> + T_4904 := UInt<1>("h00") + T_4904 := T_4903 + node T_4907 = eq(T_4579, UInt<1>("h00")) + node T_4909 = eq(T_4907, UInt<1>("h00")) + node T_4910 = and(T_4909, T_4904) + when T_4910 : + infer accessor T_4911 = T_4590[T_4581] + resp.bits.target := T_4911 + skip + when ras_update.valid : + when ras_update.bits.isCall : + node T_4913 = lt(T_4579, UInt<2>("h02")) + when T_4913 : + node T_4915 = addw(T_4579, UInt<1>("h01")) + T_4579 := T_4915 + skip + node T_4918 = lt(T_4581, UInt<1>("h01")) + node T_4919 = or(UInt<1>("h01"), T_4918) + node T_4921 = addw(T_4581, UInt<1>("h01")) + node T_4923 = mux(T_4919, T_4921, UInt<1>("h00")) + infer accessor T_4924 = T_4590[T_4923] + T_4924 := ras_update.bits.returnAddr + T_4581 := T_4923 + when T_4904 : + resp.bits.target := ras_update.bits.returnAddr + skip + skip + else : + node T_4925 = and(ras_update.bits.isReturn, ras_update.bits.prediction.valid) + when T_4925 : + node T_4927 = eq(T_4579, UInt<1>("h00")) + node T_4929 = eq(T_4927, UInt<1>("h00")) + when T_4929 : + node T_4931 = subw(T_4579, UInt<1>("h01")) + T_4579 := T_4931 + node T_4934 = gt(T_4581, UInt<1>("h00")) + node T_4935 = or(UInt<1>("h01"), T_4934) + node T_4937 = subw(T_4581, UInt<1>("h01")) + node T_4939 = mux(T_4935, T_4937, UInt<1>("h01")) + T_4581 := T_4939 + skip + skip + skip + skip + when invalidate : + T_4579 := UInt<1>("h00") + skip + + module FlowThroughSerializer : + output done : UInt<1> + output cnt : UInt<1> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} + input clock : Clock + input reset : UInt<1> + + done := UInt<1>("h00") + cnt := UInt<1>("h00") + out.bits.g_type := UInt<1>("h00") + out.bits.is_builtin_type := UInt<1>("h00") + out.bits.manager_xact_id := UInt<1>("h00") + out.bits.client_xact_id := UInt<1>("h00") + out.bits.data := UInt<1>("h00") + out.bits.addr_beat := UInt<1>("h00") + out.valid := UInt<1>("h00") + in.ready := UInt<1>("h00") + out <> in + cnt := UInt<1>("h00") + done := UInt<1>("h01") + + module ICache : + output mem_1 : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + input invalidate : UInt<1> + output resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}} + input req : {valid : UInt<1>, bits : {idx : UInt<12>, ppn : UInt<20>, kill : UInt<1>}} + input clock : Clock + input reset : UInt<1> + + mem_1.grant.ready := UInt<1>("h00") + mem_1.acquire.bits.union := UInt<1>("h00") + mem_1.acquire.bits.a_type := UInt<1>("h00") + mem_1.acquire.bits.is_builtin_type := UInt<1>("h00") + mem_1.acquire.bits.data := UInt<1>("h00") + mem_1.acquire.bits.addr_beat := UInt<1>("h00") + mem_1.acquire.bits.client_xact_id := UInt<1>("h00") + mem_1.acquire.bits.addr_block := UInt<1>("h00") + mem_1.acquire.valid := UInt<1>("h00") + resp.bits.datablock := UInt<1>("h00") + resp.bits.data := UInt<1>("h00") + resp.valid := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg invalidated : UInt<1>, clock, reset + node stall = eq(resp.ready, UInt<1>("h00")) + wire rdy : UInt<1> + rdy := UInt<1>("h00") + reg s2_valid : UInt<1>, clock, reset + onreset s2_valid := UInt<1>("h00") + reg s2_addr : UInt<32>, clock, reset + wire s2_any_tag_hit : UInt<1> + s2_any_tag_hit := UInt<1>("h00") + reg s1_valid : UInt<1>, clock, reset + onreset s1_valid := UInt<1>("h00") + reg s1_pgoff : UInt<12>, clock, reset + node s1_addr = cat(req.bits.ppn, s1_pgoff) + node s1_tag = bits(s1_addr, 31, 12) + node T_343 = and(s1_valid, stall) + node s0_valid = or(req.valid, T_343) + node T_345 = and(s1_valid, stall) + node s0_pgoff = mux(T_345, s1_pgoff, req.bits.idx) + node T_347 = and(req.valid, rdy) + node T_348 = and(s1_valid, stall) + node T_350 = eq(req.bits.kill, UInt<1>("h00")) + node T_351 = and(T_348, T_350) + node T_352 = or(T_347, T_351) + s1_valid := T_352 + node T_353 = and(req.valid, rdy) + when T_353 : + s1_pgoff := req.bits.idx + skip + node T_354 = and(s1_valid, rdy) + node T_356 = eq(req.bits.kill, UInt<1>("h00")) + node T_357 = and(T_354, T_356) + node T_358 = and(resp.valid, stall) + node T_359 = or(T_357, T_358) + s2_valid := T_359 + node T_360 = and(s1_valid, rdy) + node T_362 = eq(stall, UInt<1>("h00")) + node T_363 = and(T_360, T_362) + when T_363 : + s2_addr := s1_addr + skip + node s2_tag = bits(s2_addr, 31, 12) + node s2_idx = bits(s2_addr, 11, 6) + node s2_offset = bits(s2_addr, 5, 0) + node s2_hit = and(s2_valid, s2_any_tag_hit) + node T_369 = eq(s2_any_tag_hit, UInt<1>("h00")) + node s2_miss = and(s2_valid, T_369) + node T_371 = eq(state, UInt<1>("h00")) + node T_373 = eq(s2_miss, UInt<1>("h00")) + node T_374 = and(T_371, T_373) + rdy := T_374 + inst T_942 of FlowThroughSerializer + T_942.out.ready := UInt<1>("h00") + T_942.in.bits.g_type := UInt<1>("h00") + T_942.in.bits.is_builtin_type := UInt<1>("h00") + T_942.in.bits.manager_xact_id := UInt<1>("h00") + T_942.in.bits.client_xact_id := UInt<1>("h00") + T_942.in.bits.data := UInt<1>("h00") + T_942.in.bits.addr_beat := UInt<1>("h00") + T_942.in.valid := UInt<1>("h00") + T_942.reset := UInt<1>("h00") + T_942.clock := clock + T_942.reset := reset + T_942.in.valid := mem_1.grant.valid + T_942.in.bits <> mem_1.grant.bits + mem_1.grant.ready := T_942.in.ready + node T_384 = and(T_942.out.ready, T_942.out.valid) + reg refill_cnt : UInt<2>, clock, reset + onreset refill_cnt := UInt<2>("h00") + when T_384 : + node T_388 = eq(refill_cnt, UInt<2>("h03")) + node T_390 = and(UInt<1>("h00"), T_388) + node T_393 = addw(refill_cnt, UInt<1>("h01")) + node T_394 = mux(T_390, UInt<1>("h00"), T_393) + refill_cnt := T_394 + skip + node refill_wrap = and(T_384, T_388) + node T_396 = eq(state, UInt<2>("h03")) + node refill_done = and(T_396, refill_wrap) + T_942.out.ready := UInt<1>("h01") + reg T_400 : UInt<16>, clock, reset + onreset T_400 := UInt<16>("h01") + when s2_miss : + node T_401 = bit(T_400, 0) + node T_402 = bit(T_400, 2) + node T_403 = xor(T_401, T_402) + node T_404 = bit(T_400, 3) + node T_405 = xor(T_403, T_404) + node T_406 = bit(T_400, 5) + node T_407 = xor(T_405, T_406) + node T_408 = bits(T_400, 15, 1) + node T_409 = cat(T_407, T_408) + T_400 := T_409 + skip + node repl_way = bits(T_400, 1, 0) + cmem T_413 : UInt<80>[64], clock + node T_414 = bits(s0_pgoff, 11, 6) + node T_416 = eq(refill_done, UInt<1>("h00")) + node T_417 = and(T_416, s0_valid) + reg T_418 : UInt<6>, clock, reset + when T_417 : + T_418 := T_414 + skip + infer accessor tag_rdata = T_413[T_418] + when refill_done : + node T_421 = dshl(UInt<1>("h01"), repl_way) + node T_422 = bit(T_421, 0) + node T_423 = bit(T_421, 1) + node T_424 = bit(T_421, 2) + node T_425 = bit(T_421, 3) + wire T_427 : UInt<1>[4] + T_427[0] := T_422 + T_427[1] := T_423 + T_427[2] := T_424 + T_427[3] := T_425 + node T_434 = subw(UInt<20>("h00"), T_427[0]) + node T_436 = subw(UInt<20>("h00"), T_427[1]) + node T_438 = subw(UInt<20>("h00"), T_427[2]) + node T_440 = subw(UInt<20>("h00"), T_427[3]) + wire T_442 : UInt<20>[4] + T_442[0] := T_434 + T_442[1] := T_436 + T_442[2] := T_438 + T_442[3] := T_440 + node T_448 = cat(T_442[3], T_442[2]) + node T_449 = cat(T_442[1], T_442[0]) + node T_450 = cat(T_448, T_449) + node T_451 = cat(s2_tag, s2_tag) + node T_452 = cat(T_451, T_451) + infer accessor T_453 = T_413[s2_idx] + node T_454 = not(T_450) + node T_455 = and(T_453, T_454) + node T_456 = and(T_452, T_450) + node T_457 = or(T_455, T_456) + wire T_458 : UInt<80> + T_458 := UInt<1>("h00") + T_458 := T_457 + infer accessor T_460 = T_413[s2_idx] + T_460 := T_458 + skip + reg vb_array : UInt<256>, clock, reset + onreset vb_array := UInt<256>("h00") + node T_464 = eq(invalidated, UInt<1>("h00")) + node T_465 = and(refill_done, T_464) + when T_465 : + node T_466 = cat(repl_way, s2_idx) + node T_469 = dshl(UInt<1>("h01"), T_466) + node T_470 = or(vb_array, T_469) + node T_471 = not(vb_array) + node T_472 = or(T_471, T_469) + node T_473 = not(T_472) + node T_474 = mux(UInt<1>("h01"), T_470, T_473) + vb_array := T_474 + skip + when invalidate : + vb_array := UInt<1>("h00") + invalidated := UInt<1>("h01") + skip + wire s2_disparity : UInt<1>[4] + s2_disparity[0] := UInt<1>("h00") + s2_disparity[1] := UInt<1>("h00") + s2_disparity[2] := UInt<1>("h00") + s2_disparity[3] := UInt<1>("h00") + node T_497 = and(s2_valid, s2_disparity[0]) + when T_497 : + node T_499 = cat(UInt<1>("h00"), s2_idx) + node T_502 = dshl(UInt<1>("h01"), T_499) + node T_503 = or(vb_array, T_502) + node T_504 = not(vb_array) + node T_505 = or(T_504, T_502) + node T_506 = not(T_505) + node T_507 = mux(UInt<1>("h00"), T_503, T_506) + vb_array := T_507 + skip + node T_508 = and(s2_valid, s2_disparity[1]) + when T_508 : + node T_510 = cat(UInt<1>("h01"), s2_idx) + node T_513 = dshl(UInt<1>("h01"), T_510) + node T_514 = or(vb_array, T_513) + node T_515 = not(vb_array) + node T_516 = or(T_515, T_513) + node T_517 = not(T_516) + node T_518 = mux(UInt<1>("h00"), T_514, T_517) + vb_array := T_518 + skip + node T_519 = and(s2_valid, s2_disparity[2]) + when T_519 : + node T_521 = cat(UInt<2>("h02"), s2_idx) + node T_524 = dshl(UInt<1>("h01"), T_521) + node T_525 = or(vb_array, T_524) + node T_526 = not(vb_array) + node T_527 = or(T_526, T_524) + node T_528 = not(T_527) + node T_529 = mux(UInt<1>("h00"), T_525, T_528) + vb_array := T_529 + skip + node T_530 = and(s2_valid, s2_disparity[3]) + when T_530 : + node T_532 = cat(UInt<2>("h03"), s2_idx) + node T_535 = dshl(UInt<1>("h01"), T_532) + node T_536 = or(vb_array, T_535) + node T_537 = not(vb_array) + node T_538 = or(T_537, T_535) + node T_539 = not(T_538) + node T_540 = mux(UInt<1>("h00"), T_536, T_539) + vb_array := T_540 + skip + wire s1_tag_match : UInt<1>[4] + s1_tag_match[0] := UInt<1>("h00") + s1_tag_match[1] := UInt<1>("h00") + s1_tag_match[2] := UInt<1>("h00") + s1_tag_match[3] := UInt<1>("h00") + wire s2_tag_hit : UInt<1>[4] + s2_tag_hit[0] := UInt<1>("h00") + s2_tag_hit[1] := UInt<1>("h00") + s2_tag_hit[2] := UInt<1>("h00") + s2_tag_hit[3] := UInt<1>("h00") + reg s2_dout : UInt<128>[4], clock, reset + node T_598 = eq(invalidate, UInt<1>("h00")) + node T_600 = bits(s1_pgoff, 11, 6) + node T_601 = cat(UInt<1>("h00"), T_600) + node T_602 = dshr(vb_array, T_601) + node T_603 = bit(T_602, 0) + node T_604 = bit(T_603, 0) + node T_605 = and(T_598, T_604) + reg T_607 : UInt<1>, clock, reset + reg T_609 : UInt<1>, clock, reset + reg T_611 : UInt<1>, clock, reset + node T_612 = bits(tag_rdata, 19, 0) + node T_613 = and(s1_valid, rdy) + node T_615 = eq(stall, UInt<1>("h00")) + node T_616 = and(T_613, T_615) + when T_616 : + T_607 := T_605 + node T_619 = or(UInt<1>("h00"), UInt<1>("h00")) + T_609 := T_619 + T_611 := s1_tag_match[0] + skip + node T_620 = bits(T_612, 19, 0) + node T_621 = eq(T_620, s1_tag) + s1_tag_match[0] := T_621 + node T_622 = and(T_607, T_611) + s2_tag_hit[0] := T_622 + node T_625 = or(UInt<1>("h00"), UInt<1>("h00")) + node T_626 = or(T_609, T_625) + node T_627 = and(T_607, T_626) + s2_disparity[0] := T_627 + node T_629 = eq(invalidate, UInt<1>("h00")) + node T_631 = bits(s1_pgoff, 11, 6) + node T_632 = cat(UInt<1>("h01"), T_631) + node T_633 = dshr(vb_array, T_632) + node T_634 = bit(T_633, 0) + node T_635 = bit(T_634, 0) + node T_636 = and(T_629, T_635) + reg T_638 : UInt<1>, clock, reset + reg T_640 : UInt<1>, clock, reset + reg T_642 : UInt<1>, clock, reset + node T_643 = bits(tag_rdata, 39, 20) + node T_644 = and(s1_valid, rdy) + node T_646 = eq(stall, UInt<1>("h00")) + node T_647 = and(T_644, T_646) + when T_647 : + T_638 := T_636 + node T_650 = or(UInt<1>("h00"), UInt<1>("h00")) + T_640 := T_650 + T_642 := s1_tag_match[1] + skip + node T_651 = bits(T_643, 19, 0) + node T_652 = eq(T_651, s1_tag) + s1_tag_match[1] := T_652 + node T_653 = and(T_638, T_642) + s2_tag_hit[1] := T_653 + node T_656 = or(UInt<1>("h00"), UInt<1>("h00")) + node T_657 = or(T_640, T_656) + node T_658 = and(T_638, T_657) + s2_disparity[1] := T_658 + node T_660 = eq(invalidate, UInt<1>("h00")) + node T_662 = bits(s1_pgoff, 11, 6) + node T_663 = cat(UInt<2>("h02"), T_662) + node T_664 = dshr(vb_array, T_663) + node T_665 = bit(T_664, 0) + node T_666 = bit(T_665, 0) + node T_667 = and(T_660, T_666) + reg T_669 : UInt<1>, clock, reset + reg T_671 : UInt<1>, clock, reset + reg T_673 : UInt<1>, clock, reset + node T_674 = bits(tag_rdata, 59, 40) + node T_675 = and(s1_valid, rdy) + node T_677 = eq(stall, UInt<1>("h00")) + node T_678 = and(T_675, T_677) + when T_678 : + T_669 := T_667 + node T_681 = or(UInt<1>("h00"), UInt<1>("h00")) + T_671 := T_681 + T_673 := s1_tag_match[2] + skip + node T_682 = bits(T_674, 19, 0) + node T_683 = eq(T_682, s1_tag) + s1_tag_match[2] := T_683 + node T_684 = and(T_669, T_673) + s2_tag_hit[2] := T_684 + node T_687 = or(UInt<1>("h00"), UInt<1>("h00")) + node T_688 = or(T_671, T_687) + node T_689 = and(T_669, T_688) + s2_disparity[2] := T_689 + node T_691 = eq(invalidate, UInt<1>("h00")) + node T_693 = bits(s1_pgoff, 11, 6) + node T_694 = cat(UInt<2>("h03"), T_693) + node T_695 = dshr(vb_array, T_694) + node T_696 = bit(T_695, 0) + node T_697 = bit(T_696, 0) + node T_698 = and(T_691, T_697) + reg T_700 : UInt<1>, clock, reset + reg T_702 : UInt<1>, clock, reset + reg T_704 : UInt<1>, clock, reset + node T_705 = bits(tag_rdata, 79, 60) + node T_706 = and(s1_valid, rdy) + node T_708 = eq(stall, UInt<1>("h00")) + node T_709 = and(T_706, T_708) + when T_709 : + T_700 := T_698 + node T_712 = or(UInt<1>("h00"), UInt<1>("h00")) + T_702 := T_712 + T_704 := s1_tag_match[3] + skip + node T_713 = bits(T_705, 19, 0) + node T_714 = eq(T_713, s1_tag) + s1_tag_match[3] := T_714 + node T_715 = and(T_700, T_704) + s2_tag_hit[3] := T_715 + node T_718 = or(UInt<1>("h00"), UInt<1>("h00")) + node T_719 = or(T_702, T_718) + node T_720 = and(T_700, T_719) + s2_disparity[3] := T_720 + node T_721 = or(s2_tag_hit[0], s2_tag_hit[1]) + node T_722 = or(T_721, s2_tag_hit[2]) + node T_723 = or(T_722, s2_tag_hit[3]) + node T_724 = or(s2_disparity[0], s2_disparity[1]) + node T_725 = or(T_724, s2_disparity[2]) + node T_726 = or(T_725, s2_disparity[3]) + node T_728 = eq(T_726, UInt<1>("h00")) + node T_729 = and(T_723, T_728) + s2_any_tag_hit := T_729 + cmem T_732 : UInt<128>[256], clock + node T_734 = eq(repl_way, UInt<1>("h00")) + node T_735 = and(T_942.out.valid, T_734) + when T_735 : + node T_736 = cat(s2_idx, refill_cnt) + infer accessor T_737 = T_732[T_736] + T_737 := T_942.out.bits.data + skip + node T_738 = bits(s0_pgoff, 11, 4) + node T_740 = eq(T_735, UInt<1>("h00")) + node T_741 = and(T_740, s0_valid) + reg T_742 : UInt<8>, clock, reset + when T_741 : + T_742 := T_738 + skip + infer accessor T_743 = T_732[T_742] + node T_744 = and(s1_valid, rdy) + node T_746 = eq(stall, UInt<1>("h00")) + node T_747 = and(T_744, T_746) + node T_749 = or(UInt<1>("h00"), s1_tag_match[0]) + node T_750 = and(T_747, T_749) + when T_750 : + s2_dout[0] := T_743 + skip + cmem T_753 : UInt<128>[256], clock + node T_755 = eq(repl_way, UInt<1>("h01")) + node T_756 = and(T_942.out.valid, T_755) + when T_756 : + node T_757 = cat(s2_idx, refill_cnt) + infer accessor T_758 = T_753[T_757] + T_758 := T_942.out.bits.data + skip + node T_759 = bits(s0_pgoff, 11, 4) + node T_761 = eq(T_756, UInt<1>("h00")) + node T_762 = and(T_761, s0_valid) + reg T_763 : UInt<8>, clock, reset + when T_762 : + T_763 := T_759 + skip + infer accessor T_764 = T_753[T_763] + node T_765 = and(s1_valid, rdy) + node T_767 = eq(stall, UInt<1>("h00")) + node T_768 = and(T_765, T_767) + node T_770 = or(UInt<1>("h00"), s1_tag_match[1]) + node T_771 = and(T_768, T_770) + when T_771 : + s2_dout[1] := T_764 + skip + cmem T_774 : UInt<128>[256], clock + node T_776 = eq(repl_way, UInt<2>("h02")) + node T_777 = and(T_942.out.valid, T_776) + when T_777 : + node T_778 = cat(s2_idx, refill_cnt) + infer accessor T_779 = T_774[T_778] + T_779 := T_942.out.bits.data + skip + node T_780 = bits(s0_pgoff, 11, 4) + node T_782 = eq(T_777, UInt<1>("h00")) + node T_783 = and(T_782, s0_valid) + reg T_784 : UInt<8>, clock, reset + when T_783 : + T_784 := T_780 + skip + infer accessor T_785 = T_774[T_784] + node T_786 = and(s1_valid, rdy) + node T_788 = eq(stall, UInt<1>("h00")) + node T_789 = and(T_786, T_788) + node T_791 = or(UInt<1>("h00"), s1_tag_match[2]) + node T_792 = and(T_789, T_791) + when T_792 : + s2_dout[2] := T_785 + skip + cmem T_795 : UInt<128>[256], clock + node T_797 = eq(repl_way, UInt<2>("h03")) + node T_798 = and(T_942.out.valid, T_797) + when T_798 : + node T_799 = cat(s2_idx, refill_cnt) + infer accessor T_800 = T_795[T_799] + T_800 := T_942.out.bits.data + skip + node T_801 = bits(s0_pgoff, 11, 4) + node T_803 = eq(T_798, UInt<1>("h00")) + node T_804 = and(T_803, s0_valid) + reg T_805 : UInt<8>, clock, reset + when T_804 : + T_805 := T_801 + skip + infer accessor T_806 = T_795[T_805] + node T_807 = and(s1_valid, rdy) + node T_809 = eq(stall, UInt<1>("h00")) + node T_810 = and(T_807, T_809) + node T_812 = or(UInt<1>("h00"), s1_tag_match[3]) + node T_813 = and(T_810, T_812) + when T_813 : + s2_dout[3] := T_806 + skip + node T_814 = bits(s2_offset, 3, 2) + node T_815 = shl(T_814, 5) + node T_816 = dshr(s2_dout[0], T_815) + node T_817 = bits(T_816, 31, 0) + node T_818 = bits(s2_offset, 3, 2) + node T_819 = shl(T_818, 5) + node T_820 = dshr(s2_dout[1], T_819) + node T_821 = bits(T_820, 31, 0) + node T_822 = bits(s2_offset, 3, 2) + node T_823 = shl(T_822, 5) + node T_824 = dshr(s2_dout[2], T_823) + node T_825 = bits(T_824, 31, 0) + node T_826 = bits(s2_offset, 3, 2) + node T_827 = shl(T_826, 5) + node T_828 = dshr(s2_dout[3], T_827) + node T_829 = bits(T_828, 31, 0) + node T_831 = mux(s2_tag_hit[0], T_817, UInt<1>("h00")) + node T_833 = mux(s2_tag_hit[1], T_821, UInt<1>("h00")) + node T_835 = mux(s2_tag_hit[2], T_825, UInt<1>("h00")) + node T_837 = mux(s2_tag_hit[3], T_829, UInt<1>("h00")) + node T_839 = or(T_831, T_833) + node T_840 = or(T_839, T_835) + node T_841 = or(T_840, T_837) + wire T_842 : UInt<32> + T_842 := UInt<1>("h00") + T_842 := T_841 + resp.bits.data := T_842 + node T_845 = mux(s2_tag_hit[0], s2_dout[0], UInt<1>("h00")) + node T_847 = mux(s2_tag_hit[1], s2_dout[1], UInt<1>("h00")) + node T_849 = mux(s2_tag_hit[2], s2_dout[2], UInt<1>("h00")) + node T_851 = mux(s2_tag_hit[3], s2_dout[3], UInt<1>("h00")) + node T_853 = or(T_845, T_847) + node T_854 = or(T_853, T_849) + node T_855 = or(T_854, T_851) + wire T_856 : UInt<128> + T_856 := UInt<1>("h00") + T_856 := T_855 + resp.bits.datablock := T_856 + resp.valid := s2_hit + node T_858 = eq(state, UInt<1>("h01")) + mem_1.acquire.valid := T_858 + node T_859 = shr(s2_addr, 6) + node T_864 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_865 = cat(UInt<3>("h07"), T_864) + wire T_899 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} + T_899.union := UInt<1>("h00") + T_899.a_type := UInt<1>("h00") + T_899.is_builtin_type := UInt<1>("h00") + T_899.data := UInt<1>("h00") + T_899.addr_beat := UInt<1>("h00") + T_899.client_xact_id := UInt<1>("h00") + T_899.addr_block := UInt<1>("h00") + T_899.is_builtin_type := UInt<1>("h01") + T_899.a_type := UInt<3>("h01") + T_899.client_xact_id := UInt<1>("h00") + T_899.addr_block := T_859 + T_899.addr_beat := UInt<1>("h00") + T_899.data := UInt<1>("h00") + T_899.union := T_865 + mem_1.acquire.bits <> T_899 + node T_937 = eq(UInt<1>("h00"), state) + when T_937 : + when s2_miss : + state := UInt<1>("h01") + skip + invalidated := UInt<1>("h00") + skip + node T_939 = eq(UInt<1>("h01"), state) + when T_939 : + when mem_1.acquire.ready : + state := UInt<2>("h02") + skip + skip + node T_940 = eq(UInt<2>("h02"), state) + when T_940 : + when mem_1.grant.valid : + state := UInt<2>("h03") + skip + skip + node T_941 = eq(UInt<2>("h03"), state) + when T_941 : + when refill_done : + state := UInt<1>("h00") + skip + skip + + module RocketCAM : + input write_addr : UInt<3> + input write_tag : UInt<34> + input write : UInt<1> + output valid_bits : UInt<8> + output hits : UInt<8> + output hit : UInt<1> + input tag : UInt<34> + input clear_mask : UInt<8> + input clear : UInt<1> + input clock : Clock + input reset : UInt<1> + + valid_bits := UInt<1>("h00") + hits := UInt<1>("h00") + hit := UInt<1>("h00") + cmem cam_tags : UInt<34>[8], clock + reg vb_array : UInt<8>, clock, reset + onreset vb_array := UInt<8>("h00") + when write : + node T_20 = dshl(UInt<1>("h01"), write_addr) + node T_21 = or(vb_array, T_20) + node T_22 = not(vb_array) + node T_23 = or(T_22, T_20) + node T_24 = not(T_23) + node T_25 = mux(UInt<1>("h01"), T_21, T_24) + vb_array := T_25 + infer accessor T_26 = cam_tags[write_addr] + T_26 := write_tag + skip + when clear : + node T_27 = not(clear_mask) + node T_28 = and(vb_array, T_27) + vb_array := T_28 + skip + node T_29 = bit(vb_array, 0) + infer accessor T_31 = cam_tags[UInt<1>("h00")] + node T_32 = eq(T_31, tag) + node T_33 = and(T_29, T_32) + node T_34 = bit(vb_array, 1) + infer accessor T_36 = cam_tags[UInt<1>("h01")] + node T_37 = eq(T_36, tag) + node T_38 = and(T_34, T_37) + node T_39 = bit(vb_array, 2) + infer accessor T_41 = cam_tags[UInt<2>("h02")] + node T_42 = eq(T_41, tag) + node T_43 = and(T_39, T_42) + node T_44 = bit(vb_array, 3) + infer accessor T_46 = cam_tags[UInt<2>("h03")] + node T_47 = eq(T_46, tag) + node T_48 = and(T_44, T_47) + node T_49 = bit(vb_array, 4) + infer accessor T_51 = cam_tags[UInt<3>("h04")] + node T_52 = eq(T_51, tag) + node T_53 = and(T_49, T_52) + node T_54 = bit(vb_array, 5) + infer accessor T_56 = cam_tags[UInt<3>("h05")] + node T_57 = eq(T_56, tag) + node T_58 = and(T_54, T_57) + node T_59 = bit(vb_array, 6) + infer accessor T_61 = cam_tags[UInt<3>("h06")] + node T_62 = eq(T_61, tag) + node T_63 = and(T_59, T_62) + node T_64 = bit(vb_array, 7) + infer accessor T_66 = cam_tags[UInt<3>("h07")] + node T_67 = eq(T_66, tag) + node T_68 = and(T_64, T_67) + valid_bits := vb_array + wire T_70 : UInt<1>[8] + T_70[0] := T_33 + T_70[1] := T_38 + T_70[2] := T_43 + T_70[3] := T_48 + T_70[4] := T_53 + T_70[5] := T_58 + T_70[6] := T_63 + T_70[7] := T_68 + node T_80 = cat(T_70[7], T_70[6]) + node T_81 = cat(T_70[5], T_70[4]) + node T_82 = cat(T_80, T_81) + node T_83 = cat(T_70[3], T_70[2]) + node T_84 = cat(T_70[1], T_70[0]) + node T_85 = cat(T_83, T_84) + node T_86 = cat(T_82, T_85) + hits := T_86 + node T_88 = neq(hits, UInt<1>("h00")) + hit := T_88 + + module TLB : + output ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>} + output resp : {miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, hit_idx : UInt<8>} + input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}} + input clock : Clock + input reset : UInt<1> + + ptw.req.bits.fetch := UInt<1>("h00") + ptw.req.bits.store := UInt<1>("h00") + ptw.req.bits.prv := UInt<1>("h00") + ptw.req.bits.addr := UInt<1>("h00") + ptw.req.valid := UInt<1>("h00") + resp.hit_idx := UInt<1>("h00") + resp.xcpt_if := UInt<1>("h00") + resp.xcpt_st := UInt<1>("h00") + resp.xcpt_ld := UInt<1>("h00") + resp.ppn := UInt<1>("h00") + resp.miss := UInt<1>("h00") + req.ready := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg r_refill_tag : UInt<?>, clock, reset + reg r_refill_waddr : UInt<?>, clock, reset + reg r_req : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clock, reset + inst tag_cam of RocketCAM + tag_cam.write_addr := UInt<1>("h00") + tag_cam.write_tag := UInt<1>("h00") + tag_cam.write := UInt<1>("h00") + tag_cam.tag := UInt<1>("h00") + tag_cam.clear_mask := UInt<1>("h00") + tag_cam.clear := UInt<1>("h00") + tag_cam.reset := UInt<1>("h00") + tag_cam.clock := clock + tag_cam.reset := reset + cmem tag_ram : UInt<20>[8], clock + node lookup_tag = cat(req.bits.asid, req.bits.vpn) + tag_cam.tag := lookup_tag + node T_181 = eq(state, UInt<2>("h02")) + node T_182 = and(T_181, ptw.resp.valid) + tag_cam.write := T_182 + tag_cam.write_tag := r_refill_tag + tag_cam.write_addr := r_refill_waddr + node T_183 = bits(tag_cam.hits, 7, 4) + node T_184 = bits(tag_cam.hits, 3, 0) + node T_186 = neq(T_183, UInt<1>("h00")) + node T_187 = or(T_183, T_184) + node T_188 = bits(T_187, 3, 2) + node T_189 = bits(T_187, 1, 0) + node T_191 = neq(T_188, UInt<1>("h00")) + node T_192 = or(T_188, T_189) + node T_193 = bit(T_192, 1) + node T_194 = cat(T_191, T_193) + node tag_hit_addr = cat(T_186, T_194) + reg valid_array : UInt<1>[8], clock, reset + reg ur_array : UInt<1>[8], clock, reset + reg uw_array : UInt<1>[8], clock, reset + reg ux_array : UInt<1>[8], clock, reset + reg sr_array : UInt<1>[8], clock, reset + reg sw_array : UInt<1>[8], clock, reset + reg sx_array : UInt<1>[8], clock, reset + reg dirty_array : UInt<1>[8], clock, reset + when ptw.resp.valid : + infer accessor T_388 = tag_ram[r_refill_waddr] + T_388 := ptw.resp.bits.pte.ppn + infer accessor T_389 = valid_array[r_refill_waddr] + node T_391 = eq(ptw.resp.bits.error, UInt<1>("h00")) + T_389 := T_391 + infer accessor T_392 = ur_array[r_refill_waddr] + node T_394 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_395 = and(ptw.resp.bits.pte.v, T_394) + node T_397 = lt(ptw.resp.bits.pte.typ, UInt<4>("h08")) + node T_398 = and(T_395, T_397) + node T_400 = eq(ptw.resp.bits.error, UInt<1>("h00")) + node T_401 = and(T_398, T_400) + T_392 := T_401 + infer accessor T_402 = uw_array[r_refill_waddr] + node T_404 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_405 = and(ptw.resp.bits.pte.v, T_404) + node T_407 = lt(ptw.resp.bits.pte.typ, UInt<4>("h08")) + node T_408 = and(T_405, T_407) + node T_409 = bit(ptw.resp.bits.pte.typ, 0) + node T_410 = and(T_408, T_409) + node T_412 = eq(ptw.resp.bits.error, UInt<1>("h00")) + node T_413 = and(T_410, T_412) + T_402 := T_413 + infer accessor T_414 = ux_array[r_refill_waddr] + node T_416 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_417 = and(ptw.resp.bits.pte.v, T_416) + node T_419 = lt(ptw.resp.bits.pte.typ, UInt<4>("h08")) + node T_420 = and(T_417, T_419) + node T_421 = bit(ptw.resp.bits.pte.typ, 1) + node T_422 = and(T_420, T_421) + node T_424 = eq(ptw.resp.bits.error, UInt<1>("h00")) + node T_425 = and(T_422, T_424) + T_414 := T_425 + infer accessor T_426 = sr_array[r_refill_waddr] + node T_428 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_429 = and(ptw.resp.bits.pte.v, T_428) + node T_431 = eq(ptw.resp.bits.error, UInt<1>("h00")) + node T_432 = and(T_429, T_431) + T_426 := T_432 + infer accessor T_433 = sw_array[r_refill_waddr] + node T_435 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_436 = and(ptw.resp.bits.pte.v, T_435) + node T_437 = bit(ptw.resp.bits.pte.typ, 0) + node T_438 = and(T_436, T_437) + node T_440 = eq(ptw.resp.bits.error, UInt<1>("h00")) + node T_441 = and(T_438, T_440) + T_433 := T_441 + infer accessor T_442 = sx_array[r_refill_waddr] + node T_444 = geq(ptw.resp.bits.pte.typ, UInt<3>("h04")) + node T_445 = and(ptw.resp.bits.pte.v, T_444) + node T_446 = bit(ptw.resp.bits.pte.typ, 1) + node T_447 = and(T_445, T_446) + node T_449 = eq(ptw.resp.bits.error, UInt<1>("h00")) + node T_450 = and(T_447, T_449) + T_442 := T_450 + infer accessor T_451 = dirty_array[r_refill_waddr] + T_451 := ptw.resp.bits.pte.d + skip + node T_452 = not(tag_cam.valid_bits) + node T_454 = eq(T_452, UInt<1>("h00")) + node has_invalid_entry = eq(T_454, UInt<1>("h00")) + node T_457 = not(tag_cam.valid_bits) + node T_458 = bit(T_457, 0) + node T_459 = bit(T_457, 1) + node T_460 = bit(T_457, 2) + node T_461 = bit(T_457, 3) + node T_462 = bit(T_457, 4) + node T_463 = bit(T_457, 5) + node T_464 = bit(T_457, 6) + node T_465 = bit(T_457, 7) + wire T_467 : UInt<1>[8] + T_467[0] := T_458 + T_467[1] := T_459 + T_467[2] := T_460 + T_467[3] := T_461 + T_467[4] := T_462 + T_467[5] := T_463 + T_467[6] := T_464 + T_467[7] := T_465 + node T_485 = mux(T_467[6], UInt<3>("h06"), UInt<3>("h07")) + node T_486 = mux(T_467[5], UInt<3>("h05"), T_485) + node T_487 = mux(T_467[4], UInt<3>("h04"), T_486) + node T_488 = mux(T_467[3], UInt<2>("h03"), T_487) + node T_489 = mux(T_467[2], UInt<2>("h02"), T_488) + node T_490 = mux(T_467[1], UInt<1>("h01"), T_489) + node invalid_entry = mux(T_467[0], UInt<1>("h00"), T_490) + reg T_493 : UInt<8>, clock, reset + node T_495 = dshr(T_493, UInt<1>("h01")) + node T_496 = bit(T_495, 0) + node T_497 = cat(UInt<1>("h01"), T_496) + node T_498 = dshr(T_493, T_497) + node T_499 = bit(T_498, 0) + node T_500 = cat(T_497, T_499) + node T_501 = dshr(T_493, T_500) + node T_502 = bit(T_501, 0) + node T_503 = cat(T_500, T_502) + node T_504 = bits(T_503, 2, 0) + node repl_waddr = mux(has_invalid_entry, invalid_entry, T_504) + node T_507 = eq(req.bits.instruction, UInt<1>("h00")) + node T_508 = and(ptw.status.mprv, T_507) + node priv = mux(T_508, ptw.status.prv1, ptw.status.prv) + node priv_s = eq(priv, UInt<1>("h01")) + node priv_uses_vm = leq(priv, UInt<1>("h01")) + node T_536 = eq(r_req.store, UInt<1>("h00")) + node T_537 = or(r_req.instruction, r_req.store) + node T_539 = eq(T_537, UInt<1>("h00")) + node T_540 = cat(r_req.store, T_539) + node req_xwr = cat(T_536, T_540) + node T_542 = cat(sr_array[7], sr_array[6]) + node T_543 = cat(sr_array[5], sr_array[4]) + node T_544 = cat(T_542, T_543) + node T_545 = cat(sr_array[3], sr_array[2]) + node T_546 = cat(sr_array[1], sr_array[0]) + node T_547 = cat(T_545, T_546) + node T_548 = cat(T_544, T_547) + node T_549 = cat(ur_array[7], ur_array[6]) + node T_550 = cat(ur_array[5], ur_array[4]) + node T_551 = cat(T_549, T_550) + node T_552 = cat(ur_array[3], ur_array[2]) + node T_553 = cat(ur_array[1], ur_array[0]) + node T_554 = cat(T_552, T_553) + node T_555 = cat(T_551, T_554) + node r_array = mux(priv_s, T_548, T_555) + node T_557 = cat(sw_array[7], sw_array[6]) + node T_558 = cat(sw_array[5], sw_array[4]) + node T_559 = cat(T_557, T_558) + node T_560 = cat(sw_array[3], sw_array[2]) + node T_561 = cat(sw_array[1], sw_array[0]) + node T_562 = cat(T_560, T_561) + node T_563 = cat(T_559, T_562) + node T_564 = cat(uw_array[7], uw_array[6]) + node T_565 = cat(uw_array[5], uw_array[4]) + node T_566 = cat(T_564, T_565) + node T_567 = cat(uw_array[3], uw_array[2]) + node T_568 = cat(uw_array[1], uw_array[0]) + node T_569 = cat(T_567, T_568) + node T_570 = cat(T_566, T_569) + node w_array = mux(priv_s, T_563, T_570) + node T_572 = cat(sx_array[7], sx_array[6]) + node T_573 = cat(sx_array[5], sx_array[4]) + node T_574 = cat(T_572, T_573) + node T_575 = cat(sx_array[3], sx_array[2]) + node T_576 = cat(sx_array[1], sx_array[0]) + node T_577 = cat(T_575, T_576) + node T_578 = cat(T_574, T_577) + node T_579 = cat(ux_array[7], ux_array[6]) + node T_580 = cat(ux_array[5], ux_array[4]) + node T_581 = cat(T_579, T_580) + node T_582 = cat(ux_array[3], ux_array[2]) + node T_583 = cat(ux_array[1], ux_array[0]) + node T_584 = cat(T_582, T_583) + node T_585 = cat(T_581, T_584) + node x_array = mux(priv_s, T_578, T_585) + node T_587 = bit(ptw.status.vm, 3) + node vm_enabled = and(T_587, priv_uses_vm) + node T_589 = bit(req.bits.vpn, 27) + node T_590 = bit(req.bits.vpn, 26) + node bad_va = neq(T_589, T_590) + node T_592 = cat(dirty_array[7], dirty_array[6]) + node T_593 = cat(dirty_array[5], dirty_array[4]) + node T_594 = cat(T_592, T_593) + node T_595 = cat(dirty_array[3], dirty_array[2]) + node T_596 = cat(dirty_array[1], dirty_array[0]) + node T_597 = cat(T_595, T_596) + node T_598 = cat(T_594, T_597) + node T_600 = mux(req.bits.store, w_array, UInt<1>("h00")) + node T_601 = not(T_600) + node T_602 = or(T_598, T_601) + node tag_hits = and(tag_cam.hits, T_602) + node tag_hit = neq(tag_hits, UInt<1>("h00")) + node tlb_hit = and(vm_enabled, tag_hit) + node T_608 = eq(tag_hit, UInt<1>("h00")) + node T_609 = and(vm_enabled, T_608) + node T_611 = eq(bad_va, UInt<1>("h00")) + node tlb_miss = and(T_609, T_611) + node T_613 = and(req.valid, tlb_hit) + when T_613 : + node T_614 = bits(tag_cam.hits, 7, 4) + node T_615 = bits(tag_cam.hits, 3, 0) + node T_617 = neq(T_614, UInt<1>("h00")) + node T_618 = or(T_614, T_615) + node T_619 = bits(T_618, 3, 2) + node T_620 = bits(T_618, 1, 0) + node T_622 = neq(T_619, UInt<1>("h00")) + node T_623 = or(T_619, T_620) + node T_624 = bit(T_623, 1) + node T_625 = cat(T_622, T_624) + node T_626 = cat(T_617, T_625) + node T_628 = bit(T_626, 2) + node T_630 = dshl(UInt<8>("h01"), UInt<1>("h01")) + node T_631 = bits(T_630, 7, 0) + node T_632 = not(T_631) + node T_633 = and(T_493, T_632) + node T_635 = mux(T_628, UInt<1>("h00"), T_631) + node T_636 = or(T_633, T_635) + node T_637 = cat(UInt<1>("h01"), T_628) + node T_638 = bit(T_626, 1) + node T_640 = dshl(UInt<8>("h01"), T_637) + node T_641 = bits(T_640, 7, 0) + node T_642 = not(T_641) + node T_643 = and(T_636, T_642) + node T_645 = mux(T_638, UInt<1>("h00"), T_641) + node T_646 = or(T_643, T_645) + node T_647 = cat(T_637, T_638) + node T_648 = bit(T_626, 0) + node T_650 = dshl(UInt<8>("h01"), T_647) + node T_651 = bits(T_650, 7, 0) + node T_652 = not(T_651) + node T_653 = and(T_646, T_652) + node T_655 = mux(T_648, UInt<1>("h00"), T_651) + node T_656 = or(T_653, T_655) + node T_657 = cat(T_647, T_648) + T_493 := T_656 + skip + node T_658 = eq(state, UInt<1>("h00")) + req.ready := T_658 + node T_659 = and(r_array, tag_cam.hits) + node T_661 = neq(T_659, UInt<1>("h00")) + node T_663 = eq(T_661, UInt<1>("h00")) + node T_664 = and(tlb_hit, T_663) + node T_665 = or(bad_va, T_664) + resp.xcpt_ld := T_665 + node T_666 = and(w_array, tag_cam.hits) + node T_668 = neq(T_666, UInt<1>("h00")) + node T_670 = eq(T_668, UInt<1>("h00")) + node T_671 = and(tlb_hit, T_670) + node T_672 = or(bad_va, T_671) + resp.xcpt_st := T_672 + node T_673 = and(x_array, tag_cam.hits) + node T_675 = neq(T_673, UInt<1>("h00")) + node T_677 = eq(T_675, UInt<1>("h00")) + node T_678 = and(tlb_hit, T_677) + node T_679 = or(bad_va, T_678) + resp.xcpt_if := T_679 + resp.miss := tlb_miss + node T_681 = eq(req.bits.passthrough, UInt<1>("h00")) + node T_682 = and(vm_enabled, T_681) + node T_683 = bit(tag_cam.hits, 0) + node T_684 = bit(tag_cam.hits, 1) + node T_685 = bit(tag_cam.hits, 2) + node T_686 = bit(tag_cam.hits, 3) + node T_687 = bit(tag_cam.hits, 4) + node T_688 = bit(tag_cam.hits, 5) + node T_689 = bit(tag_cam.hits, 6) + node T_690 = bit(tag_cam.hits, 7) + infer accessor T_692 = tag_ram[UInt<1>("h00")] + infer accessor T_694 = tag_ram[UInt<1>("h01")] + infer accessor T_696 = tag_ram[UInt<2>("h02")] + infer accessor T_698 = tag_ram[UInt<2>("h03")] + infer accessor T_700 = tag_ram[UInt<3>("h04")] + infer accessor T_702 = tag_ram[UInt<3>("h05")] + infer accessor T_704 = tag_ram[UInt<3>("h06")] + infer accessor T_706 = tag_ram[UInt<3>("h07")] + node T_708 = mux(T_683, T_692, UInt<1>("h00")) + node T_710 = mux(T_684, T_694, UInt<1>("h00")) + node T_712 = mux(T_685, T_696, UInt<1>("h00")) + node T_714 = mux(T_686, T_698, UInt<1>("h00")) + node T_716 = mux(T_687, T_700, UInt<1>("h00")) + node T_718 = mux(T_688, T_702, UInt<1>("h00")) + node T_720 = mux(T_689, T_704, UInt<1>("h00")) + node T_722 = mux(T_690, T_706, UInt<1>("h00")) + node T_724 = or(T_708, T_710) + node T_725 = or(T_724, T_712) + node T_726 = or(T_725, T_714) + node T_727 = or(T_726, T_716) + node T_728 = or(T_727, T_718) + node T_729 = or(T_728, T_720) + node T_730 = or(T_729, T_722) + wire T_731 : UInt<20> + T_731 := UInt<1>("h00") + T_731 := T_730 + node T_733 = bits(req.bits.vpn, 19, 0) + node T_734 = mux(T_682, T_731, T_733) + resp.ppn := T_734 + resp.hit_idx := tag_cam.hits + node T_735 = and(req.ready, req.valid) + node T_736 = or(ptw.invalidate, T_735) + tag_cam.clear := T_736 + node T_737 = cat(valid_array[7], valid_array[6]) + node T_738 = cat(valid_array[5], valid_array[4]) + node T_739 = cat(T_737, T_738) + node T_740 = cat(valid_array[3], valid_array[2]) + node T_741 = cat(valid_array[1], valid_array[0]) + node T_742 = cat(T_740, T_741) + node T_743 = cat(T_739, T_742) + node T_744 = not(T_743) + node T_745 = not(tag_hits) + node T_746 = and(tag_cam.hits, T_745) + node T_747 = or(T_744, T_746) + tag_cam.clear_mask := T_747 + when ptw.invalidate : + node T_749 = not(UInt<8>("h00")) + tag_cam.clear_mask := T_749 + skip + node T_750 = eq(state, UInt<1>("h01")) + ptw.req.valid := T_750 + ptw.req.bits.addr := r_refill_tag + ptw.req.bits.prv := ptw.status.prv + ptw.req.bits.store := r_req.store + ptw.req.bits.fetch := r_req.instruction + node T_751 = and(req.ready, req.valid) + node T_752 = and(T_751, tlb_miss) + when T_752 : + state := UInt<1>("h01") + r_refill_tag := lookup_tag + r_refill_waddr := repl_waddr + r_req <> req.bits + skip + node T_753 = eq(state, UInt<1>("h01")) + when T_753 : + when ptw.invalidate : + state := UInt<1>("h00") + skip + when ptw.req.ready : + state := UInt<2>("h02") + when ptw.invalidate : + state := UInt<2>("h03") + skip + skip + skip + node T_754 = eq(state, UInt<2>("h02")) + node T_755 = and(T_754, ptw.invalidate) + when T_755 : + state := UInt<2>("h03") + skip + when ptw.resp.valid : + state := UInt<1>("h00") + skip + + module Frontend : + output mem_1 : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + output ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>} + input cpu : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>} + input clock : Clock + input reset : UInt<1> + + mem_1.grant.ready := UInt<1>("h00") + mem_1.acquire.bits.union := UInt<1>("h00") + mem_1.acquire.bits.a_type := UInt<1>("h00") + mem_1.acquire.bits.is_builtin_type := UInt<1>("h00") + mem_1.acquire.bits.data := UInt<1>("h00") + mem_1.acquire.bits.addr_beat := UInt<1>("h00") + mem_1.acquire.bits.client_xact_id := UInt<1>("h00") + mem_1.acquire.bits.addr_block := UInt<1>("h00") + mem_1.acquire.valid := UInt<1>("h00") + ptw.req.bits.fetch := UInt<1>("h00") + ptw.req.bits.store := UInt<1>("h00") + ptw.req.bits.prv := UInt<1>("h00") + ptw.req.bits.addr := UInt<1>("h00") + ptw.req.valid := UInt<1>("h00") + cpu.npc := UInt<1>("h00") + cpu.btb_resp.bits.bht.value := UInt<1>("h00") + cpu.btb_resp.bits.bht.history := UInt<1>("h00") + cpu.btb_resp.bits.entry := UInt<1>("h00") + cpu.btb_resp.bits.target := UInt<1>("h00") + cpu.btb_resp.bits.bridx := UInt<1>("h00") + cpu.btb_resp.bits.mask := UInt<1>("h00") + cpu.btb_resp.bits.taken := UInt<1>("h00") + cpu.btb_resp.valid := UInt<1>("h00") + cpu.resp.bits.xcpt_if := UInt<1>("h00") + cpu.resp.bits.mask := UInt<1>("h00") + cpu.resp.bits.data[0] := UInt<1>("h00") + cpu.resp.bits.pc := UInt<1>("h00") + cpu.resp.valid := UInt<1>("h00") + inst btb of BTB + btb.invalidate := UInt<1>("h00") + btb.ras_update.bits.prediction.bits.bht.value := UInt<1>("h00") + btb.ras_update.bits.prediction.bits.bht.history := UInt<1>("h00") + btb.ras_update.bits.prediction.bits.entry := UInt<1>("h00") + btb.ras_update.bits.prediction.bits.target := UInt<1>("h00") + btb.ras_update.bits.prediction.bits.bridx := UInt<1>("h00") + btb.ras_update.bits.prediction.bits.mask := UInt<1>("h00") + btb.ras_update.bits.prediction.bits.taken := UInt<1>("h00") + btb.ras_update.bits.prediction.valid := UInt<1>("h00") + btb.ras_update.bits.returnAddr := UInt<1>("h00") + btb.ras_update.bits.isReturn := UInt<1>("h00") + btb.ras_update.bits.isCall := UInt<1>("h00") + btb.ras_update.valid := UInt<1>("h00") + btb.bht_update.bits.mispredict := UInt<1>("h00") + btb.bht_update.bits.taken := UInt<1>("h00") + btb.bht_update.bits.pc := UInt<1>("h00") + btb.bht_update.bits.prediction.bits.bht.value := UInt<1>("h00") + btb.bht_update.bits.prediction.bits.bht.history := UInt<1>("h00") + btb.bht_update.bits.prediction.bits.entry := UInt<1>("h00") + btb.bht_update.bits.prediction.bits.target := UInt<1>("h00") + btb.bht_update.bits.prediction.bits.bridx := UInt<1>("h00") + btb.bht_update.bits.prediction.bits.mask := UInt<1>("h00") + btb.bht_update.bits.prediction.bits.taken := UInt<1>("h00") + btb.bht_update.bits.prediction.valid := UInt<1>("h00") + btb.bht_update.valid := UInt<1>("h00") + btb.btb_update.bits.br_pc := UInt<1>("h00") + btb.btb_update.bits.isReturn := UInt<1>("h00") + btb.btb_update.bits.isJump := UInt<1>("h00") + btb.btb_update.bits.taken := UInt<1>("h00") + btb.btb_update.bits.target := UInt<1>("h00") + btb.btb_update.bits.pc := UInt<1>("h00") + btb.btb_update.bits.prediction.bits.bht.value := UInt<1>("h00") + btb.btb_update.bits.prediction.bits.bht.history := UInt<1>("h00") + btb.btb_update.bits.prediction.bits.entry := UInt<1>("h00") + btb.btb_update.bits.prediction.bits.target := UInt<1>("h00") + btb.btb_update.bits.prediction.bits.bridx := UInt<1>("h00") + btb.btb_update.bits.prediction.bits.mask := UInt<1>("h00") + btb.btb_update.bits.prediction.bits.taken := UInt<1>("h00") + btb.btb_update.bits.prediction.valid := UInt<1>("h00") + btb.btb_update.valid := UInt<1>("h00") + btb.req.bits.addr := UInt<1>("h00") + btb.req.valid := UInt<1>("h00") + btb.reset := UInt<1>("h00") + btb.clock := clock + btb.reset := reset + inst icache of ICache + icache.mem_1.grant.bits.g_type := UInt<1>("h00") + icache.mem_1.grant.bits.is_builtin_type := UInt<1>("h00") + icache.mem_1.grant.bits.manager_xact_id := UInt<1>("h00") + icache.mem_1.grant.bits.client_xact_id := UInt<1>("h00") + icache.mem_1.grant.bits.data := UInt<1>("h00") + icache.mem_1.grant.bits.addr_beat := UInt<1>("h00") + icache.mem_1.grant.valid := UInt<1>("h00") + icache.mem_1.acquire.ready := UInt<1>("h00") + icache.invalidate := UInt<1>("h00") + icache.resp.ready := UInt<1>("h00") + icache.req.bits.kill := UInt<1>("h00") + icache.req.bits.ppn := UInt<1>("h00") + icache.req.bits.idx := UInt<1>("h00") + icache.req.valid := UInt<1>("h00") + icache.reset := UInt<1>("h00") + icache.clock := clock + icache.reset := reset + inst tlb of TLB + tlb.ptw.invalidate := UInt<1>("h00") + tlb.ptw.status.ie := UInt<1>("h00") + tlb.ptw.status.prv := UInt<1>("h00") + tlb.ptw.status.ie1 := UInt<1>("h00") + tlb.ptw.status.prv1 := UInt<1>("h00") + tlb.ptw.status.ie2 := UInt<1>("h00") + tlb.ptw.status.prv2 := UInt<1>("h00") + tlb.ptw.status.ie3 := UInt<1>("h00") + tlb.ptw.status.prv3 := UInt<1>("h00") + tlb.ptw.status.fs := UInt<1>("h00") + tlb.ptw.status.xs := UInt<1>("h00") + tlb.ptw.status.mprv := UInt<1>("h00") + tlb.ptw.status.vm := UInt<1>("h00") + tlb.ptw.status.zero1 := UInt<1>("h00") + tlb.ptw.status.sd_rv32 := UInt<1>("h00") + tlb.ptw.status.zero2 := UInt<1>("h00") + tlb.ptw.status.sd := UInt<1>("h00") + tlb.ptw.resp.bits.pte.v := UInt<1>("h00") + tlb.ptw.resp.bits.pte.typ := UInt<1>("h00") + tlb.ptw.resp.bits.pte.r := UInt<1>("h00") + tlb.ptw.resp.bits.pte.d := UInt<1>("h00") + tlb.ptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") + tlb.ptw.resp.bits.pte.ppn := UInt<1>("h00") + tlb.ptw.resp.bits.error := UInt<1>("h00") + tlb.ptw.resp.valid := UInt<1>("h00") + tlb.ptw.req.ready := UInt<1>("h00") + tlb.req.bits.store := UInt<1>("h00") + tlb.req.bits.instruction := UInt<1>("h00") + tlb.req.bits.passthrough := UInt<1>("h00") + tlb.req.bits.vpn := UInt<1>("h00") + tlb.req.bits.asid := UInt<1>("h00") + tlb.req.valid := UInt<1>("h00") + tlb.reset := UInt<1>("h00") + tlb.clock := clock + tlb.reset := reset + reg s1_pc_ : UInt<?>, clock, reset + node T_1322 = not(s1_pc_) + node T_1324 = or(T_1322, UInt<2>("h03")) + node s1_pc = not(T_1324) + reg s1_same_block : UInt<1>, clock, reset + reg s2_valid : UInt<1>, clock, reset + onreset s2_valid := UInt<1>("h01") + reg s2_pc : UInt<?>, clock, reset + onreset s2_pc := UInt<10>("h0200") + reg s2_btb_resp_valid : UInt<1>, clock, reset + onreset s2_btb_resp_valid := UInt<1>("h00") + reg s2_btb_resp_bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock, reset + reg s2_xcpt_if : UInt<1>, clock, reset + onreset s2_xcpt_if := UInt<1>("h00") + node T_1345 = bit(btb.resp.bits.target, 38) + node btbTarget = cat(T_1345, btb.resp.bits.target) + node ntpc_0 = addw(s1_pc, UInt<3>("h04")) + node T_1349 = bit(s1_pc, 38) + node T_1350 = bit(ntpc_0, 38) + node T_1351 = and(T_1349, T_1350) + node T_1352 = bits(ntpc_0, 38, 2) + node T_1354 = cat(T_1352, UInt<2>("h00")) + node ntpc = cat(T_1351, T_1354) + node T_1357 = eq(icache.resp.valid, UInt<1>("h00")) + node icmiss = and(s2_valid, T_1357) + node predicted_npc = mux(btb.resp.bits.taken, btbTarget, ntpc) + node npc = mux(icmiss, s2_pc, predicted_npc) + node T_1362 = eq(icmiss, UInt<1>("h00")) + node T_1364 = eq(cpu.req.valid, UInt<1>("h00")) + node T_1365 = and(T_1362, T_1364) + node T_1367 = eq(btb.resp.bits.taken, UInt<1>("h00")) + node T_1368 = and(T_1365, T_1367) + node T_1370 = and(ntpc, UInt<5>("h010")) + node T_1372 = and(s1_pc, UInt<5>("h010")) + node T_1373 = eq(T_1370, T_1372) + node s0_same_block = and(T_1368, T_1373) + node T_1376 = eq(cpu.resp.ready, UInt<1>("h00")) + node stall = and(cpu.resp.valid, T_1376) + node T_1379 = eq(stall, UInt<1>("h00")) + when T_1379 : + node T_1381 = eq(tlb.resp.miss, UInt<1>("h00")) + node T_1382 = and(s0_same_block, T_1381) + s1_same_block := T_1382 + s1_pc_ := npc + node T_1384 = eq(icmiss, UInt<1>("h00")) + s2_valid := T_1384 + node T_1386 = eq(icmiss, UInt<1>("h00")) + when T_1386 : + s2_pc := s1_pc + s2_btb_resp_valid := btb.resp.valid + when btb.resp.valid : + s2_btb_resp_bits <> btb.resp.bits + skip + s2_xcpt_if := tlb.resp.xcpt_if + skip + skip + when cpu.req.valid : + s1_same_block := UInt<1>("h00") + s1_pc_ := cpu.req.bits.pc + s2_valid := UInt<1>("h00") + skip + node T_1390 = eq(stall, UInt<1>("h00")) + node T_1392 = eq(icmiss, UInt<1>("h00")) + node T_1393 = and(T_1390, T_1392) + btb.req.valid := T_1393 + btb.req.bits.addr := s1_pc + btb.btb_update <> cpu.btb_update + btb.bht_update <> cpu.bht_update + btb.ras_update <> cpu.ras_update + node T_1394 = or(cpu.invalidate, ptw.invalidate) + btb.invalidate := T_1394 + ptw <> tlb.ptw + node T_1396 = eq(stall, UInt<1>("h00")) + node T_1398 = eq(icmiss, UInt<1>("h00")) + node T_1399 = and(T_1396, T_1398) + tlb.req.valid := T_1399 + node T_1400 = shr(s1_pc, 12) + tlb.req.bits.vpn := T_1400 + tlb.req.bits.asid := UInt<1>("h00") + tlb.req.bits.passthrough := UInt<1>("h00") + tlb.req.bits.instruction := UInt<1>("h01") + tlb.req.bits.store := UInt<1>("h00") + mem_1 <> icache.mem_1 + node T_1406 = eq(stall, UInt<1>("h00")) + node T_1408 = eq(s0_same_block, UInt<1>("h00")) + node T_1409 = and(T_1406, T_1408) + icache.req.valid := T_1409 + icache.req.bits.idx := cpu.npc + icache.invalidate := cpu.invalidate + icache.req.bits.ppn := tlb.resp.ppn + node T_1410 = or(cpu.req.valid, tlb.resp.miss) + node T_1411 = or(T_1410, icmiss) + node T_1412 = or(T_1411, ptw.invalidate) + icache.req.bits.kill := T_1412 + node T_1414 = eq(stall, UInt<1>("h00")) + node T_1416 = eq(s1_same_block, UInt<1>("h00")) + node T_1417 = and(T_1414, T_1416) + icache.resp.ready := T_1417 + node T_1418 = or(s2_xcpt_if, icache.resp.valid) + node T_1419 = and(s2_valid, T_1418) + cpu.resp.valid := T_1419 + cpu.resp.bits.pc := s2_pc + node T_1420 = mux(cpu.req.valid, cpu.req.bits.pc, npc) + cpu.npc := T_1420 + node T_1421 = bits(s2_pc, 3, 2) + node T_1422 = shl(T_1421, 5) + node fetch_data = dshr(icache.resp.bits.datablock, T_1422) + node T_1424 = bits(fetch_data, 31, 0) + cpu.resp.bits.data[0] := T_1424 + node T_1426 = and(UInt<2>("h03"), s2_btb_resp_bits.mask) + node T_1427 = mux(s2_btb_resp_valid, T_1426, UInt<2>("h03")) + cpu.resp.bits.mask := T_1427 + cpu.resp.bits.xcpt_if := s2_xcpt_if + cpu.btb_resp.valid := s2_btb_resp_valid + cpu.btb_resp.bits <> s2_btb_resp_bits + + module WritebackUnit : + output release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} + input data_resp : UInt<128> + output data_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}} + output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}} + input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}} + input clock : Clock + input reset : UInt<1> + + release.bits.voluntary := UInt<1>("h00") + release.bits.r_type := UInt<1>("h00") + release.bits.data := UInt<1>("h00") + release.bits.addr_beat := UInt<1>("h00") + release.bits.client_xact_id := UInt<1>("h00") + release.bits.addr_block := UInt<1>("h00") + release.valid := UInt<1>("h00") + data_req.bits.addr := UInt<1>("h00") + data_req.bits.way_en := UInt<1>("h00") + data_req.valid := UInt<1>("h00") + meta_read.bits.tag := UInt<1>("h00") + meta_read.bits.idx := UInt<1>("h00") + meta_read.valid := UInt<1>("h00") + req.ready := UInt<1>("h00") + reg active : UInt<1>, clock, reset + onreset active := UInt<1>("h00") + reg r1_data_req_fired : UInt<1>, clock, reset + onreset r1_data_req_fired := UInt<1>("h00") + reg r2_data_req_fired : UInt<1>, clock, reset + onreset r2_data_req_fired := UInt<1>("h00") + reg data_req_cnt : UInt<3>, clock, reset + onreset data_req_cnt := UInt<3>("h00") + node T_292 = not(UInt<1>("h01")) + node beat_done = eq(T_292, UInt<1>("h00")) + node T_295 = and(release.ready, release.valid) + reg beat_cnt : UInt<2>, clock, reset + onreset beat_cnt := UInt<2>("h00") + when T_295 : + node T_299 = eq(beat_cnt, UInt<2>("h03")) + node T_301 = and(UInt<1>("h00"), T_299) + node T_304 = addw(beat_cnt, UInt<1>("h01")) + node T_305 = mux(T_301, UInt<1>("h00"), T_304) + beat_cnt := T_305 + skip + node all_beats_done = and(T_295, T_299) + reg req_1 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}, clock, reset + release.valid := UInt<1>("h00") + when active : + r1_data_req_fired := UInt<1>("h00") + r2_data_req_fired := r1_data_req_fired + node T_371 = and(data_req.ready, data_req.valid) + node T_372 = and(meta_read.ready, meta_read.valid) + node T_373 = and(T_371, T_372) + when T_373 : + r1_data_req_fired := UInt<1>("h01") + node T_376 = addw(data_req_cnt, UInt<1>("h01")) + data_req_cnt := T_376 + skip + when r2_data_req_fired : + release.valid := beat_done + when beat_done : + node T_378 = eq(release.ready, UInt<1>("h00")) + when T_378 : + r1_data_req_fired := UInt<1>("h00") + r2_data_req_fired := UInt<1>("h00") + node T_382 = and(UInt<1>("h01"), r1_data_req_fired) + node T_385 = mux(T_382, UInt<2>("h02"), UInt<1>("h01")) + node T_386 = subw(data_req_cnt, T_385) + data_req_cnt := T_386 + skip + else : + skip + skip + node T_388 = eq(r1_data_req_fired, UInt<1>("h00")) + when T_388 : + node T_390 = lt(data_req_cnt, UInt<3>("h04")) + node T_392 = eq(release.ready, UInt<1>("h00")) + node T_393 = or(T_390, T_392) + active := T_393 + skip + skip + skip + node T_394 = and(req.ready, req.valid) + when T_394 : + active := UInt<1>("h01") + data_req_cnt := UInt<1>("h00") + req_1 <> req.bits + skip + node T_398 = eq(active, UInt<1>("h00")) + req.ready := T_398 + node req_idx = bits(req_1.addr_block, 5, 0) + node T_401 = lt(data_req_cnt, UInt<3>("h04")) + node fire = and(active, T_401) + meta_read.valid := fire + meta_read.bits.idx := req_idx + node T_403 = shr(req_1.addr_block, 6) + meta_read.bits.tag := T_403 + data_req.valid := fire + data_req.bits.way_en := req_1.way_en + node T_404 = bits(data_req_cnt, 1, 0) + node T_405 = cat(req_idx, T_404) + node T_406 = shl(T_405, 4) + data_req.bits.addr := T_406 + release.bits <> req_1 + release.bits.addr_beat := beat_cnt + release.bits.data := data_resp + + module ProbeUnit : + input block_state : {state : UInt<2>} + input mshr_rdy : UInt<1> + input way_en : UInt<4> + output wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}} + output meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}} + output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}} + output rep : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} + input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<1>}} + input clock : Clock + input reset : UInt<1> + + wb_req.bits.way_en := UInt<1>("h00") + wb_req.bits.voluntary := UInt<1>("h00") + wb_req.bits.r_type := UInt<1>("h00") + wb_req.bits.data := UInt<1>("h00") + wb_req.bits.addr_beat := UInt<1>("h00") + wb_req.bits.client_xact_id := UInt<1>("h00") + wb_req.bits.addr_block := UInt<1>("h00") + wb_req.valid := UInt<1>("h00") + meta_write.bits.data.coh.state := UInt<1>("h00") + meta_write.bits.data.tag := UInt<1>("h00") + meta_write.bits.way_en := UInt<1>("h00") + meta_write.bits.idx := UInt<1>("h00") + meta_write.valid := UInt<1>("h00") + meta_read.bits.tag := UInt<1>("h00") + meta_read.bits.idx := UInt<1>("h00") + meta_read.valid := UInt<1>("h00") + rep.bits.voluntary := UInt<1>("h00") + rep.bits.r_type := UInt<1>("h00") + rep.bits.data := UInt<1>("h00") + rep.bits.addr_beat := UInt<1>("h00") + rep.bits.client_xact_id := UInt<1>("h00") + rep.bits.addr_block := UInt<1>("h00") + rep.valid := UInt<1>("h00") + req.ready := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg old_coh : {state : UInt<2>}, clock, reset + reg way_en_1 : UInt<?>, clock, reset + reg req_2 : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<1>}, clock, reset + node tag_matches = neq(way_en_1, UInt<1>("h00")) + node T_637 = eq(state, UInt<3>("h07")) + node T_638 = and(T_637, meta_write.ready) + when T_638 : + state := UInt<1>("h00") + skip + node T_639 = eq(state, UInt<3>("h06")) + node T_640 = and(T_639, wb_req.ready) + when T_640 : + state := UInt<3>("h07") + skip + node T_641 = eq(state, UInt<3>("h05")) + node T_642 = and(T_641, wb_req.ready) + when T_642 : + state := UInt<3>("h06") + skip + node T_643 = eq(state, UInt<3>("h04")) + node T_644 = and(T_643, rep.ready) + when T_644 : + state := UInt<1>("h00") + when tag_matches : + wire T_646 : UInt<2>[1] + T_646[0] := UInt<2>("h03") + node T_649 = eq(T_646[0], old_coh.state) + node T_651 = or(UInt<1>("h00"), T_649) + node T_652 = mux(T_651, UInt<3>("h05"), UInt<3>("h07")) + state := T_652 + skip + skip + node T_653 = eq(state, UInt<2>("h03")) + when T_653 : + state := UInt<3>("h04") + old_coh <> block_state + way_en_1 := way_en + node T_655 = eq(mshr_rdy, UInt<1>("h00")) + when T_655 : + state := UInt<1>("h01") + skip + skip + node T_656 = eq(state, UInt<2>("h02")) + when T_656 : + state := UInt<2>("h03") + skip + node T_657 = eq(state, UInt<1>("h01")) + node T_658 = and(T_657, meta_read.ready) + when T_658 : + state := UInt<2>("h02") + skip + node T_659 = eq(state, UInt<1>("h00")) + node T_660 = and(T_659, req.valid) + when T_660 : + state := UInt<1>("h01") + req_2 <> req.bits + skip + wire T_665 : UInt<2>[1] + T_665[0] := UInt<2>("h03") + node T_668 = eq(T_665[0], old_coh.state) + node T_670 = or(UInt<1>("h00"), T_668) + node T_671 = mux(T_670, UInt<1>("h00"), UInt<2>("h03")) + node T_672 = mux(T_670, UInt<1>("h01"), UInt<3>("h04")) + node T_673 = mux(T_670, UInt<2>("h02"), UInt<3>("h05")) + node T_674 = eq(UInt<5>("h013"), UInt<5>("h010")) + node T_675 = mux(T_674, T_673, UInt<3>("h05")) + node T_676 = eq(UInt<5>("h011"), UInt<5>("h010")) + node T_677 = mux(T_676, T_672, T_675) + node T_678 = eq(UInt<5>("h010"), UInt<5>("h010")) + node T_679 = mux(T_678, T_671, T_677) + wire T_681 : UInt<2>[1] + T_681[0] := UInt<2>("h03") + node T_684 = eq(T_681[0], old_coh.state) + node T_686 = or(UInt<1>("h00"), T_684) + node T_687 = mux(T_686, UInt<1>("h00"), UInt<2>("h03")) + node T_688 = mux(T_686, UInt<1>("h01"), UInt<3>("h04")) + node T_689 = mux(T_686, UInt<2>("h02"), UInt<3>("h05")) + node T_690 = eq(UInt<5>("h013"), UInt<5>("h011")) + node T_691 = mux(T_690, T_689, UInt<3>("h05")) + node T_692 = eq(UInt<5>("h011"), UInt<5>("h011")) + node T_693 = mux(T_692, T_688, T_691) + node T_694 = eq(UInt<5>("h010"), UInt<5>("h011")) + node T_695 = mux(T_694, T_687, T_693) + wire T_697 : UInt<2>[1] + T_697[0] := UInt<2>("h03") + node T_700 = eq(T_697[0], old_coh.state) + node T_702 = or(UInt<1>("h00"), T_700) + node T_703 = mux(T_702, UInt<1>("h00"), UInt<2>("h03")) + node T_704 = mux(T_702, UInt<1>("h01"), UInt<3>("h04")) + node T_705 = mux(T_702, UInt<2>("h02"), UInt<3>("h05")) + node T_706 = eq(UInt<5>("h013"), UInt<5>("h013")) + node T_707 = mux(T_706, T_705, UInt<3>("h05")) + node T_708 = eq(UInt<5>("h011"), UInt<5>("h013")) + node T_709 = mux(T_708, T_704, T_707) + node T_710 = eq(UInt<5>("h010"), UInt<5>("h013")) + node T_711 = mux(T_710, T_703, T_709) + node T_712 = eq(UInt<2>("h02"), req_2.p_type) + node T_713 = mux(T_712, T_711, UInt<2>("h03")) + node T_714 = eq(UInt<1>("h01"), req_2.p_type) + node T_715 = mux(T_714, T_695, T_713) + node T_716 = eq(UInt<1>("h00"), req_2.p_type) + node T_717 = mux(T_716, T_679, T_715) + wire reply : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>} + reply.voluntary := UInt<1>("h00") + reply.r_type := UInt<1>("h00") + reply.data := UInt<1>("h00") + reply.addr_beat := UInt<1>("h00") + reply.client_xact_id := UInt<1>("h00") + reply.addr_block := UInt<1>("h00") + reply.r_type := T_717 + reply.client_xact_id := UInt<1>("h00") + reply.addr_block := req_2.addr_block + reply.addr_beat := UInt<1>("h00") + reply.data := UInt<1>("h00") + reply.voluntary := UInt<1>("h00") + node T_785 = eq(state, UInt<1>("h00")) + req.ready := T_785 + node T_786 = eq(state, UInt<3>("h04")) + wire T_788 : UInt<2>[1] + T_788[0] := UInt<2>("h03") + node T_791 = eq(T_788[0], old_coh.state) + node T_793 = or(UInt<1>("h00"), T_791) + node T_794 = and(tag_matches, T_793) + node T_796 = eq(T_794, UInt<1>("h00")) + node T_797 = and(T_786, T_796) + rep.valid := T_797 + rep.bits <> reply + node T_798 = eq(state, UInt<1>("h01")) + meta_read.valid := T_798 + meta_read.bits.idx := req_2.addr_block + node T_799 = shr(req_2.addr_block, 6) + meta_read.bits.tag := T_799 + node T_800 = eq(state, UInt<3>("h07")) + meta_write.valid := T_800 + meta_write.bits.way_en := way_en_1 + meta_write.bits.idx := req_2.addr_block + node T_801 = shr(req_2.addr_block, 6) + meta_write.bits.data.tag := T_801 + node T_802 = eq(UInt<2>("h02"), req_2.p_type) + node T_803 = mux(T_802, old_coh.state, old_coh.state) + node T_804 = eq(UInt<1>("h01"), req_2.p_type) + node T_805 = mux(T_804, UInt<1>("h01"), T_803) + node T_806 = eq(UInt<1>("h00"), req_2.p_type) + node T_807 = mux(T_806, UInt<1>("h00"), T_805) + wire T_833 : {state : UInt<2>} + T_833.state := UInt<1>("h00") + T_833.state := T_807 + meta_write.bits.data.coh <> T_833 + node T_859 = eq(state, UInt<3>("h05")) + wb_req.valid := T_859 + wb_req.bits <> reply + wb_req.bits.way_en := way_en_1 + + module Arbiter_52 : + output chosen : UInt<1> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}[2] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.tag := UInt<1>("h00") + out.bits.idx := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + wire T_108 : UInt<1> + T_108 := UInt<1>("h00") + infer accessor T_110 = in[T_108] + out.valid := T_110.valid + infer accessor T_119 = in[T_108] + out.bits <> T_119.bits + chosen := T_108 + infer accessor T_128 = in[T_108] + T_128.ready := UInt<1>("h00") + node T_140 = or(UInt<1>("h00"), in[0].valid) + node T_142 = eq(T_140, UInt<1>("h00")) + node T_144 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_145 = mux(UInt<1>("h00"), T_144, UInt<1>("h01")) + node T_146 = and(T_145, out.ready) + in[0].ready := T_146 + node T_148 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_149 = mux(UInt<1>("h00"), T_148, T_142) + node T_150 = and(T_149, out.ready) + in[1].ready := T_150 + node T_153 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_154 = mux(UInt<1>("h00"), UInt<1>("h01"), T_153) + T_108 := T_154 + + module Arbiter_53 : + output chosen : UInt<1> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}[2] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.data.coh.state := UInt<1>("h00") + out.bits.data.tag := UInt<1>("h00") + out.bits.way_en := UInt<1>("h00") + out.bits.idx := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + wire T_702 : UInt<1> + T_702 := UInt<1>("h00") + infer accessor T_704 = in[T_702] + out.valid := T_704.valid + infer accessor T_767 = in[T_702] + out.bits <> T_767.bits + chosen := T_702 + infer accessor T_830 = in[T_702] + T_830.ready := UInt<1>("h00") + node T_896 = or(UInt<1>("h00"), in[0].valid) + node T_898 = eq(T_896, UInt<1>("h00")) + node T_900 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_901 = mux(UInt<1>("h00"), T_900, UInt<1>("h01")) + node T_902 = and(T_901, out.ready) + in[0].ready := T_902 + node T_904 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_905 = mux(UInt<1>("h00"), T_904, T_898) + node T_906 = and(T_905, out.ready) + in[1].ready := T_906 + node T_909 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_910 = mux(UInt<1>("h00"), UInt<1>("h01"), T_909) + T_702 := T_910 + + module LockingArbiter : + output chosen : UInt<1> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}[2] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.union := UInt<1>("h00") + out.bits.a_type := UInt<1>("h00") + out.bits.is_builtin_type := UInt<1>("h00") + out.bits.data := UInt<1>("h00") + out.bits.addr_beat := UInt<1>("h00") + out.bits.client_xact_id := UInt<1>("h00") + out.bits.addr_block := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + reg T_722 : UInt<1>, clock, reset + onreset T_722 := UInt<1>("h00") + reg T_724 : UInt<?>, clock, reset + onreset T_724 := UInt<1>("h01") + wire T_726 : UInt<1> + T_726 := UInt<1>("h00") + infer accessor T_728 = in[T_726] + out.valid := T_728.valid + infer accessor T_793 = in[T_726] + out.bits <> T_793.bits + chosen := T_726 + infer accessor T_858 = in[T_726] + T_858.ready := UInt<1>("h00") + node T_926 = or(UInt<1>("h00"), in[0].valid) + node T_928 = eq(T_926, UInt<1>("h00")) + node T_930 = eq(T_724, UInt<1>("h00")) + node T_931 = mux(T_722, T_930, UInt<1>("h01")) + node T_932 = and(T_931, out.ready) + in[0].ready := T_932 + node T_934 = eq(T_724, UInt<1>("h01")) + node T_935 = mux(T_722, T_934, T_928) + node T_936 = and(T_935, out.ready) + in[1].ready := T_936 + reg T_938 : UInt<2>, clock, reset + onreset T_938 := UInt<2>("h00") + node T_940 = addw(T_938, UInt<1>("h01")) + node T_941 = and(out.ready, out.valid) + when T_941 : + node T_943 = and(UInt<1>("h01"), out.bits.is_builtin_type) + wire T_946 : UInt<3>[1] + T_946[0] := UInt<3>("h03") + node T_949 = eq(T_946[0], out.bits.a_type) + node T_951 = or(UInt<1>("h00"), T_949) + node T_952 = and(T_943, T_951) + when T_952 : + T_938 := T_940 + node T_954 = eq(T_722, UInt<1>("h00")) + when T_954 : + T_722 := UInt<1>("h01") + node T_956 = and(in[0].ready, in[0].valid) + node T_957 = and(in[1].ready, in[1].valid) + wire T_959 : UInt<1>[2] + T_959[0] := T_956 + T_959[1] := T_957 + node T_965 = mux(T_959[0], UInt<1>("h00"), UInt<1>("h01")) + T_724 := T_965 + skip + skip + node T_967 = eq(T_940, UInt<1>("h00")) + when T_967 : + T_722 := UInt<1>("h00") + skip + skip + node choose = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_972 = mux(T_722, T_724, choose) + T_726 := T_972 + + module Arbiter_54 : + output chosen : UInt<1> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}[2] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.way_en := UInt<1>("h00") + out.bits.voluntary := UInt<1>("h00") + out.bits.r_type := UInt<1>("h00") + out.bits.data := UInt<1>("h00") + out.bits.addr_beat := UInt<1>("h00") + out.bits.client_xact_id := UInt<1>("h00") + out.bits.addr_block := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + wire T_724 : UInt<1> + T_724 := UInt<1>("h00") + infer accessor T_726 = in[T_724] + out.valid := T_726.valid + infer accessor T_791 = in[T_724] + out.bits <> T_791.bits + chosen := T_724 + infer accessor T_856 = in[T_724] + T_856.ready := UInt<1>("h00") + node T_924 = or(UInt<1>("h00"), in[0].valid) + node T_926 = eq(T_924, UInt<1>("h00")) + node T_928 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_929 = mux(UInt<1>("h00"), T_928, UInt<1>("h01")) + node T_930 = and(T_929, out.ready) + in[0].ready := T_930 + node T_932 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_933 = mux(UInt<1>("h00"), T_932, T_926) + node T_934 = and(T_933, out.ready) + in[1].ready := T_934 + node T_937 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_938 = mux(UInt<1>("h00"), UInt<1>("h01"), T_937) + T_724 := T_938 + + module Arbiter_55 : + output chosen : UInt<1> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}[2] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.sdq_id := UInt<1>("h00") + out.bits.phys := UInt<1>("h00") + out.bits.kill := UInt<1>("h00") + out.bits.typ := UInt<1>("h00") + out.bits.cmd := UInt<1>("h00") + out.bits.tag := UInt<1>("h00") + out.bits.addr := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + wire T_218 : UInt<1> + T_218 := UInt<1>("h00") + infer accessor T_220 = in[T_218] + out.valid := T_220.valid + infer accessor T_239 = in[T_218] + out.bits <> T_239.bits + chosen := T_218 + infer accessor T_258 = in[T_218] + T_258.ready := UInt<1>("h00") + node T_280 = or(UInt<1>("h00"), in[0].valid) + node T_282 = eq(T_280, UInt<1>("h00")) + node T_284 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_285 = mux(UInt<1>("h00"), T_284, UInt<1>("h01")) + node T_286 = and(T_285, out.ready) + in[0].ready := T_286 + node T_288 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_289 = mux(UInt<1>("h00"), T_288, T_282) + node T_290 = and(T_289, out.ready) + in[1].ready := T_290 + node T_293 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_294 = mux(UInt<1>("h00"), UInt<1>("h01"), T_293) + T_218 := T_294 + + module Arbiter_56 : + output chosen : UInt<1> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[2] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + wire T_64 : UInt<1> + T_64 := UInt<1>("h00") + infer accessor T_66 = in[T_64] + out.valid := T_66.valid + infer accessor T_71 = in[T_64] + out.bits := T_71.bits + chosen := T_64 + infer accessor T_76 = in[T_64] + T_76.ready := UInt<1>("h00") + node T_84 = or(UInt<1>("h00"), in[0].valid) + node T_86 = eq(T_84, UInt<1>("h00")) + node T_88 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_89 = mux(UInt<1>("h00"), T_88, UInt<1>("h01")) + node T_90 = and(T_89, out.ready) + in[0].ready := T_90 + node T_92 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_93 = mux(UInt<1>("h00"), T_92, T_86) + node T_94 = and(T_93, out.ready) + in[1].ready := T_94 + node T_97 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_98 = mux(UInt<1>("h00"), UInt<1>("h01"), T_97) + T_64 := T_98 + + module Queue_57 : + output count : UInt<5> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.sdq_id := UInt<1>("h00") + deq.bits.phys := UInt<1>("h00") + deq.bits.kill := UInt<1>("h00") + deq.bits.typ := UInt<1>("h00") + deq.bits.cmd := UInt<1>("h00") + deq.bits.tag := UInt<1>("h00") + deq.bits.addr := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}[16], clock + reg T_88 : UInt<4>, clock, reset + onreset T_88 := UInt<4>("h00") + reg T_90 : UInt<4>, clock, reset + onreset T_90 := UInt<4>("h00") + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(T_88, T_90) + node T_95 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_95) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_101 = and(enq.ready, enq.valid) + node T_103 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_101, T_103) + node T_105 = and(deq.ready, deq.valid) + node T_107 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_105, T_107) + when do_enq : + infer accessor T_109 = ram[T_88] + T_109 <> enq.bits + node T_118 = eq(T_88, UInt<4>("h0f")) + node T_120 = and(UInt<1>("h00"), T_118) + node T_123 = addw(T_88, UInt<1>("h01")) + node T_124 = mux(T_120, UInt<1>("h00"), T_123) + T_88 := T_124 + skip + when do_deq : + node T_126 = eq(T_90, UInt<4>("h0f")) + node T_128 = and(UInt<1>("h00"), T_126) + node T_131 = addw(T_90, UInt<1>("h01")) + node T_132 = mux(T_128, UInt<1>("h00"), T_131) + T_90 := T_132 + skip + node T_133 = neq(do_enq, do_deq) + when T_133 : + maybe_full := do_enq + skip + node T_135 = eq(empty, UInt<1>("h00")) + node T_137 = and(UInt<1>("h00"), enq.valid) + node T_138 = or(T_135, T_137) + deq.valid := T_138 + node T_140 = eq(full, UInt<1>("h00")) + node T_142 = and(UInt<1>("h00"), deq.ready) + node T_143 = or(T_140, T_142) + enq.ready := T_143 + infer accessor T_144 = ram[T_90] + wire T_160 : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>} + T_160 <> T_144 + when maybe_flow : + T_160 <> enq.bits + skip + deq.bits <> T_160 + node ptr_diff = subw(T_88, T_90) + node T_169 = and(maybe_full, ptr_match) + node T_170 = cat(T_169, ptr_diff) + count := T_170 + + module MSHR : + output probe_rdy : UInt<1> + output wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}} + input mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} + output replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}} + output meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}} + output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}} + output refill : {way_en : UInt<4>, addr : UInt<12>} + output mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} + output tag : UInt<20> + output idx_match : UInt<1> + input req_bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>} + output req_sec_rdy : UInt<1> + input req_sec_val : UInt<1> + output req_pri_rdy : UInt<1> + input req_pri_val : UInt<1> + input clock : Clock + input reset : UInt<1> + + probe_rdy := UInt<1>("h00") + wb_req.bits.way_en := UInt<1>("h00") + wb_req.bits.voluntary := UInt<1>("h00") + wb_req.bits.r_type := UInt<1>("h00") + wb_req.bits.data := UInt<1>("h00") + wb_req.bits.addr_beat := UInt<1>("h00") + wb_req.bits.client_xact_id := UInt<1>("h00") + wb_req.bits.addr_block := UInt<1>("h00") + wb_req.valid := UInt<1>("h00") + replay.bits.sdq_id := UInt<1>("h00") + replay.bits.phys := UInt<1>("h00") + replay.bits.kill := UInt<1>("h00") + replay.bits.typ := UInt<1>("h00") + replay.bits.cmd := UInt<1>("h00") + replay.bits.tag := UInt<1>("h00") + replay.bits.addr := UInt<1>("h00") + replay.valid := UInt<1>("h00") + meta_write.bits.data.coh.state := UInt<1>("h00") + meta_write.bits.data.tag := UInt<1>("h00") + meta_write.bits.way_en := UInt<1>("h00") + meta_write.bits.idx := UInt<1>("h00") + meta_write.valid := UInt<1>("h00") + meta_read.bits.tag := UInt<1>("h00") + meta_read.bits.idx := UInt<1>("h00") + meta_read.valid := UInt<1>("h00") + refill.addr := UInt<1>("h00") + refill.way_en := UInt<1>("h00") + mem_req.bits.union := UInt<1>("h00") + mem_req.bits.a_type := UInt<1>("h00") + mem_req.bits.is_builtin_type := UInt<1>("h00") + mem_req.bits.data := UInt<1>("h00") + mem_req.bits.addr_beat := UInt<1>("h00") + mem_req.bits.client_xact_id := UInt<1>("h00") + mem_req.bits.addr_block := UInt<1>("h00") + mem_req.valid := UInt<1>("h00") + tag := UInt<1>("h00") + idx_match := UInt<1>("h00") + req_sec_rdy := UInt<1>("h00") + req_pri_rdy := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + wire T_657 : {state : UInt<2>} + T_657.state := UInt<1>("h00") + T_657.state := UInt<1>("h00") + reg new_coh_state : {state : UInt<2>}, clock, reset + onreset new_coh_state := T_657 + reg req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clock, reset + node req_idx = bits(req.addr, 11, 6) + node T_783 = bits(req_bits.addr, 11, 6) + node idx_match_1 = eq(req_idx, T_783) + node T_785 = eq(req_bits.cmd, UInt<5>("h01")) + node T_786 = eq(req_bits.cmd, UInt<5>("h07")) + node T_787 = or(T_785, T_786) + node T_788 = bit(req_bits.cmd, 3) + node T_789 = eq(req_bits.cmd, UInt<5>("h04")) + node T_790 = or(T_788, T_789) + node T_791 = or(T_787, T_790) + node T_792 = eq(req_bits.cmd, UInt<5>("h03")) + node T_793 = or(T_791, T_792) + node T_794 = eq(req_bits.cmd, UInt<5>("h06")) + node T_795 = or(T_793, T_794) + node T_796 = eq(req.cmd, UInt<5>("h01")) + node T_797 = eq(req.cmd, UInt<5>("h07")) + node T_798 = or(T_796, T_797) + node T_799 = bit(req.cmd, 3) + node T_800 = eq(req.cmd, UInt<5>("h04")) + node T_801 = or(T_799, T_800) + node T_802 = or(T_798, T_801) + node T_803 = eq(req.cmd, UInt<5>("h03")) + node T_804 = or(T_802, T_803) + node T_805 = eq(req.cmd, UInt<5>("h06")) + node T_806 = or(T_804, T_805) + node T_808 = eq(T_806, UInt<1>("h00")) + node cmd_requires_second_acquire = and(T_795, T_808) + wire states_before_refill : UInt<2>[3] + states_before_refill[0] := UInt<1>("h01") + states_before_refill[1] := UInt<2>("h02") + states_before_refill[2] := UInt<2>("h03") + node T_816 = eq(states_before_refill[0], state) + node T_817 = eq(states_before_refill[1], state) + node T_818 = eq(states_before_refill[2], state) + node T_820 = or(UInt<1>("h00"), T_816) + node T_821 = or(T_820, T_817) + node T_822 = or(T_821, T_818) + wire T_824 : UInt<3>[2] + T_824[0] := UInt<3>("h04") + T_824[1] := UInt<3>("h05") + node T_828 = eq(T_824[0], state) + node T_829 = eq(T_824[1], state) + node T_831 = or(UInt<1>("h00"), T_828) + node T_832 = or(T_831, T_829) + node T_834 = eq(cmd_requires_second_acquire, UInt<1>("h00")) + node T_835 = and(T_832, T_834) + node T_836 = or(T_822, T_835) + node sec_rdy = and(idx_match_1, T_836) + wire T_841 : UInt<3>[1] + T_841[0] := UInt<3>("h05") + node T_844 = eq(T_841[0], mem_grant.bits.g_type) + node T_846 = or(UInt<1>("h00"), T_844) + wire T_848 : UInt<1>[2] + T_848[0] := UInt<1>("h00") + T_848[1] := UInt<1>("h01") + node T_852 = eq(T_848[0], mem_grant.bits.g_type) + node T_853 = eq(T_848[1], mem_grant.bits.g_type) + node T_855 = or(UInt<1>("h00"), T_852) + node T_856 = or(T_855, T_853) + node T_857 = mux(mem_grant.bits.is_builtin_type, T_846, T_856) + node gnt_multi_data = and(UInt<1>("h01"), T_857) + node T_859 = and(mem_grant.valid, gnt_multi_data) + reg refill_cnt : UInt<2>, clock, reset + onreset refill_cnt := UInt<2>("h00") + when T_859 : + node T_863 = eq(refill_cnt, UInt<2>("h03")) + node T_865 = and(UInt<1>("h00"), T_863) + node T_868 = addw(refill_cnt, UInt<1>("h01")) + node T_869 = mux(T_865, UInt<1>("h00"), T_868) + refill_cnt := T_869 + skip + node refill_count_done = and(T_859, T_863) + node T_872 = eq(gnt_multi_data, UInt<1>("h00")) + node T_873 = or(T_872, refill_count_done) + node refill_done = and(mem_grant.valid, T_873) + inst rpq of Queue_57 + rpq.deq.ready := UInt<1>("h00") + rpq.enq.bits.sdq_id := UInt<1>("h00") + rpq.enq.bits.phys := UInt<1>("h00") + rpq.enq.bits.kill := UInt<1>("h00") + rpq.enq.bits.typ := UInt<1>("h00") + rpq.enq.bits.cmd := UInt<1>("h00") + rpq.enq.bits.tag := UInt<1>("h00") + rpq.enq.bits.addr := UInt<1>("h00") + rpq.enq.valid := UInt<1>("h00") + rpq.reset := UInt<1>("h00") + rpq.clock := clock + rpq.reset := reset + node T_893 = and(req_pri_val, req_pri_rdy) + node T_894 = and(req_sec_val, sec_rdy) + node T_895 = or(T_893, T_894) + node T_896 = eq(req_bits.cmd, UInt<5>("h02")) + node T_897 = eq(req_bits.cmd, UInt<5>("h03")) + node T_898 = or(T_896, T_897) + node T_900 = eq(T_898, UInt<1>("h00")) + node T_901 = and(T_895, T_900) + rpq.enq.valid := T_901 + rpq.enq.bits <> req_bits + node T_902 = eq(state, UInt<4>("h08")) + node T_903 = and(replay.ready, T_902) + node T_904 = eq(state, UInt<1>("h00")) + node T_905 = or(T_903, T_904) + rpq.deq.ready := T_905 + node T_906 = eq(req.cmd, UInt<5>("h01")) + node T_907 = eq(req.cmd, UInt<5>("h07")) + node T_908 = or(T_906, T_907) + node T_909 = bit(req.cmd, 3) + node T_910 = eq(req.cmd, UInt<5>("h04")) + node T_911 = or(T_909, T_910) + node T_912 = or(T_908, T_911) + node T_913 = mux(T_912, UInt<2>("h03"), UInt<2>("h02")) + node T_914 = eq(UInt<2>("h02"), mem_grant.bits.g_type) + node T_915 = mux(T_914, UInt<2>("h03"), UInt<1>("h00")) + node T_916 = eq(UInt<1>("h01"), mem_grant.bits.g_type) + node T_917 = mux(T_916, T_913, T_915) + node T_918 = eq(UInt<1>("h00"), mem_grant.bits.g_type) + node T_919 = mux(T_918, UInt<1>("h01"), T_917) + node T_920 = mux(mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_919) + wire coh_on_grant : {state : UInt<2>} + coh_on_grant.state := UInt<1>("h00") + coh_on_grant.state := T_920 + node T_972 = eq(req_bits.cmd, UInt<5>("h01")) + node T_973 = eq(req_bits.cmd, UInt<5>("h07")) + node T_974 = or(T_972, T_973) + node T_975 = bit(req_bits.cmd, 3) + node T_976 = eq(req_bits.cmd, UInt<5>("h04")) + node T_977 = or(T_975, T_976) + node T_978 = or(T_974, T_977) + node T_979 = mux(T_978, UInt<2>("h03"), req_bits.old_meta.coh.state) + wire coh_on_hit : {state : UInt<2>} + coh_on_hit.state := UInt<1>("h00") + coh_on_hit.state := T_979 + node T_1031 = eq(state, UInt<4>("h08")) + node T_1033 = eq(rpq.deq.valid, UInt<1>("h00")) + node T_1034 = and(T_1031, T_1033) + when T_1034 : + state := UInt<1>("h00") + skip + node T_1035 = eq(state, UInt<3>("h07")) + when T_1035 : + state := UInt<4>("h08") + skip + node T_1036 = eq(state, UInt<3>("h06")) + node T_1037 = and(T_1036, meta_write.ready) + when T_1037 : + state := UInt<3>("h07") + skip + node T_1038 = eq(state, UInt<3>("h05")) + when T_1038 : + when mem_grant.valid : + new_coh_state <> coh_on_grant + skip + when refill_done : + state := UInt<3>("h06") + skip + skip + node T_1039 = and(mem_req.ready, mem_req.valid) + when T_1039 : + state := UInt<3>("h05") + skip + node T_1040 = eq(state, UInt<2>("h03")) + node T_1041 = and(T_1040, meta_write.ready) + when T_1041 : + state := UInt<3>("h04") + skip + node T_1042 = eq(state, UInt<2>("h02")) + node T_1043 = and(T_1042, mem_grant.valid) + when T_1043 : + state := UInt<2>("h03") + skip + node T_1044 = and(wb_req.ready, wb_req.valid) + when T_1044 : + node T_1047 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1048 = mux(T_1047, UInt<2>("h02"), UInt<2>("h03")) + state := T_1048 + skip + node T_1049 = and(req_sec_val, req_sec_rdy) + when T_1049 : + when cmd_requires_second_acquire : + req.cmd := req_bits.cmd + skip + skip + node T_1050 = and(req_pri_val, req_pri_rdy) + when T_1050 : + req <> req_bits + when req_bits.tag_match : + node T_1051 = eq(req_bits.cmd, UInt<5>("h01")) + node T_1052 = eq(req_bits.cmd, UInt<5>("h07")) + node T_1053 = or(T_1051, T_1052) + node T_1054 = bit(req_bits.cmd, 3) + node T_1055 = eq(req_bits.cmd, UInt<5>("h04")) + node T_1056 = or(T_1054, T_1055) + node T_1057 = or(T_1053, T_1056) + node T_1058 = eq(req_bits.cmd, UInt<5>("h03")) + node T_1059 = or(T_1057, T_1058) + node T_1060 = eq(req_bits.cmd, UInt<5>("h06")) + node T_1061 = or(T_1059, T_1060) + wire T_1063 : UInt<2>[2] + T_1063[0] := UInt<2>("h02") + T_1063[1] := UInt<2>("h03") + node T_1067 = eq(T_1063[0], req_bits.old_meta.coh.state) + node T_1068 = eq(T_1063[1], req_bits.old_meta.coh.state) + node T_1070 = or(UInt<1>("h00"), T_1067) + node T_1071 = or(T_1070, T_1068) + wire T_1073 : UInt<2>[3] + T_1073[0] := UInt<1>("h01") + T_1073[1] := UInt<2>("h02") + T_1073[2] := UInt<2>("h03") + node T_1078 = eq(T_1073[0], req_bits.old_meta.coh.state) + node T_1079 = eq(T_1073[1], req_bits.old_meta.coh.state) + node T_1080 = eq(T_1073[2], req_bits.old_meta.coh.state) + node T_1082 = or(UInt<1>("h00"), T_1078) + node T_1083 = or(T_1082, T_1079) + node T_1084 = or(T_1083, T_1080) + node T_1085 = mux(T_1061, T_1071, T_1084) + when T_1085 : + state := UInt<3>("h06") + new_coh_state <> coh_on_hit + skip + else : + state := UInt<3>("h04") + skip + skip + else : + wire T_1087 : UInt<2>[1] + T_1087[0] := UInt<2>("h03") + node T_1090 = eq(T_1087[0], req_bits.old_meta.coh.state) + node T_1092 = or(UInt<1>("h00"), T_1090) + node T_1093 = mux(T_1092, UInt<1>("h01"), UInt<2>("h03")) + state := T_1093 + skip + skip + node T_1094 = neq(state, UInt<1>("h00")) + node T_1095 = and(T_1094, idx_match_1) + idx_match := T_1095 + refill.way_en := req.way_en + node T_1096 = cat(req_idx, refill_cnt) + node T_1097 = shl(T_1096, 4) + refill.addr := T_1097 + node T_1098 = shr(req.addr, 12) + tag := T_1098 + node T_1099 = eq(state, UInt<1>("h00")) + req_pri_rdy := T_1099 + node T_1100 = and(sec_rdy, rpq.enq.ready) + req_sec_rdy := T_1100 + reg meta_hazard : UInt<2>, clock, reset + onreset meta_hazard := UInt<2>("h00") + node T_1104 = neq(meta_hazard, UInt<1>("h00")) + when T_1104 : + node T_1106 = addw(meta_hazard, UInt<1>("h01")) + meta_hazard := T_1106 + skip + node T_1107 = and(meta_write.ready, meta_write.valid) + when T_1107 : + meta_hazard := UInt<1>("h01") + skip + node T_1110 = eq(idx_match_1, UInt<1>("h00")) + node T_1111 = eq(states_before_refill[0], state) + node T_1112 = eq(states_before_refill[1], state) + node T_1113 = eq(states_before_refill[2], state) + node T_1115 = or(UInt<1>("h00"), T_1111) + node T_1116 = or(T_1115, T_1112) + node T_1117 = or(T_1116, T_1113) + node T_1119 = eq(T_1117, UInt<1>("h00")) + node T_1121 = eq(meta_hazard, UInt<1>("h00")) + node T_1122 = and(T_1119, T_1121) + node T_1123 = or(T_1110, T_1122) + probe_rdy := T_1123 + node T_1124 = eq(state, UInt<3>("h06")) + node T_1125 = eq(state, UInt<2>("h03")) + node T_1126 = or(T_1124, T_1125) + meta_write.valid := T_1126 + meta_write.bits.idx := req_idx + node T_1127 = eq(state, UInt<2>("h03")) + wire T_1129 : UInt<2>[2] + T_1129[0] := UInt<2>("h02") + T_1129[1] := UInt<2>("h03") + node T_1133 = eq(T_1129[0], req.old_meta.coh.state) + node T_1134 = eq(T_1129[1], req.old_meta.coh.state) + node T_1136 = or(UInt<1>("h00"), T_1133) + node T_1137 = or(T_1136, T_1134) + node T_1138 = mux(T_1137, UInt<1>("h01"), req.old_meta.coh.state) + node T_1139 = eq(req.old_meta.coh.state, UInt<2>("h03")) + node T_1140 = mux(T_1139, UInt<2>("h02"), req.old_meta.coh.state) + node T_1141 = eq(UInt<5>("h013"), UInt<5>("h010")) + node T_1142 = mux(T_1141, T_1140, req.old_meta.coh.state) + node T_1143 = eq(UInt<5>("h011"), UInt<5>("h010")) + node T_1144 = mux(T_1143, T_1138, T_1142) + node T_1145 = eq(UInt<5>("h010"), UInt<5>("h010")) + node T_1146 = mux(T_1145, UInt<1>("h00"), T_1144) + wire T_1172 : {state : UInt<2>} + T_1172.state := UInt<1>("h00") + T_1172.state := T_1146 + wire T_1223 : {state : UInt<2>} + T_1223 <> new_coh_state + when T_1127 : + T_1223 <> T_1172 + skip + meta_write.bits.data.coh <> T_1223 + meta_write.bits.data.tag := tag + meta_write.bits.way_en := req.way_en + node T_1248 = eq(state, UInt<1>("h01")) + wb_req.valid := T_1248 + node T_1250 = cat(req.old_meta.tag, req_idx) + wire T_1255 : UInt<2>[1] + T_1255[0] := UInt<2>("h03") + node T_1258 = eq(T_1255[0], req.old_meta.coh.state) + node T_1260 = or(UInt<1>("h00"), T_1258) + node T_1261 = mux(T_1260, UInt<1>("h00"), UInt<2>("h03")) + node T_1262 = mux(T_1260, UInt<1>("h01"), UInt<3>("h04")) + node T_1263 = mux(T_1260, UInt<2>("h02"), UInt<3>("h05")) + node T_1264 = eq(UInt<5>("h013"), UInt<5>("h010")) + node T_1265 = mux(T_1264, T_1263, UInt<3>("h05")) + node T_1266 = eq(UInt<5>("h011"), UInt<5>("h010")) + node T_1267 = mux(T_1266, T_1262, T_1265) + node T_1268 = eq(UInt<5>("h010"), UInt<5>("h010")) + node T_1269 = mux(T_1268, T_1261, T_1267) + wire T_1300 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>} + T_1300.voluntary := UInt<1>("h00") + T_1300.r_type := UInt<1>("h00") + T_1300.data := UInt<1>("h00") + T_1300.addr_beat := UInt<1>("h00") + T_1300.client_xact_id := UInt<1>("h00") + T_1300.addr_block := UInt<1>("h00") + T_1300.r_type := T_1269 + T_1300.client_xact_id := UInt<1>("h00") + T_1300.addr_block := T_1250 + T_1300.addr_beat := UInt<1>("h00") + T_1300.data := UInt<1>("h00") + T_1300.voluntary := UInt<1>("h01") + wb_req.bits <> T_1300 + wb_req.bits.way_en := req.way_en + node T_1336 = eq(state, UInt<3>("h04")) + mem_req.valid := T_1336 + node T_1337 = cat(tag, req_idx) + node T_1340 = eq(req.cmd, UInt<5>("h01")) + node T_1341 = eq(req.cmd, UInt<5>("h07")) + node T_1342 = or(T_1340, T_1341) + node T_1343 = bit(req.cmd, 3) + node T_1344 = eq(req.cmd, UInt<5>("h04")) + node T_1345 = or(T_1343, T_1344) + node T_1346 = or(T_1342, T_1345) + node T_1347 = eq(req.cmd, UInt<5>("h03")) + node T_1348 = or(T_1346, T_1347) + node T_1349 = eq(req.cmd, UInt<5>("h06")) + node T_1350 = or(T_1348, T_1349) + node T_1351 = mux(T_1350, UInt<1>("h01"), UInt<1>("h00")) + node T_1353 = cat(req.cmd, UInt<1>("h01")) + wire T_1387 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} + T_1387.union := UInt<1>("h00") + T_1387.a_type := UInt<1>("h00") + T_1387.is_builtin_type := UInt<1>("h00") + T_1387.data := UInt<1>("h00") + T_1387.addr_beat := UInt<1>("h00") + T_1387.client_xact_id := UInt<1>("h00") + T_1387.addr_block := UInt<1>("h00") + T_1387.is_builtin_type := UInt<1>("h00") + T_1387.a_type := T_1351 + T_1387.client_xact_id := UInt<1>("h00") + T_1387.addr_block := T_1337 + T_1387.addr_beat := UInt<1>("h00") + T_1387.data := UInt<1>("h00") + T_1387.union := T_1353 + mem_req.bits <> T_1387 + node T_1425 = eq(state, UInt<4>("h08")) + meta_read.valid := T_1425 + meta_read.bits.idx := req_idx + meta_read.bits.tag := tag + node T_1426 = eq(state, UInt<4>("h08")) + node T_1427 = and(T_1426, rpq.deq.valid) + replay.valid := T_1427 + replay.bits <> rpq.deq.bits + replay.bits.phys := UInt<1>("h01") + node T_1429 = bits(rpq.deq.bits.addr, 5, 0) + node T_1430 = cat(req_idx, T_1429) + node T_1431 = cat(tag, T_1430) + replay.bits.addr := T_1431 + node T_1433 = eq(meta_read.ready, UInt<1>("h00")) + when T_1433 : + rpq.deq.ready := UInt<1>("h00") + replay.bits.cmd := UInt<5>("h05") + skip + + module MSHR_58 : + output probe_rdy : UInt<1> + output wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}} + input mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} + output replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}} + output meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}} + output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}} + output refill : {way_en : UInt<4>, addr : UInt<12>} + output mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} + output tag : UInt<20> + output idx_match : UInt<1> + input req_bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>} + output req_sec_rdy : UInt<1> + input req_sec_val : UInt<1> + output req_pri_rdy : UInt<1> + input req_pri_val : UInt<1> + input clock : Clock + input reset : UInt<1> + + probe_rdy := UInt<1>("h00") + wb_req.bits.way_en := UInt<1>("h00") + wb_req.bits.voluntary := UInt<1>("h00") + wb_req.bits.r_type := UInt<1>("h00") + wb_req.bits.data := UInt<1>("h00") + wb_req.bits.addr_beat := UInt<1>("h00") + wb_req.bits.client_xact_id := UInt<1>("h00") + wb_req.bits.addr_block := UInt<1>("h00") + wb_req.valid := UInt<1>("h00") + replay.bits.sdq_id := UInt<1>("h00") + replay.bits.phys := UInt<1>("h00") + replay.bits.kill := UInt<1>("h00") + replay.bits.typ := UInt<1>("h00") + replay.bits.cmd := UInt<1>("h00") + replay.bits.tag := UInt<1>("h00") + replay.bits.addr := UInt<1>("h00") + replay.valid := UInt<1>("h00") + meta_write.bits.data.coh.state := UInt<1>("h00") + meta_write.bits.data.tag := UInt<1>("h00") + meta_write.bits.way_en := UInt<1>("h00") + meta_write.bits.idx := UInt<1>("h00") + meta_write.valid := UInt<1>("h00") + meta_read.bits.tag := UInt<1>("h00") + meta_read.bits.idx := UInt<1>("h00") + meta_read.valid := UInt<1>("h00") + refill.addr := UInt<1>("h00") + refill.way_en := UInt<1>("h00") + mem_req.bits.union := UInt<1>("h00") + mem_req.bits.a_type := UInt<1>("h00") + mem_req.bits.is_builtin_type := UInt<1>("h00") + mem_req.bits.data := UInt<1>("h00") + mem_req.bits.addr_beat := UInt<1>("h00") + mem_req.bits.client_xact_id := UInt<1>("h00") + mem_req.bits.addr_block := UInt<1>("h00") + mem_req.valid := UInt<1>("h00") + tag := UInt<1>("h00") + idx_match := UInt<1>("h00") + req_sec_rdy := UInt<1>("h00") + req_pri_rdy := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + wire T_657 : {state : UInt<2>} + T_657.state := UInt<1>("h00") + T_657.state := UInt<1>("h00") + reg new_coh_state : {state : UInt<2>}, clock, reset + onreset new_coh_state := T_657 + reg req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clock, reset + node req_idx = bits(req.addr, 11, 6) + node T_783 = bits(req_bits.addr, 11, 6) + node idx_match_1 = eq(req_idx, T_783) + node T_785 = eq(req_bits.cmd, UInt<5>("h01")) + node T_786 = eq(req_bits.cmd, UInt<5>("h07")) + node T_787 = or(T_785, T_786) + node T_788 = bit(req_bits.cmd, 3) + node T_789 = eq(req_bits.cmd, UInt<5>("h04")) + node T_790 = or(T_788, T_789) + node T_791 = or(T_787, T_790) + node T_792 = eq(req_bits.cmd, UInt<5>("h03")) + node T_793 = or(T_791, T_792) + node T_794 = eq(req_bits.cmd, UInt<5>("h06")) + node T_795 = or(T_793, T_794) + node T_796 = eq(req.cmd, UInt<5>("h01")) + node T_797 = eq(req.cmd, UInt<5>("h07")) + node T_798 = or(T_796, T_797) + node T_799 = bit(req.cmd, 3) + node T_800 = eq(req.cmd, UInt<5>("h04")) + node T_801 = or(T_799, T_800) + node T_802 = or(T_798, T_801) + node T_803 = eq(req.cmd, UInt<5>("h03")) + node T_804 = or(T_802, T_803) + node T_805 = eq(req.cmd, UInt<5>("h06")) + node T_806 = or(T_804, T_805) + node T_808 = eq(T_806, UInt<1>("h00")) + node cmd_requires_second_acquire = and(T_795, T_808) + wire states_before_refill : UInt<2>[3] + states_before_refill[0] := UInt<1>("h01") + states_before_refill[1] := UInt<2>("h02") + states_before_refill[2] := UInt<2>("h03") + node T_816 = eq(states_before_refill[0], state) + node T_817 = eq(states_before_refill[1], state) + node T_818 = eq(states_before_refill[2], state) + node T_820 = or(UInt<1>("h00"), T_816) + node T_821 = or(T_820, T_817) + node T_822 = or(T_821, T_818) + wire T_824 : UInt<3>[2] + T_824[0] := UInt<3>("h04") + T_824[1] := UInt<3>("h05") + node T_828 = eq(T_824[0], state) + node T_829 = eq(T_824[1], state) + node T_831 = or(UInt<1>("h00"), T_828) + node T_832 = or(T_831, T_829) + node T_834 = eq(cmd_requires_second_acquire, UInt<1>("h00")) + node T_835 = and(T_832, T_834) + node T_836 = or(T_822, T_835) + node sec_rdy = and(idx_match_1, T_836) + wire T_841 : UInt<3>[1] + T_841[0] := UInt<3>("h05") + node T_844 = eq(T_841[0], mem_grant.bits.g_type) + node T_846 = or(UInt<1>("h00"), T_844) + wire T_848 : UInt<1>[2] + T_848[0] := UInt<1>("h00") + T_848[1] := UInt<1>("h01") + node T_852 = eq(T_848[0], mem_grant.bits.g_type) + node T_853 = eq(T_848[1], mem_grant.bits.g_type) + node T_855 = or(UInt<1>("h00"), T_852) + node T_856 = or(T_855, T_853) + node T_857 = mux(mem_grant.bits.is_builtin_type, T_846, T_856) + node gnt_multi_data = and(UInt<1>("h01"), T_857) + node T_859 = and(mem_grant.valid, gnt_multi_data) + reg refill_cnt : UInt<2>, clock, reset + onreset refill_cnt := UInt<2>("h00") + when T_859 : + node T_863 = eq(refill_cnt, UInt<2>("h03")) + node T_865 = and(UInt<1>("h00"), T_863) + node T_868 = addw(refill_cnt, UInt<1>("h01")) + node T_869 = mux(T_865, UInt<1>("h00"), T_868) + refill_cnt := T_869 + skip + node refill_count_done = and(T_859, T_863) + node T_872 = eq(gnt_multi_data, UInt<1>("h00")) + node T_873 = or(T_872, refill_count_done) + node refill_done = and(mem_grant.valid, T_873) + inst rpq of Queue_57 + rpq.deq.ready := UInt<1>("h00") + rpq.enq.bits.sdq_id := UInt<1>("h00") + rpq.enq.bits.phys := UInt<1>("h00") + rpq.enq.bits.kill := UInt<1>("h00") + rpq.enq.bits.typ := UInt<1>("h00") + rpq.enq.bits.cmd := UInt<1>("h00") + rpq.enq.bits.tag := UInt<1>("h00") + rpq.enq.bits.addr := UInt<1>("h00") + rpq.enq.valid := UInt<1>("h00") + rpq.reset := UInt<1>("h00") + rpq.clock := clock + rpq.reset := reset + node T_893 = and(req_pri_val, req_pri_rdy) + node T_894 = and(req_sec_val, sec_rdy) + node T_895 = or(T_893, T_894) + node T_896 = eq(req_bits.cmd, UInt<5>("h02")) + node T_897 = eq(req_bits.cmd, UInt<5>("h03")) + node T_898 = or(T_896, T_897) + node T_900 = eq(T_898, UInt<1>("h00")) + node T_901 = and(T_895, T_900) + rpq.enq.valid := T_901 + rpq.enq.bits <> req_bits + node T_902 = eq(state, UInt<4>("h08")) + node T_903 = and(replay.ready, T_902) + node T_904 = eq(state, UInt<1>("h00")) + node T_905 = or(T_903, T_904) + rpq.deq.ready := T_905 + node T_906 = eq(req.cmd, UInt<5>("h01")) + node T_907 = eq(req.cmd, UInt<5>("h07")) + node T_908 = or(T_906, T_907) + node T_909 = bit(req.cmd, 3) + node T_910 = eq(req.cmd, UInt<5>("h04")) + node T_911 = or(T_909, T_910) + node T_912 = or(T_908, T_911) + node T_913 = mux(T_912, UInt<2>("h03"), UInt<2>("h02")) + node T_914 = eq(UInt<2>("h02"), mem_grant.bits.g_type) + node T_915 = mux(T_914, UInt<2>("h03"), UInt<1>("h00")) + node T_916 = eq(UInt<1>("h01"), mem_grant.bits.g_type) + node T_917 = mux(T_916, T_913, T_915) + node T_918 = eq(UInt<1>("h00"), mem_grant.bits.g_type) + node T_919 = mux(T_918, UInt<1>("h01"), T_917) + node T_920 = mux(mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_919) + wire coh_on_grant : {state : UInt<2>} + coh_on_grant.state := UInt<1>("h00") + coh_on_grant.state := T_920 + node T_972 = eq(req_bits.cmd, UInt<5>("h01")) + node T_973 = eq(req_bits.cmd, UInt<5>("h07")) + node T_974 = or(T_972, T_973) + node T_975 = bit(req_bits.cmd, 3) + node T_976 = eq(req_bits.cmd, UInt<5>("h04")) + node T_977 = or(T_975, T_976) + node T_978 = or(T_974, T_977) + node T_979 = mux(T_978, UInt<2>("h03"), req_bits.old_meta.coh.state) + wire coh_on_hit : {state : UInt<2>} + coh_on_hit.state := UInt<1>("h00") + coh_on_hit.state := T_979 + node T_1031 = eq(state, UInt<4>("h08")) + node T_1033 = eq(rpq.deq.valid, UInt<1>("h00")) + node T_1034 = and(T_1031, T_1033) + when T_1034 : + state := UInt<1>("h00") + skip + node T_1035 = eq(state, UInt<3>("h07")) + when T_1035 : + state := UInt<4>("h08") + skip + node T_1036 = eq(state, UInt<3>("h06")) + node T_1037 = and(T_1036, meta_write.ready) + when T_1037 : + state := UInt<3>("h07") + skip + node T_1038 = eq(state, UInt<3>("h05")) + when T_1038 : + when mem_grant.valid : + new_coh_state <> coh_on_grant + skip + when refill_done : + state := UInt<3>("h06") + skip + skip + node T_1039 = and(mem_req.ready, mem_req.valid) + when T_1039 : + state := UInt<3>("h05") + skip + node T_1040 = eq(state, UInt<2>("h03")) + node T_1041 = and(T_1040, meta_write.ready) + when T_1041 : + state := UInt<3>("h04") + skip + node T_1042 = eq(state, UInt<2>("h02")) + node T_1043 = and(T_1042, mem_grant.valid) + when T_1043 : + state := UInt<2>("h03") + skip + node T_1044 = and(wb_req.ready, wb_req.valid) + when T_1044 : + node T_1047 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1048 = mux(T_1047, UInt<2>("h02"), UInt<2>("h03")) + state := T_1048 + skip + node T_1049 = and(req_sec_val, req_sec_rdy) + when T_1049 : + when cmd_requires_second_acquire : + req.cmd := req_bits.cmd + skip + skip + node T_1050 = and(req_pri_val, req_pri_rdy) + when T_1050 : + req <> req_bits + when req_bits.tag_match : + node T_1051 = eq(req_bits.cmd, UInt<5>("h01")) + node T_1052 = eq(req_bits.cmd, UInt<5>("h07")) + node T_1053 = or(T_1051, T_1052) + node T_1054 = bit(req_bits.cmd, 3) + node T_1055 = eq(req_bits.cmd, UInt<5>("h04")) + node T_1056 = or(T_1054, T_1055) + node T_1057 = or(T_1053, T_1056) + node T_1058 = eq(req_bits.cmd, UInt<5>("h03")) + node T_1059 = or(T_1057, T_1058) + node T_1060 = eq(req_bits.cmd, UInt<5>("h06")) + node T_1061 = or(T_1059, T_1060) + wire T_1063 : UInt<2>[2] + T_1063[0] := UInt<2>("h02") + T_1063[1] := UInt<2>("h03") + node T_1067 = eq(T_1063[0], req_bits.old_meta.coh.state) + node T_1068 = eq(T_1063[1], req_bits.old_meta.coh.state) + node T_1070 = or(UInt<1>("h00"), T_1067) + node T_1071 = or(T_1070, T_1068) + wire T_1073 : UInt<2>[3] + T_1073[0] := UInt<1>("h01") + T_1073[1] := UInt<2>("h02") + T_1073[2] := UInt<2>("h03") + node T_1078 = eq(T_1073[0], req_bits.old_meta.coh.state) + node T_1079 = eq(T_1073[1], req_bits.old_meta.coh.state) + node T_1080 = eq(T_1073[2], req_bits.old_meta.coh.state) + node T_1082 = or(UInt<1>("h00"), T_1078) + node T_1083 = or(T_1082, T_1079) + node T_1084 = or(T_1083, T_1080) + node T_1085 = mux(T_1061, T_1071, T_1084) + when T_1085 : + state := UInt<3>("h06") + new_coh_state <> coh_on_hit + skip + else : + state := UInt<3>("h04") + skip + skip + else : + wire T_1087 : UInt<2>[1] + T_1087[0] := UInt<2>("h03") + node T_1090 = eq(T_1087[0], req_bits.old_meta.coh.state) + node T_1092 = or(UInt<1>("h00"), T_1090) + node T_1093 = mux(T_1092, UInt<1>("h01"), UInt<2>("h03")) + state := T_1093 + skip + skip + node T_1094 = neq(state, UInt<1>("h00")) + node T_1095 = and(T_1094, idx_match_1) + idx_match := T_1095 + refill.way_en := req.way_en + node T_1096 = cat(req_idx, refill_cnt) + node T_1097 = shl(T_1096, 4) + refill.addr := T_1097 + node T_1098 = shr(req.addr, 12) + tag := T_1098 + node T_1099 = eq(state, UInt<1>("h00")) + req_pri_rdy := T_1099 + node T_1100 = and(sec_rdy, rpq.enq.ready) + req_sec_rdy := T_1100 + reg meta_hazard : UInt<2>, clock, reset + onreset meta_hazard := UInt<2>("h00") + node T_1104 = neq(meta_hazard, UInt<1>("h00")) + when T_1104 : + node T_1106 = addw(meta_hazard, UInt<1>("h01")) + meta_hazard := T_1106 + skip + node T_1107 = and(meta_write.ready, meta_write.valid) + when T_1107 : + meta_hazard := UInt<1>("h01") + skip + node T_1110 = eq(idx_match_1, UInt<1>("h00")) + node T_1111 = eq(states_before_refill[0], state) + node T_1112 = eq(states_before_refill[1], state) + node T_1113 = eq(states_before_refill[2], state) + node T_1115 = or(UInt<1>("h00"), T_1111) + node T_1116 = or(T_1115, T_1112) + node T_1117 = or(T_1116, T_1113) + node T_1119 = eq(T_1117, UInt<1>("h00")) + node T_1121 = eq(meta_hazard, UInt<1>("h00")) + node T_1122 = and(T_1119, T_1121) + node T_1123 = or(T_1110, T_1122) + probe_rdy := T_1123 + node T_1124 = eq(state, UInt<3>("h06")) + node T_1125 = eq(state, UInt<2>("h03")) + node T_1126 = or(T_1124, T_1125) + meta_write.valid := T_1126 + meta_write.bits.idx := req_idx + node T_1127 = eq(state, UInt<2>("h03")) + wire T_1129 : UInt<2>[2] + T_1129[0] := UInt<2>("h02") + T_1129[1] := UInt<2>("h03") + node T_1133 = eq(T_1129[0], req.old_meta.coh.state) + node T_1134 = eq(T_1129[1], req.old_meta.coh.state) + node T_1136 = or(UInt<1>("h00"), T_1133) + node T_1137 = or(T_1136, T_1134) + node T_1138 = mux(T_1137, UInt<1>("h01"), req.old_meta.coh.state) + node T_1139 = eq(req.old_meta.coh.state, UInt<2>("h03")) + node T_1140 = mux(T_1139, UInt<2>("h02"), req.old_meta.coh.state) + node T_1141 = eq(UInt<5>("h013"), UInt<5>("h010")) + node T_1142 = mux(T_1141, T_1140, req.old_meta.coh.state) + node T_1143 = eq(UInt<5>("h011"), UInt<5>("h010")) + node T_1144 = mux(T_1143, T_1138, T_1142) + node T_1145 = eq(UInt<5>("h010"), UInt<5>("h010")) + node T_1146 = mux(T_1145, UInt<1>("h00"), T_1144) + wire T_1172 : {state : UInt<2>} + T_1172.state := UInt<1>("h00") + T_1172.state := T_1146 + wire T_1223 : {state : UInt<2>} + T_1223 <> new_coh_state + when T_1127 : + T_1223 <> T_1172 + skip + meta_write.bits.data.coh <> T_1223 + meta_write.bits.data.tag := tag + meta_write.bits.way_en := req.way_en + node T_1248 = eq(state, UInt<1>("h01")) + wb_req.valid := T_1248 + node T_1250 = cat(req.old_meta.tag, req_idx) + wire T_1255 : UInt<2>[1] + T_1255[0] := UInt<2>("h03") + node T_1258 = eq(T_1255[0], req.old_meta.coh.state) + node T_1260 = or(UInt<1>("h00"), T_1258) + node T_1261 = mux(T_1260, UInt<1>("h00"), UInt<2>("h03")) + node T_1262 = mux(T_1260, UInt<1>("h01"), UInt<3>("h04")) + node T_1263 = mux(T_1260, UInt<2>("h02"), UInt<3>("h05")) + node T_1264 = eq(UInt<5>("h013"), UInt<5>("h010")) + node T_1265 = mux(T_1264, T_1263, UInt<3>("h05")) + node T_1266 = eq(UInt<5>("h011"), UInt<5>("h010")) + node T_1267 = mux(T_1266, T_1262, T_1265) + node T_1268 = eq(UInt<5>("h010"), UInt<5>("h010")) + node T_1269 = mux(T_1268, T_1261, T_1267) + wire T_1300 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>} + T_1300.voluntary := UInt<1>("h00") + T_1300.r_type := UInt<1>("h00") + T_1300.data := UInt<1>("h00") + T_1300.addr_beat := UInt<1>("h00") + T_1300.client_xact_id := UInt<1>("h00") + T_1300.addr_block := UInt<1>("h00") + T_1300.r_type := T_1269 + T_1300.client_xact_id := UInt<1>("h01") + T_1300.addr_block := T_1250 + T_1300.addr_beat := UInt<1>("h00") + T_1300.data := UInt<1>("h00") + T_1300.voluntary := UInt<1>("h01") + wb_req.bits <> T_1300 + wb_req.bits.way_en := req.way_en + node T_1336 = eq(state, UInt<3>("h04")) + mem_req.valid := T_1336 + node T_1337 = cat(tag, req_idx) + node T_1340 = eq(req.cmd, UInt<5>("h01")) + node T_1341 = eq(req.cmd, UInt<5>("h07")) + node T_1342 = or(T_1340, T_1341) + node T_1343 = bit(req.cmd, 3) + node T_1344 = eq(req.cmd, UInt<5>("h04")) + node T_1345 = or(T_1343, T_1344) + node T_1346 = or(T_1342, T_1345) + node T_1347 = eq(req.cmd, UInt<5>("h03")) + node T_1348 = or(T_1346, T_1347) + node T_1349 = eq(req.cmd, UInt<5>("h06")) + node T_1350 = or(T_1348, T_1349) + node T_1351 = mux(T_1350, UInt<1>("h01"), UInt<1>("h00")) + node T_1353 = cat(req.cmd, UInt<1>("h01")) + wire T_1387 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>} + T_1387.union := UInt<1>("h00") + T_1387.a_type := UInt<1>("h00") + T_1387.is_builtin_type := UInt<1>("h00") + T_1387.data := UInt<1>("h00") + T_1387.addr_beat := UInt<1>("h00") + T_1387.client_xact_id := UInt<1>("h00") + T_1387.addr_block := UInt<1>("h00") + T_1387.is_builtin_type := UInt<1>("h00") + T_1387.a_type := T_1351 + T_1387.client_xact_id := UInt<1>("h01") + T_1387.addr_block := T_1337 + T_1387.addr_beat := UInt<1>("h00") + T_1387.data := UInt<1>("h00") + T_1387.union := T_1353 + mem_req.bits <> T_1387 + node T_1425 = eq(state, UInt<4>("h08")) + meta_read.valid := T_1425 + meta_read.bits.idx := req_idx + meta_read.bits.tag := tag + node T_1426 = eq(state, UInt<4>("h08")) + node T_1427 = and(T_1426, rpq.deq.valid) + replay.valid := T_1427 + replay.bits <> rpq.deq.bits + replay.bits.phys := UInt<1>("h01") + node T_1429 = bits(rpq.deq.bits.addr, 5, 0) + node T_1430 = cat(req_idx, T_1429) + node T_1431 = cat(tag, T_1430) + replay.bits.addr := T_1431 + node T_1433 = eq(meta_read.ready, UInt<1>("h00")) + when T_1433 : + rpq.deq.ready := UInt<1>("h00") + replay.bits.cmd := UInt<5>("h05") + skip + + module MSHRFile : + output fence_rdy : UInt<1> + output probe_rdy : UInt<1> + output wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}} + input mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}} + output replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}} + output meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}} + output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}} + output refill : {way_en : UInt<4>, addr : UInt<12>} + output mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}} + output secondary_miss : UInt<1> + input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}} + input clock : Clock + input reset : UInt<1> + + fence_rdy := UInt<1>("h00") + probe_rdy := UInt<1>("h00") + wb_req.bits.way_en := UInt<1>("h00") + wb_req.bits.voluntary := UInt<1>("h00") + wb_req.bits.r_type := UInt<1>("h00") + wb_req.bits.data := UInt<1>("h00") + wb_req.bits.addr_beat := UInt<1>("h00") + wb_req.bits.client_xact_id := UInt<1>("h00") + wb_req.bits.addr_block := UInt<1>("h00") + wb_req.valid := UInt<1>("h00") + replay.bits.data := UInt<1>("h00") + replay.bits.phys := UInt<1>("h00") + replay.bits.kill := UInt<1>("h00") + replay.bits.typ := UInt<1>("h00") + replay.bits.cmd := UInt<1>("h00") + replay.bits.tag := UInt<1>("h00") + replay.bits.addr := UInt<1>("h00") + replay.valid := UInt<1>("h00") + meta_write.bits.data.coh.state := UInt<1>("h00") + meta_write.bits.data.tag := UInt<1>("h00") + meta_write.bits.way_en := UInt<1>("h00") + meta_write.bits.idx := UInt<1>("h00") + meta_write.valid := UInt<1>("h00") + meta_read.bits.tag := UInt<1>("h00") + meta_read.bits.idx := UInt<1>("h00") + meta_read.valid := UInt<1>("h00") + refill.addr := UInt<1>("h00") + refill.way_en := UInt<1>("h00") + mem_req.bits.union := UInt<1>("h00") + mem_req.bits.a_type := UInt<1>("h00") + mem_req.bits.is_builtin_type := UInt<1>("h00") + mem_req.bits.data := UInt<1>("h00") + mem_req.bits.addr_beat := UInt<1>("h00") + mem_req.bits.client_xact_id := UInt<1>("h00") + mem_req.bits.addr_block := UInt<1>("h00") + mem_req.valid := UInt<1>("h00") + secondary_miss := UInt<1>("h00") + req.ready := UInt<1>("h00") + reg sdq_val : UInt<17>, clock, reset + onreset sdq_val := UInt<17>("h00") + node T_710 = bits(sdq_val, 16, 0) + node T_711 = not(T_710) + node T_712 = bit(T_711, 0) + node T_713 = bit(T_711, 1) + node T_714 = bit(T_711, 2) + node T_715 = bit(T_711, 3) + node T_716 = bit(T_711, 4) + node T_717 = bit(T_711, 5) + node T_718 = bit(T_711, 6) + node T_719 = bit(T_711, 7) + node T_720 = bit(T_711, 8) + node T_721 = bit(T_711, 9) + node T_722 = bit(T_711, 10) + node T_723 = bit(T_711, 11) + node T_724 = bit(T_711, 12) + node T_725 = bit(T_711, 13) + node T_726 = bit(T_711, 14) + node T_727 = bit(T_711, 15) + node T_728 = bit(T_711, 16) + wire T_730 : UInt<1>[17] + T_730[0] := T_712 + T_730[1] := T_713 + T_730[2] := T_714 + T_730[3] := T_715 + T_730[4] := T_716 + T_730[5] := T_717 + T_730[6] := T_718 + T_730[7] := T_719 + T_730[8] := T_720 + T_730[9] := T_721 + T_730[10] := T_722 + T_730[11] := T_723 + T_730[12] := T_724 + T_730[13] := T_725 + T_730[14] := T_726 + T_730[15] := T_727 + T_730[16] := T_728 + node T_766 = mux(T_730[15], UInt<4>("h0f"), UInt<5>("h010")) + node T_767 = mux(T_730[14], UInt<4>("h0e"), T_766) + node T_768 = mux(T_730[13], UInt<4>("h0d"), T_767) + node T_769 = mux(T_730[12], UInt<4>("h0c"), T_768) + node T_770 = mux(T_730[11], UInt<4>("h0b"), T_769) + node T_771 = mux(T_730[10], UInt<4>("h0a"), T_770) + node T_772 = mux(T_730[9], UInt<4>("h09"), T_771) + node T_773 = mux(T_730[8], UInt<4>("h08"), T_772) + node T_774 = mux(T_730[7], UInt<3>("h07"), T_773) + node T_775 = mux(T_730[6], UInt<3>("h06"), T_774) + node T_776 = mux(T_730[5], UInt<3>("h05"), T_775) + node T_777 = mux(T_730[4], UInt<3>("h04"), T_776) + node T_778 = mux(T_730[3], UInt<2>("h03"), T_777) + node T_779 = mux(T_730[2], UInt<2>("h02"), T_778) + node T_780 = mux(T_730[1], UInt<1>("h01"), T_779) + node sdq_alloc_id = mux(T_730[0], UInt<1>("h00"), T_780) + node T_782 = not(sdq_val) + node T_784 = eq(T_782, UInt<1>("h00")) + node sdq_rdy = eq(T_784, UInt<1>("h00")) + node T_787 = and(req.valid, req.ready) + node T_788 = eq(req.bits.cmd, UInt<5>("h01")) + node T_789 = eq(req.bits.cmd, UInt<5>("h07")) + node T_790 = or(T_788, T_789) + node T_791 = bit(req.bits.cmd, 3) + node T_792 = eq(req.bits.cmd, UInt<5>("h04")) + node T_793 = or(T_791, T_792) + node T_794 = or(T_790, T_793) + node sdq_enq = and(T_787, T_794) + cmem sdq : UInt<64>[17], clock + when sdq_enq : + infer accessor T_798 = sdq[sdq_alloc_id] + T_798 := req.bits.data + skip + wire idxMatch : UInt<1>[2] + idxMatch[0] := UInt<1>("h00") + idxMatch[1] := UInt<1>("h00") + wire tagList : UInt<20>[2] + tagList[0] := UInt<1>("h00") + tagList[1] := UInt<1>("h00") + node T_828 = mux(idxMatch[0], tagList[0], UInt<1>("h00")) + node T_830 = mux(idxMatch[1], tagList[1], UInt<1>("h00")) + node T_832 = or(T_828, T_830) + wire T_833 : UInt<20> + T_833 := UInt<1>("h00") + T_833 := T_832 + node T_835 = shr(req.bits.addr, 12) + node tag_match = eq(T_833, T_835) + wire wbTagList : UInt<?>[2] + wbTagList[0] := UInt<1>("h00") + wbTagList[1] := UInt<1>("h00") + wire refillMux : {way_en : UInt<4>, addr : UInt<12>}[2] + refillMux[0].addr := UInt<1>("h00") + refillMux[0].way_en := UInt<1>("h00") + refillMux[1].addr := UInt<1>("h00") + refillMux[1].way_en := UInt<1>("h00") + inst meta_read_arb of Arbiter_52 + meta_read_arb.out.ready := UInt<1>("h00") + meta_read_arb.in[0].bits.tag := UInt<1>("h00") + meta_read_arb.in[0].bits.idx := UInt<1>("h00") + meta_read_arb.in[0].valid := UInt<1>("h00") + meta_read_arb.in[1].bits.tag := UInt<1>("h00") + meta_read_arb.in[1].bits.idx := UInt<1>("h00") + meta_read_arb.in[1].valid := UInt<1>("h00") + meta_read_arb.reset := UInt<1>("h00") + meta_read_arb.clock := clock + meta_read_arb.reset := reset + inst meta_write_arb of Arbiter_53 + meta_write_arb.out.ready := UInt<1>("h00") + meta_write_arb.in[0].bits.data.coh.state := UInt<1>("h00") + meta_write_arb.in[0].bits.data.tag := UInt<1>("h00") + meta_write_arb.in[0].bits.way_en := UInt<1>("h00") + meta_write_arb.in[0].bits.idx := UInt<1>("h00") + meta_write_arb.in[0].valid := UInt<1>("h00") + meta_write_arb.in[1].bits.data.coh.state := UInt<1>("h00") + meta_write_arb.in[1].bits.data.tag := UInt<1>("h00") + meta_write_arb.in[1].bits.way_en := UInt<1>("h00") + meta_write_arb.in[1].bits.idx := UInt<1>("h00") + meta_write_arb.in[1].valid := UInt<1>("h00") + meta_write_arb.reset := UInt<1>("h00") + meta_write_arb.clock := clock + meta_write_arb.reset := reset + inst mem_req_arb of LockingArbiter + mem_req_arb.out.ready := UInt<1>("h00") + mem_req_arb.in[0].bits.union := UInt<1>("h00") + mem_req_arb.in[0].bits.a_type := UInt<1>("h00") + mem_req_arb.in[0].bits.is_builtin_type := UInt<1>("h00") + mem_req_arb.in[0].bits.data := UInt<1>("h00") + mem_req_arb.in[0].bits.addr_beat := UInt<1>("h00") + mem_req_arb.in[0].bits.client_xact_id := UInt<1>("h00") + mem_req_arb.in[0].bits.addr_block := UInt<1>("h00") + mem_req_arb.in[0].valid := UInt<1>("h00") + mem_req_arb.in[1].bits.union := UInt<1>("h00") + mem_req_arb.in[1].bits.a_type := UInt<1>("h00") + mem_req_arb.in[1].bits.is_builtin_type := UInt<1>("h00") + mem_req_arb.in[1].bits.data := UInt<1>("h00") + mem_req_arb.in[1].bits.addr_beat := UInt<1>("h00") + mem_req_arb.in[1].bits.client_xact_id := UInt<1>("h00") + mem_req_arb.in[1].bits.addr_block := UInt<1>("h00") + mem_req_arb.in[1].valid := UInt<1>("h00") + mem_req_arb.reset := UInt<1>("h00") + mem_req_arb.clock := clock + mem_req_arb.reset := reset + inst wb_req_arb of Arbiter_54 + wb_req_arb.out.ready := UInt<1>("h00") + wb_req_arb.in[0].bits.way_en := UInt<1>("h00") + wb_req_arb.in[0].bits.voluntary := UInt<1>("h00") + wb_req_arb.in[0].bits.r_type := UInt<1>("h00") + wb_req_arb.in[0].bits.data := UInt<1>("h00") + wb_req_arb.in[0].bits.addr_beat := UInt<1>("h00") + wb_req_arb.in[0].bits.client_xact_id := UInt<1>("h00") + wb_req_arb.in[0].bits.addr_block := UInt<1>("h00") + wb_req_arb.in[0].valid := UInt<1>("h00") + wb_req_arb.in[1].bits.way_en := UInt<1>("h00") + wb_req_arb.in[1].bits.voluntary := UInt<1>("h00") + wb_req_arb.in[1].bits.r_type := UInt<1>("h00") + wb_req_arb.in[1].bits.data := UInt<1>("h00") + wb_req_arb.in[1].bits.addr_beat := UInt<1>("h00") + wb_req_arb.in[1].bits.client_xact_id := UInt<1>("h00") + wb_req_arb.in[1].bits.addr_block := UInt<1>("h00") + wb_req_arb.in[1].valid := UInt<1>("h00") + wb_req_arb.reset := UInt<1>("h00") + wb_req_arb.clock := clock + wb_req_arb.reset := reset + inst replay_arb of Arbiter_55 + replay_arb.out.ready := UInt<1>("h00") + replay_arb.in[0].bits.sdq_id := UInt<1>("h00") + replay_arb.in[0].bits.phys := UInt<1>("h00") + replay_arb.in[0].bits.kill := UInt<1>("h00") + replay_arb.in[0].bits.typ := UInt<1>("h00") + replay_arb.in[0].bits.cmd := UInt<1>("h00") + replay_arb.in[0].bits.tag := UInt<1>("h00") + replay_arb.in[0].bits.addr := UInt<1>("h00") + replay_arb.in[0].valid := UInt<1>("h00") + replay_arb.in[1].bits.sdq_id := UInt<1>("h00") + replay_arb.in[1].bits.phys := UInt<1>("h00") + replay_arb.in[1].bits.kill := UInt<1>("h00") + replay_arb.in[1].bits.typ := UInt<1>("h00") + replay_arb.in[1].bits.cmd := UInt<1>("h00") + replay_arb.in[1].bits.tag := UInt<1>("h00") + replay_arb.in[1].bits.addr := UInt<1>("h00") + replay_arb.in[1].valid := UInt<1>("h00") + replay_arb.reset := UInt<1>("h00") + replay_arb.clock := clock + replay_arb.reset := reset + inst alloc_arb of Arbiter_56 + alloc_arb.out.ready := UInt<1>("h00") + alloc_arb.in[0].bits := UInt<1>("h00") + alloc_arb.in[0].valid := UInt<1>("h00") + alloc_arb.in[1].bits := UInt<1>("h00") + alloc_arb.in[1].valid := UInt<1>("h00") + alloc_arb.reset := UInt<1>("h00") + alloc_arb.clock := clock + alloc_arb.reset := reset + fence_rdy := UInt<1>("h01") + probe_rdy := UInt<1>("h01") + inst T_1299 of MSHR + T_1299.wb_req.ready := UInt<1>("h00") + T_1299.mem_grant.bits.g_type := UInt<1>("h00") + T_1299.mem_grant.bits.is_builtin_type := UInt<1>("h00") + T_1299.mem_grant.bits.manager_xact_id := UInt<1>("h00") + T_1299.mem_grant.bits.client_xact_id := UInt<1>("h00") + T_1299.mem_grant.bits.data := UInt<1>("h00") + T_1299.mem_grant.bits.addr_beat := UInt<1>("h00") + T_1299.mem_grant.valid := UInt<1>("h00") + T_1299.replay.ready := UInt<1>("h00") + T_1299.meta_write.ready := UInt<1>("h00") + T_1299.meta_read.ready := UInt<1>("h00") + T_1299.mem_req.ready := UInt<1>("h00") + T_1299.req_bits.way_en := UInt<1>("h00") + T_1299.req_bits.old_meta.coh.state := UInt<1>("h00") + T_1299.req_bits.old_meta.tag := UInt<1>("h00") + T_1299.req_bits.tag_match := UInt<1>("h00") + T_1299.req_bits.sdq_id := UInt<1>("h00") + T_1299.req_bits.phys := UInt<1>("h00") + T_1299.req_bits.kill := UInt<1>("h00") + T_1299.req_bits.typ := UInt<1>("h00") + T_1299.req_bits.cmd := UInt<1>("h00") + T_1299.req_bits.tag := UInt<1>("h00") + T_1299.req_bits.addr := UInt<1>("h00") + T_1299.req_sec_val := UInt<1>("h00") + T_1299.req_pri_val := UInt<1>("h00") + T_1299.reset := UInt<1>("h00") + T_1299.clock := clock + T_1299.reset := reset + idxMatch[0] := T_1299.idx_match + tagList[0] := T_1299.tag + node T_1129 = shr(T_1299.wb_req.bits.addr_block, 6) + wbTagList[0] := T_1129 + alloc_arb.in[0].valid := T_1299.req_pri_rdy + T_1299.req_pri_val := alloc_arb.in[0].ready + node T_1130 = and(req.valid, sdq_rdy) + node T_1131 = and(T_1130, tag_match) + T_1299.req_sec_val := T_1131 + T_1299.req_bits <> req.bits + T_1299.req_bits.sdq_id := sdq_alloc_id + meta_read_arb.in[0] <> T_1299.meta_read + meta_write_arb.in[0] <> T_1299.meta_write + mem_req_arb.in[0] <> T_1299.mem_req + wb_req_arb.in[0] <> T_1299.wb_req + replay_arb.in[0] <> T_1299.replay + node T_1133 = eq(mem_grant.bits.client_xact_id, UInt<1>("h00")) + node T_1134 = and(mem_grant.valid, T_1133) + T_1299.mem_grant.valid := T_1134 + T_1299.mem_grant.bits <> mem_grant.bits + refillMux[0] <> T_1299.refill + node T_1135 = or(UInt<1>("h00"), T_1299.req_pri_rdy) + node T_1136 = or(UInt<1>("h00"), T_1299.req_sec_rdy) + node T_1137 = or(UInt<1>("h00"), T_1299.idx_match) + node T_1139 = eq(T_1299.req_pri_rdy, UInt<1>("h00")) + when T_1139 : + fence_rdy := UInt<1>("h00") + skip + node T_1142 = eq(T_1299.probe_rdy, UInt<1>("h00")) + when T_1142 : + probe_rdy := UInt<1>("h00") + skip + inst T_1300 of MSHR_58 + T_1300.wb_req.ready := UInt<1>("h00") + T_1300.mem_grant.bits.g_type := UInt<1>("h00") + T_1300.mem_grant.bits.is_builtin_type := UInt<1>("h00") + T_1300.mem_grant.bits.manager_xact_id := UInt<1>("h00") + T_1300.mem_grant.bits.client_xact_id := UInt<1>("h00") + T_1300.mem_grant.bits.data := UInt<1>("h00") + T_1300.mem_grant.bits.addr_beat := UInt<1>("h00") + T_1300.mem_grant.valid := UInt<1>("h00") + T_1300.replay.ready := UInt<1>("h00") + T_1300.meta_write.ready := UInt<1>("h00") + T_1300.meta_read.ready := UInt<1>("h00") + T_1300.mem_req.ready := UInt<1>("h00") + T_1300.req_bits.way_en := UInt<1>("h00") + T_1300.req_bits.old_meta.coh.state := UInt<1>("h00") + T_1300.req_bits.old_meta.tag := UInt<1>("h00") + T_1300.req_bits.tag_match := UInt<1>("h00") + T_1300.req_bits.sdq_id := UInt<1>("h00") + T_1300.req_bits.phys := UInt<1>("h00") + T_1300.req_bits.kill := UInt<1>("h00") + T_1300.req_bits.typ := UInt<1>("h00") + T_1300.req_bits.cmd := UInt<1>("h00") + T_1300.req_bits.tag := UInt<1>("h00") + T_1300.req_bits.addr := UInt<1>("h00") + T_1300.req_sec_val := UInt<1>("h00") + T_1300.req_pri_val := UInt<1>("h00") + T_1300.reset := UInt<1>("h00") + T_1300.clock := clock + T_1300.reset := reset + idxMatch[1] := T_1300.idx_match + tagList[1] := T_1300.tag + node T_1170 = shr(T_1300.wb_req.bits.addr_block, 6) + wbTagList[1] := T_1170 + alloc_arb.in[1].valid := T_1300.req_pri_rdy + T_1300.req_pri_val := alloc_arb.in[1].ready + node T_1171 = and(req.valid, sdq_rdy) + node T_1172 = and(T_1171, tag_match) + T_1300.req_sec_val := T_1172 + T_1300.req_bits <> req.bits + T_1300.req_bits.sdq_id := sdq_alloc_id + meta_read_arb.in[1] <> T_1300.meta_read + meta_write_arb.in[1] <> T_1300.meta_write + mem_req_arb.in[1] <> T_1300.mem_req + wb_req_arb.in[1] <> T_1300.wb_req + replay_arb.in[1] <> T_1300.replay + node T_1174 = eq(mem_grant.bits.client_xact_id, UInt<1>("h01")) + node T_1175 = and(mem_grant.valid, T_1174) + T_1300.mem_grant.valid := T_1175 + T_1300.mem_grant.bits <> mem_grant.bits + refillMux[1] <> T_1300.refill + node pri_rdy = or(T_1135, T_1300.req_pri_rdy) + node sec_rdy = or(T_1136, T_1300.req_sec_rdy) + node idx_match = or(T_1137, T_1300.idx_match) + node T_1180 = eq(T_1300.req_pri_rdy, UInt<1>("h00")) + when T_1180 : + fence_rdy := UInt<1>("h00") + skip + node T_1183 = eq(T_1300.probe_rdy, UInt<1>("h00")) + when T_1183 : + probe_rdy := UInt<1>("h00") + skip + node T_1185 = and(req.valid, sdq_rdy) + node T_1187 = eq(idx_match, UInt<1>("h00")) + node T_1188 = and(T_1185, T_1187) + alloc_arb.out.ready := T_1188 + meta_read <> meta_read_arb.out + meta_write <> meta_write_arb.out + mem_req <> mem_req_arb.out + wb_req <> wb_req_arb.out + node T_1189 = and(tag_match, sec_rdy) + node T_1190 = mux(idx_match, T_1189, pri_rdy) + node T_1191 = and(T_1190, sdq_rdy) + req.ready := T_1191 + secondary_miss := idx_match + infer accessor T_1192 = refillMux[mem_grant.bits.client_xact_id] + refill <> T_1192 + node T_1195 = and(replay.ready, replay.valid) + node T_1196 = eq(replay.bits.cmd, UInt<5>("h01")) + node T_1197 = eq(replay.bits.cmd, UInt<5>("h07")) + node T_1198 = or(T_1196, T_1197) + node T_1199 = bit(replay.bits.cmd, 3) + node T_1200 = eq(replay.bits.cmd, UInt<5>("h04")) + node T_1201 = or(T_1199, T_1200) + node T_1202 = or(T_1198, T_1201) + node free_sdq = and(T_1195, T_1202) + reg T_1204 : UInt<5>, clock, reset + when free_sdq : + T_1204 := replay_arb.out.bits.sdq_id + skip + infer accessor T_1205 = sdq[T_1204] + replay.bits.data := T_1205 + replay <> replay_arb.out + node T_1206 = or(replay.valid, sdq_enq) + when T_1206 : + node T_1208 = dshl(UInt<1>("h01"), replay_arb.out.bits.sdq_id) + node T_1210 = subw(UInt<17>("h00"), free_sdq) + node T_1211 = and(T_1208, T_1210) + node T_1212 = not(T_1211) + node T_1213 = and(sdq_val, T_1212) + node T_1214 = bits(sdq_val, 16, 0) + node T_1215 = not(T_1214) + node T_1216 = bit(T_1215, 0) + node T_1217 = bit(T_1215, 1) + node T_1218 = bit(T_1215, 2) + node T_1219 = bit(T_1215, 3) + node T_1220 = bit(T_1215, 4) + node T_1221 = bit(T_1215, 5) + node T_1222 = bit(T_1215, 6) + node T_1223 = bit(T_1215, 7) + node T_1224 = bit(T_1215, 8) + node T_1225 = bit(T_1215, 9) + node T_1226 = bit(T_1215, 10) + node T_1227 = bit(T_1215, 11) + node T_1228 = bit(T_1215, 12) + node T_1229 = bit(T_1215, 13) + node T_1230 = bit(T_1215, 14) + node T_1231 = bit(T_1215, 15) + node T_1232 = bit(T_1215, 16) + wire T_1251 : UInt<17>[17] + T_1251[0] := UInt<17>("h01") + T_1251[1] := UInt<17>("h02") + T_1251[2] := UInt<17>("h04") + T_1251[3] := UInt<17>("h08") + T_1251[4] := UInt<17>("h010") + T_1251[5] := UInt<17>("h020") + T_1251[6] := UInt<17>("h040") + T_1251[7] := UInt<17>("h080") + T_1251[8] := UInt<17>("h0100") + T_1251[9] := UInt<17>("h0200") + T_1251[10] := UInt<17>("h0400") + T_1251[11] := UInt<17>("h0800") + T_1251[12] := UInt<17>("h01000") + T_1251[13] := UInt<17>("h02000") + T_1251[14] := UInt<17>("h04000") + T_1251[15] := UInt<17>("h08000") + T_1251[16] := UInt<17>("h010000") + node T_1272 = mux(T_1232, T_1251[16], UInt<17>("h00")) + node T_1273 = mux(T_1231, T_1251[15], T_1272) + node T_1274 = mux(T_1230, T_1251[14], T_1273) + node T_1275 = mux(T_1229, T_1251[13], T_1274) + node T_1276 = mux(T_1228, T_1251[12], T_1275) + node T_1277 = mux(T_1227, T_1251[11], T_1276) + node T_1278 = mux(T_1226, T_1251[10], T_1277) + node T_1279 = mux(T_1225, T_1251[9], T_1278) + node T_1280 = mux(T_1224, T_1251[8], T_1279) + node T_1281 = mux(T_1223, T_1251[7], T_1280) + node T_1282 = mux(T_1222, T_1251[6], T_1281) + node T_1283 = mux(T_1221, T_1251[5], T_1282) + node T_1284 = mux(T_1220, T_1251[4], T_1283) + node T_1285 = mux(T_1219, T_1251[3], T_1284) + node T_1286 = mux(T_1218, T_1251[2], T_1285) + node T_1287 = mux(T_1217, T_1251[1], T_1286) + node T_1288 = mux(T_1216, T_1251[0], T_1287) + node T_1290 = subw(UInt<17>("h00"), sdq_enq) + node T_1291 = and(T_1288, T_1290) + node T_1292 = or(T_1213, T_1291) + sdq_val := T_1292 + skip + + module TLB_60 : + output ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>} + output resp : {miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, hit_idx : UInt<8>} + input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}} + input clock : Clock + input reset : UInt<1> + + ptw.req.bits.fetch := UInt<1>("h00") + ptw.req.bits.store := UInt<1>("h00") + ptw.req.bits.prv := UInt<1>("h00") + ptw.req.bits.addr := UInt<1>("h00") + ptw.req.valid := UInt<1>("h00") + resp.hit_idx := UInt<1>("h00") + resp.xcpt_if := UInt<1>("h00") + resp.xcpt_st := UInt<1>("h00") + resp.xcpt_ld := UInt<1>("h00") + resp.ppn := UInt<1>("h00") + resp.miss := UInt<1>("h00") + req.ready := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg r_refill_tag : UInt<?>, clock, reset + reg r_refill_waddr : UInt<?>, clock, reset + reg r_req : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clock, reset + inst tag_cam of RocketCAM + tag_cam.write_addr := UInt<1>("h00") + tag_cam.write_tag := UInt<1>("h00") + tag_cam.write := UInt<1>("h00") + tag_cam.tag := UInt<1>("h00") + tag_cam.clear_mask := UInt<1>("h00") + tag_cam.clear := UInt<1>("h00") + tag_cam.reset := UInt<1>("h00") + tag_cam.clock := clock + tag_cam.reset := reset + cmem tag_ram : UInt<20>[8], clock + node lookup_tag = cat(req.bits.asid, req.bits.vpn) + tag_cam.tag := lookup_tag + node T_181 = eq(state, UInt<2>("h02")) + node T_182 = and(T_181, ptw.resp.valid) + tag_cam.write := T_182 + tag_cam.write_tag := r_refill_tag + tag_cam.write_addr := r_refill_waddr + node T_183 = bits(tag_cam.hits, 7, 4) + node T_184 = bits(tag_cam.hits, 3, 0) + node T_186 = neq(T_183, UInt<1>("h00")) + node T_187 = or(T_183, T_184) + node T_188 = bits(T_187, 3, 2) + node T_189 = bits(T_187, 1, 0) + node T_191 = neq(T_188, UInt<1>("h00")) + node T_192 = or(T_188, T_189) + node T_193 = bit(T_192, 1) + node T_194 = cat(T_191, T_193) + node tag_hit_addr = cat(T_186, T_194) + reg valid_array : UInt<1>[8], clock, reset + reg ur_array : UInt<1>[8], clock, reset + reg uw_array : UInt<1>[8], clock, reset + reg ux_array : UInt<1>[8], clock, reset + reg sr_array : UInt<1>[8], clock, reset + reg sw_array : UInt<1>[8], clock, reset + reg sx_array : UInt<1>[8], clock, reset + reg dirty_array : UInt<1>[8], clock, reset + when ptw.resp.valid : + infer accessor T_388 = tag_ram[r_refill_waddr] + T_388 := ptw.resp.bits.pte.ppn + infer accessor T_389 = valid_array[r_refill_waddr] + node T_391 = eq(ptw.resp.bits.error, UInt<1>("h00")) + T_389 := T_391 + infer accessor T_392 = ur_array[r_refill_waddr] + node T_394 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_395 = and(ptw.resp.bits.pte.v, T_394) + node T_397 = lt(ptw.resp.bits.pte.typ, UInt<4>("h08")) + node T_398 = and(T_395, T_397) + node T_400 = eq(ptw.resp.bits.error, UInt<1>("h00")) + node T_401 = and(T_398, T_400) + T_392 := T_401 + infer accessor T_402 = uw_array[r_refill_waddr] + node T_404 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_405 = and(ptw.resp.bits.pte.v, T_404) + node T_407 = lt(ptw.resp.bits.pte.typ, UInt<4>("h08")) + node T_408 = and(T_405, T_407) + node T_409 = bit(ptw.resp.bits.pte.typ, 0) + node T_410 = and(T_408, T_409) + node T_412 = eq(ptw.resp.bits.error, UInt<1>("h00")) + node T_413 = and(T_410, T_412) + T_402 := T_413 + infer accessor T_414 = ux_array[r_refill_waddr] + node T_416 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_417 = and(ptw.resp.bits.pte.v, T_416) + node T_419 = lt(ptw.resp.bits.pte.typ, UInt<4>("h08")) + node T_420 = and(T_417, T_419) + node T_421 = bit(ptw.resp.bits.pte.typ, 1) + node T_422 = and(T_420, T_421) + node T_424 = eq(ptw.resp.bits.error, UInt<1>("h00")) + node T_425 = and(T_422, T_424) + T_414 := T_425 + infer accessor T_426 = sr_array[r_refill_waddr] + node T_428 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_429 = and(ptw.resp.bits.pte.v, T_428) + node T_431 = eq(ptw.resp.bits.error, UInt<1>("h00")) + node T_432 = and(T_429, T_431) + T_426 := T_432 + infer accessor T_433 = sw_array[r_refill_waddr] + node T_435 = geq(ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_436 = and(ptw.resp.bits.pte.v, T_435) + node T_437 = bit(ptw.resp.bits.pte.typ, 0) + node T_438 = and(T_436, T_437) + node T_440 = eq(ptw.resp.bits.error, UInt<1>("h00")) + node T_441 = and(T_438, T_440) + T_433 := T_441 + infer accessor T_442 = sx_array[r_refill_waddr] + node T_444 = geq(ptw.resp.bits.pte.typ, UInt<3>("h04")) + node T_445 = and(ptw.resp.bits.pte.v, T_444) + node T_446 = bit(ptw.resp.bits.pte.typ, 1) + node T_447 = and(T_445, T_446) + node T_449 = eq(ptw.resp.bits.error, UInt<1>("h00")) + node T_450 = and(T_447, T_449) + T_442 := T_450 + infer accessor T_451 = dirty_array[r_refill_waddr] + T_451 := ptw.resp.bits.pte.d + skip + node T_452 = not(tag_cam.valid_bits) + node T_454 = eq(T_452, UInt<1>("h00")) + node has_invalid_entry = eq(T_454, UInt<1>("h00")) + node T_457 = not(tag_cam.valid_bits) + node T_458 = bit(T_457, 0) + node T_459 = bit(T_457, 1) + node T_460 = bit(T_457, 2) + node T_461 = bit(T_457, 3) + node T_462 = bit(T_457, 4) + node T_463 = bit(T_457, 5) + node T_464 = bit(T_457, 6) + node T_465 = bit(T_457, 7) + wire T_467 : UInt<1>[8] + T_467[0] := T_458 + T_467[1] := T_459 + T_467[2] := T_460 + T_467[3] := T_461 + T_467[4] := T_462 + T_467[5] := T_463 + T_467[6] := T_464 + T_467[7] := T_465 + node T_485 = mux(T_467[6], UInt<3>("h06"), UInt<3>("h07")) + node T_486 = mux(T_467[5], UInt<3>("h05"), T_485) + node T_487 = mux(T_467[4], UInt<3>("h04"), T_486) + node T_488 = mux(T_467[3], UInt<2>("h03"), T_487) + node T_489 = mux(T_467[2], UInt<2>("h02"), T_488) + node T_490 = mux(T_467[1], UInt<1>("h01"), T_489) + node invalid_entry = mux(T_467[0], UInt<1>("h00"), T_490) + reg T_493 : UInt<8>, clock, reset + node T_495 = dshr(T_493, UInt<1>("h01")) + node T_496 = bit(T_495, 0) + node T_497 = cat(UInt<1>("h01"), T_496) + node T_498 = dshr(T_493, T_497) + node T_499 = bit(T_498, 0) + node T_500 = cat(T_497, T_499) + node T_501 = dshr(T_493, T_500) + node T_502 = bit(T_501, 0) + node T_503 = cat(T_500, T_502) + node T_504 = bits(T_503, 2, 0) + node repl_waddr = mux(has_invalid_entry, invalid_entry, T_504) + node T_507 = eq(req.bits.instruction, UInt<1>("h00")) + node T_508 = and(ptw.status.mprv, T_507) + node priv = mux(T_508, ptw.status.prv1, ptw.status.prv) + node priv_s = eq(priv, UInt<1>("h01")) + node priv_uses_vm = leq(priv, UInt<1>("h01")) + node T_515 = eq(r_req.store, UInt<1>("h00")) + node T_516 = or(r_req.instruction, r_req.store) + node T_518 = eq(T_516, UInt<1>("h00")) + node T_519 = cat(r_req.store, T_518) + node req_xwr = cat(T_515, T_519) + node T_521 = cat(sr_array[7], sr_array[6]) + node T_522 = cat(sr_array[5], sr_array[4]) + node T_523 = cat(T_521, T_522) + node T_524 = cat(sr_array[3], sr_array[2]) + node T_525 = cat(sr_array[1], sr_array[0]) + node T_526 = cat(T_524, T_525) + node T_527 = cat(T_523, T_526) + node T_528 = cat(ur_array[7], ur_array[6]) + node T_529 = cat(ur_array[5], ur_array[4]) + node T_530 = cat(T_528, T_529) + node T_531 = cat(ur_array[3], ur_array[2]) + node T_532 = cat(ur_array[1], ur_array[0]) + node T_533 = cat(T_531, T_532) + node T_534 = cat(T_530, T_533) + node r_array = mux(priv_s, T_527, T_534) + node T_536 = cat(sw_array[7], sw_array[6]) + node T_537 = cat(sw_array[5], sw_array[4]) + node T_538 = cat(T_536, T_537) + node T_539 = cat(sw_array[3], sw_array[2]) + node T_540 = cat(sw_array[1], sw_array[0]) + node T_541 = cat(T_539, T_540) + node T_542 = cat(T_538, T_541) + node T_543 = cat(uw_array[7], uw_array[6]) + node T_544 = cat(uw_array[5], uw_array[4]) + node T_545 = cat(T_543, T_544) + node T_546 = cat(uw_array[3], uw_array[2]) + node T_547 = cat(uw_array[1], uw_array[0]) + node T_548 = cat(T_546, T_547) + node T_549 = cat(T_545, T_548) + node w_array = mux(priv_s, T_542, T_549) + node T_551 = cat(sx_array[7], sx_array[6]) + node T_552 = cat(sx_array[5], sx_array[4]) + node T_553 = cat(T_551, T_552) + node T_554 = cat(sx_array[3], sx_array[2]) + node T_555 = cat(sx_array[1], sx_array[0]) + node T_556 = cat(T_554, T_555) + node T_557 = cat(T_553, T_556) + node T_558 = cat(ux_array[7], ux_array[6]) + node T_559 = cat(ux_array[5], ux_array[4]) + node T_560 = cat(T_558, T_559) + node T_561 = cat(ux_array[3], ux_array[2]) + node T_562 = cat(ux_array[1], ux_array[0]) + node T_563 = cat(T_561, T_562) + node T_564 = cat(T_560, T_563) + node x_array = mux(priv_s, T_557, T_564) + node T_566 = bit(ptw.status.vm, 3) + node vm_enabled = and(T_566, priv_uses_vm) + node T_568 = bit(req.bits.vpn, 27) + node T_569 = bit(req.bits.vpn, 26) + node bad_va = neq(T_568, T_569) + node T_571 = cat(dirty_array[7], dirty_array[6]) + node T_572 = cat(dirty_array[5], dirty_array[4]) + node T_573 = cat(T_571, T_572) + node T_574 = cat(dirty_array[3], dirty_array[2]) + node T_575 = cat(dirty_array[1], dirty_array[0]) + node T_576 = cat(T_574, T_575) + node T_577 = cat(T_573, T_576) + node T_579 = mux(req.bits.store, w_array, UInt<1>("h00")) + node T_580 = not(T_579) + node T_581 = or(T_577, T_580) + node tag_hits = and(tag_cam.hits, T_581) + node tag_hit = neq(tag_hits, UInt<1>("h00")) + node tlb_hit = and(vm_enabled, tag_hit) + node T_587 = eq(tag_hit, UInt<1>("h00")) + node T_588 = and(vm_enabled, T_587) + node T_590 = eq(bad_va, UInt<1>("h00")) + node tlb_miss = and(T_588, T_590) + node T_592 = and(req.valid, tlb_hit) + when T_592 : + node T_593 = bits(tag_cam.hits, 7, 4) + node T_594 = bits(tag_cam.hits, 3, 0) + node T_596 = neq(T_593, UInt<1>("h00")) + node T_597 = or(T_593, T_594) + node T_598 = bits(T_597, 3, 2) + node T_599 = bits(T_597, 1, 0) + node T_601 = neq(T_598, UInt<1>("h00")) + node T_602 = or(T_598, T_599) + node T_603 = bit(T_602, 1) + node T_604 = cat(T_601, T_603) + node T_605 = cat(T_596, T_604) + node T_607 = bit(T_605, 2) + node T_609 = dshl(UInt<8>("h01"), UInt<1>("h01")) + node T_610 = bits(T_609, 7, 0) + node T_611 = not(T_610) + node T_612 = and(T_493, T_611) + node T_614 = mux(T_607, UInt<1>("h00"), T_610) + node T_615 = or(T_612, T_614) + node T_616 = cat(UInt<1>("h01"), T_607) + node T_617 = bit(T_605, 1) + node T_619 = dshl(UInt<8>("h01"), T_616) + node T_620 = bits(T_619, 7, 0) + node T_621 = not(T_620) + node T_622 = and(T_615, T_621) + node T_624 = mux(T_617, UInt<1>("h00"), T_620) + node T_625 = or(T_622, T_624) + node T_626 = cat(T_616, T_617) + node T_627 = bit(T_605, 0) + node T_629 = dshl(UInt<8>("h01"), T_626) + node T_630 = bits(T_629, 7, 0) + node T_631 = not(T_630) + node T_632 = and(T_625, T_631) + node T_634 = mux(T_627, UInt<1>("h00"), T_630) + node T_635 = or(T_632, T_634) + node T_636 = cat(T_626, T_627) + T_493 := T_635 + skip + node T_637 = eq(state, UInt<1>("h00")) + req.ready := T_637 + node T_638 = and(r_array, tag_cam.hits) + node T_640 = neq(T_638, UInt<1>("h00")) + node T_642 = eq(T_640, UInt<1>("h00")) + node T_643 = and(tlb_hit, T_642) + node T_644 = or(bad_va, T_643) + resp.xcpt_ld := T_644 + node T_645 = and(w_array, tag_cam.hits) + node T_647 = neq(T_645, UInt<1>("h00")) + node T_649 = eq(T_647, UInt<1>("h00")) + node T_650 = and(tlb_hit, T_649) + node T_651 = or(bad_va, T_650) + resp.xcpt_st := T_651 + node T_652 = and(x_array, tag_cam.hits) + node T_654 = neq(T_652, UInt<1>("h00")) + node T_656 = eq(T_654, UInt<1>("h00")) + node T_657 = and(tlb_hit, T_656) + node T_658 = or(bad_va, T_657) + resp.xcpt_if := T_658 + resp.miss := tlb_miss + node T_660 = eq(req.bits.passthrough, UInt<1>("h00")) + node T_661 = and(vm_enabled, T_660) + node T_662 = bit(tag_cam.hits, 0) + node T_663 = bit(tag_cam.hits, 1) + node T_664 = bit(tag_cam.hits, 2) + node T_665 = bit(tag_cam.hits, 3) + node T_666 = bit(tag_cam.hits, 4) + node T_667 = bit(tag_cam.hits, 5) + node T_668 = bit(tag_cam.hits, 6) + node T_669 = bit(tag_cam.hits, 7) + infer accessor T_671 = tag_ram[UInt<1>("h00")] + infer accessor T_673 = tag_ram[UInt<1>("h01")] + infer accessor T_675 = tag_ram[UInt<2>("h02")] + infer accessor T_677 = tag_ram[UInt<2>("h03")] + infer accessor T_679 = tag_ram[UInt<3>("h04")] + infer accessor T_681 = tag_ram[UInt<3>("h05")] + infer accessor T_683 = tag_ram[UInt<3>("h06")] + infer accessor T_685 = tag_ram[UInt<3>("h07")] + node T_687 = mux(T_662, T_671, UInt<1>("h00")) + node T_689 = mux(T_663, T_673, UInt<1>("h00")) + node T_691 = mux(T_664, T_675, UInt<1>("h00")) + node T_693 = mux(T_665, T_677, UInt<1>("h00")) + node T_695 = mux(T_666, T_679, UInt<1>("h00")) + node T_697 = mux(T_667, T_681, UInt<1>("h00")) + node T_699 = mux(T_668, T_683, UInt<1>("h00")) + node T_701 = mux(T_669, T_685, UInt<1>("h00")) + node T_703 = or(T_687, T_689) + node T_704 = or(T_703, T_691) + node T_705 = or(T_704, T_693) + node T_706 = or(T_705, T_695) + node T_707 = or(T_706, T_697) + node T_708 = or(T_707, T_699) + node T_709 = or(T_708, T_701) + wire T_710 : UInt<20> + T_710 := UInt<1>("h00") + T_710 := T_709 + node T_712 = bits(req.bits.vpn, 19, 0) + node T_713 = mux(T_661, T_710, T_712) + resp.ppn := T_713 + resp.hit_idx := tag_cam.hits + node T_714 = and(req.ready, req.valid) + node T_715 = or(ptw.invalidate, T_714) + tag_cam.clear := T_715 + node T_716 = cat(valid_array[7], valid_array[6]) + node T_717 = cat(valid_array[5], valid_array[4]) + node T_718 = cat(T_716, T_717) + node T_719 = cat(valid_array[3], valid_array[2]) + node T_720 = cat(valid_array[1], valid_array[0]) + node T_721 = cat(T_719, T_720) + node T_722 = cat(T_718, T_721) + node T_723 = not(T_722) + node T_724 = not(tag_hits) + node T_725 = and(tag_cam.hits, T_724) + node T_726 = or(T_723, T_725) + tag_cam.clear_mask := T_726 + when ptw.invalidate : + node T_728 = not(UInt<8>("h00")) + tag_cam.clear_mask := T_728 + skip + node T_729 = eq(state, UInt<1>("h01")) + ptw.req.valid := T_729 + ptw.req.bits.addr := r_refill_tag + ptw.req.bits.prv := ptw.status.prv + ptw.req.bits.store := r_req.store + ptw.req.bits.fetch := r_req.instruction + node T_730 = and(req.ready, req.valid) + node T_731 = and(T_730, tlb_miss) + when T_731 : + state := UInt<1>("h01") + r_refill_tag := lookup_tag + r_refill_waddr := repl_waddr + r_req <> req.bits + skip + node T_732 = eq(state, UInt<1>("h01")) + when T_732 : + when ptw.invalidate : + state := UInt<1>("h00") + skip + when ptw.req.ready : + state := UInt<2>("h02") + when ptw.invalidate : + state := UInt<2>("h03") + skip + skip + skip + node T_733 = eq(state, UInt<2>("h02")) + node T_734 = and(T_733, ptw.invalidate) + when T_734 : + state := UInt<2>("h03") + skip + when ptw.resp.valid : + state := UInt<1>("h00") + skip + + module MetadataArray : + output resp : {tag : UInt<20>, coh : {state : UInt<2>}}[4] + input write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}} + input read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}} + input clock : Clock + input reset : UInt<1> + + write.ready := UInt<1>("h00") + read.ready := UInt<1>("h00") + wire T_53 : {state : UInt<2>} + T_53.state := UInt<1>("h00") + T_53.state := UInt<1>("h00") + wire rstVal : {tag : UInt<20>, coh : {state : UInt<2>}} + rstVal.coh.state := UInt<1>("h00") + rstVal.tag := UInt<1>("h00") + rstVal.tag := UInt<1>("h00") + rstVal.coh <> T_53 + reg rst_cnt : UInt<7>, clock, reset + onreset rst_cnt := UInt<7>("h00") + node rst = lt(rst_cnt, UInt<7>("h040")) + node waddr = mux(rst, rst_cnt, write.bits.idx) + wire T_557 : {tag : UInt<20>, coh : {state : UInt<2>}} + T_557 <> write.bits.data + when rst : + T_557 <> rstVal + skip + node wdata = cat(T_557.tag, T_557.coh.state) + node T_586 = asSInt(write.bits.way_en) + node T_587 = mux(rst, asSInt(UInt<1>("h01")), T_586) + node wmask = asUInt(T_587) + when rst : + node T_590 = addw(rst_cnt, UInt<1>("h01")) + rst_cnt := T_590 + skip + cmem T_593 : UInt<88>[64], clock + node T_594 = or(rst, write.valid) + when T_594 : + node T_595 = cat(wdata, wdata) + node T_596 = cat(T_595, T_595) + node T_597 = bit(wmask, 0) + node T_598 = bit(wmask, 1) + node T_599 = bit(wmask, 2) + node T_600 = bit(wmask, 3) + wire T_602 : UInt<1>[4] + T_602[0] := T_597 + T_602[1] := T_598 + T_602[2] := T_599 + T_602[3] := T_600 + node T_609 = subw(UInt<22>("h00"), T_602[0]) + node T_611 = subw(UInt<22>("h00"), T_602[1]) + node T_613 = subw(UInt<22>("h00"), T_602[2]) + node T_615 = subw(UInt<22>("h00"), T_602[3]) + wire T_617 : UInt<22>[4] + T_617[0] := T_609 + T_617[1] := T_611 + T_617[2] := T_613 + T_617[3] := T_615 + node T_623 = cat(T_617[3], T_617[2]) + node T_624 = cat(T_617[1], T_617[0]) + node T_625 = cat(T_623, T_624) + infer accessor T_626 = T_593[waddr] + node T_627 = not(T_625) + node T_628 = and(T_626, T_627) + node T_629 = and(T_596, T_625) + node T_630 = or(T_628, T_629) + wire T_631 : UInt<88> + T_631 := UInt<1>("h00") + T_631 := T_630 + infer accessor T_633 = T_593[waddr] + T_633 := T_631 + skip + reg T_634 : UInt<6>, clock, reset + when read.valid : + T_634 := read.bits.idx + skip + infer accessor tags = T_593[T_634] + wire T_880 : {tag : UInt<20>, coh : {state : UInt<2>}}[4] + T_880[0].coh.state := UInt<1>("h00") + T_880[0].tag := UInt<1>("h00") + T_880[1].coh.state := UInt<1>("h00") + T_880[1].tag := UInt<1>("h00") + T_880[2].coh.state := UInt<1>("h00") + T_880[2].tag := UInt<1>("h00") + T_880[3].coh.state := UInt<1>("h00") + T_880[3].tag := UInt<1>("h00") + node T_1024 = bits(tags, 1, 0) + T_880[0].coh.state := T_1024 + node T_1025 = bits(tags, 21, 2) + T_880[0].tag := T_1025 + node T_1026 = bits(tags, 23, 22) + T_880[1].coh.state := T_1026 + node T_1027 = bits(tags, 43, 24) + T_880[1].tag := T_1027 + node T_1028 = bits(tags, 45, 44) + T_880[2].coh.state := T_1028 + node T_1029 = bits(tags, 65, 46) + T_880[2].tag := T_1029 + node T_1030 = bits(tags, 67, 66) + T_880[3].coh.state := T_1030 + node T_1031 = bits(tags, 87, 68) + T_880[3].tag := T_1031 + resp := T_880 + node T_1033 = eq(rst, UInt<1>("h00")) + node T_1035 = eq(write.valid, UInt<1>("h00")) + node T_1036 = and(T_1033, T_1035) + read.ready := T_1036 + node T_1038 = eq(rst, UInt<1>("h00")) + write.ready := T_1038 + + module Arbiter_62 : + output chosen : UInt<3> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}[5] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.idx := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + in[2].ready := UInt<1>("h00") + in[3].ready := UInt<1>("h00") + in[4].ready := UInt<1>("h00") + wire T_128 : UInt<3> + T_128 := UInt<1>("h00") + infer accessor T_130 = in[T_128] + out.valid := T_130.valid + infer accessor T_137 = in[T_128] + out.bits <> T_137.bits + chosen := T_128 + infer accessor T_144 = in[T_128] + T_144.ready := UInt<1>("h00") + node T_154 = or(UInt<1>("h00"), in[0].valid) + node T_156 = eq(T_154, UInt<1>("h00")) + node T_158 = or(UInt<1>("h00"), in[0].valid) + node T_159 = or(T_158, in[1].valid) + node T_161 = eq(T_159, UInt<1>("h00")) + node T_163 = or(UInt<1>("h00"), in[0].valid) + node T_164 = or(T_163, in[1].valid) + node T_165 = or(T_164, in[2].valid) + node T_167 = eq(T_165, UInt<1>("h00")) + node T_169 = or(UInt<1>("h00"), in[0].valid) + node T_170 = or(T_169, in[1].valid) + node T_171 = or(T_170, in[2].valid) + node T_172 = or(T_171, in[3].valid) + node T_174 = eq(T_172, UInt<1>("h00")) + node T_176 = eq(UInt<3>("h04"), UInt<1>("h00")) + node T_177 = mux(UInt<1>("h00"), T_176, UInt<1>("h01")) + node T_178 = and(T_177, out.ready) + in[0].ready := T_178 + node T_180 = eq(UInt<3>("h04"), UInt<1>("h01")) + node T_181 = mux(UInt<1>("h00"), T_180, T_156) + node T_182 = and(T_181, out.ready) + in[1].ready := T_182 + node T_184 = eq(UInt<3>("h04"), UInt<2>("h02")) + node T_185 = mux(UInt<1>("h00"), T_184, T_161) + node T_186 = and(T_185, out.ready) + in[2].ready := T_186 + node T_188 = eq(UInt<3>("h04"), UInt<2>("h03")) + node T_189 = mux(UInt<1>("h00"), T_188, T_167) + node T_190 = and(T_189, out.ready) + in[3].ready := T_190 + node T_192 = eq(UInt<3>("h04"), UInt<3>("h04")) + node T_193 = mux(UInt<1>("h00"), T_192, T_174) + node T_194 = and(T_193, out.ready) + in[4].ready := T_194 + node T_197 = mux(in[3].valid, UInt<2>("h03"), UInt<3>("h04")) + node T_199 = mux(in[2].valid, UInt<2>("h02"), T_197) + node T_201 = mux(in[1].valid, UInt<1>("h01"), T_199) + node T_203 = mux(in[0].valid, UInt<1>("h00"), T_201) + node T_204 = mux(UInt<1>("h00"), UInt<3>("h04"), T_203) + T_128 := T_204 + + module DataArray : + output resp : UInt<128>[4] + input write : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}} + input read : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}} + input clock : Clock + input reset : UInt<1> + + resp[0] := UInt<1>("h00") + resp[1] := UInt<1>("h00") + resp[2] := UInt<1>("h00") + resp[3] := UInt<1>("h00") + write.ready := UInt<1>("h00") + read.ready := UInt<1>("h00") + node waddr = shr(write.bits.addr, 4) + node raddr = shr(read.bits.addr, 4) + node T_65 = bits(write.bits.way_en, 1, 0) + node T_66 = bits(read.bits.way_en, 1, 0) + wire T_75 : UInt<128>[2] + T_75[0] := UInt<1>("h00") + T_75[1] := UInt<1>("h00") + reg T_81 : UInt<12>, clock, reset + when read.valid : + T_81 := read.bits.addr + skip + cmem T_84 : UInt<128>[256], clock + node T_86 = neq(T_65, UInt<1>("h00")) + node T_87 = and(T_86, write.valid) + node T_88 = bit(write.bits.wmask, 0) + node T_89 = and(T_87, T_88) + when T_89 : + node T_90 = bits(write.bits.data, 63, 0) + node T_91 = cat(T_90, T_90) + node T_92 = bit(T_65, 0) + node T_93 = bit(T_65, 1) + wire T_95 : UInt<1>[2] + T_95[0] := T_92 + T_95[1] := T_93 + node T_100 = subw(UInt<64>("h00"), T_95[0]) + node T_102 = subw(UInt<64>("h00"), T_95[1]) + wire T_104 : UInt<64>[2] + T_104[0] := T_100 + T_104[1] := T_102 + node T_108 = cat(T_104[1], T_104[0]) + infer accessor T_109 = T_84[waddr] + node T_110 = not(T_108) + node T_111 = and(T_109, T_110) + node T_112 = and(T_91, T_108) + node T_113 = or(T_111, T_112) + wire T_114 : UInt<128> + T_114 := UInt<1>("h00") + T_114 := T_113 + infer accessor T_116 = T_84[waddr] + T_116 := T_114 + skip + node T_118 = neq(T_66, UInt<1>("h00")) + node T_119 = and(T_118, read.valid) + reg T_120 : UInt<8>, clock, reset + when T_119 : + T_120 := raddr + skip + infer accessor T_121 = T_84[T_120] + T_75[0] := T_121 + cmem T_124 : UInt<128>[256], clock + node T_126 = neq(T_65, UInt<1>("h00")) + node T_127 = and(T_126, write.valid) + node T_128 = bit(write.bits.wmask, 1) + node T_129 = and(T_127, T_128) + when T_129 : + node T_130 = bits(write.bits.data, 127, 64) + node T_131 = cat(T_130, T_130) + node T_132 = bit(T_65, 0) + node T_133 = bit(T_65, 1) + wire T_135 : UInt<1>[2] + T_135[0] := T_132 + T_135[1] := T_133 + node T_140 = subw(UInt<64>("h00"), T_135[0]) + node T_142 = subw(UInt<64>("h00"), T_135[1]) + wire T_144 : UInt<64>[2] + T_144[0] := T_140 + T_144[1] := T_142 + node T_148 = cat(T_144[1], T_144[0]) + infer accessor T_149 = T_124[waddr] + node T_150 = not(T_148) + node T_151 = and(T_149, T_150) + node T_152 = and(T_131, T_148) + node T_153 = or(T_151, T_152) + wire T_154 : UInt<128> + T_154 := UInt<1>("h00") + T_154 := T_153 + infer accessor T_156 = T_124[waddr] + T_156 := T_154 + skip + node T_158 = neq(T_66, UInt<1>("h00")) + node T_159 = and(T_158, read.valid) + reg T_160 : UInt<8>, clock, reset + when T_159 : + T_160 := raddr + skip + infer accessor T_161 = T_124[T_160] + T_75[1] := T_161 + node T_162 = bits(T_75[0], 63, 0) + node T_163 = bits(T_75[1], 63, 0) + wire T_165 : UInt<64>[2] + T_165[0] := T_162 + T_165[1] := T_163 + node T_169 = bits(T_81, 3, 3) + infer accessor T_170 = T_165[T_169] + wire T_172 : UInt<64>[2] + T_172[0] := T_170 + T_172[1] := T_165[1] + node T_176 = cat(T_172[1], T_172[0]) + resp[0] := T_176 + node T_177 = bits(T_75[0], 127, 64) + node T_178 = bits(T_75[1], 127, 64) + wire T_180 : UInt<64>[2] + T_180[0] := T_177 + T_180[1] := T_178 + node T_184 = bits(T_81, 3, 3) + infer accessor T_185 = T_180[T_184] + wire T_187 : UInt<64>[2] + T_187[0] := T_185 + T_187[1] := T_180[1] + node T_191 = cat(T_187[1], T_187[0]) + resp[1] := T_191 + node T_192 = bits(write.bits.way_en, 3, 2) + node T_193 = bits(read.bits.way_en, 3, 2) + wire T_202 : UInt<128>[2] + T_202[0] := UInt<1>("h00") + T_202[1] := UInt<1>("h00") + reg T_208 : UInt<12>, clock, reset + when read.valid : + T_208 := read.bits.addr + skip + cmem T_211 : UInt<128>[256], clock + node T_213 = neq(T_192, UInt<1>("h00")) + node T_214 = and(T_213, write.valid) + node T_215 = bit(write.bits.wmask, 0) + node T_216 = and(T_214, T_215) + when T_216 : + node T_217 = bits(write.bits.data, 63, 0) + node T_218 = cat(T_217, T_217) + node T_219 = bit(T_192, 0) + node T_220 = bit(T_192, 1) + wire T_222 : UInt<1>[2] + T_222[0] := T_219 + T_222[1] := T_220 + node T_227 = subw(UInt<64>("h00"), T_222[0]) + node T_229 = subw(UInt<64>("h00"), T_222[1]) + wire T_231 : UInt<64>[2] + T_231[0] := T_227 + T_231[1] := T_229 + node T_235 = cat(T_231[1], T_231[0]) + infer accessor T_236 = T_211[waddr] + node T_237 = not(T_235) + node T_238 = and(T_236, T_237) + node T_239 = and(T_218, T_235) + node T_240 = or(T_238, T_239) + wire T_241 : UInt<128> + T_241 := UInt<1>("h00") + T_241 := T_240 + infer accessor T_243 = T_211[waddr] + T_243 := T_241 + skip + node T_245 = neq(T_193, UInt<1>("h00")) + node T_246 = and(T_245, read.valid) + reg T_247 : UInt<8>, clock, reset + when T_246 : + T_247 := raddr + skip + infer accessor T_248 = T_211[T_247] + T_202[0] := T_248 + cmem T_251 : UInt<128>[256], clock + node T_253 = neq(T_192, UInt<1>("h00")) + node T_254 = and(T_253, write.valid) + node T_255 = bit(write.bits.wmask, 1) + node T_256 = and(T_254, T_255) + when T_256 : + node T_257 = bits(write.bits.data, 127, 64) + node T_258 = cat(T_257, T_257) + node T_259 = bit(T_192, 0) + node T_260 = bit(T_192, 1) + wire T_262 : UInt<1>[2] + T_262[0] := T_259 + T_262[1] := T_260 + node T_267 = subw(UInt<64>("h00"), T_262[0]) + node T_269 = subw(UInt<64>("h00"), T_262[1]) + wire T_271 : UInt<64>[2] + T_271[0] := T_267 + T_271[1] := T_269 + node T_275 = cat(T_271[1], T_271[0]) + infer accessor T_276 = T_251[waddr] + node T_277 = not(T_275) + node T_278 = and(T_276, T_277) + node T_279 = and(T_258, T_275) + node T_280 = or(T_278, T_279) + wire T_281 : UInt<128> + T_281 := UInt<1>("h00") + T_281 := T_280 + infer accessor T_283 = T_251[waddr] + T_283 := T_281 + skip + node T_285 = neq(T_193, UInt<1>("h00")) + node T_286 = and(T_285, read.valid) + reg T_287 : UInt<8>, clock, reset + when T_286 : + T_287 := raddr + skip + infer accessor T_288 = T_251[T_287] + T_202[1] := T_288 + node T_289 = bits(T_202[0], 63, 0) + node T_290 = bits(T_202[1], 63, 0) + wire T_292 : UInt<64>[2] + T_292[0] := T_289 + T_292[1] := T_290 + node T_296 = bits(T_208, 3, 3) + infer accessor T_297 = T_292[T_296] + wire T_299 : UInt<64>[2] + T_299[0] := T_297 + T_299[1] := T_292[1] + node T_303 = cat(T_299[1], T_299[0]) + resp[2] := T_303 + node T_304 = bits(T_202[0], 127, 64) + node T_305 = bits(T_202[1], 127, 64) + wire T_307 : UInt<64>[2] + T_307[0] := T_304 + T_307[1] := T_305 + node T_311 = bits(T_208, 3, 3) + infer accessor T_312 = T_307[T_311] + wire T_314 : UInt<64>[2] + T_314[0] := T_312 + T_314[1] := T_307[1] + node T_318 = cat(T_314[1], T_314[0]) + resp[3] := T_318 + read.ready := UInt<1>("h01") + write.ready := UInt<1>("h01") + + module Arbiter_64 : + output chosen : UInt<2> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}[4] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.addr := UInt<1>("h00") + out.bits.way_en := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + in[2].ready := UInt<1>("h00") + in[3].ready := UInt<1>("h00") + wire T_144 : UInt<2> + T_144 := UInt<1>("h00") + infer accessor T_146 = in[T_144] + out.valid := T_146.valid + infer accessor T_155 = in[T_144] + out.bits <> T_155.bits + chosen := T_144 + infer accessor T_164 = in[T_144] + T_164.ready := UInt<1>("h00") + node T_176 = or(UInt<1>("h00"), in[0].valid) + node T_178 = eq(T_176, UInt<1>("h00")) + node T_180 = or(UInt<1>("h00"), in[0].valid) + node T_181 = or(T_180, in[1].valid) + node T_183 = eq(T_181, UInt<1>("h00")) + node T_185 = or(UInt<1>("h00"), in[0].valid) + node T_186 = or(T_185, in[1].valid) + node T_187 = or(T_186, in[2].valid) + node T_189 = eq(T_187, UInt<1>("h00")) + node T_191 = eq(UInt<2>("h03"), UInt<1>("h00")) + node T_192 = mux(UInt<1>("h00"), T_191, UInt<1>("h01")) + node T_193 = and(T_192, out.ready) + in[0].ready := T_193 + node T_195 = eq(UInt<2>("h03"), UInt<1>("h01")) + node T_196 = mux(UInt<1>("h00"), T_195, T_178) + node T_197 = and(T_196, out.ready) + in[1].ready := T_197 + node T_199 = eq(UInt<2>("h03"), UInt<2>("h02")) + node T_200 = mux(UInt<1>("h00"), T_199, T_183) + node T_201 = and(T_200, out.ready) + in[2].ready := T_201 + node T_203 = eq(UInt<2>("h03"), UInt<2>("h03")) + node T_204 = mux(UInt<1>("h00"), T_203, T_189) + node T_205 = and(T_204, out.ready) + in[3].ready := T_205 + node T_208 = mux(in[2].valid, UInt<2>("h02"), UInt<2>("h03")) + node T_210 = mux(in[1].valid, UInt<1>("h01"), T_208) + node T_212 = mux(in[0].valid, UInt<1>("h00"), T_210) + node T_213 = mux(UInt<1>("h00"), UInt<2>("h03"), T_212) + T_144 := T_213 + + module Arbiter_65 : + output chosen : UInt<1> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}[2] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.data := UInt<1>("h00") + out.bits.wmask := UInt<1>("h00") + out.bits.addr := UInt<1>("h00") + out.bits.way_en := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + wire T_152 : UInt<1> + T_152 := UInt<1>("h00") + infer accessor T_154 = in[T_152] + out.valid := T_154.valid + infer accessor T_167 = in[T_152] + out.bits <> T_167.bits + chosen := T_152 + infer accessor T_180 = in[T_152] + T_180.ready := UInt<1>("h00") + node T_196 = or(UInt<1>("h00"), in[0].valid) + node T_198 = eq(T_196, UInt<1>("h00")) + node T_200 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_201 = mux(UInt<1>("h00"), T_200, UInt<1>("h01")) + node T_202 = and(T_201, out.ready) + in[0].ready := T_202 + node T_204 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_205 = mux(UInt<1>("h00"), T_204, T_198) + node T_206 = and(T_205, out.ready) + in[1].ready := T_206 + node T_209 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_210 = mux(UInt<1>("h00"), UInt<1>("h01"), T_209) + T_152 := T_210 + + module AMOALU : + output out : UInt<64> + input rhs : UInt<64> + input lhs : UInt<64> + input typ : UInt<3> + input cmd : UInt<5> + input addr : UInt<6> + input clock : Clock + input reset : UInt<1> + + out := UInt<1>("h00") + node T_11 = eq(typ, UInt<3>("h00")) + node T_12 = eq(typ, UInt<3>("h04")) + node T_13 = or(T_11, T_12) + node T_14 = eq(typ, UInt<3>("h01")) + node T_15 = eq(typ, UInt<3>("h05")) + node T_16 = or(T_14, T_15) + node T_17 = eq(typ, UInt<3>("h02")) + node T_18 = eq(typ, UInt<3>("h06")) + node T_19 = or(T_17, T_18) + node T_20 = bits(rhs, 31, 0) + node T_21 = cat(T_20, T_20) + node rhs_1 = mux(T_19, T_21, rhs) + node T_23 = eq(cmd, UInt<5>("h0c")) + node T_24 = eq(cmd, UInt<5>("h0d")) + node sgned = or(T_23, T_24) + node T_26 = eq(cmd, UInt<5>("h0d")) + node T_27 = eq(cmd, UInt<5>("h0f")) + node max = or(T_26, T_27) + node T_29 = eq(cmd, UInt<5>("h0c")) + node T_30 = eq(cmd, UInt<5>("h0e")) + node min = or(T_29, T_30) + node T_32 = eq(typ, UInt<3>("h02")) + node T_33 = eq(typ, UInt<3>("h06")) + node T_34 = or(T_32, T_33) + node T_35 = eq(typ, UInt<3>("h00")) + node T_36 = or(T_34, T_35) + node T_37 = eq(typ, UInt<3>("h04")) + node word = or(T_36, T_37) + node T_40 = not(UInt<64>("h00")) + node T_41 = bit(addr, 2) + node T_42 = shl(T_41, 31) + node mask = xor(T_40, T_42) + node T_44 = and(lhs, mask) + node T_45 = and(rhs_1, mask) + node adder_out = addw(T_44, T_45) + node T_47 = bit(addr, 2) + node T_49 = eq(T_47, UInt<1>("h00")) + node T_50 = and(word, T_49) + node T_51 = bit(lhs, 31) + node T_52 = bit(lhs, 63) + node cmp_lhs = mux(T_50, T_51, T_52) + node T_54 = bit(addr, 2) + node T_56 = eq(T_54, UInt<1>("h00")) + node T_57 = and(word, T_56) + node T_58 = bit(rhs_1, 31) + node T_59 = bit(rhs_1, 63) + node cmp_rhs = mux(T_57, T_58, T_59) + node T_61 = bits(lhs, 31, 0) + node T_62 = bits(rhs_1, 31, 0) + node lt_lo = lt(T_61, T_62) + node T_64 = bits(lhs, 63, 32) + node T_65 = bits(rhs_1, 63, 32) + node lt_hi = lt(T_64, T_65) + node T_67 = bits(lhs, 63, 32) + node T_68 = bits(rhs_1, 63, 32) + node eq_hi = eq(T_67, T_68) + node T_70 = bit(addr, 2) + node T_71 = mux(T_70, lt_hi, lt_lo) + node T_72 = and(eq_hi, lt_lo) + node T_73 = or(lt_hi, T_72) + node lt = mux(word, T_71, T_73) + node T_75 = eq(cmp_lhs, cmp_rhs) + node T_76 = mux(sgned, cmp_lhs, cmp_rhs) + node less = mux(T_75, lt, T_76) + node T_78 = eq(cmd, UInt<5>("h08")) + node T_79 = eq(cmd, UInt<5>("h0b")) + node T_80 = and(lhs, rhs_1) + node T_81 = eq(cmd, UInt<5>("h0a")) + node T_82 = or(lhs, rhs_1) + node T_83 = eq(cmd, UInt<5>("h09")) + node T_84 = xor(lhs, rhs_1) + node T_85 = mux(less, min, max) + node T_86 = bits(rhs, 7, 0) + node T_87 = cat(T_86, T_86) + node T_88 = cat(T_87, T_87) + node T_89 = cat(T_88, T_88) + node T_90 = bits(rhs, 15, 0) + node T_91 = cat(T_90, T_90) + node T_92 = cat(T_91, T_91) + node T_93 = mux(T_16, T_92, rhs_1) + node T_94 = mux(T_13, T_89, T_93) + node T_95 = mux(T_85, lhs, T_94) + node T_96 = mux(T_83, T_84, T_95) + node T_97 = mux(T_81, T_82, T_96) + node T_98 = mux(T_79, T_80, T_97) + node out_2 = mux(T_78, adder_out, T_98) + node T_101 = bits(addr, 2, 0) + node T_102 = dshl(UInt<1>("h01"), T_101) + node T_104 = bits(addr, 2, 1) + node T_106 = cat(T_104, UInt<1>("h00")) + node T_107 = dshl(UInt<2>("h03"), T_106) + node T_109 = bit(addr, 2) + node T_111 = cat(T_109, UInt<2>("h00")) + node T_112 = dshl(UInt<4>("h0f"), T_111) + node T_114 = mux(T_19, T_112, UInt<8>("h0ff")) + node T_115 = mux(T_16, T_107, T_114) + node T_116 = mux(T_13, T_102, T_115) + node T_117 = bit(T_116, 0) + node T_118 = bit(T_116, 1) + node T_119 = bit(T_116, 2) + node T_120 = bit(T_116, 3) + node T_121 = bit(T_116, 4) + node T_122 = bit(T_116, 5) + node T_123 = bit(T_116, 6) + node T_124 = bit(T_116, 7) + node T_125 = bit(T_116, 8) + node T_126 = bit(T_116, 9) + node T_127 = bit(T_116, 10) + wire T_129 : UInt<1>[11] + T_129[0] := T_117 + T_129[1] := T_118 + T_129[2] := T_119 + T_129[3] := T_120 + T_129[4] := T_121 + T_129[5] := T_122 + T_129[6] := T_123 + T_129[7] := T_124 + T_129[8] := T_125 + T_129[9] := T_126 + T_129[10] := T_127 + node T_143 = subw(UInt<8>("h00"), T_129[0]) + node T_145 = subw(UInt<8>("h00"), T_129[1]) + node T_147 = subw(UInt<8>("h00"), T_129[2]) + node T_149 = subw(UInt<8>("h00"), T_129[3]) + node T_151 = subw(UInt<8>("h00"), T_129[4]) + node T_153 = subw(UInt<8>("h00"), T_129[5]) + node T_155 = subw(UInt<8>("h00"), T_129[6]) + node T_157 = subw(UInt<8>("h00"), T_129[7]) + node T_159 = subw(UInt<8>("h00"), T_129[8]) + node T_161 = subw(UInt<8>("h00"), T_129[9]) + node T_163 = subw(UInt<8>("h00"), T_129[10]) + wire T_165 : UInt<8>[11] + T_165[0] := T_143 + T_165[1] := T_145 + T_165[2] := T_147 + T_165[3] := T_149 + T_165[4] := T_151 + T_165[5] := T_153 + T_165[6] := T_155 + T_165[7] := T_157 + T_165[8] := T_159 + T_165[9] := T_161 + T_165[10] := T_163 + node T_178 = cat(T_165[10], T_165[9]) + node T_179 = cat(T_165[7], T_165[6]) + node T_180 = cat(T_165[8], T_179) + node T_181 = cat(T_178, T_180) + node T_182 = cat(T_165[4], T_165[3]) + node T_183 = cat(T_165[5], T_182) + node T_184 = cat(T_165[1], T_165[0]) + node T_185 = cat(T_165[2], T_184) + node T_186 = cat(T_183, T_185) + node wmask = cat(T_181, T_186) + node T_188 = and(wmask, out_2) + node T_189 = not(wmask) + node T_190 = and(T_189, lhs) + node T_191 = or(T_188, T_190) + out := T_191 + + module LockingArbiter_66 : + output chosen : UInt<1> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[2] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.voluntary := UInt<1>("h00") + out.bits.r_type := UInt<1>("h00") + out.bits.data := UInt<1>("h00") + out.bits.addr_beat := UInt<1>("h00") + out.bits.client_xact_id := UInt<1>("h00") + out.bits.addr_block := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + reg T_700 : UInt<1>, clock, reset + onreset T_700 := UInt<1>("h00") + reg T_702 : UInt<?>, clock, reset + onreset T_702 := UInt<1>("h01") + wire T_704 : UInt<1> + T_704 := UInt<1>("h00") + infer accessor T_706 = in[T_704] + out.valid := T_706.valid + infer accessor T_769 = in[T_704] + out.bits <> T_769.bits + chosen := T_704 + infer accessor T_832 = in[T_704] + T_832.ready := UInt<1>("h00") + node T_898 = or(UInt<1>("h00"), in[0].valid) + node T_900 = eq(T_898, UInt<1>("h00")) + node T_902 = eq(T_702, UInt<1>("h00")) + node T_903 = mux(T_700, T_902, UInt<1>("h01")) + node T_904 = and(T_903, out.ready) + in[0].ready := T_904 + node T_906 = eq(T_702, UInt<1>("h01")) + node T_907 = mux(T_700, T_906, T_900) + node T_908 = and(T_907, out.ready) + in[1].ready := T_908 + reg T_910 : UInt<2>, clock, reset + onreset T_910 := UInt<2>("h00") + node T_912 = addw(T_910, UInt<1>("h01")) + node T_913 = and(out.ready, out.valid) + when T_913 : + wire T_916 : UInt<2>[3] + T_916[0] := UInt<1>("h00") + T_916[1] := UInt<1>("h01") + T_916[2] := UInt<2>("h02") + node T_921 = eq(T_916[0], out.bits.r_type) + node T_922 = eq(T_916[1], out.bits.r_type) + node T_923 = eq(T_916[2], out.bits.r_type) + node T_925 = or(UInt<1>("h00"), T_921) + node T_926 = or(T_925, T_922) + node T_927 = or(T_926, T_923) + node T_928 = and(UInt<1>("h01"), T_927) + when T_928 : + T_910 := T_912 + node T_930 = eq(T_700, UInt<1>("h00")) + when T_930 : + T_700 := UInt<1>("h01") + node T_932 = and(in[0].ready, in[0].valid) + node T_933 = and(in[1].ready, in[1].valid) + wire T_935 : UInt<1>[2] + T_935[0] := T_932 + T_935[1] := T_933 + node T_941 = mux(T_935[0], UInt<1>("h00"), UInt<1>("h01")) + T_702 := T_941 + skip + skip + node T_943 = eq(T_912, UInt<1>("h00")) + when T_943 : + T_700 := UInt<1>("h00") + skip + skip + node choose = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_948 = mux(T_700, T_702, choose) + T_704 := T_948 + + module HellaCache : + output mem_1 : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + output ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>} + input cpu : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>} + input clock : Clock + input reset : UInt<1> + + mem_1.release.bits.voluntary := UInt<1>("h00") + mem_1.release.bits.r_type := UInt<1>("h00") + mem_1.release.bits.data := UInt<1>("h00") + mem_1.release.bits.addr_beat := UInt<1>("h00") + mem_1.release.bits.client_xact_id := UInt<1>("h00") + mem_1.release.bits.addr_block := UInt<1>("h00") + mem_1.release.valid := UInt<1>("h00") + mem_1.probe.ready := UInt<1>("h00") + mem_1.grant.ready := UInt<1>("h00") + mem_1.acquire.bits.union := UInt<1>("h00") + mem_1.acquire.bits.a_type := UInt<1>("h00") + mem_1.acquire.bits.is_builtin_type := UInt<1>("h00") + mem_1.acquire.bits.data := UInt<1>("h00") + mem_1.acquire.bits.addr_beat := UInt<1>("h00") + mem_1.acquire.bits.client_xact_id := UInt<1>("h00") + mem_1.acquire.bits.addr_block := UInt<1>("h00") + mem_1.acquire.valid := UInt<1>("h00") + ptw.req.bits.fetch := UInt<1>("h00") + ptw.req.bits.store := UInt<1>("h00") + ptw.req.bits.prv := UInt<1>("h00") + ptw.req.bits.addr := UInt<1>("h00") + ptw.req.valid := UInt<1>("h00") + cpu.ordered := UInt<1>("h00") + cpu.xcpt.pf.st := UInt<1>("h00") + cpu.xcpt.pf.ld := UInt<1>("h00") + cpu.xcpt.ma.st := UInt<1>("h00") + cpu.xcpt.ma.ld := UInt<1>("h00") + cpu.replay_next.bits := UInt<1>("h00") + cpu.replay_next.valid := UInt<1>("h00") + cpu.resp.bits.store_data := UInt<1>("h00") + cpu.resp.bits.data_subword := UInt<1>("h00") + cpu.resp.bits.has_data := UInt<1>("h00") + cpu.resp.bits.replay := UInt<1>("h00") + cpu.resp.bits.nack := UInt<1>("h00") + cpu.resp.bits.data := UInt<1>("h00") + cpu.resp.bits.typ := UInt<1>("h00") + cpu.resp.bits.cmd := UInt<1>("h00") + cpu.resp.bits.tag := UInt<1>("h00") + cpu.resp.bits.addr := UInt<1>("h00") + cpu.resp.valid := UInt<1>("h00") + cpu.req.ready := UInt<1>("h00") + inst wb of WritebackUnit + wb.release.ready := UInt<1>("h00") + wb.data_resp := UInt<1>("h00") + wb.data_req.ready := UInt<1>("h00") + wb.meta_read.ready := UInt<1>("h00") + wb.req.bits.way_en := UInt<1>("h00") + wb.req.bits.voluntary := UInt<1>("h00") + wb.req.bits.r_type := UInt<1>("h00") + wb.req.bits.data := UInt<1>("h00") + wb.req.bits.addr_beat := UInt<1>("h00") + wb.req.bits.client_xact_id := UInt<1>("h00") + wb.req.bits.addr_block := UInt<1>("h00") + wb.req.valid := UInt<1>("h00") + wb.reset := UInt<1>("h00") + wb.clock := clock + wb.reset := reset + inst prober of ProbeUnit + prober.block_state.state := UInt<1>("h00") + prober.mshr_rdy := UInt<1>("h00") + prober.way_en := UInt<1>("h00") + prober.wb_req.ready := UInt<1>("h00") + prober.meta_write.ready := UInt<1>("h00") + prober.meta_read.ready := UInt<1>("h00") + prober.rep.ready := UInt<1>("h00") + prober.req.bits.client_xact_id := UInt<1>("h00") + prober.req.bits.p_type := UInt<1>("h00") + prober.req.bits.addr_block := UInt<1>("h00") + prober.req.valid := UInt<1>("h00") + prober.reset := UInt<1>("h00") + prober.clock := clock + prober.reset := reset + inst mshrs of MSHRFile + mshrs.wb_req.ready := UInt<1>("h00") + mshrs.mem_grant.bits.g_type := UInt<1>("h00") + mshrs.mem_grant.bits.is_builtin_type := UInt<1>("h00") + mshrs.mem_grant.bits.manager_xact_id := UInt<1>("h00") + mshrs.mem_grant.bits.client_xact_id := UInt<1>("h00") + mshrs.mem_grant.bits.data := UInt<1>("h00") + mshrs.mem_grant.bits.addr_beat := UInt<1>("h00") + mshrs.mem_grant.valid := UInt<1>("h00") + mshrs.replay.ready := UInt<1>("h00") + mshrs.meta_write.ready := UInt<1>("h00") + mshrs.meta_read.ready := UInt<1>("h00") + mshrs.mem_req.ready := UInt<1>("h00") + mshrs.req.bits.way_en := UInt<1>("h00") + mshrs.req.bits.old_meta.coh.state := UInt<1>("h00") + mshrs.req.bits.old_meta.tag := UInt<1>("h00") + mshrs.req.bits.tag_match := UInt<1>("h00") + mshrs.req.bits.data := UInt<1>("h00") + mshrs.req.bits.phys := UInt<1>("h00") + mshrs.req.bits.kill := UInt<1>("h00") + mshrs.req.bits.typ := UInt<1>("h00") + mshrs.req.bits.cmd := UInt<1>("h00") + mshrs.req.bits.tag := UInt<1>("h00") + mshrs.req.bits.addr := UInt<1>("h00") + mshrs.req.valid := UInt<1>("h00") + mshrs.reset := UInt<1>("h00") + mshrs.clock := clock + mshrs.reset := reset + cpu.req.ready := UInt<1>("h01") + node T_887 = and(cpu.req.ready, cpu.req.valid) + reg s1_valid : UInt<1>, clock, reset + onreset s1_valid := UInt<1>("h00") + s1_valid := T_887 + reg s1_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clock, reset + node T_899 = eq(cpu.req.bits.kill, UInt<1>("h00")) + node s1_valid_masked = and(s1_valid, T_899) + reg s1_replay : UInt<1>, clock, reset + onreset s1_replay := UInt<1>("h00") + reg s1_clk_en : UInt<1>, clock, reset + reg s2_valid : UInt<1>, clock, reset + onreset s2_valid := UInt<1>("h00") + s2_valid := s1_valid_masked + reg s2_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clock, reset + reg T_916 : UInt<1>, clock, reset + onreset T_916 := UInt<1>("h00") + T_916 := s1_replay + node T_917 = neq(s2_req.cmd, UInt<5>("h05")) + node s2_replay = and(T_916, T_917) + wire s2_recycle : UInt<1> + s2_recycle := UInt<1>("h00") + wire s2_valid_masked : UInt<1> + s2_valid_masked := UInt<1>("h00") + reg s3_valid : UInt<1>, clock, reset + onreset s3_valid := UInt<1>("h00") + reg s3_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clock, reset + reg s3_way : UInt<?>, clock, reset + reg s1_recycled : UInt<1>, clock, reset + onreset s1_recycled := UInt<1>("h00") + when s1_clk_en : + s1_recycled := s2_recycle + skip + node T_939 = eq(s1_req.cmd, UInt<5>("h00")) + node T_940 = eq(s1_req.cmd, UInt<5>("h06")) + node T_941 = or(T_939, T_940) + node T_942 = bit(s1_req.cmd, 3) + node T_943 = eq(s1_req.cmd, UInt<5>("h04")) + node T_944 = or(T_942, T_943) + node s1_read = or(T_941, T_944) + node T_946 = eq(s1_req.cmd, UInt<5>("h01")) + node T_947 = eq(s1_req.cmd, UInt<5>("h07")) + node T_948 = or(T_946, T_947) + node T_949 = bit(s1_req.cmd, 3) + node T_950 = eq(s1_req.cmd, UInt<5>("h04")) + node T_951 = or(T_949, T_950) + node s1_write = or(T_948, T_951) + node s1_sc = eq(s1_req.cmd, UInt<5>("h07")) + node T_954 = or(s1_read, s1_write) + node T_955 = eq(s1_req.cmd, UInt<5>("h02")) + node T_956 = eq(s1_req.cmd, UInt<5>("h03")) + node T_957 = or(T_955, T_956) + node s1_readwrite = or(T_954, T_957) + inst dtlb of TLB_60 + dtlb.ptw.invalidate := UInt<1>("h00") + dtlb.ptw.status.ie := UInt<1>("h00") + dtlb.ptw.status.prv := UInt<1>("h00") + dtlb.ptw.status.ie1 := UInt<1>("h00") + dtlb.ptw.status.prv1 := UInt<1>("h00") + dtlb.ptw.status.ie2 := UInt<1>("h00") + dtlb.ptw.status.prv2 := UInt<1>("h00") + dtlb.ptw.status.ie3 := UInt<1>("h00") + dtlb.ptw.status.prv3 := UInt<1>("h00") + dtlb.ptw.status.fs := UInt<1>("h00") + dtlb.ptw.status.xs := UInt<1>("h00") + dtlb.ptw.status.mprv := UInt<1>("h00") + dtlb.ptw.status.vm := UInt<1>("h00") + dtlb.ptw.status.zero1 := UInt<1>("h00") + dtlb.ptw.status.sd_rv32 := UInt<1>("h00") + dtlb.ptw.status.zero2 := UInt<1>("h00") + dtlb.ptw.status.sd := UInt<1>("h00") + dtlb.ptw.resp.bits.pte.v := UInt<1>("h00") + dtlb.ptw.resp.bits.pte.typ := UInt<1>("h00") + dtlb.ptw.resp.bits.pte.r := UInt<1>("h00") + dtlb.ptw.resp.bits.pte.d := UInt<1>("h00") + dtlb.ptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") + dtlb.ptw.resp.bits.pte.ppn := UInt<1>("h00") + dtlb.ptw.resp.bits.error := UInt<1>("h00") + dtlb.ptw.resp.valid := UInt<1>("h00") + dtlb.ptw.req.ready := UInt<1>("h00") + dtlb.req.bits.store := UInt<1>("h00") + dtlb.req.bits.instruction := UInt<1>("h00") + dtlb.req.bits.passthrough := UInt<1>("h00") + dtlb.req.bits.vpn := UInt<1>("h00") + dtlb.req.bits.asid := UInt<1>("h00") + dtlb.req.valid := UInt<1>("h00") + dtlb.reset := UInt<1>("h00") + dtlb.clock := clock + dtlb.reset := reset + ptw <> dtlb.ptw + node T_992 = and(s1_valid_masked, s1_readwrite) + node T_994 = eq(s1_req.phys, UInt<1>("h00")) + node T_995 = and(T_992, T_994) + dtlb.req.valid := T_995 + dtlb.req.bits.passthrough := s1_req.phys + dtlb.req.bits.asid := UInt<1>("h00") + node T_997 = shr(s1_req.addr, 12) + dtlb.req.bits.vpn := T_997 + dtlb.req.bits.instruction := UInt<1>("h00") + dtlb.req.bits.store := s1_write + node T_1000 = eq(dtlb.req.ready, UInt<1>("h00")) + node T_1002 = eq(cpu.req.bits.phys, UInt<1>("h00")) + node T_1003 = and(T_1000, T_1002) + when T_1003 : + cpu.req.ready := UInt<1>("h00") + skip + when cpu.req.valid : + s1_req <> cpu.req.bits + skip + when wb.meta_read.valid : + node T_1005 = cat(wb.meta_read.bits.tag, wb.meta_read.bits.idx) + node T_1006 = shl(T_1005, 6) + s1_req.addr := T_1006 + s1_req.phys := UInt<1>("h01") + skip + when prober.meta_read.valid : + node T_1008 = cat(prober.meta_read.bits.tag, prober.meta_read.bits.idx) + node T_1009 = shl(T_1008, 6) + s1_req.addr := T_1009 + s1_req.phys := UInt<1>("h01") + skip + when mshrs.replay.valid : + s1_req <> mshrs.replay.bits + skip + when s2_recycle : + s1_req <> s2_req + skip + node T_1011 = bits(s1_req.addr, 11, 0) + node s1_addr = cat(dtlb.resp.ppn, T_1011) + when s1_clk_en : + s2_req.kill := s1_req.kill + s2_req.typ := s1_req.typ + s2_req.phys := s1_req.phys + s2_req.addr := s1_addr + when s1_write : + node T_1013 = mux(s1_replay, mshrs.replay.bits.data, cpu.req.bits.data) + s2_req.data := T_1013 + skip + when s1_recycled : + s2_req.data := s1_req.data + skip + s2_req.tag := s1_req.tag + s2_req.cmd := s1_req.cmd + skip + node T_1014 = eq(s1_req.typ, UInt<3>("h01")) + node T_1015 = eq(s1_req.typ, UInt<3>("h05")) + node T_1016 = or(T_1014, T_1015) + node T_1017 = bit(s1_req.addr, 0) + node T_1019 = neq(T_1017, UInt<1>("h00")) + node T_1020 = and(T_1016, T_1019) + node T_1021 = eq(s1_req.typ, UInt<3>("h02")) + node T_1022 = eq(s1_req.typ, UInt<3>("h06")) + node T_1023 = or(T_1021, T_1022) + node T_1024 = bits(s1_req.addr, 1, 0) + node T_1026 = neq(T_1024, UInt<1>("h00")) + node T_1027 = and(T_1023, T_1026) + node T_1028 = or(T_1020, T_1027) + node T_1029 = eq(s1_req.typ, UInt<3>("h03")) + node T_1030 = bits(s1_req.addr, 2, 0) + node T_1032 = neq(T_1030, UInt<1>("h00")) + node T_1033 = and(T_1029, T_1032) + node misaligned = or(T_1028, T_1033) + node T_1035 = and(s1_read, misaligned) + cpu.xcpt.ma.ld := T_1035 + node T_1036 = and(s1_write, misaligned) + cpu.xcpt.ma.st := T_1036 + node T_1038 = eq(s1_req.phys, UInt<1>("h00")) + node T_1039 = and(T_1038, s1_read) + node T_1040 = and(T_1039, dtlb.resp.xcpt_ld) + cpu.xcpt.pf.ld := T_1040 + node T_1042 = eq(s1_req.phys, UInt<1>("h00")) + node T_1043 = and(T_1042, s1_write) + node T_1044 = and(T_1043, dtlb.resp.xcpt_st) + cpu.xcpt.pf.st := T_1044 + node T_1045 = or(cpu.xcpt.ma.ld, cpu.xcpt.ma.st) + node T_1046 = or(T_1045, cpu.xcpt.pf.ld) + node T_1047 = or(T_1046, cpu.xcpt.pf.st) + reg T_1048 : UInt<1>, clock, reset + T_1048 := T_1047 + node T_1049 = and(T_1048, cpu.resp.valid) + node T_1051 = eq(T_1049, UInt<1>("h00")) + inst meta of MetadataArray + meta.write.bits.data.coh.state := UInt<1>("h00") + meta.write.bits.data.tag := UInt<1>("h00") + meta.write.bits.way_en := UInt<1>("h00") + meta.write.bits.idx := UInt<1>("h00") + meta.write.valid := UInt<1>("h00") + meta.read.bits.idx := UInt<1>("h00") + meta.read.valid := UInt<1>("h00") + meta.reset := UInt<1>("h00") + meta.clock := clock + meta.reset := reset + inst metaReadArb of Arbiter_62 + metaReadArb.out.ready := UInt<1>("h00") + metaReadArb.in[0].bits.idx := UInt<1>("h00") + metaReadArb.in[0].valid := UInt<1>("h00") + metaReadArb.in[1].bits.idx := UInt<1>("h00") + metaReadArb.in[1].valid := UInt<1>("h00") + metaReadArb.in[2].bits.idx := UInt<1>("h00") + metaReadArb.in[2].valid := UInt<1>("h00") + metaReadArb.in[3].bits.idx := UInt<1>("h00") + metaReadArb.in[3].valid := UInt<1>("h00") + metaReadArb.in[4].bits.idx := UInt<1>("h00") + metaReadArb.in[4].valid := UInt<1>("h00") + metaReadArb.reset := UInt<1>("h00") + metaReadArb.clock := clock + metaReadArb.reset := reset + inst metaWriteArb of Arbiter_53 + metaWriteArb.out.ready := UInt<1>("h00") + metaWriteArb.in[0].bits.data.coh.state := UInt<1>("h00") + metaWriteArb.in[0].bits.data.tag := UInt<1>("h00") + metaWriteArb.in[0].bits.way_en := UInt<1>("h00") + metaWriteArb.in[0].bits.idx := UInt<1>("h00") + metaWriteArb.in[0].valid := UInt<1>("h00") + metaWriteArb.in[1].bits.data.coh.state := UInt<1>("h00") + metaWriteArb.in[1].bits.data.tag := UInt<1>("h00") + metaWriteArb.in[1].bits.way_en := UInt<1>("h00") + metaWriteArb.in[1].bits.idx := UInt<1>("h00") + metaWriteArb.in[1].valid := UInt<1>("h00") + metaWriteArb.reset := UInt<1>("h00") + metaWriteArb.clock := clock + metaWriteArb.reset := reset + meta.read <> metaReadArb.out + meta.write <> metaWriteArb.out + inst data of DataArray + data.write.bits.data := UInt<1>("h00") + data.write.bits.wmask := UInt<1>("h00") + data.write.bits.addr := UInt<1>("h00") + data.write.bits.way_en := UInt<1>("h00") + data.write.valid := UInt<1>("h00") + data.read.bits.addr := UInt<1>("h00") + data.read.bits.way_en := UInt<1>("h00") + data.read.valid := UInt<1>("h00") + data.reset := UInt<1>("h00") + data.clock := clock + data.reset := reset + inst readArb of Arbiter_64 + readArb.out.ready := UInt<1>("h00") + readArb.in[0].bits.addr := UInt<1>("h00") + readArb.in[0].bits.way_en := UInt<1>("h00") + readArb.in[0].valid := UInt<1>("h00") + readArb.in[1].bits.addr := UInt<1>("h00") + readArb.in[1].bits.way_en := UInt<1>("h00") + readArb.in[1].valid := UInt<1>("h00") + readArb.in[2].bits.addr := UInt<1>("h00") + readArb.in[2].bits.way_en := UInt<1>("h00") + readArb.in[2].valid := UInt<1>("h00") + readArb.in[3].bits.addr := UInt<1>("h00") + readArb.in[3].bits.way_en := UInt<1>("h00") + readArb.in[3].valid := UInt<1>("h00") + readArb.reset := UInt<1>("h00") + readArb.clock := clock + readArb.reset := reset + inst writeArb of Arbiter_65 + writeArb.out.ready := UInt<1>("h00") + writeArb.in[0].bits.data := UInt<1>("h00") + writeArb.in[0].bits.wmask := UInt<1>("h00") + writeArb.in[0].bits.addr := UInt<1>("h00") + writeArb.in[0].bits.way_en := UInt<1>("h00") + writeArb.in[0].valid := UInt<1>("h00") + writeArb.in[1].bits.data := UInt<1>("h00") + writeArb.in[1].bits.wmask := UInt<1>("h00") + writeArb.in[1].bits.addr := UInt<1>("h00") + writeArb.in[1].bits.way_en := UInt<1>("h00") + writeArb.in[1].valid := UInt<1>("h00") + writeArb.reset := UInt<1>("h00") + writeArb.clock := clock + writeArb.reset := reset + data.write.valid := writeArb.out.valid + writeArb.out.ready := data.write.ready + data.write.bits <> writeArb.out.bits + node T_1186 = bits(writeArb.out.bits.data, 63, 0) + node T_1187 = bits(writeArb.out.bits.data, 127, 64) + wire T_1189 : UInt<64>[2] + T_1189[0] := T_1186 + T_1189[1] := T_1187 + node T_1193 = cat(T_1189[1], T_1189[0]) + data.write.bits.data := T_1193 + metaReadArb.in[4].valid := cpu.req.valid + node T_1194 = shr(cpu.req.bits.addr, 6) + metaReadArb.in[4].bits.idx := T_1194 + node T_1196 = eq(metaReadArb.in[4].ready, UInt<1>("h00")) + when T_1196 : + cpu.req.ready := UInt<1>("h00") + skip + readArb.in[3].valid := cpu.req.valid + readArb.in[3].bits.addr := cpu.req.bits.addr + node T_1199 = not(UInt<4>("h00")) + readArb.in[3].bits.way_en := T_1199 + node T_1201 = eq(readArb.in[3].ready, UInt<1>("h00")) + when T_1201 : + cpu.req.ready := UInt<1>("h00") + skip + metaReadArb.in[0].valid := s2_recycle + node T_1203 = shr(s2_req.addr, 6) + metaReadArb.in[0].bits.idx := T_1203 + readArb.in[0].valid := s2_recycle + readArb.in[0].bits.addr := s2_req.addr + node T_1205 = not(UInt<4>("h00")) + readArb.in[0].bits.way_en := T_1205 + node T_1206 = shr(s1_addr, 12) + node T_1207 = eq(meta.resp[0].tag, T_1206) + node T_1208 = shr(s1_addr, 12) + node T_1209 = eq(meta.resp[1].tag, T_1208) + node T_1210 = shr(s1_addr, 12) + node T_1211 = eq(meta.resp[2].tag, T_1210) + node T_1212 = shr(s1_addr, 12) + node T_1213 = eq(meta.resp[3].tag, T_1212) + wire T_1215 : UInt<1>[4] + T_1215[0] := T_1207 + T_1215[1] := T_1209 + T_1215[2] := T_1211 + T_1215[3] := T_1213 + node T_1221 = cat(T_1215[3], T_1215[2]) + node T_1222 = cat(T_1215[1], T_1215[0]) + node s1_tag_eq_way = cat(T_1221, T_1222) + node T_1224 = bit(s1_tag_eq_way, 0) + node T_1225 = neq(meta.resp[0].coh.state, UInt<1>("h00")) + node T_1226 = and(T_1224, T_1225) + node T_1227 = bit(s1_tag_eq_way, 1) + node T_1228 = neq(meta.resp[1].coh.state, UInt<1>("h00")) + node T_1229 = and(T_1227, T_1228) + node T_1230 = bit(s1_tag_eq_way, 2) + node T_1231 = neq(meta.resp[2].coh.state, UInt<1>("h00")) + node T_1232 = and(T_1230, T_1231) + node T_1233 = bit(s1_tag_eq_way, 3) + node T_1234 = neq(meta.resp[3].coh.state, UInt<1>("h00")) + node T_1235 = and(T_1233, T_1234) + wire T_1237 : UInt<1>[4] + T_1237[0] := T_1226 + T_1237[1] := T_1229 + T_1237[2] := T_1232 + T_1237[3] := T_1235 + node T_1243 = cat(T_1237[3], T_1237[2]) + node T_1244 = cat(T_1237[1], T_1237[0]) + node s1_tag_match_way = cat(T_1243, T_1244) + s1_clk_en := metaReadArb.out.valid + node T_1247 = eq(s1_valid, UInt<1>("h00")) + node T_1248 = and(s1_clk_en, T_1247) + node T_1250 = eq(s1_replay, UInt<1>("h00")) + node s1_writeback = and(T_1248, T_1250) + reg s2_tag_match_way : UInt<4>, clock, reset + when s1_clk_en : + s2_tag_match_way := s1_tag_match_way + skip + node s2_tag_match = neq(s2_tag_match_way, UInt<1>("h00")) + reg T_1255 : {state : UInt<2>}, clock, reset + when s1_clk_en : + T_1255 <> meta.resp[0].coh + skip + reg T_1280 : {state : UInt<2>}, clock, reset + when s1_clk_en : + T_1280 <> meta.resp[1].coh + skip + reg T_1305 : {state : UInt<2>}, clock, reset + when s1_clk_en : + T_1305 <> meta.resp[2].coh + skip + reg T_1330 : {state : UInt<2>}, clock, reset + when s1_clk_en : + T_1330 <> meta.resp[3].coh + skip + wire T_1380 : {state : UInt<2>}[4] + T_1380[0] <> T_1255 + T_1380[1] <> T_1280 + T_1380[2] <> T_1305 + T_1380[3] <> T_1330 + node T_1506 = bit(s2_tag_match_way, 0) + node T_1507 = bit(s2_tag_match_way, 1) + node T_1508 = bit(s2_tag_match_way, 2) + node T_1509 = bit(s2_tag_match_way, 3) + node T_1511 = mux(T_1506, T_1380[0].state, UInt<1>("h00")) + node T_1513 = mux(T_1507, T_1380[1].state, UInt<1>("h00")) + node T_1515 = mux(T_1508, T_1380[2].state, UInt<1>("h00")) + node T_1517 = mux(T_1509, T_1380[3].state, UInt<1>("h00")) + node T_1543 = or(T_1511, T_1513) + node T_1544 = or(T_1543, T_1515) + node T_1545 = or(T_1544, T_1517) + wire s2_hit_state : {state : UInt<2>} + s2_hit_state.state := UInt<1>("h00") + node T_1597 = bits(T_1545, 1, 0) + s2_hit_state.state := T_1597 + node T_1598 = eq(s2_req.cmd, UInt<5>("h01")) + node T_1599 = eq(s2_req.cmd, UInt<5>("h07")) + node T_1600 = or(T_1598, T_1599) + node T_1601 = bit(s2_req.cmd, 3) + node T_1602 = eq(s2_req.cmd, UInt<5>("h04")) + node T_1603 = or(T_1601, T_1602) + node T_1604 = or(T_1600, T_1603) + node T_1605 = eq(s2_req.cmd, UInt<5>("h03")) + node T_1606 = or(T_1604, T_1605) + node T_1607 = eq(s2_req.cmd, UInt<5>("h06")) + node T_1608 = or(T_1606, T_1607) + wire T_1610 : UInt<2>[2] + T_1610[0] := UInt<2>("h02") + T_1610[1] := UInt<2>("h03") + node T_1614 = eq(T_1610[0], s2_hit_state.state) + node T_1615 = eq(T_1610[1], s2_hit_state.state) + node T_1617 = or(UInt<1>("h00"), T_1614) + node T_1618 = or(T_1617, T_1615) + wire T_1620 : UInt<2>[3] + T_1620[0] := UInt<1>("h01") + T_1620[1] := UInt<2>("h02") + T_1620[2] := UInt<2>("h03") + node T_1625 = eq(T_1620[0], s2_hit_state.state) + node T_1626 = eq(T_1620[1], s2_hit_state.state) + node T_1627 = eq(T_1620[2], s2_hit_state.state) + node T_1629 = or(UInt<1>("h00"), T_1625) + node T_1630 = or(T_1629, T_1626) + node T_1631 = or(T_1630, T_1627) + node T_1632 = mux(T_1608, T_1618, T_1631) + node T_1633 = and(s2_tag_match, T_1632) + node T_1634 = eq(s2_req.cmd, UInt<5>("h01")) + node T_1635 = eq(s2_req.cmd, UInt<5>("h07")) + node T_1636 = or(T_1634, T_1635) + node T_1637 = bit(s2_req.cmd, 3) + node T_1638 = eq(s2_req.cmd, UInt<5>("h04")) + node T_1639 = or(T_1637, T_1638) + node T_1640 = or(T_1636, T_1639) + node T_1641 = mux(T_1640, UInt<2>("h03"), s2_hit_state.state) + wire T_1667 : {state : UInt<2>} + T_1667.state := UInt<1>("h00") + T_1667.state := T_1641 + node T_1693 = eq(s2_hit_state.state, T_1667.state) + node s2_hit = and(T_1633, T_1693) + reg lrsc_count : UInt<?>, clock, reset + onreset lrsc_count := UInt<1>("h00") + node lrsc_valid = neq(lrsc_count, UInt<1>("h00")) + reg lrsc_addr : UInt<?>, clock, reset + node s2_lr = eq(s2_req.cmd, UInt<5>("h06")) + node s2_sc = eq(s2_req.cmd, UInt<5>("h07")) + node T_1703 = shr(s2_req.addr, 6) + node T_1704 = eq(lrsc_addr, T_1703) + node s2_lrsc_addr_match = and(lrsc_valid, T_1704) + node T_1707 = eq(s2_lrsc_addr_match, UInt<1>("h00")) + node s2_sc_fail = and(s2_sc, T_1707) + when lrsc_valid : + node T_1710 = subw(lrsc_count, UInt<1>("h01")) + lrsc_count := T_1710 + skip + node T_1711 = and(s2_valid_masked, s2_hit) + node T_1712 = or(T_1711, s2_replay) + when T_1712 : + when s2_lr : + node T_1714 = eq(lrsc_valid, UInt<1>("h00")) + when T_1714 : + lrsc_count := UInt<5>("h01f") + skip + node T_1716 = shr(s2_req.addr, 6) + lrsc_addr := T_1716 + skip + when s2_sc : + lrsc_count := UInt<1>("h00") + skip + skip + when cpu.invalidate_lr : + lrsc_count := UInt<1>("h00") + skip + wire s2_data : UInt<128>[4] + s2_data[0] := UInt<1>("h00") + s2_data[1] := UInt<1>("h00") + s2_data[2] := UInt<1>("h00") + s2_data[3] := UInt<1>("h00") + reg T_1747 : UInt<64>[2], clock, reset + node T_1751 = bit(s1_tag_eq_way, 0) + node T_1752 = and(s1_clk_en, T_1751) + node T_1756 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_1757 = or(UInt<1>("h01"), T_1756) + node T_1758 = or(T_1757, s1_writeback) + node T_1759 = and(T_1752, T_1758) + when T_1759 : + node T_1760 = shr(data.resp[0], 0) + T_1747[0] := T_1760 + skip + node T_1764 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_1765 = or(UInt<1>("h00"), T_1764) + node T_1766 = or(T_1765, s1_writeback) + node T_1767 = and(T_1752, T_1766) + when T_1767 : + node T_1768 = shr(data.resp[0], 64) + T_1747[1] := T_1768 + skip + node T_1769 = cat(T_1747[1], T_1747[0]) + s2_data[0] := T_1769 + reg T_1778 : UInt<64>[2], clock, reset + node T_1782 = bit(s1_tag_eq_way, 1) + node T_1783 = and(s1_clk_en, T_1782) + node T_1787 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_1788 = or(UInt<1>("h01"), T_1787) + node T_1789 = or(T_1788, s1_writeback) + node T_1790 = and(T_1783, T_1789) + when T_1790 : + node T_1791 = shr(data.resp[1], 0) + T_1778[0] := T_1791 + skip + node T_1795 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_1796 = or(UInt<1>("h00"), T_1795) + node T_1797 = or(T_1796, s1_writeback) + node T_1798 = and(T_1783, T_1797) + when T_1798 : + node T_1799 = shr(data.resp[1], 64) + T_1778[1] := T_1799 + skip + node T_1800 = cat(T_1778[1], T_1778[0]) + s2_data[1] := T_1800 + reg T_1809 : UInt<64>[2], clock, reset + node T_1813 = bit(s1_tag_eq_way, 2) + node T_1814 = and(s1_clk_en, T_1813) + node T_1818 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_1819 = or(UInt<1>("h01"), T_1818) + node T_1820 = or(T_1819, s1_writeback) + node T_1821 = and(T_1814, T_1820) + when T_1821 : + node T_1822 = shr(data.resp[2], 0) + T_1809[0] := T_1822 + skip + node T_1826 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_1827 = or(UInt<1>("h00"), T_1826) + node T_1828 = or(T_1827, s1_writeback) + node T_1829 = and(T_1814, T_1828) + when T_1829 : + node T_1830 = shr(data.resp[2], 64) + T_1809[1] := T_1830 + skip + node T_1831 = cat(T_1809[1], T_1809[0]) + s2_data[2] := T_1831 + reg T_1840 : UInt<64>[2], clock, reset + node T_1844 = bit(s1_tag_eq_way, 3) + node T_1845 = and(s1_clk_en, T_1844) + node T_1849 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_1850 = or(UInt<1>("h01"), T_1849) + node T_1851 = or(T_1850, s1_writeback) + node T_1852 = and(T_1845, T_1851) + when T_1852 : + node T_1853 = shr(data.resp[3], 0) + T_1840[0] := T_1853 + skip + node T_1857 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_1858 = or(UInt<1>("h00"), T_1857) + node T_1859 = or(T_1858, s1_writeback) + node T_1860 = and(T_1845, T_1859) + when T_1860 : + node T_1861 = shr(data.resp[3], 64) + T_1840[1] := T_1861 + skip + node T_1862 = cat(T_1840[1], T_1840[0]) + s2_data[3] := T_1862 + node T_1863 = bit(s2_tag_match_way, 0) + node T_1864 = bit(s2_tag_match_way, 1) + node T_1865 = bit(s2_tag_match_way, 2) + node T_1866 = bit(s2_tag_match_way, 3) + node T_1868 = mux(T_1863, s2_data[0], UInt<1>("h00")) + node T_1870 = mux(T_1864, s2_data[1], UInt<1>("h00")) + node T_1872 = mux(T_1865, s2_data[2], UInt<1>("h00")) + node T_1874 = mux(T_1866, s2_data[3], UInt<1>("h00")) + node T_1876 = or(T_1868, T_1870) + node T_1877 = or(T_1876, T_1872) + node T_1878 = or(T_1877, T_1874) + wire s2_data_muxed : UInt<128> + s2_data_muxed := UInt<1>("h00") + s2_data_muxed := T_1878 + node T_1881 = bits(s2_data_muxed, 63, 0) + node T_1882 = bits(s2_data_muxed, 127, 64) + wire T_1884 : UInt<64>[2] + T_1884[0] := T_1881 + T_1884[1] := T_1882 + node s2_data_corrected = cat(T_1884[1], T_1884[0]) + wire T_1890 : UInt<64>[2] + T_1890[0] := T_1881 + T_1890[1] := T_1882 + node s2_data_uncorrected = cat(T_1890[1], T_1890[0]) + wire T_1899 : UInt<1>[2] + T_1899[0] := UInt<1>("h00") + T_1899[1] := UInt<1>("h00") + node T_1903 = cat(T_1899[1], T_1899[0]) + node T_1904 = dshr(T_1903, UInt<1>("h00")) + node s2_data_correctable = bit(T_1904, 0) + node T_1906 = and(s2_valid_masked, s2_hit) + node T_1907 = or(T_1906, s2_replay) + node T_1909 = eq(s2_sc_fail, UInt<1>("h00")) + node T_1910 = and(T_1907, T_1909) + node T_1911 = eq(s2_req.cmd, UInt<5>("h01")) + node T_1912 = eq(s2_req.cmd, UInt<5>("h07")) + node T_1913 = or(T_1911, T_1912) + node T_1914 = bit(s2_req.cmd, 3) + node T_1915 = eq(s2_req.cmd, UInt<5>("h04")) + node T_1916 = or(T_1914, T_1915) + node T_1917 = or(T_1913, T_1916) + node T_1918 = and(T_1910, T_1917) + s3_valid := T_1918 + inst amoalu of AMOALU + amoalu.rhs := UInt<1>("h00") + amoalu.lhs := UInt<1>("h00") + amoalu.typ := UInt<1>("h00") + amoalu.cmd := UInt<1>("h00") + amoalu.addr := UInt<1>("h00") + amoalu.reset := UInt<1>("h00") + amoalu.clock := clock + amoalu.reset := reset + node T_1925 = or(s2_valid, s2_replay) + node T_1926 = eq(s2_req.cmd, UInt<5>("h01")) + node T_1927 = eq(s2_req.cmd, UInt<5>("h07")) + node T_1928 = or(T_1926, T_1927) + node T_1929 = bit(s2_req.cmd, 3) + node T_1930 = eq(s2_req.cmd, UInt<5>("h04")) + node T_1931 = or(T_1929, T_1930) + node T_1932 = or(T_1928, T_1931) + node T_1933 = or(T_1932, s2_data_correctable) + node T_1934 = and(T_1925, T_1933) + when T_1934 : + s3_req <> s2_req + node T_1935 = mux(s2_data_correctable, s2_data_corrected, amoalu.out) + s3_req.data := T_1935 + s3_way := s2_tag_match_way + skip + writeArb.in[0].bits.addr := s3_req.addr + node rowIdx = bits(s3_req.addr, 3, 3) + node rowWMask = dshl(UInt<1>("h01"), rowIdx) + writeArb.in[0].bits.wmask := rowWMask + node T_1939 = cat(s3_req.data, s3_req.data) + writeArb.in[0].bits.data := T_1939 + writeArb.in[0].valid := s3_valid + writeArb.in[0].bits.way_en := s3_way + wire T_1941 : UInt<1> + T_1941 := UInt<1>("h00") + T_1941 := UInt<1>("h00") + reg T_1945 : UInt<16>, clock, reset + onreset T_1945 := UInt<16>("h01") + when T_1941 : + node T_1946 = bit(T_1945, 0) + node T_1947 = bit(T_1945, 2) + node T_1948 = xor(T_1946, T_1947) + node T_1949 = bit(T_1945, 3) + node T_1950 = xor(T_1948, T_1949) + node T_1951 = bit(T_1945, 5) + node T_1952 = xor(T_1950, T_1951) + node T_1953 = bits(T_1945, 15, 1) + node T_1954 = cat(T_1952, T_1953) + T_1945 := T_1954 + skip + node T_1955 = bits(T_1945, 1, 0) + node s1_replaced_way_en = dshl(UInt<1>("h01"), T_1955) + node T_1958 = bits(T_1945, 1, 0) + reg T_1959 : UInt<2>, clock, reset + when s1_clk_en : + T_1959 := T_1958 + skip + node s2_replaced_way_en = dshl(UInt<1>("h01"), T_1959) + node T_1962 = bit(s1_replaced_way_en, 0) + node T_1963 = and(s1_clk_en, T_1962) + reg T_1964 : {tag : UInt<20>, coh : {state : UInt<2>}}, clock, reset + when T_1963 : + T_1964 <> meta.resp[0] + skip + node T_1991 = bit(s1_replaced_way_en, 1) + node T_1992 = and(s1_clk_en, T_1991) + reg T_1993 : {tag : UInt<20>, coh : {state : UInt<2>}}, clock, reset + when T_1992 : + T_1993 <> meta.resp[1] + skip + node T_2020 = bit(s1_replaced_way_en, 2) + node T_2021 = and(s1_clk_en, T_2020) + reg T_2022 : {tag : UInt<20>, coh : {state : UInt<2>}}, clock, reset + when T_2021 : + T_2022 <> meta.resp[2] + skip + node T_2049 = bit(s1_replaced_way_en, 3) + node T_2050 = and(s1_clk_en, T_2049) + reg T_2051 : {tag : UInt<20>, coh : {state : UInt<2>}}, clock, reset + when T_2050 : + T_2051 <> meta.resp[3] + skip + wire T_2105 : {tag : UInt<20>, coh : {state : UInt<2>}}[4] + T_2105[0] <> T_1964 + T_2105[1] <> T_1993 + T_2105[2] <> T_2022 + T_2105[3] <> T_2051 + node T_2241 = bit(s2_replaced_way_en, 0) + node T_2242 = bit(s2_replaced_way_en, 1) + node T_2243 = bit(s2_replaced_way_en, 2) + node T_2244 = bit(s2_replaced_way_en, 3) + node T_2245 = cat(T_2105[0].tag, T_2105[0].coh.state) + node T_2247 = mux(T_2241, T_2245, UInt<1>("h00")) + node T_2248 = cat(T_2105[1].tag, T_2105[1].coh.state) + node T_2250 = mux(T_2242, T_2248, UInt<1>("h00")) + node T_2251 = cat(T_2105[2].tag, T_2105[2].coh.state) + node T_2253 = mux(T_2243, T_2251, UInt<1>("h00")) + node T_2254 = cat(T_2105[3].tag, T_2105[3].coh.state) + node T_2256 = mux(T_2244, T_2254, UInt<1>("h00")) + node T_2284 = or(T_2247, T_2250) + node T_2285 = or(T_2284, T_2253) + node T_2286 = or(T_2285, T_2256) + wire s2_repl_meta : {tag : UInt<20>, coh : {state : UInt<2>}} + s2_repl_meta.coh.state := UInt<1>("h00") + s2_repl_meta.tag := UInt<1>("h00") + node T_2343 = bits(T_2286, 1, 0) + s2_repl_meta.coh.state := T_2343 + node T_2344 = bits(T_2286, 21, 2) + s2_repl_meta.tag := T_2344 + node T_2346 = eq(s2_hit, UInt<1>("h00")) + node T_2347 = and(s2_valid_masked, T_2346) + node T_2348 = eq(s2_req.cmd, UInt<5>("h02")) + node T_2349 = eq(s2_req.cmd, UInt<5>("h03")) + node T_2350 = or(T_2348, T_2349) + node T_2351 = eq(s2_req.cmd, UInt<5>("h00")) + node T_2352 = eq(s2_req.cmd, UInt<5>("h06")) + node T_2353 = or(T_2351, T_2352) + node T_2354 = bit(s2_req.cmd, 3) + node T_2355 = eq(s2_req.cmd, UInt<5>("h04")) + node T_2356 = or(T_2354, T_2355) + node T_2357 = or(T_2353, T_2356) + node T_2358 = or(T_2350, T_2357) + node T_2359 = eq(s2_req.cmd, UInt<5>("h01")) + node T_2360 = eq(s2_req.cmd, UInt<5>("h07")) + node T_2361 = or(T_2359, T_2360) + node T_2362 = bit(s2_req.cmd, 3) + node T_2363 = eq(s2_req.cmd, UInt<5>("h04")) + node T_2364 = or(T_2362, T_2363) + node T_2365 = or(T_2361, T_2364) + node T_2366 = or(T_2358, T_2365) + node T_2367 = and(T_2347, T_2366) + mshrs.req.valid := T_2367 + mshrs.req.bits <> s2_req + mshrs.req.bits.tag_match := s2_tag_match + wire T_2395 : {tag : UInt<20>, coh : {state : UInt<2>}} + T_2395.coh.state := UInt<1>("h00") + T_2395.tag := UInt<1>("h00") + T_2395.tag := s2_repl_meta.tag + T_2395.coh <> s2_hit_state + wire T_2451 : {tag : UInt<20>, coh : {state : UInt<2>}} + T_2451 <> s2_repl_meta + when s2_tag_match : + T_2451 <> T_2395 + skip + mshrs.req.bits.old_meta <> T_2451 + node T_2478 = mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en) + mshrs.req.bits.way_en := T_2478 + mshrs.req.bits.data := s2_req.data + node T_2479 = and(mshrs.req.ready, mshrs.req.valid) + when T_2479 : + T_1941 := UInt<1>("h01") + skip + mem_1.acquire <> mshrs.mem_req + readArb.in[1].valid := mshrs.replay.valid + readArb.in[1].bits <> mshrs.replay.bits + node T_2482 = not(UInt<4>("h00")) + readArb.in[1].bits.way_en := T_2482 + mshrs.replay.ready := readArb.in[1].ready + node T_2483 = and(mshrs.replay.valid, readArb.in[1].ready) + s1_replay := T_2483 + metaReadArb.in[1] <> mshrs.meta_read + metaWriteArb.in[0] <> mshrs.meta_write + inst releaseArb of LockingArbiter_66 + releaseArb.out.ready := UInt<1>("h00") + releaseArb.in[0].bits.voluntary := UInt<1>("h00") + releaseArb.in[0].bits.r_type := UInt<1>("h00") + releaseArb.in[0].bits.data := UInt<1>("h00") + releaseArb.in[0].bits.addr_beat := UInt<1>("h00") + releaseArb.in[0].bits.client_xact_id := UInt<1>("h00") + releaseArb.in[0].bits.addr_block := UInt<1>("h00") + releaseArb.in[0].valid := UInt<1>("h00") + releaseArb.in[1].bits.voluntary := UInt<1>("h00") + releaseArb.in[1].bits.r_type := UInt<1>("h00") + releaseArb.in[1].bits.data := UInt<1>("h00") + releaseArb.in[1].bits.addr_beat := UInt<1>("h00") + releaseArb.in[1].bits.client_xact_id := UInt<1>("h00") + releaseArb.in[1].bits.addr_block := UInt<1>("h00") + releaseArb.in[1].valid := UInt<1>("h00") + releaseArb.reset := UInt<1>("h00") + releaseArb.clock := clock + releaseArb.reset := reset + mem_1.release <> releaseArb.out + node T_2531 = eq(lrsc_valid, UInt<1>("h00")) + node T_2532 = and(mem_1.probe.valid, T_2531) + prober.req.valid := T_2532 + node T_2534 = eq(lrsc_valid, UInt<1>("h00")) + node T_2535 = and(prober.req.ready, T_2534) + mem_1.probe.ready := T_2535 + prober.req.bits <> mem_1.probe.bits + releaseArb.in[1] <> prober.rep + prober.way_en := s2_tag_match_way + prober.block_state <> s2_hit_state + metaReadArb.in[2] <> prober.meta_read + metaWriteArb.in[1] <> prober.meta_write + prober.mshr_rdy := mshrs.probe_rdy + inst T_2836 of FlowThroughSerializer + T_2836.out.ready := UInt<1>("h00") + T_2836.in.bits.g_type := UInt<1>("h00") + T_2836.in.bits.is_builtin_type := UInt<1>("h00") + T_2836.in.bits.manager_xact_id := UInt<1>("h00") + T_2836.in.bits.client_xact_id := UInt<1>("h00") + T_2836.in.bits.data := UInt<1>("h00") + T_2836.in.bits.addr_beat := UInt<1>("h00") + T_2836.in.valid := UInt<1>("h00") + T_2836.reset := UInt<1>("h00") + T_2836.clock := clock + T_2836.reset := reset + T_2836.in.valid := mem_1.grant.valid + T_2836.in.bits <> mem_1.grant.bits + mem_1.grant.ready := T_2836.in.ready + node T_2545 = and(T_2836.out.ready, T_2836.out.valid) + mshrs.mem_grant.valid := T_2545 + mshrs.mem_grant.bits <> T_2836.out.bits + wire T_2549 : UInt<3>[2] + T_2549[0] := UInt<3>("h05") + T_2549[1] := UInt<3>("h04") + node T_2553 = eq(T_2549[0], T_2836.out.bits.g_type) + node T_2554 = eq(T_2549[1], T_2836.out.bits.g_type) + node T_2556 = or(UInt<1>("h00"), T_2553) + node T_2557 = or(T_2556, T_2554) + wire T_2559 : UInt<1>[2] + T_2559[0] := UInt<1>("h00") + T_2559[1] := UInt<1>("h01") + node T_2563 = eq(T_2559[0], T_2836.out.bits.g_type) + node T_2564 = eq(T_2559[1], T_2836.out.bits.g_type) + node T_2566 = or(UInt<1>("h00"), T_2563) + node T_2567 = or(T_2566, T_2564) + node T_2568 = mux(T_2836.out.bits.is_builtin_type, T_2557, T_2567) + node T_2570 = eq(T_2568, UInt<1>("h00")) + node T_2571 = or(writeArb.in[1].ready, T_2570) + T_2836.out.ready := T_2571 + wire T_2575 : UInt<3>[2] + T_2575[0] := UInt<3>("h05") + T_2575[1] := UInt<3>("h04") + node T_2579 = eq(T_2575[0], T_2836.out.bits.g_type) + node T_2580 = eq(T_2575[1], T_2836.out.bits.g_type) + node T_2582 = or(UInt<1>("h00"), T_2579) + node T_2583 = or(T_2582, T_2580) + wire T_2585 : UInt<1>[2] + T_2585[0] := UInt<1>("h00") + T_2585[1] := UInt<1>("h01") + node T_2589 = eq(T_2585[0], T_2836.out.bits.g_type) + node T_2590 = eq(T_2585[1], T_2836.out.bits.g_type) + node T_2592 = or(UInt<1>("h00"), T_2589) + node T_2593 = or(T_2592, T_2590) + node T_2594 = mux(T_2836.out.bits.is_builtin_type, T_2583, T_2593) + node T_2595 = and(T_2836.out.valid, T_2594) + writeArb.in[1].valid := T_2595 + writeArb.in[1].bits.addr := mshrs.refill.addr + writeArb.in[1].bits.way_en := mshrs.refill.way_en + node T_2597 = not(UInt<4>("h00")) + writeArb.in[1].bits.wmask := T_2597 + node T_2598 = bits(T_2836.out.bits.data, 127, 0) + writeArb.in[1].bits.data := T_2598 + data.read <> readArb.out + node T_2600 = eq(T_2836.out.valid, UInt<1>("h00")) + node T_2601 = or(T_2600, T_2836.out.ready) + readArb.out.ready := T_2601 + inst wbArb of Arbiter_54 + wbArb.out.ready := UInt<1>("h00") + wbArb.in[0].bits.way_en := UInt<1>("h00") + wbArb.in[0].bits.voluntary := UInt<1>("h00") + wbArb.in[0].bits.r_type := UInt<1>("h00") + wbArb.in[0].bits.data := UInt<1>("h00") + wbArb.in[0].bits.addr_beat := UInt<1>("h00") + wbArb.in[0].bits.client_xact_id := UInt<1>("h00") + wbArb.in[0].bits.addr_block := UInt<1>("h00") + wbArb.in[0].valid := UInt<1>("h00") + wbArb.in[1].bits.way_en := UInt<1>("h00") + wbArb.in[1].bits.voluntary := UInt<1>("h00") + wbArb.in[1].bits.r_type := UInt<1>("h00") + wbArb.in[1].bits.data := UInt<1>("h00") + wbArb.in[1].bits.addr_beat := UInt<1>("h00") + wbArb.in[1].bits.client_xact_id := UInt<1>("h00") + wbArb.in[1].bits.addr_block := UInt<1>("h00") + wbArb.in[1].valid := UInt<1>("h00") + wbArb.reset := UInt<1>("h00") + wbArb.clock := clock + wbArb.reset := reset + wbArb.in[0] <> prober.wb_req + wbArb.in[1] <> mshrs.wb_req + wb.req <> wbArb.out + metaReadArb.in[3] <> wb.meta_read + readArb.in[2] <> wb.data_req + wb.data_resp := s2_data_corrected + releaseArb.in[0] <> wb.release + reg s4_valid : UInt<1>, clock, reset + onreset s4_valid := UInt<1>("h00") + s4_valid := s3_valid + node T_2653 = and(s3_valid, metaReadArb.out.valid) + reg s4_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clock, reset + when T_2653 : + s4_req <> s3_req + skip + node T_2662 = or(s2_valid_masked, s2_replay) + node T_2664 = eq(s2_sc_fail, UInt<1>("h00")) + node T_2665 = and(T_2662, T_2664) + node T_2666 = shr(s1_addr, 3) + node T_2667 = shr(s2_req.addr, 3) + node T_2668 = eq(T_2666, T_2667) + node T_2669 = and(T_2665, T_2668) + node T_2670 = eq(s2_req.cmd, UInt<5>("h01")) + node T_2671 = eq(s2_req.cmd, UInt<5>("h07")) + node T_2672 = or(T_2670, T_2671) + node T_2673 = bit(s2_req.cmd, 3) + node T_2674 = eq(s2_req.cmd, UInt<5>("h04")) + node T_2675 = or(T_2673, T_2674) + node T_2676 = or(T_2672, T_2675) + node T_2677 = and(T_2669, T_2676) + node T_2678 = shr(s1_addr, 3) + node T_2679 = shr(s3_req.addr, 3) + node T_2680 = eq(T_2678, T_2679) + node T_2681 = and(s3_valid, T_2680) + node T_2682 = eq(s3_req.cmd, UInt<5>("h01")) + node T_2683 = eq(s3_req.cmd, UInt<5>("h07")) + node T_2684 = or(T_2682, T_2683) + node T_2685 = bit(s3_req.cmd, 3) + node T_2686 = eq(s3_req.cmd, UInt<5>("h04")) + node T_2687 = or(T_2685, T_2686) + node T_2688 = or(T_2684, T_2687) + node T_2689 = and(T_2681, T_2688) + node T_2690 = shr(s1_addr, 3) + node T_2691 = shr(s4_req.addr, 3) + node T_2692 = eq(T_2690, T_2691) + node T_2693 = and(s4_valid, T_2692) + node T_2694 = eq(s4_req.cmd, UInt<5>("h01")) + node T_2695 = eq(s4_req.cmd, UInt<5>("h07")) + node T_2696 = or(T_2694, T_2695) + node T_2697 = bit(s4_req.cmd, 3) + node T_2698 = eq(s4_req.cmd, UInt<5>("h04")) + node T_2699 = or(T_2697, T_2698) + node T_2700 = or(T_2696, T_2699) + node T_2701 = and(T_2693, T_2700) + reg s2_store_bypass_data : UInt<64>, clock, reset + reg s2_store_bypass : UInt<1>, clock, reset + when s1_clk_en : + s2_store_bypass := UInt<1>("h00") + node T_2707 = or(T_2677, T_2689) + node T_2708 = or(T_2707, T_2701) + when T_2708 : + node T_2709 = mux(T_2689, s3_req.data, s4_req.data) + node T_2710 = mux(T_2677, amoalu.out, T_2709) + s2_store_bypass_data := T_2710 + s2_store_bypass := UInt<1>("h01") + skip + skip + node T_2713 = cat(UInt<1>("h00"), UInt<6>("h00")) + node s2_data_word_prebypass = dshr(s2_data_uncorrected, T_2713) + node s2_data_word = mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass) + node T_2716 = eq(s2_req.typ, UInt<3>("h00")) + node T_2717 = eq(s2_req.typ, UInt<3>("h04")) + node T_2718 = or(T_2716, T_2717) + node T_2719 = eq(s2_req.typ, UInt<3>("h01")) + node T_2720 = eq(s2_req.typ, UInt<3>("h05")) + node T_2721 = or(T_2719, T_2720) + node T_2722 = eq(s2_req.typ, UInt<3>("h02")) + node T_2723 = eq(s2_req.typ, UInt<3>("h06")) + node T_2724 = or(T_2722, T_2723) + node T_2725 = eq(s2_req.typ, UInt<3>("h00")) + node T_2726 = eq(s2_req.typ, UInt<3>("h01")) + node T_2727 = or(T_2725, T_2726) + node T_2728 = eq(s2_req.typ, UInt<3>("h02")) + node T_2729 = or(T_2727, T_2728) + node T_2730 = eq(s2_req.typ, UInt<3>("h03")) + node T_2731 = or(T_2729, T_2730) + node T_2732 = bit(s2_req.addr, 2) + node T_2733 = bits(s2_data_word, 63, 32) + node T_2734 = bits(s2_data_word, 31, 0) + node T_2735 = mux(T_2732, T_2733, T_2734) + node T_2736 = bit(T_2735, 31) + node T_2737 = and(T_2731, T_2736) + node T_2739 = subw(UInt<32>("h00"), T_2737) + node T_2740 = bits(s2_data_word, 63, 32) + node T_2741 = mux(T_2724, T_2739, T_2740) + node T_2742 = cat(T_2741, T_2735) + node T_2743 = bit(s2_req.addr, 1) + node T_2744 = bits(T_2742, 31, 16) + node T_2745 = bits(T_2742, 15, 0) + node T_2746 = mux(T_2743, T_2744, T_2745) + node T_2747 = bit(T_2746, 15) + node T_2748 = and(T_2731, T_2747) + node T_2750 = subw(UInt<48>("h00"), T_2748) + node T_2751 = bits(T_2742, 63, 16) + node T_2752 = mux(T_2721, T_2750, T_2751) + node T_2753 = cat(T_2752, T_2746) + node T_2755 = bit(s2_req.addr, 0) + node T_2756 = bits(T_2753, 15, 8) + node T_2757 = bits(T_2753, 7, 0) + node T_2758 = mux(T_2755, T_2756, T_2757) + node T_2759 = mux(s2_sc, UInt<1>("h00"), T_2758) + node T_2760 = or(s2_sc, T_2718) + node T_2761 = bit(T_2759, 7) + node T_2762 = and(T_2731, T_2761) + node T_2764 = subw(UInt<56>("h00"), T_2762) + node T_2765 = bits(T_2753, 63, 8) + node T_2766 = mux(T_2760, T_2764, T_2765) + node T_2767 = cat(T_2766, T_2759) + amoalu.addr := s2_req.addr + amoalu.cmd := s2_req.cmd + amoalu.typ := s2_req.typ + amoalu.lhs := s2_data_word + amoalu.rhs := s2_req.data + node T_2768 = and(dtlb.req.valid, dtlb.resp.miss) + node T_2769 = bits(s1_req.addr, 11, 6) + node T_2770 = eq(T_2769, prober.meta_write.bits.idx) + node T_2772 = eq(prober.req.ready, UInt<1>("h00")) + node T_2773 = and(T_2770, T_2772) + node s1_nack = or(T_2768, T_2773) + node T_2775 = or(s1_valid, s1_replay) + reg s2_nack_hit : UInt<1>, clock, reset + when T_2775 : + s2_nack_hit := s1_nack + skip + when s2_nack_hit : + mshrs.req.valid := UInt<1>("h00") + skip + node s2_nack_victim = and(s2_hit, mshrs.secondary_miss) + node T_2780 = eq(s2_hit, UInt<1>("h00")) + node T_2782 = eq(mshrs.req.ready, UInt<1>("h00")) + node s2_nack_miss = and(T_2780, T_2782) + node T_2784 = or(s2_nack_hit, s2_nack_victim) + node s2_nack = or(T_2784, s2_nack_miss) + node T_2787 = eq(s2_nack, UInt<1>("h00")) + node T_2788 = and(s2_valid, T_2787) + s2_valid_masked := T_2788 + node T_2789 = or(s2_valid, s2_replay) + node T_2790 = and(T_2789, s2_hit) + node s2_recycle_ecc = and(T_2790, s2_data_correctable) + reg s2_recycle_next : UInt<1>, clock, reset + onreset s2_recycle_next := UInt<1>("h00") + node T_2794 = or(s1_valid, s1_replay) + when T_2794 : + s2_recycle_next := s2_recycle_ecc + skip + node T_2795 = or(s2_recycle_ecc, s2_recycle_next) + s2_recycle := T_2795 + reg block_miss : UInt<1>, clock, reset + onreset block_miss := UInt<1>("h00") + node T_2798 = or(s2_valid, block_miss) + node T_2799 = and(T_2798, s2_nack_miss) + block_miss := T_2799 + when block_miss : + cpu.req.ready := UInt<1>("h00") + skip + node T_2801 = and(s2_valid_masked, s2_hit) + node T_2802 = or(s2_replay, T_2801) + node T_2804 = eq(s2_data_correctable, UInt<1>("h00")) + node T_2805 = and(T_2802, T_2804) + cpu.resp.valid := T_2805 + node T_2806 = and(s2_valid, s2_nack) + cpu.resp.bits.nack := T_2806 + cpu.resp.bits <> s2_req + node T_2807 = eq(s2_req.cmd, UInt<5>("h00")) + node T_2808 = eq(s2_req.cmd, UInt<5>("h06")) + node T_2809 = or(T_2807, T_2808) + node T_2810 = bit(s2_req.cmd, 3) + node T_2811 = eq(s2_req.cmd, UInt<5>("h04")) + node T_2812 = or(T_2810, T_2811) + node T_2813 = or(T_2809, T_2812) + node T_2814 = or(T_2813, s2_sc) + cpu.resp.bits.has_data := T_2814 + cpu.resp.bits.replay := s2_replay + cpu.resp.bits.data := T_2742 + node T_2815 = or(T_2767, s2_sc_fail) + cpu.resp.bits.data_subword := T_2815 + cpu.resp.bits.store_data := s2_req.data + node T_2817 = eq(s1_valid, UInt<1>("h00")) + node T_2818 = and(mshrs.fence_rdy, T_2817) + node T_2820 = eq(s2_valid, UInt<1>("h00")) + node T_2821 = and(T_2818, T_2820) + cpu.ordered := T_2821 + node T_2822 = or(s1_read, s1_sc) + node T_2823 = and(s1_replay, T_2822) + cpu.replay_next.valid := T_2823 + cpu.replay_next.bits := s1_req.tag + + module RRArbiter_69 : + output chosen : UInt<1> + output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}} + input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}[2] + input clock : Clock + input reset : UInt<1> + + chosen := UInt<1>("h00") + out.bits.fetch := UInt<1>("h00") + out.bits.store := UInt<1>("h00") + out.bits.prv := UInt<1>("h00") + out.bits.addr := UInt<1>("h00") + out.valid := UInt<1>("h00") + in[0].ready := UInt<1>("h00") + in[1].ready := UInt<1>("h00") + wire T_152 : UInt<1> + T_152 := UInt<1>("h00") + infer accessor T_154 = in[T_152] + out.valid := T_154.valid + infer accessor T_167 = in[T_152] + out.bits <> T_167.bits + chosen := T_152 + infer accessor T_180 = in[T_152] + T_180.ready := UInt<1>("h00") + reg T_196 : UInt<1>, clock, reset + onreset T_196 := UInt<1>("h00") + node T_197 = gt(UInt<1>("h00"), T_196) + node T_198 = and(in[0].valid, T_197) + node T_200 = gt(UInt<1>("h01"), T_196) + node T_201 = and(in[1].valid, T_200) + node T_204 = or(UInt<1>("h00"), T_198) + node T_206 = eq(T_204, UInt<1>("h00")) + node T_208 = or(UInt<1>("h00"), T_198) + node T_209 = or(T_208, T_201) + node T_211 = eq(T_209, UInt<1>("h00")) + node T_213 = or(UInt<1>("h00"), T_198) + node T_214 = or(T_213, T_201) + node T_215 = or(T_214, in[0].valid) + node T_217 = eq(T_215, UInt<1>("h00")) + node T_219 = gt(UInt<1>("h00"), T_196) + node T_220 = and(UInt<1>("h01"), T_219) + node T_221 = or(T_220, T_211) + node T_223 = gt(UInt<1>("h01"), T_196) + node T_224 = and(T_206, T_223) + node T_225 = or(T_224, T_217) + node T_227 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_228 = mux(UInt<1>("h00"), T_227, T_221) + node T_229 = and(T_228, out.ready) + in[0].ready := T_229 + node T_231 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_232 = mux(UInt<1>("h00"), T_231, T_225) + node T_233 = and(T_232, out.ready) + in[1].ready := T_233 + node T_236 = mux(in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_238 = gt(UInt<1>("h01"), T_196) + node T_239 = and(in[1].valid, T_238) + node T_241 = mux(T_239, UInt<1>("h01"), T_236) + node T_242 = mux(UInt<1>("h00"), UInt<1>("h01"), T_241) + T_152 := T_242 + node T_243 = and(out.ready, out.valid) + when T_243 : + T_196 := T_152 + skip + + module PTW : + output dpath : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}} + output mem_1 : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>} + input requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}[2] + input clock : Clock + input reset : UInt<1> + + mem_1.invalidate_lr := UInt<1>("h00") + mem_1.req.bits.data := UInt<1>("h00") + mem_1.req.bits.phys := UInt<1>("h00") + mem_1.req.bits.kill := UInt<1>("h00") + mem_1.req.bits.typ := UInt<1>("h00") + mem_1.req.bits.cmd := UInt<1>("h00") + mem_1.req.bits.tag := UInt<1>("h00") + mem_1.req.bits.addr := UInt<1>("h00") + mem_1.req.valid := UInt<1>("h00") + requestor[0].invalidate := UInt<1>("h00") + requestor[0].status.ie := UInt<1>("h00") + requestor[0].status.prv := UInt<1>("h00") + requestor[0].status.ie1 := UInt<1>("h00") + requestor[0].status.prv1 := UInt<1>("h00") + requestor[0].status.ie2 := UInt<1>("h00") + requestor[0].status.prv2 := UInt<1>("h00") + requestor[0].status.ie3 := UInt<1>("h00") + requestor[0].status.prv3 := UInt<1>("h00") + requestor[0].status.fs := UInt<1>("h00") + requestor[0].status.xs := UInt<1>("h00") + requestor[0].status.mprv := UInt<1>("h00") + requestor[0].status.vm := UInt<1>("h00") + requestor[0].status.zero1 := UInt<1>("h00") + requestor[0].status.sd_rv32 := UInt<1>("h00") + requestor[0].status.zero2 := UInt<1>("h00") + requestor[0].status.sd := UInt<1>("h00") + requestor[0].resp.bits.pte.v := UInt<1>("h00") + requestor[0].resp.bits.pte.typ := UInt<1>("h00") + requestor[0].resp.bits.pte.r := UInt<1>("h00") + requestor[0].resp.bits.pte.d := UInt<1>("h00") + requestor[0].resp.bits.pte.reserved_for_software := UInt<1>("h00") + requestor[0].resp.bits.pte.ppn := UInt<1>("h00") + requestor[0].resp.bits.error := UInt<1>("h00") + requestor[0].resp.valid := UInt<1>("h00") + requestor[0].req.ready := UInt<1>("h00") + requestor[1].invalidate := UInt<1>("h00") + requestor[1].status.ie := UInt<1>("h00") + requestor[1].status.prv := UInt<1>("h00") + requestor[1].status.ie1 := UInt<1>("h00") + requestor[1].status.prv1 := UInt<1>("h00") + requestor[1].status.ie2 := UInt<1>("h00") + requestor[1].status.prv2 := UInt<1>("h00") + requestor[1].status.ie3 := UInt<1>("h00") + requestor[1].status.prv3 := UInt<1>("h00") + requestor[1].status.fs := UInt<1>("h00") + requestor[1].status.xs := UInt<1>("h00") + requestor[1].status.mprv := UInt<1>("h00") + requestor[1].status.vm := UInt<1>("h00") + requestor[1].status.zero1 := UInt<1>("h00") + requestor[1].status.sd_rv32 := UInt<1>("h00") + requestor[1].status.zero2 := UInt<1>("h00") + requestor[1].status.sd := UInt<1>("h00") + requestor[1].resp.bits.pte.v := UInt<1>("h00") + requestor[1].resp.bits.pte.typ := UInt<1>("h00") + requestor[1].resp.bits.pte.r := UInt<1>("h00") + requestor[1].resp.bits.pte.d := UInt<1>("h00") + requestor[1].resp.bits.pte.reserved_for_software := UInt<1>("h00") + requestor[1].resp.bits.pte.ppn := UInt<1>("h00") + requestor[1].resp.bits.error := UInt<1>("h00") + requestor[1].resp.valid := UInt<1>("h00") + requestor[1].req.ready := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg count : UInt<2>, clock, reset + reg r_req : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}, clock, reset + reg r_req_dest : UInt<?>, clock, reset + reg r_pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}, clock, reset + node T_1222 = shr(r_req.addr, 18) + node T_1223 = bits(T_1222, 8, 0) + node T_1224 = shr(r_req.addr, 9) + node T_1225 = bits(T_1224, 8, 0) + node T_1226 = shr(r_req.addr, 0) + node T_1227 = bits(T_1226, 8, 0) + wire T_1229 : UInt<9>[3] + T_1229[0] := T_1223 + T_1229[1] := T_1225 + T_1229[2] := T_1227 + infer accessor vpn_idx = T_1229[count] + inst arb of RRArbiter_69 + arb.out.ready := UInt<1>("h00") + arb.in[0].bits.fetch := UInt<1>("h00") + arb.in[0].bits.store := UInt<1>("h00") + arb.in[0].bits.prv := UInt<1>("h00") + arb.in[0].bits.addr := UInt<1>("h00") + arb.in[0].valid := UInt<1>("h00") + arb.in[1].bits.fetch := UInt<1>("h00") + arb.in[1].bits.store := UInt<1>("h00") + arb.in[1].bits.prv := UInt<1>("h00") + arb.in[1].bits.addr := UInt<1>("h00") + arb.in[1].valid := UInt<1>("h00") + arb.reset := UInt<1>("h00") + arb.clock := clock + arb.reset := reset + arb.in[0] <> requestor[0].req + arb.in[1] <> requestor[1].req + node T_1252 = eq(state, UInt<1>("h00")) + arb.out.ready := T_1252 + wire pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} + pte.v := UInt<1>("h00") + pte.typ := UInt<1>("h00") + pte.r := UInt<1>("h00") + pte.d := UInt<1>("h00") + pte.reserved_for_software := UInt<1>("h00") + pte.ppn := UInt<1>("h00") + node T_1280 = bits(mem_1.resp.bits.data, 0, 0) + pte.v := T_1280 + node T_1281 = bits(mem_1.resp.bits.data, 4, 1) + pte.typ := T_1281 + node T_1282 = bits(mem_1.resp.bits.data, 5, 5) + pte.r := T_1282 + node T_1283 = bits(mem_1.resp.bits.data, 6, 6) + pte.d := T_1283 + node T_1284 = bits(mem_1.resp.bits.data, 9, 7) + pte.reserved_for_software := T_1284 + node T_1285 = bits(mem_1.resp.bits.data, 29, 10) + pte.ppn := T_1285 + node T_1286 = cat(r_pte.ppn, vpn_idx) + node pte_addr = shl(T_1286, 3) + node T_1288 = and(arb.out.ready, arb.out.valid) + when T_1288 : + r_req <> arb.out.bits + r_req_dest := arb.chosen + node T_1289 = bits(dpath.ptbr, 31, 12) + r_pte.ppn := T_1289 + skip + reg T_1291 : UInt<3>, clock, reset + reg T_1301 : UInt<1>[3], clock, reset + node T_1306 = cat(T_1301[1], T_1301[0]) + node T_1307 = cat(T_1301[2], T_1306) + cmem T_1310 : UInt<32>[3], clock + cmem T_1313 : UInt<20>[3], clock + infer accessor T_1315 = T_1310[UInt<1>("h00")] + node T_1316 = eq(T_1315, pte_addr) + infer accessor T_1318 = T_1310[UInt<1>("h01")] + node T_1319 = eq(T_1318, pte_addr) + infer accessor T_1321 = T_1310[UInt<2>("h02")] + node T_1322 = eq(T_1321, pte_addr) + wire T_1324 : UInt<1>[3] + T_1324[0] := T_1316 + T_1324[1] := T_1319 + T_1324[2] := T_1322 + node T_1329 = cat(T_1324[1], T_1324[0]) + node T_1330 = cat(T_1324[2], T_1329) + node T_1331 = and(T_1330, T_1307) + node pte_cache_hit = neq(T_1331, UInt<1>("h00")) + node T_1335 = lt(pte.typ, UInt<2>("h02")) + node T_1336 = and(pte.v, T_1335) + node T_1337 = and(mem_1.resp.valid, T_1336) + node T_1339 = eq(pte_cache_hit, UInt<1>("h00")) + node T_1340 = and(T_1337, T_1339) + when T_1340 : + node T_1341 = not(T_1307) + node T_1343 = eq(T_1341, UInt<1>("h00")) + node T_1345 = dshr(T_1291, UInt<1>("h01")) + node T_1346 = bit(T_1345, 0) + node T_1347 = cat(UInt<1>("h01"), T_1346) + node T_1348 = dshr(T_1291, T_1347) + node T_1349 = bit(T_1348, 0) + node T_1350 = cat(T_1347, T_1349) + node T_1351 = bits(T_1350, 1, 0) + node T_1352 = not(T_1307) + node T_1353 = bit(T_1352, 0) + node T_1354 = bit(T_1352, 1) + node T_1355 = bit(T_1352, 2) + wire T_1357 : UInt<1>[3] + T_1357[0] := T_1353 + T_1357[1] := T_1354 + T_1357[2] := T_1355 + node T_1365 = mux(T_1357[1], UInt<1>("h01"), UInt<2>("h02")) + node T_1366 = mux(T_1357[0], UInt<1>("h00"), T_1365) + node T_1367 = mux(T_1343, T_1351, T_1366) + infer accessor T_1368 = T_1301[T_1367] + T_1368 := UInt<1>("h01") + infer accessor T_1370 = T_1310[T_1367] + T_1370 := pte_addr + infer accessor T_1371 = T_1313[T_1367] + T_1371 := pte.ppn + skip + node T_1372 = eq(state, UInt<1>("h01")) + node T_1373 = and(pte_cache_hit, T_1372) + when T_1373 : + node T_1374 = bits(T_1331, 2, 2) + node T_1375 = bits(T_1331, 1, 0) + node T_1377 = neq(T_1374, UInt<1>("h00")) + node T_1378 = or(T_1374, T_1375) + node T_1379 = bit(T_1378, 1) + node T_1380 = cat(T_1377, T_1379) + node T_1382 = bit(T_1380, 1) + node T_1384 = dshl(UInt<3>("h01"), UInt<1>("h01")) + node T_1385 = bits(T_1384, 2, 0) + node T_1386 = not(T_1385) + node T_1387 = and(T_1291, T_1386) + node T_1389 = mux(T_1382, UInt<1>("h00"), T_1385) + node T_1390 = or(T_1387, T_1389) + node T_1391 = cat(UInt<1>("h01"), T_1382) + node T_1392 = bit(T_1380, 0) + node T_1394 = dshl(UInt<3>("h01"), T_1391) + node T_1395 = bits(T_1394, 2, 0) + node T_1396 = not(T_1395) + node T_1397 = and(T_1390, T_1396) + node T_1399 = mux(T_1392, UInt<1>("h00"), T_1395) + node T_1400 = or(T_1397, T_1399) + node T_1401 = cat(T_1391, T_1392) + T_1291 := T_1400 + skip + node T_1402 = or(reset, dpath.invalidate) + when T_1402 : + T_1301[0] := UInt<1>("h00") + T_1301[1] := UInt<1>("h00") + T_1301[2] := UInt<1>("h00") + skip + node T_1406 = bit(T_1331, 0) + node T_1407 = bit(T_1331, 1) + node T_1408 = bit(T_1331, 2) + infer accessor T_1410 = T_1313[UInt<1>("h00")] + infer accessor T_1412 = T_1313[UInt<1>("h01")] + infer accessor T_1414 = T_1313[UInt<2>("h02")] + node T_1416 = mux(T_1406, T_1410, UInt<1>("h00")) + node T_1418 = mux(T_1407, T_1412, UInt<1>("h00")) + node T_1420 = mux(T_1408, T_1414, UInt<1>("h00")) + node T_1422 = or(T_1416, T_1418) + node T_1423 = or(T_1422, T_1420) + wire pte_cache_data : UInt<20> + pte_cache_data := UInt<1>("h00") + pte_cache_data := T_1423 + node T_1426 = bit(r_req.prv, 0) + node T_1428 = geq(pte.typ, UInt<3>("h04")) + node T_1429 = and(pte.v, T_1428) + node T_1430 = bit(pte.typ, 1) + node T_1431 = and(T_1429, T_1430) + node T_1433 = geq(pte.typ, UInt<2>("h02")) + node T_1434 = and(pte.v, T_1433) + node T_1435 = bit(pte.typ, 0) + node T_1436 = and(T_1434, T_1435) + node T_1438 = geq(pte.typ, UInt<2>("h02")) + node T_1439 = and(pte.v, T_1438) + node T_1440 = mux(r_req.store, T_1436, T_1439) + node T_1441 = mux(r_req.fetch, T_1431, T_1440) + node T_1443 = geq(pte.typ, UInt<2>("h02")) + node T_1444 = and(pte.v, T_1443) + node T_1446 = lt(pte.typ, UInt<4>("h08")) + node T_1447 = and(T_1444, T_1446) + node T_1448 = bit(pte.typ, 1) + node T_1449 = and(T_1447, T_1448) + node T_1451 = geq(pte.typ, UInt<2>("h02")) + node T_1452 = and(pte.v, T_1451) + node T_1454 = lt(pte.typ, UInt<4>("h08")) + node T_1455 = and(T_1452, T_1454) + node T_1456 = bit(pte.typ, 0) + node T_1457 = and(T_1455, T_1456) + node T_1459 = geq(pte.typ, UInt<2>("h02")) + node T_1460 = and(pte.v, T_1459) + node T_1462 = lt(pte.typ, UInt<4>("h08")) + node T_1463 = and(T_1460, T_1462) + node T_1464 = mux(r_req.store, T_1457, T_1463) + node T_1465 = mux(r_req.fetch, T_1449, T_1464) + node perm_ok = mux(T_1426, T_1441, T_1465) + node T_1468 = eq(pte.r, UInt<1>("h00")) + node T_1470 = eq(pte.d, UInt<1>("h00")) + node T_1471 = and(r_req.store, T_1470) + node T_1472 = or(T_1468, T_1471) + node set_dirty_bit = and(perm_ok, T_1472) + node T_1474 = eq(state, UInt<2>("h02")) + node T_1475 = and(mem_1.resp.valid, T_1474) + node T_1477 = eq(set_dirty_bit, UInt<1>("h00")) + node T_1478 = and(T_1475, T_1477) + when T_1478 : + r_pte <> pte + skip + wire T_1494 : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} + T_1494.v := UInt<1>("h00") + T_1494.typ := UInt<1>("h00") + T_1494.r := UInt<1>("h00") + T_1494.d := UInt<1>("h00") + T_1494.reserved_for_software := UInt<1>("h00") + T_1494.ppn := UInt<1>("h00") + T_1494.v := UInt<1>("h00") + T_1494.typ := UInt<4>("h00") + T_1494.r := UInt<1>("h00") + T_1494.d := UInt<1>("h00") + T_1494.reserved_for_software := UInt<3>("h00") + T_1494.ppn := UInt<20>("h00") + wire pte_wdata : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} + pte_wdata <> T_1494 + pte_wdata.r := UInt<1>("h01") + pte_wdata.d := r_req.store + node T_1521 = eq(state, UInt<1>("h01")) + node T_1522 = eq(state, UInt<2>("h03")) + node T_1523 = or(T_1521, T_1522) + mem_1.req.valid := T_1523 + mem_1.req.bits.phys := UInt<1>("h01") + node T_1525 = eq(state, UInt<2>("h03")) + node T_1526 = mux(T_1525, UInt<5>("h0a"), UInt<5>("h00")) + mem_1.req.bits.cmd := T_1526 + mem_1.req.bits.typ := UInt<3>("h03") + mem_1.req.bits.addr := pte_addr + mem_1.req.bits.kill := UInt<1>("h00") + node T_1528 = cat(pte_wdata.reserved_for_software, pte_wdata.d) + node T_1529 = cat(pte_wdata.ppn, T_1528) + node T_1530 = cat(pte_wdata.typ, pte_wdata.v) + node T_1531 = cat(pte_wdata.r, T_1530) + node T_1532 = cat(T_1529, T_1531) + mem_1.req.bits.data := T_1532 + node resp_err = eq(state, UInt<3>("h06")) + node T_1534 = eq(state, UInt<3>("h05")) + node resp_val = or(T_1534, resp_err) + node r_resp_ppn = shr(mem_1.req.bits.addr, 12) + node T_1537 = shr(r_resp_ppn, 18) + node T_1538 = bits(r_req.addr, 17, 0) + node T_1539 = cat(T_1537, T_1538) + node T_1540 = shr(r_resp_ppn, 9) + node T_1541 = bits(r_req.addr, 8, 0) + node T_1542 = cat(T_1540, T_1541) + wire T_1544 : UInt<28>[3] + T_1544[0] := T_1539 + T_1544[1] := T_1542 + T_1544[2] := r_resp_ppn + infer accessor resp_ppn = T_1544[count] + node T_1551 = eq(r_req_dest, UInt<1>("h00")) + node T_1552 = and(resp_val, T_1551) + requestor[0].resp.valid := T_1552 + requestor[0].resp.bits.error := resp_err + requestor[0].resp.bits.pte <> r_pte + requestor[0].resp.bits.pte.ppn := resp_ppn + requestor[0].invalidate := dpath.invalidate + requestor[0].status <> dpath.status + node T_1554 = eq(r_req_dest, UInt<1>("h01")) + node T_1555 = and(resp_val, T_1554) + requestor[1].resp.valid := T_1555 + requestor[1].resp.bits.error := resp_err + requestor[1].resp.bits.pte <> r_pte + requestor[1].resp.bits.pte.ppn := resp_ppn + requestor[1].invalidate := dpath.invalidate + requestor[1].status <> dpath.status + node T_1556 = eq(UInt<1>("h00"), state) + when T_1556 : + when arb.out.valid : + state := UInt<1>("h01") + skip + count := UInt<1>("h00") + skip + node T_1558 = eq(UInt<1>("h01"), state) + when T_1558 : + node T_1560 = lt(count, UInt<2>("h02")) + node T_1561 = and(pte_cache_hit, T_1560) + when T_1561 : + mem_1.req.valid := UInt<1>("h00") + state := UInt<1>("h01") + node T_1564 = addw(count, UInt<1>("h01")) + count := T_1564 + r_pte.ppn := pte_cache_data + skip + else : + when mem_1.req.ready : + state := UInt<2>("h02") + skip + skip + skip + node T_1565 = eq(UInt<2>("h02"), state) + when T_1565 : + when mem_1.resp.bits.nack : + state := UInt<1>("h01") + skip + when mem_1.resp.valid : + state := UInt<3>("h06") + node T_1567 = lt(pte.typ, UInt<2>("h02")) + node T_1568 = and(pte.v, T_1567) + node T_1570 = lt(count, UInt<2>("h02")) + node T_1571 = and(T_1568, T_1570) + when T_1571 : + state := UInt<1>("h01") + node T_1573 = addw(count, UInt<1>("h01")) + count := T_1573 + skip + node T_1575 = geq(pte.typ, UInt<2>("h02")) + node T_1576 = and(pte.v, T_1575) + when T_1576 : + node T_1577 = mux(set_dirty_bit, UInt<2>("h03"), UInt<3>("h05")) + state := T_1577 + skip + skip + skip + node T_1578 = eq(UInt<2>("h03"), state) + when T_1578 : + when mem_1.req.ready : + state := UInt<3>("h04") + skip + skip + node T_1579 = eq(UInt<3>("h04"), state) + when T_1579 : + when mem_1.resp.bits.nack : + state := UInt<2>("h03") + skip + when mem_1.resp.valid : + state := UInt<1>("h01") + skip + skip + node T_1580 = eq(UInt<3>("h05"), state) + when T_1580 : + state := UInt<1>("h00") + skip + node T_1581 = eq(UInt<3>("h06"), state) + when T_1581 : + state := UInt<1>("h00") + skip + + module CSRFile : + output interrupt_cause : UInt<64> + output interrupt : UInt<1> + input rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst_1 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem_1 : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, imem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, dmem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, flip exception : UInt<1>} + input fcsr_flags : {valid : UInt<1>, bits : UInt<5>} + output fcsr_rm : UInt<3> + output time : UInt<64> + output fatc : UInt<1> + input pc : UInt<40> + input cause : UInt<64> + input custom_mrw_csrs : UInt<64>[0] + input uarch_counters : UInt<1>[16] + input retire : UInt<1> + input exception : UInt<1> + output evec : UInt<40> + output ptbr : UInt<32> + output status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>} + output eret : UInt<1> + output csr_xcpt : UInt<1> + output csr_stall : UInt<1> + output csr_replay : UInt<1> + output rw : {flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>} + output host : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>} + input clock : Clock + input reset : UInt<1> + + interrupt_cause := UInt<1>("h00") + interrupt := UInt<1>("h00") + rocc.exception := UInt<1>("h00") + rocc.pptw.invalidate := UInt<1>("h00") + rocc.pptw.status.ie := UInt<1>("h00") + rocc.pptw.status.prv := UInt<1>("h00") + rocc.pptw.status.ie1 := UInt<1>("h00") + rocc.pptw.status.prv1 := UInt<1>("h00") + rocc.pptw.status.ie2 := UInt<1>("h00") + rocc.pptw.status.prv2 := UInt<1>("h00") + rocc.pptw.status.ie3 := UInt<1>("h00") + rocc.pptw.status.prv3 := UInt<1>("h00") + rocc.pptw.status.fs := UInt<1>("h00") + rocc.pptw.status.xs := UInt<1>("h00") + rocc.pptw.status.mprv := UInt<1>("h00") + rocc.pptw.status.vm := UInt<1>("h00") + rocc.pptw.status.zero1 := UInt<1>("h00") + rocc.pptw.status.sd_rv32 := UInt<1>("h00") + rocc.pptw.status.zero2 := UInt<1>("h00") + rocc.pptw.status.sd := UInt<1>("h00") + rocc.pptw.resp.bits.pte.v := UInt<1>("h00") + rocc.pptw.resp.bits.pte.typ := UInt<1>("h00") + rocc.pptw.resp.bits.pte.r := UInt<1>("h00") + rocc.pptw.resp.bits.pte.d := UInt<1>("h00") + rocc.pptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") + rocc.pptw.resp.bits.pte.ppn := UInt<1>("h00") + rocc.pptw.resp.bits.error := UInt<1>("h00") + rocc.pptw.resp.valid := UInt<1>("h00") + rocc.pptw.req.ready := UInt<1>("h00") + rocc.dptw.invalidate := UInt<1>("h00") + rocc.dptw.status.ie := UInt<1>("h00") + rocc.dptw.status.prv := UInt<1>("h00") + rocc.dptw.status.ie1 := UInt<1>("h00") + rocc.dptw.status.prv1 := UInt<1>("h00") + rocc.dptw.status.ie2 := UInt<1>("h00") + rocc.dptw.status.prv2 := UInt<1>("h00") + rocc.dptw.status.ie3 := UInt<1>("h00") + rocc.dptw.status.prv3 := UInt<1>("h00") + rocc.dptw.status.fs := UInt<1>("h00") + rocc.dptw.status.xs := UInt<1>("h00") + rocc.dptw.status.mprv := UInt<1>("h00") + rocc.dptw.status.vm := UInt<1>("h00") + rocc.dptw.status.zero1 := UInt<1>("h00") + rocc.dptw.status.sd_rv32 := UInt<1>("h00") + rocc.dptw.status.zero2 := UInt<1>("h00") + rocc.dptw.status.sd := UInt<1>("h00") + rocc.dptw.resp.bits.pte.v := UInt<1>("h00") + rocc.dptw.resp.bits.pte.typ := UInt<1>("h00") + rocc.dptw.resp.bits.pte.r := UInt<1>("h00") + rocc.dptw.resp.bits.pte.d := UInt<1>("h00") + rocc.dptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") + rocc.dptw.resp.bits.pte.ppn := UInt<1>("h00") + rocc.dptw.resp.bits.error := UInt<1>("h00") + rocc.dptw.resp.valid := UInt<1>("h00") + rocc.dptw.req.ready := UInt<1>("h00") + rocc.iptw.invalidate := UInt<1>("h00") + rocc.iptw.status.ie := UInt<1>("h00") + rocc.iptw.status.prv := UInt<1>("h00") + rocc.iptw.status.ie1 := UInt<1>("h00") + rocc.iptw.status.prv1 := UInt<1>("h00") + rocc.iptw.status.ie2 := UInt<1>("h00") + rocc.iptw.status.prv2 := UInt<1>("h00") + rocc.iptw.status.ie3 := UInt<1>("h00") + rocc.iptw.status.prv3 := UInt<1>("h00") + rocc.iptw.status.fs := UInt<1>("h00") + rocc.iptw.status.xs := UInt<1>("h00") + rocc.iptw.status.mprv := UInt<1>("h00") + rocc.iptw.status.vm := UInt<1>("h00") + rocc.iptw.status.zero1 := UInt<1>("h00") + rocc.iptw.status.sd_rv32 := UInt<1>("h00") + rocc.iptw.status.zero2 := UInt<1>("h00") + rocc.iptw.status.sd := UInt<1>("h00") + rocc.iptw.resp.bits.pte.v := UInt<1>("h00") + rocc.iptw.resp.bits.pte.typ := UInt<1>("h00") + rocc.iptw.resp.bits.pte.r := UInt<1>("h00") + rocc.iptw.resp.bits.pte.d := UInt<1>("h00") + rocc.iptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") + rocc.iptw.resp.bits.pte.ppn := UInt<1>("h00") + rocc.iptw.resp.bits.error := UInt<1>("h00") + rocc.iptw.resp.valid := UInt<1>("h00") + rocc.iptw.req.ready := UInt<1>("h00") + rocc.dmem.grant.bits.g_type := UInt<1>("h00") + rocc.dmem.grant.bits.is_builtin_type := UInt<1>("h00") + rocc.dmem.grant.bits.manager_xact_id := UInt<1>("h00") + rocc.dmem.grant.bits.client_xact_id := UInt<1>("h00") + rocc.dmem.grant.bits.data := UInt<1>("h00") + rocc.dmem.grant.bits.addr_beat := UInt<1>("h00") + rocc.dmem.grant.valid := UInt<1>("h00") + rocc.dmem.acquire.ready := UInt<1>("h00") + rocc.imem.grant.bits.g_type := UInt<1>("h00") + rocc.imem.grant.bits.is_builtin_type := UInt<1>("h00") + rocc.imem.grant.bits.manager_xact_id := UInt<1>("h00") + rocc.imem.grant.bits.client_xact_id := UInt<1>("h00") + rocc.imem.grant.bits.data := UInt<1>("h00") + rocc.imem.grant.bits.addr_beat := UInt<1>("h00") + rocc.imem.grant.valid := UInt<1>("h00") + rocc.imem.acquire.ready := UInt<1>("h00") + rocc.s := UInt<1>("h00") + rocc.mem_1.ordered := UInt<1>("h00") + rocc.mem_1.xcpt.pf.st := UInt<1>("h00") + rocc.mem_1.xcpt.pf.ld := UInt<1>("h00") + rocc.mem_1.xcpt.ma.st := UInt<1>("h00") + rocc.mem_1.xcpt.ma.ld := UInt<1>("h00") + rocc.mem_1.replay_next.bits := UInt<1>("h00") + rocc.mem_1.replay_next.valid := UInt<1>("h00") + rocc.mem_1.resp.bits.store_data := UInt<1>("h00") + rocc.mem_1.resp.bits.data_subword := UInt<1>("h00") + rocc.mem_1.resp.bits.has_data := UInt<1>("h00") + rocc.mem_1.resp.bits.replay := UInt<1>("h00") + rocc.mem_1.resp.bits.nack := UInt<1>("h00") + rocc.mem_1.resp.bits.data := UInt<1>("h00") + rocc.mem_1.resp.bits.typ := UInt<1>("h00") + rocc.mem_1.resp.bits.cmd := UInt<1>("h00") + rocc.mem_1.resp.bits.tag := UInt<1>("h00") + rocc.mem_1.resp.bits.addr := UInt<1>("h00") + rocc.mem_1.resp.valid := UInt<1>("h00") + rocc.mem_1.req.ready := UInt<1>("h00") + rocc.resp.ready := UInt<1>("h00") + rocc.cmd.bits.rs2 := UInt<1>("h00") + rocc.cmd.bits.rs1 := UInt<1>("h00") + rocc.cmd.bits.inst_1.opcode := UInt<1>("h00") + rocc.cmd.bits.inst_1.rd := UInt<1>("h00") + rocc.cmd.bits.inst_1.xs2 := UInt<1>("h00") + rocc.cmd.bits.inst_1.xs1 := UInt<1>("h00") + rocc.cmd.bits.inst_1.xd := UInt<1>("h00") + rocc.cmd.bits.inst_1.rs1 := UInt<1>("h00") + rocc.cmd.bits.inst_1.rs2 := UInt<1>("h00") + rocc.cmd.bits.inst_1.funct := UInt<1>("h00") + rocc.cmd.valid := UInt<1>("h00") + fcsr_rm := UInt<1>("h00") + time := UInt<1>("h00") + fatc := UInt<1>("h00") + evec := UInt<1>("h00") + ptbr := UInt<1>("h00") + status.ie := UInt<1>("h00") + status.prv := UInt<1>("h00") + status.ie1 := UInt<1>("h00") + status.prv1 := UInt<1>("h00") + status.ie2 := UInt<1>("h00") + status.prv2 := UInt<1>("h00") + status.ie3 := UInt<1>("h00") + status.prv3 := UInt<1>("h00") + status.fs := UInt<1>("h00") + status.xs := UInt<1>("h00") + status.mprv := UInt<1>("h00") + status.vm := UInt<1>("h00") + status.zero1 := UInt<1>("h00") + status.sd_rv32 := UInt<1>("h00") + status.zero2 := UInt<1>("h00") + status.sd := UInt<1>("h00") + eret := UInt<1>("h00") + csr_xcpt := UInt<1>("h00") + csr_stall := UInt<1>("h00") + csr_replay := UInt<1>("h00") + rw.rdata := UInt<1>("h00") + host.debug_stats_pcr := UInt<1>("h00") + host.ipi_rep.ready := UInt<1>("h00") + host.ipi_req.bits := UInt<1>("h00") + host.ipi_req.valid := UInt<1>("h00") + host.pcr_rep.bits := UInt<1>("h00") + host.pcr_rep.valid := UInt<1>("h00") + host.pcr_req.ready := UInt<1>("h00") + reg reg_mstatus : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, clock, reset + wire T_2310 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_2310.usip := UInt<1>("h00") + T_2310.ssip := UInt<1>("h00") + T_2310.hsip := UInt<1>("h00") + T_2310.msip := UInt<1>("h00") + T_2310.utip := UInt<1>("h00") + T_2310.stip := UInt<1>("h00") + T_2310.htip := UInt<1>("h00") + T_2310.mtip := UInt<1>("h00") + T_2310.usip := UInt<1>("h00") + T_2310.ssip := UInt<1>("h00") + T_2310.hsip := UInt<1>("h00") + T_2310.msip := UInt<1>("h00") + T_2310.utip := UInt<1>("h00") + T_2310.stip := UInt<1>("h00") + T_2310.htip := UInt<1>("h00") + T_2310.mtip := UInt<1>("h00") + reg reg_mie : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock, reset + onreset reg_mie := T_2310 + wire T_2363 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_2363.usip := UInt<1>("h00") + T_2363.ssip := UInt<1>("h00") + T_2363.hsip := UInt<1>("h00") + T_2363.msip := UInt<1>("h00") + T_2363.utip := UInt<1>("h00") + T_2363.stip := UInt<1>("h00") + T_2363.htip := UInt<1>("h00") + T_2363.mtip := UInt<1>("h00") + T_2363.usip := UInt<1>("h00") + T_2363.ssip := UInt<1>("h00") + T_2363.hsip := UInt<1>("h00") + T_2363.msip := UInt<1>("h00") + T_2363.utip := UInt<1>("h00") + T_2363.stip := UInt<1>("h00") + T_2363.htip := UInt<1>("h00") + T_2363.mtip := UInt<1>("h00") + reg reg_mip : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock, reset + onreset reg_mip := T_2363 + reg reg_mepc : UInt<40>, clock, reset + reg reg_mcause : UInt<64>, clock, reset + reg reg_mbadaddr : UInt<40>, clock, reset + reg reg_mscratch : UInt<64>, clock, reset + reg reg_sepc : UInt<40>, clock, reset + reg reg_scause : UInt<64>, clock, reset + reg reg_sbadaddr : UInt<40>, clock, reset + reg reg_sscratch : UInt<64>, clock, reset + reg reg_stvec : UInt<39>, clock, reset + reg reg_mtimecmp : UInt<64>, clock, reset + reg reg_sptbr : UInt<32>, clock, reset + reg reg_wfi : UInt<1>, clock, reset + onreset reg_wfi := UInt<1>("h00") + reg reg_tohost : UInt<64>, clock, reset + onreset reg_tohost := UInt<64>("h00") + reg reg_fromhost : UInt<64>, clock, reset + onreset reg_fromhost := UInt<64>("h00") + reg reg_stats : UInt<1>, clock, reset + onreset reg_stats := UInt<1>("h00") + reg reg_time : UInt<64>, clock, reset + reg T_2431 : UInt<6>, clock, reset + onreset T_2431 := UInt<6>("h00") + node T_2433 = neq(UInt<1>("h01"), UInt<1>("h00")) + node T_2435 = addw(T_2431, UInt<7>("h01")) + when T_2433 : + node T_2436 = bits(T_2435, 5, 0) + T_2431 := T_2436 + skip + reg T_2438 : UInt<58>, clock, reset + onreset T_2438 := UInt<58>("h00") + node T_2439 = bit(T_2435, 6) + node T_2440 = and(T_2433, T_2439) + when T_2440 : + node T_2442 = addw(T_2438, UInt<1>("h01")) + T_2438 := T_2442 + skip + node T_2443 = cat(T_2438, T_2431) + reg T_2445 : UInt<6>, clock, reset + onreset T_2445 := UInt<6>("h00") + node T_2447 = neq(retire, UInt<1>("h00")) + node T_2449 = addw(T_2445, UInt<7>("h01")) + when T_2447 : + node T_2450 = bits(T_2449, 5, 0) + T_2445 := T_2450 + skip + reg T_2452 : UInt<58>, clock, reset + onreset T_2452 := UInt<58>("h00") + node T_2453 = bit(T_2449, 6) + node T_2454 = and(T_2447, T_2453) + when T_2454 : + node T_2456 = addw(T_2452, UInt<1>("h01")) + T_2452 := T_2456 + skip + node T_2457 = cat(T_2452, T_2445) + reg T_2459 : UInt<6>, clock, reset + onreset T_2459 := UInt<6>("h00") + node T_2461 = neq(uarch_counters[0], UInt<1>("h00")) + node T_2463 = addw(T_2459, UInt<7>("h01")) + when T_2461 : + node T_2464 = bits(T_2463, 5, 0) + T_2459 := T_2464 + skip + reg T_2466 : UInt<58>, clock, reset + onreset T_2466 := UInt<58>("h00") + node T_2467 = bit(T_2463, 6) + node T_2468 = and(T_2461, T_2467) + when T_2468 : + node T_2470 = addw(T_2466, UInt<1>("h01")) + T_2466 := T_2470 + skip + node T_2471 = cat(T_2466, T_2459) + reg T_2473 : UInt<6>, clock, reset + onreset T_2473 := UInt<6>("h00") + node T_2475 = neq(uarch_counters[1], UInt<1>("h00")) + node T_2477 = addw(T_2473, UInt<7>("h01")) + when T_2475 : + node T_2478 = bits(T_2477, 5, 0) + T_2473 := T_2478 + skip + reg T_2480 : UInt<58>, clock, reset + onreset T_2480 := UInt<58>("h00") + node T_2481 = bit(T_2477, 6) + node T_2482 = and(T_2475, T_2481) + when T_2482 : + node T_2484 = addw(T_2480, UInt<1>("h01")) + T_2480 := T_2484 + skip + node T_2485 = cat(T_2480, T_2473) + reg T_2487 : UInt<6>, clock, reset + onreset T_2487 := UInt<6>("h00") + node T_2489 = neq(uarch_counters[2], UInt<1>("h00")) + node T_2491 = addw(T_2487, UInt<7>("h01")) + when T_2489 : + node T_2492 = bits(T_2491, 5, 0) + T_2487 := T_2492 + skip + reg T_2494 : UInt<58>, clock, reset + onreset T_2494 := UInt<58>("h00") + node T_2495 = bit(T_2491, 6) + node T_2496 = and(T_2489, T_2495) + when T_2496 : + node T_2498 = addw(T_2494, UInt<1>("h01")) + T_2494 := T_2498 + skip + node T_2499 = cat(T_2494, T_2487) + reg T_2501 : UInt<6>, clock, reset + onreset T_2501 := UInt<6>("h00") + node T_2503 = neq(uarch_counters[3], UInt<1>("h00")) + node T_2505 = addw(T_2501, UInt<7>("h01")) + when T_2503 : + node T_2506 = bits(T_2505, 5, 0) + T_2501 := T_2506 + skip + reg T_2508 : UInt<58>, clock, reset + onreset T_2508 := UInt<58>("h00") + node T_2509 = bit(T_2505, 6) + node T_2510 = and(T_2503, T_2509) + when T_2510 : + node T_2512 = addw(T_2508, UInt<1>("h01")) + T_2508 := T_2512 + skip + node T_2513 = cat(T_2508, T_2501) + reg T_2515 : UInt<6>, clock, reset + onreset T_2515 := UInt<6>("h00") + node T_2517 = neq(uarch_counters[4], UInt<1>("h00")) + node T_2519 = addw(T_2515, UInt<7>("h01")) + when T_2517 : + node T_2520 = bits(T_2519, 5, 0) + T_2515 := T_2520 + skip + reg T_2522 : UInt<58>, clock, reset + onreset T_2522 := UInt<58>("h00") + node T_2523 = bit(T_2519, 6) + node T_2524 = and(T_2517, T_2523) + when T_2524 : + node T_2526 = addw(T_2522, UInt<1>("h01")) + T_2522 := T_2526 + skip + node T_2527 = cat(T_2522, T_2515) + reg T_2529 : UInt<6>, clock, reset + onreset T_2529 := UInt<6>("h00") + node T_2531 = neq(uarch_counters[5], UInt<1>("h00")) + node T_2533 = addw(T_2529, UInt<7>("h01")) + when T_2531 : + node T_2534 = bits(T_2533, 5, 0) + T_2529 := T_2534 + skip + reg T_2536 : UInt<58>, clock, reset + onreset T_2536 := UInt<58>("h00") + node T_2537 = bit(T_2533, 6) + node T_2538 = and(T_2531, T_2537) + when T_2538 : + node T_2540 = addw(T_2536, UInt<1>("h01")) + T_2536 := T_2540 + skip + node T_2541 = cat(T_2536, T_2529) + reg T_2543 : UInt<6>, clock, reset + onreset T_2543 := UInt<6>("h00") + node T_2545 = neq(uarch_counters[6], UInt<1>("h00")) + node T_2547 = addw(T_2543, UInt<7>("h01")) + when T_2545 : + node T_2548 = bits(T_2547, 5, 0) + T_2543 := T_2548 + skip + reg T_2550 : UInt<58>, clock, reset + onreset T_2550 := UInt<58>("h00") + node T_2551 = bit(T_2547, 6) + node T_2552 = and(T_2545, T_2551) + when T_2552 : + node T_2554 = addw(T_2550, UInt<1>("h01")) + T_2550 := T_2554 + skip + node T_2555 = cat(T_2550, T_2543) + reg T_2557 : UInt<6>, clock, reset + onreset T_2557 := UInt<6>("h00") + node T_2559 = neq(uarch_counters[7], UInt<1>("h00")) + node T_2561 = addw(T_2557, UInt<7>("h01")) + when T_2559 : + node T_2562 = bits(T_2561, 5, 0) + T_2557 := T_2562 + skip + reg T_2564 : UInt<58>, clock, reset + onreset T_2564 := UInt<58>("h00") + node T_2565 = bit(T_2561, 6) + node T_2566 = and(T_2559, T_2565) + when T_2566 : + node T_2568 = addw(T_2564, UInt<1>("h01")) + T_2564 := T_2568 + skip + node T_2569 = cat(T_2564, T_2557) + reg T_2571 : UInt<6>, clock, reset + onreset T_2571 := UInt<6>("h00") + node T_2573 = neq(uarch_counters[8], UInt<1>("h00")) + node T_2575 = addw(T_2571, UInt<7>("h01")) + when T_2573 : + node T_2576 = bits(T_2575, 5, 0) + T_2571 := T_2576 + skip + reg T_2578 : UInt<58>, clock, reset + onreset T_2578 := UInt<58>("h00") + node T_2579 = bit(T_2575, 6) + node T_2580 = and(T_2573, T_2579) + when T_2580 : + node T_2582 = addw(T_2578, UInt<1>("h01")) + T_2578 := T_2582 + skip + node T_2583 = cat(T_2578, T_2571) + reg T_2585 : UInt<6>, clock, reset + onreset T_2585 := UInt<6>("h00") + node T_2587 = neq(uarch_counters[9], UInt<1>("h00")) + node T_2589 = addw(T_2585, UInt<7>("h01")) + when T_2587 : + node T_2590 = bits(T_2589, 5, 0) + T_2585 := T_2590 + skip + reg T_2592 : UInt<58>, clock, reset + onreset T_2592 := UInt<58>("h00") + node T_2593 = bit(T_2589, 6) + node T_2594 = and(T_2587, T_2593) + when T_2594 : + node T_2596 = addw(T_2592, UInt<1>("h01")) + T_2592 := T_2596 + skip + node T_2597 = cat(T_2592, T_2585) + reg T_2599 : UInt<6>, clock, reset + onreset T_2599 := UInt<6>("h00") + node T_2601 = neq(uarch_counters[10], UInt<1>("h00")) + node T_2603 = addw(T_2599, UInt<7>("h01")) + when T_2601 : + node T_2604 = bits(T_2603, 5, 0) + T_2599 := T_2604 + skip + reg T_2606 : UInt<58>, clock, reset + onreset T_2606 := UInt<58>("h00") + node T_2607 = bit(T_2603, 6) + node T_2608 = and(T_2601, T_2607) + when T_2608 : + node T_2610 = addw(T_2606, UInt<1>("h01")) + T_2606 := T_2610 + skip + node T_2611 = cat(T_2606, T_2599) + reg T_2613 : UInt<6>, clock, reset + onreset T_2613 := UInt<6>("h00") + node T_2615 = neq(uarch_counters[11], UInt<1>("h00")) + node T_2617 = addw(T_2613, UInt<7>("h01")) + when T_2615 : + node T_2618 = bits(T_2617, 5, 0) + T_2613 := T_2618 + skip + reg T_2620 : UInt<58>, clock, reset + onreset T_2620 := UInt<58>("h00") + node T_2621 = bit(T_2617, 6) + node T_2622 = and(T_2615, T_2621) + when T_2622 : + node T_2624 = addw(T_2620, UInt<1>("h01")) + T_2620 := T_2624 + skip + node T_2625 = cat(T_2620, T_2613) + reg T_2627 : UInt<6>, clock, reset + onreset T_2627 := UInt<6>("h00") + node T_2629 = neq(uarch_counters[12], UInt<1>("h00")) + node T_2631 = addw(T_2627, UInt<7>("h01")) + when T_2629 : + node T_2632 = bits(T_2631, 5, 0) + T_2627 := T_2632 + skip + reg T_2634 : UInt<58>, clock, reset + onreset T_2634 := UInt<58>("h00") + node T_2635 = bit(T_2631, 6) + node T_2636 = and(T_2629, T_2635) + when T_2636 : + node T_2638 = addw(T_2634, UInt<1>("h01")) + T_2634 := T_2638 + skip + node T_2639 = cat(T_2634, T_2627) + reg T_2641 : UInt<6>, clock, reset + onreset T_2641 := UInt<6>("h00") + node T_2643 = neq(uarch_counters[13], UInt<1>("h00")) + node T_2645 = addw(T_2641, UInt<7>("h01")) + when T_2643 : + node T_2646 = bits(T_2645, 5, 0) + T_2641 := T_2646 + skip + reg T_2648 : UInt<58>, clock, reset + onreset T_2648 := UInt<58>("h00") + node T_2649 = bit(T_2645, 6) + node T_2650 = and(T_2643, T_2649) + when T_2650 : + node T_2652 = addw(T_2648, UInt<1>("h01")) + T_2648 := T_2652 + skip + node T_2653 = cat(T_2648, T_2641) + reg T_2655 : UInt<6>, clock, reset + onreset T_2655 := UInt<6>("h00") + node T_2657 = neq(uarch_counters[14], UInt<1>("h00")) + node T_2659 = addw(T_2655, UInt<7>("h01")) + when T_2657 : + node T_2660 = bits(T_2659, 5, 0) + T_2655 := T_2660 + skip + reg T_2662 : UInt<58>, clock, reset + onreset T_2662 := UInt<58>("h00") + node T_2663 = bit(T_2659, 6) + node T_2664 = and(T_2657, T_2663) + when T_2664 : + node T_2666 = addw(T_2662, UInt<1>("h01")) + T_2662 := T_2666 + skip + node T_2667 = cat(T_2662, T_2655) + reg T_2669 : UInt<6>, clock, reset + onreset T_2669 := UInt<6>("h00") + node T_2671 = neq(uarch_counters[15], UInt<1>("h00")) + node T_2673 = addw(T_2669, UInt<7>("h01")) + when T_2671 : + node T_2674 = bits(T_2673, 5, 0) + T_2669 := T_2674 + skip + reg T_2676 : UInt<58>, clock, reset + onreset T_2676 := UInt<58>("h00") + node T_2677 = bit(T_2673, 6) + node T_2678 = and(T_2671, T_2677) + when T_2678 : + node T_2680 = addw(T_2676, UInt<1>("h01")) + T_2676 := T_2680 + skip + node T_2681 = cat(T_2676, T_2669) + reg reg_fflags : UInt<5>, clock, reset + reg reg_frm : UInt<3>, clock, reset + node irq_rocc = and(UInt<1>("h00"), rocc.interrupt) + interrupt_cause := UInt<1>("h00") + node T_2689 = bit(interrupt_cause, 63) + interrupt := T_2689 + wire some_interrupt_pending : UInt<1> + some_interrupt_pending := UInt<1>("h00") + node T_2693 = and(reg_mie.ssip, reg_mip.ssip) + node T_2694 = lt(reg_mstatus.prv, UInt<1>("h01")) + node T_2695 = eq(reg_mstatus.prv, UInt<1>("h01")) + node T_2696 = and(T_2695, reg_mstatus.ie) + node T_2697 = or(T_2694, T_2696) + node T_2698 = and(T_2693, T_2697) + when T_2698 : + interrupt_cause := UInt<64>("h08000000000000000") + skip + node T_2700 = leq(reg_mstatus.prv, UInt<1>("h01")) + node T_2701 = and(T_2693, T_2700) + when T_2701 : + some_interrupt_pending := UInt<1>("h01") + skip + node T_2704 = and(reg_mie.msip, reg_mip.msip) + node T_2705 = lt(reg_mstatus.prv, UInt<2>("h03")) + node T_2706 = eq(reg_mstatus.prv, UInt<2>("h03")) + node T_2707 = and(T_2706, reg_mstatus.ie) + node T_2708 = or(T_2705, T_2707) + node T_2709 = and(T_2704, T_2708) + when T_2709 : + interrupt_cause := UInt<64>("h08000000000000000") + skip + node T_2711 = leq(reg_mstatus.prv, UInt<2>("h03")) + node T_2712 = and(T_2704, T_2711) + when T_2712 : + some_interrupt_pending := UInt<1>("h01") + skip + node T_2715 = and(reg_mie.stip, reg_mip.stip) + node T_2716 = lt(reg_mstatus.prv, UInt<1>("h01")) + node T_2717 = eq(reg_mstatus.prv, UInt<1>("h01")) + node T_2718 = and(T_2717, reg_mstatus.ie) + node T_2719 = or(T_2716, T_2718) + node T_2720 = and(T_2715, T_2719) + when T_2720 : + interrupt_cause := UInt<64>("h08000000000000001") + skip + node T_2722 = leq(reg_mstatus.prv, UInt<1>("h01")) + node T_2723 = and(T_2715, T_2722) + when T_2723 : + some_interrupt_pending := UInt<1>("h01") + skip + node T_2726 = and(reg_mie.mtip, reg_mip.mtip) + node T_2727 = lt(reg_mstatus.prv, UInt<2>("h03")) + node T_2728 = eq(reg_mstatus.prv, UInt<2>("h03")) + node T_2729 = and(T_2728, reg_mstatus.ie) + node T_2730 = or(T_2727, T_2729) + node T_2731 = and(T_2726, T_2730) + when T_2731 : + interrupt_cause := UInt<64>("h08000000000000001") + skip + node T_2733 = leq(reg_mstatus.prv, UInt<2>("h03")) + node T_2734 = and(T_2726, T_2733) + when T_2734 : + some_interrupt_pending := UInt<1>("h01") + skip + node T_2738 = neq(reg_fromhost, UInt<1>("h00")) + node T_2739 = lt(reg_mstatus.prv, UInt<2>("h03")) + node T_2740 = eq(reg_mstatus.prv, UInt<2>("h03")) + node T_2741 = and(T_2740, reg_mstatus.ie) + node T_2742 = or(T_2739, T_2741) + node T_2743 = and(T_2738, T_2742) + when T_2743 : + interrupt_cause := UInt<64>("h08000000000000002") + skip + node T_2745 = leq(reg_mstatus.prv, UInt<2>("h03")) + node T_2746 = and(T_2738, T_2745) + when T_2746 : + some_interrupt_pending := UInt<1>("h01") + skip + node T_2749 = lt(reg_mstatus.prv, UInt<2>("h03")) + node T_2750 = eq(reg_mstatus.prv, UInt<2>("h03")) + node T_2751 = and(T_2750, reg_mstatus.ie) + node T_2752 = or(T_2749, T_2751) + node T_2753 = and(irq_rocc, T_2752) + when T_2753 : + interrupt_cause := UInt<64>("h08000000000000003") + skip + node T_2755 = leq(reg_mstatus.prv, UInt<2>("h03")) + node T_2756 = and(irq_rocc, T_2755) + when T_2756 : + some_interrupt_pending := UInt<1>("h01") + skip + node system_insn = eq(rw.cmd, UInt<3>("h04")) + node T_2759 = neq(rw.cmd, UInt<3>("h00")) + node T_2761 = eq(system_insn, UInt<1>("h00")) + node cpu_ren = and(T_2759, T_2761) + reg host_pcr_req_valid : UInt<1>, clock, reset + node T_2766 = eq(cpu_ren, UInt<1>("h00")) + node host_pcr_req_fire = and(host_pcr_req_valid, T_2766) + reg host_pcr_rep_valid : UInt<1>, clock, reset + reg host_pcr_bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}, clock, reset + node T_2775 = eq(host_pcr_req_valid, UInt<1>("h00")) + node T_2777 = eq(host_pcr_rep_valid, UInt<1>("h00")) + node T_2778 = and(T_2775, T_2777) + host.pcr_req.ready := T_2778 + host.pcr_rep.valid := host_pcr_rep_valid + host.pcr_rep.bits := host_pcr_bits.data + node T_2779 = and(host.pcr_req.ready, host.pcr_req.valid) + when T_2779 : + host_pcr_req_valid := UInt<1>("h01") + host_pcr_bits <> host.pcr_req.bits + skip + when host_pcr_req_fire : + host_pcr_req_valid := UInt<1>("h00") + host_pcr_rep_valid := UInt<1>("h01") + host_pcr_bits.data := rw.rdata + skip + node T_2783 = and(host.pcr_rep.ready, host.pcr_rep.valid) + when T_2783 : + host_pcr_rep_valid := UInt<1>("h00") + skip + host.debug_stats_pcr := reg_stats + node T_2785 = cat(status.sd, status.zero2) + node T_2786 = cat(status.sd_rv32, status.zero1) + node T_2787 = cat(T_2785, T_2786) + node T_2788 = cat(status.vm, status.mprv) + node T_2789 = cat(status.xs, status.fs) + node T_2790 = cat(T_2788, T_2789) + node T_2791 = cat(T_2787, T_2790) + node T_2792 = cat(status.prv3, status.ie3) + node T_2793 = cat(status.prv2, status.ie2) + node T_2794 = cat(T_2792, T_2793) + node T_2795 = cat(status.prv1, status.ie1) + node T_2796 = cat(status.prv, status.ie) + node T_2797 = cat(T_2795, T_2796) + node T_2798 = cat(T_2794, T_2797) + node read_mstatus = cat(T_2791, T_2798) + node T_2800 = cat(reg_frm, reg_fflags) + node T_2806 = cat(reg_mip.mtip, reg_mip.htip) + node T_2807 = cat(reg_mip.stip, reg_mip.utip) + node T_2808 = cat(T_2806, T_2807) + node T_2809 = cat(reg_mip.msip, reg_mip.hsip) + node T_2810 = cat(reg_mip.ssip, reg_mip.usip) + node T_2811 = cat(T_2809, T_2810) + node T_2812 = cat(T_2808, T_2811) + node T_2813 = cat(reg_mie.mtip, reg_mie.htip) + node T_2814 = cat(reg_mie.stip, reg_mie.utip) + node T_2815 = cat(T_2813, T_2814) + node T_2816 = cat(reg_mie.msip, reg_mie.hsip) + node T_2817 = cat(reg_mie.ssip, reg_mie.usip) + node T_2818 = cat(T_2816, T_2817) + node T_2819 = cat(T_2815, T_2818) + node T_2820 = bit(reg_mepc, 39) + node T_2822 = subw(UInt<24>("h00"), T_2820) + node T_2823 = cat(T_2822, reg_mepc) + node T_2824 = bit(reg_mbadaddr, 39) + node T_2826 = subw(UInt<24>("h00"), T_2824) + node T_2827 = cat(T_2826, reg_mbadaddr) + wire T_2854 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} + T_2854.ie := UInt<1>("h00") + T_2854.zero1 := UInt<1>("h00") + T_2854.pie := UInt<1>("h00") + T_2854.ps := UInt<1>("h00") + T_2854.zero2 := UInt<1>("h00") + T_2854.fs := UInt<1>("h00") + T_2854.xs := UInt<1>("h00") + T_2854.mprv := UInt<1>("h00") + T_2854.zero3 := UInt<1>("h00") + T_2854.sd_rv32 := UInt<1>("h00") + T_2854.zero4 := UInt<1>("h00") + T_2854.sd := UInt<1>("h00") + node T_2879 = bits(read_mstatus, 0, 0) + T_2854.ie := T_2879 + node T_2880 = bits(read_mstatus, 2, 1) + T_2854.zero1 := T_2880 + node T_2881 = bits(read_mstatus, 3, 3) + T_2854.pie := T_2881 + node T_2882 = bits(read_mstatus, 4, 4) + T_2854.ps := T_2882 + node T_2883 = bits(read_mstatus, 11, 5) + T_2854.zero2 := T_2883 + node T_2884 = bits(read_mstatus, 13, 12) + T_2854.fs := T_2884 + node T_2885 = bits(read_mstatus, 15, 14) + T_2854.xs := T_2885 + node T_2886 = bits(read_mstatus, 16, 16) + T_2854.mprv := T_2886 + node T_2887 = bits(read_mstatus, 30, 17) + T_2854.zero3 := T_2887 + node T_2888 = bits(read_mstatus, 31, 31) + T_2854.sd_rv32 := T_2888 + node T_2889 = bits(read_mstatus, 62, 32) + T_2854.zero4 := T_2889 + node T_2890 = bits(read_mstatus, 63, 63) + T_2854.sd := T_2890 + wire T_2891 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} + T_2891 <> T_2854 + T_2891.zero1 := UInt<1>("h00") + T_2891.zero2 := UInt<1>("h00") + T_2891.zero3 := UInt<1>("h00") + T_2891.zero4 := UInt<1>("h00") + wire T_2927 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_2927.usip := UInt<1>("h00") + T_2927.ssip := UInt<1>("h00") + T_2927.hsip := UInt<1>("h00") + T_2927.msip := UInt<1>("h00") + T_2927.utip := UInt<1>("h00") + T_2927.stip := UInt<1>("h00") + T_2927.htip := UInt<1>("h00") + T_2927.mtip := UInt<1>("h00") + T_2927.usip := UInt<1>("h00") + T_2927.ssip := UInt<1>("h00") + T_2927.hsip := UInt<1>("h00") + T_2927.msip := UInt<1>("h00") + T_2927.utip := UInt<1>("h00") + T_2927.stip := UInt<1>("h00") + T_2927.htip := UInt<1>("h00") + T_2927.mtip := UInt<1>("h00") + wire T_2952 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_2952 <> T_2927 + T_2952.ssip := reg_mip.ssip + T_2952.stip := reg_mip.stip + wire T_2980 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_2980.usip := UInt<1>("h00") + T_2980.ssip := UInt<1>("h00") + T_2980.hsip := UInt<1>("h00") + T_2980.msip := UInt<1>("h00") + T_2980.utip := UInt<1>("h00") + T_2980.stip := UInt<1>("h00") + T_2980.htip := UInt<1>("h00") + T_2980.mtip := UInt<1>("h00") + T_2980.usip := UInt<1>("h00") + T_2980.ssip := UInt<1>("h00") + T_2980.hsip := UInt<1>("h00") + T_2980.msip := UInt<1>("h00") + T_2980.utip := UInt<1>("h00") + T_2980.stip := UInt<1>("h00") + T_2980.htip := UInt<1>("h00") + T_2980.mtip := UInt<1>("h00") + wire T_3005 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_3005 <> T_2980 + T_3005.ssip := reg_mie.ssip + T_3005.stip := reg_mie.stip + node T_3014 = cat(T_2891.zero4, T_2891.sd_rv32) + node T_3015 = cat(T_2891.sd, T_3014) + node T_3016 = cat(T_2891.mprv, T_2891.xs) + node T_3017 = cat(T_2891.zero3, T_3016) + node T_3018 = cat(T_3015, T_3017) + node T_3019 = cat(T_2891.zero2, T_2891.ps) + node T_3020 = cat(T_2891.fs, T_3019) + node T_3021 = cat(T_2891.zero1, T_2891.ie) + node T_3022 = cat(T_2891.pie, T_3021) + node T_3023 = cat(T_3020, T_3022) + node T_3024 = cat(T_3018, T_3023) + node T_3025 = cat(T_2952.mtip, T_2952.htip) + node T_3026 = cat(T_2952.stip, T_2952.utip) + node T_3027 = cat(T_3025, T_3026) + node T_3028 = cat(T_2952.msip, T_2952.hsip) + node T_3029 = cat(T_2952.ssip, T_2952.usip) + node T_3030 = cat(T_3028, T_3029) + node T_3031 = cat(T_3027, T_3030) + node T_3032 = cat(T_3005.mtip, T_3005.htip) + node T_3033 = cat(T_3005.stip, T_3005.utip) + node T_3034 = cat(T_3032, T_3033) + node T_3035 = cat(T_3005.msip, T_3005.hsip) + node T_3036 = cat(T_3005.ssip, T_3005.usip) + node T_3037 = cat(T_3035, T_3036) + node T_3038 = cat(T_3034, T_3037) + node T_3039 = bit(reg_sbadaddr, 39) + node T_3041 = subw(UInt<24>("h00"), T_3039) + node T_3042 = cat(T_3041, reg_sbadaddr) + node T_3044 = bit(reg_sepc, 39) + node T_3046 = subw(UInt<24>("h00"), T_3044) + node T_3047 = cat(T_3046, reg_sepc) + node T_3048 = bit(reg_stvec, 38) + node T_3050 = subw(UInt<25>("h00"), T_3048) + node T_3051 = cat(T_3050, reg_stvec) + node addr = mux(cpu_ren, rw.addr, host_pcr_bits.addr) + node T_3054 = eq(addr, UInt<1>("h01")) + node T_3056 = eq(addr, UInt<2>("h02")) + node T_3058 = eq(addr, UInt<2>("h03")) + node T_3060 = eq(addr, UInt<12>("h0c00")) + node T_3062 = eq(addr, UInt<12>("h0900")) + node T_3064 = eq(addr, UInt<12>("h0c02")) + node T_3066 = eq(addr, UInt<12>("h0902")) + node T_3068 = eq(addr, UInt<12>("h0c01")) + node T_3070 = eq(addr, UInt<12>("h0901")) + node T_3072 = eq(addr, UInt<12>("h0d01")) + node T_3074 = eq(addr, UInt<12>("h0a01")) + node T_3076 = eq(addr, UInt<11>("h0701")) + node T_3078 = eq(addr, UInt<12>("h0f00")) + node T_3080 = eq(addr, UInt<12>("h0f01")) + node T_3082 = eq(addr, UInt<10>("h0300")) + node T_3084 = eq(addr, UInt<10>("h0302")) + node T_3086 = eq(addr, UInt<11>("h0782")) + node T_3088 = eq(addr, UInt<10>("h0301")) + node T_3090 = eq(addr, UInt<10>("h0344")) + node T_3092 = eq(addr, UInt<10>("h0304")) + node T_3094 = eq(addr, UInt<10>("h0340")) + node T_3096 = eq(addr, UInt<10>("h0341")) + node T_3098 = eq(addr, UInt<10>("h0343")) + node T_3100 = eq(addr, UInt<10>("h0342")) + node T_3102 = eq(addr, UInt<10>("h0321")) + node T_3104 = eq(addr, UInt<12>("h0f10")) + node T_3106 = eq(addr, UInt<11>("h0783")) + node T_3108 = eq(addr, UInt<8>("h0c0")) + node T_3110 = eq(addr, UInt<11>("h0780")) + node T_3112 = eq(addr, UInt<11>("h0781")) + node T_3114 = eq(addr, UInt<9>("h0100")) + node T_3116 = eq(addr, UInt<9>("h0144")) + node T_3118 = eq(addr, UInt<9>("h0104")) + node T_3120 = eq(addr, UInt<9>("h0140")) + node T_3122 = eq(addr, UInt<12>("h0d42")) + node T_3124 = eq(addr, UInt<12>("h0d43")) + node T_3126 = eq(addr, UInt<9>("h0180")) + node T_3128 = eq(addr, UInt<9>("h0181")) + node T_3130 = eq(addr, UInt<9>("h0141")) + node T_3132 = eq(addr, UInt<9>("h0101")) + node T_3134 = eq(addr, UInt<12>("h0cc0")) + node T_3136 = eq(addr, UInt<12>("h0cc1")) + node T_3138 = eq(addr, UInt<12>("h0cc2")) + node T_3140 = eq(addr, UInt<12>("h0cc3")) + node T_3142 = eq(addr, UInt<12>("h0cc4")) + node T_3144 = eq(addr, UInt<12>("h0cc5")) + node T_3146 = eq(addr, UInt<12>("h0cc6")) + node T_3148 = eq(addr, UInt<12>("h0cc7")) + node T_3150 = eq(addr, UInt<12>("h0cc8")) + node T_3152 = eq(addr, UInt<12>("h0cc9")) + node T_3154 = eq(addr, UInt<12>("h0cca")) + node T_3156 = eq(addr, UInt<12>("h0ccb")) + node T_3158 = eq(addr, UInt<12>("h0ccc")) + node T_3160 = eq(addr, UInt<12>("h0ccd")) + node T_3162 = eq(addr, UInt<12>("h0cce")) + node T_3164 = eq(addr, UInt<12>("h0ccf")) + node T_3165 = or(T_3054, T_3056) + node T_3166 = or(T_3165, T_3058) + node T_3167 = or(T_3166, T_3060) + node T_3168 = or(T_3167, T_3062) + node T_3169 = or(T_3168, T_3064) + node T_3170 = or(T_3169, T_3066) + node T_3171 = or(T_3170, T_3068) + node T_3172 = or(T_3171, T_3070) + node T_3173 = or(T_3172, T_3072) + node T_3174 = or(T_3173, T_3074) + node T_3175 = or(T_3174, T_3076) + node T_3176 = or(T_3175, T_3078) + node T_3177 = or(T_3176, T_3080) + node T_3178 = or(T_3177, T_3082) + node T_3179 = or(T_3178, T_3084) + node T_3180 = or(T_3179, T_3086) + node T_3181 = or(T_3180, T_3088) + node T_3182 = or(T_3181, T_3090) + node T_3183 = or(T_3182, T_3092) + node T_3184 = or(T_3183, T_3094) + node T_3185 = or(T_3184, T_3096) + node T_3186 = or(T_3185, T_3098) + node T_3187 = or(T_3186, T_3100) + node T_3188 = or(T_3187, T_3102) + node T_3189 = or(T_3188, T_3104) + node T_3190 = or(T_3189, T_3106) + node T_3191 = or(T_3190, T_3108) + node T_3192 = or(T_3191, T_3110) + node T_3193 = or(T_3192, T_3112) + node T_3194 = or(T_3193, T_3114) + node T_3195 = or(T_3194, T_3116) + node T_3196 = or(T_3195, T_3118) + node T_3197 = or(T_3196, T_3120) + node T_3198 = or(T_3197, T_3122) + node T_3199 = or(T_3198, T_3124) + node T_3200 = or(T_3199, T_3126) + node T_3201 = or(T_3200, T_3128) + node T_3202 = or(T_3201, T_3130) + node T_3203 = or(T_3202, T_3132) + node T_3204 = or(T_3203, T_3134) + node T_3205 = or(T_3204, T_3136) + node T_3206 = or(T_3205, T_3138) + node T_3207 = or(T_3206, T_3140) + node T_3208 = or(T_3207, T_3142) + node T_3209 = or(T_3208, T_3144) + node T_3210 = or(T_3209, T_3146) + node T_3211 = or(T_3210, T_3148) + node T_3212 = or(T_3211, T_3150) + node T_3213 = or(T_3212, T_3152) + node T_3214 = or(T_3213, T_3154) + node T_3215 = or(T_3214, T_3156) + node T_3216 = or(T_3215, T_3158) + node T_3217 = or(T_3216, T_3160) + node T_3218 = or(T_3217, T_3162) + node addr_valid = or(T_3218, T_3164) + node T_3220 = or(T_3054, T_3056) + node fp_csr = or(T_3220, T_3058) + node csr_addr_priv = bits(rw.addr, 9, 8) + node priv_sufficient = geq(reg_mstatus.prv, csr_addr_priv) + node T_3224 = bits(rw.addr, 11, 10) + node T_3225 = not(T_3224) + node read_only = eq(T_3225, UInt<1>("h00")) + node T_3228 = neq(rw.cmd, UInt<3>("h05")) + node T_3229 = and(cpu_ren, T_3228) + node cpu_wen = and(T_3229, priv_sufficient) + node T_3232 = eq(read_only, UInt<1>("h00")) + node T_3233 = and(cpu_wen, T_3232) + node T_3234 = and(host_pcr_req_fire, host_pcr_bits.rw) + node wen = or(T_3233, T_3234) + node T_3236 = eq(rw.cmd, UInt<3>("h01")) + node T_3237 = eq(rw.cmd, UInt<3>("h03")) + node T_3238 = not(rw.wdata) + node T_3239 = and(rw.rdata, T_3238) + node T_3240 = eq(rw.cmd, UInt<3>("h02")) + node T_3241 = or(rw.rdata, rw.wdata) + node T_3242 = mux(T_3240, T_3241, host_pcr_bits.data) + node T_3243 = mux(T_3237, T_3239, T_3242) + node wdata = mux(T_3236, rw.wdata, T_3243) + node T_3245 = bit(rw.addr, 8) + node T_3247 = eq(T_3245, UInt<1>("h00")) + node T_3248 = bit(rw.addr, 0) + node T_3250 = eq(T_3248, UInt<1>("h00")) + node T_3251 = and(T_3247, T_3250) + node insn_call = and(T_3251, system_insn) + node T_3253 = bit(rw.addr, 8) + node T_3255 = eq(T_3253, UInt<1>("h00")) + node T_3256 = bit(rw.addr, 0) + node T_3257 = and(T_3255, T_3256) + node insn_break = and(T_3257, system_insn) + node T_3259 = bit(rw.addr, 8) + node T_3260 = bit(rw.addr, 1) + node T_3262 = eq(T_3260, UInt<1>("h00")) + node T_3263 = and(T_3259, T_3262) + node T_3264 = bit(rw.addr, 0) + node T_3266 = eq(T_3264, UInt<1>("h00")) + node T_3267 = and(T_3263, T_3266) + node T_3268 = and(T_3267, system_insn) + node insn_ret = and(T_3268, priv_sufficient) + node T_3270 = bit(rw.addr, 8) + node T_3271 = bit(rw.addr, 1) + node T_3273 = eq(T_3271, UInt<1>("h00")) + node T_3274 = and(T_3270, T_3273) + node T_3275 = bit(rw.addr, 0) + node T_3276 = and(T_3274, T_3275) + node T_3277 = and(T_3276, system_insn) + node insn_sfence_vm = and(T_3277, priv_sufficient) + node T_3279 = bit(rw.addr, 2) + node maybe_insn_redirect_trap = and(T_3279, system_insn) + node insn_redirect_trap = and(maybe_insn_redirect_trap, priv_sufficient) + node T_3282 = bit(rw.addr, 8) + node T_3283 = bit(rw.addr, 1) + node T_3284 = and(T_3282, T_3283) + node T_3285 = bit(rw.addr, 0) + node T_3287 = eq(T_3285, UInt<1>("h00")) + node T_3288 = and(T_3284, T_3287) + node T_3289 = and(T_3288, system_insn) + node insn_wfi = and(T_3289, priv_sufficient) + node T_3291 = and(cpu_wen, read_only) + node T_3293 = eq(priv_sufficient, UInt<1>("h00")) + node T_3295 = eq(addr_valid, UInt<1>("h00")) + node T_3296 = or(T_3293, T_3295) + node T_3298 = neq(status.fs, UInt<1>("h00")) + node T_3300 = eq(T_3298, UInt<1>("h00")) + node T_3301 = and(fp_csr, T_3300) + node T_3302 = or(T_3296, T_3301) + node T_3303 = and(cpu_ren, T_3302) + node T_3304 = or(T_3291, T_3303) + node T_3306 = eq(priv_sufficient, UInt<1>("h00")) + node T_3307 = and(system_insn, T_3306) + node T_3308 = or(T_3304, T_3307) + node T_3309 = or(T_3308, insn_call) + node csr_xcpt_2 = or(T_3309, insn_break) + when insn_wfi : + reg_wfi := UInt<1>("h01") + skip + when some_interrupt_pending : + reg_wfi := UInt<1>("h00") + skip + fatc := insn_sfence_vm + node T_3313 = or(exception, csr_xcpt_2) + node T_3314 = shl(reg_mstatus.prv, 6) + node T_3316 = addw(T_3314, UInt<9>("h0100")) + node T_3317 = bit(reg_stvec, 38) + node T_3318 = cat(T_3317, reg_stvec) + node T_3319 = bit(reg_mstatus.prv, 1) + node T_3320 = mux(T_3319, reg_mepc, reg_sepc) + node T_3321 = mux(maybe_insn_redirect_trap, T_3318, T_3320) + node T_3322 = mux(T_3313, T_3316, T_3321) + evec := T_3322 + ptbr := reg_sptbr + csr_xcpt := csr_xcpt_2 + node T_3323 = or(insn_ret, insn_redirect_trap) + eret := T_3323 + status <> reg_mstatus + node T_3325 = neq(reg_mstatus.fs, UInt<1>("h00")) + node T_3327 = subw(UInt<2>("h00"), T_3325) + status.fs := T_3327 + node T_3329 = neq(reg_mstatus.xs, UInt<1>("h00")) + node T_3331 = subw(UInt<2>("h00"), T_3329) + status.xs := T_3331 + node T_3332 = not(status.fs) + node T_3334 = eq(T_3332, UInt<1>("h00")) + node T_3335 = not(status.xs) + node T_3337 = eq(T_3335, UInt<1>("h00")) + node T_3338 = or(T_3334, T_3337) + status.sd := T_3338 + node T_3339 = or(exception, csr_xcpt_2) + when T_3339 : + reg_mstatus.ie := UInt<1>("h00") + reg_mstatus.prv := UInt<2>("h03") + reg_mstatus.mprv := UInt<1>("h00") + reg_mstatus.prv1 := reg_mstatus.prv + reg_mstatus.ie1 := reg_mstatus.ie + reg_mstatus.prv2 := reg_mstatus.prv1 + reg_mstatus.ie2 := reg_mstatus.ie1 + node T_3343 = not(pc) + node T_3345 = or(T_3343, UInt<2>("h03")) + node T_3346 = not(T_3345) + reg_mepc := T_3346 + reg_mcause := cause + when csr_xcpt_2 : + reg_mcause := UInt<2>("h02") + when insn_break : + reg_mcause := UInt<2>("h03") + skip + when insn_call : + node T_3350 = addw(reg_mstatus.prv, UInt<4>("h08")) + reg_mcause := T_3350 + skip + skip + reg_mbadaddr := pc + node T_3352 = eq(cause, UInt<3>("h05")) + node T_3354 = eq(cause, UInt<3>("h04")) + node T_3355 = or(T_3352, T_3354) + node T_3357 = eq(cause, UInt<3>("h07")) + node T_3358 = or(T_3355, T_3357) + node T_3360 = eq(cause, UInt<3>("h06")) + node T_3361 = or(T_3358, T_3360) + when T_3361 : + node T_3362 = bits(rw.wdata, 63, 39) + node T_3363 = bits(rw.wdata, 38, 0) + node T_3364 = asSInt(T_3363) + node T_3366 = lt(T_3364, asSInt(UInt<1>("h00"))) + node T_3367 = not(T_3362) + node T_3369 = eq(T_3367, UInt<1>("h00")) + node T_3371 = neq(T_3362, UInt<1>("h00")) + node T_3372 = mux(T_3366, T_3369, T_3371) + node T_3373 = cat(T_3372, T_3363) + reg_mbadaddr := T_3373 + skip + skip + when insn_ret : + reg_mstatus.ie := reg_mstatus.ie1 + reg_mstatus.prv := reg_mstatus.prv1 + reg_mstatus.prv1 := reg_mstatus.prv2 + reg_mstatus.ie1 := reg_mstatus.ie2 + reg_mstatus.prv2 := UInt<1>("h00") + reg_mstatus.ie2 := UInt<1>("h01") + skip + when insn_redirect_trap : + reg_mstatus.prv := UInt<1>("h01") + reg_sbadaddr := reg_mbadaddr + reg_scause := reg_mcause + reg_sepc := reg_mepc + skip + node T_3378 = cat(UInt<1>("h00"), insn_redirect_trap) + node T_3379 = addw(insn_ret, T_3378) + node T_3383 = cat(UInt<1>("h00"), csr_replay) + node T_3384 = addw(csr_xcpt_2, T_3383) + node T_3385 = cat(UInt<1>("h00"), T_3384) + node T_3386 = addw(exception, T_3385) + node T_3387 = cat(UInt<1>("h00"), T_3386) + node T_3388 = addw(T_3379, T_3387) + node T_3390 = leq(T_3388, UInt<1>("h01")) + node T_3391 = geq(reg_time, reg_mtimecmp) + when T_3391 : + reg_mip.mtip := UInt<1>("h01") + skip + time := T_2443 + node T_3393 = and(cpu_wen, T_3106) + host.ipi_req.valid := T_3393 + host.ipi_req.bits := rw.wdata + node T_3395 = eq(host.ipi_req.ready, UInt<1>("h00")) + node T_3396 = and(host.ipi_req.valid, T_3395) + csr_replay := T_3396 + csr_stall := reg_wfi + node T_3398 = eq(host_pcr_bits.rw, UInt<1>("h00")) + node T_3399 = and(host_pcr_req_fire, T_3398) + node T_3400 = and(T_3399, T_3110) + when T_3400 : + reg_tohost := UInt<1>("h00") + skip + node T_3403 = mux(T_3054, reg_fflags, UInt<1>("h00")) + node T_3405 = mux(T_3056, reg_frm, UInt<1>("h00")) + node T_3407 = mux(T_3058, T_2800, UInt<1>("h00")) + node T_3409 = mux(T_3060, T_2443, UInt<1>("h00")) + node T_3411 = mux(T_3062, T_2443, UInt<1>("h00")) + node T_3413 = mux(T_3064, T_2457, UInt<1>("h00")) + node T_3415 = mux(T_3066, T_2457, UInt<1>("h00")) + node T_3417 = mux(T_3068, reg_time, UInt<1>("h00")) + node T_3419 = mux(T_3070, reg_time, UInt<1>("h00")) + node T_3421 = mux(T_3072, reg_time, UInt<1>("h00")) + node T_3423 = mux(T_3074, reg_time, UInt<1>("h00")) + node T_3425 = mux(T_3076, reg_time, UInt<1>("h00")) + node T_3427 = mux(T_3078, UInt<64>("h08000000000041129"), UInt<1>("h00")) + node T_3429 = mux(T_3080, UInt<1>("h01"), UInt<1>("h00")) + node T_3431 = mux(T_3082, read_mstatus, UInt<1>("h00")) + node T_3433 = mux(T_3084, UInt<1>("h00"), UInt<1>("h00")) + node T_3435 = mux(T_3086, UInt<1>("h00"), UInt<1>("h00")) + node T_3437 = mux(T_3088, UInt<9>("h0100"), UInt<1>("h00")) + node T_3439 = mux(T_3090, T_2812, UInt<1>("h00")) + node T_3441 = mux(T_3092, T_2819, UInt<1>("h00")) + node T_3443 = mux(T_3094, reg_mscratch, UInt<1>("h00")) + node T_3445 = mux(T_3096, T_2823, UInt<1>("h00")) + node T_3447 = mux(T_3098, T_2827, UInt<1>("h00")) + node T_3449 = mux(T_3100, reg_mcause, UInt<1>("h00")) + node T_3451 = mux(T_3102, reg_mtimecmp, UInt<1>("h00")) + node T_3453 = mux(T_3104, host.id, UInt<1>("h00")) + node T_3455 = mux(T_3106, host.id, UInt<1>("h00")) + node T_3457 = shl(reg_stats, 0) + node T_3458 = mux(T_3108, T_3457, UInt<1>("h00")) + node T_3460 = mux(T_3110, reg_tohost, UInt<1>("h00")) + node T_3462 = mux(T_3112, reg_fromhost, UInt<1>("h00")) + node T_3464 = mux(T_3114, T_3024, UInt<1>("h00")) + node T_3466 = mux(T_3116, T_3031, UInt<1>("h00")) + node T_3468 = mux(T_3118, T_3038, UInt<1>("h00")) + node T_3470 = mux(T_3120, reg_sscratch, UInt<1>("h00")) + node T_3472 = mux(T_3122, reg_scause, UInt<1>("h00")) + node T_3474 = mux(T_3124, T_3042, UInt<1>("h00")) + node T_3476 = mux(T_3126, reg_sptbr, UInt<1>("h00")) + node T_3478 = mux(T_3128, UInt<1>("h00"), UInt<1>("h00")) + node T_3480 = mux(T_3130, T_3047, UInt<1>("h00")) + node T_3482 = mux(T_3132, T_3051, UInt<1>("h00")) + node T_3484 = mux(T_3134, T_2471, UInt<1>("h00")) + node T_3486 = mux(T_3136, T_2485, UInt<1>("h00")) + node T_3488 = mux(T_3138, T_2499, UInt<1>("h00")) + node T_3490 = mux(T_3140, T_2513, UInt<1>("h00")) + node T_3492 = mux(T_3142, T_2527, UInt<1>("h00")) + node T_3494 = mux(T_3144, T_2541, UInt<1>("h00")) + node T_3496 = mux(T_3146, T_2555, UInt<1>("h00")) + node T_3498 = mux(T_3148, T_2569, UInt<1>("h00")) + node T_3500 = mux(T_3150, T_2583, UInt<1>("h00")) + node T_3502 = mux(T_3152, T_2597, UInt<1>("h00")) + node T_3504 = mux(T_3154, T_2611, UInt<1>("h00")) + node T_3506 = mux(T_3156, T_2625, UInt<1>("h00")) + node T_3508 = mux(T_3158, T_2639, UInt<1>("h00")) + node T_3510 = mux(T_3160, T_2653, UInt<1>("h00")) + node T_3512 = mux(T_3162, T_2667, UInt<1>("h00")) + node T_3514 = mux(T_3164, T_2681, UInt<1>("h00")) + node T_3516 = or(T_3403, T_3405) + node T_3517 = or(T_3516, T_3407) + node T_3518 = or(T_3517, T_3409) + node T_3519 = or(T_3518, T_3411) + node T_3520 = or(T_3519, T_3413) + node T_3521 = or(T_3520, T_3415) + node T_3522 = or(T_3521, T_3417) + node T_3523 = or(T_3522, T_3419) + node T_3524 = or(T_3523, T_3421) + node T_3525 = or(T_3524, T_3423) + node T_3526 = or(T_3525, T_3425) + node T_3527 = or(T_3526, T_3427) + node T_3528 = or(T_3527, T_3429) + node T_3529 = or(T_3528, T_3431) + node T_3530 = or(T_3529, T_3433) + node T_3531 = or(T_3530, T_3435) + node T_3532 = or(T_3531, T_3437) + node T_3533 = or(T_3532, T_3439) + node T_3534 = or(T_3533, T_3441) + node T_3535 = or(T_3534, T_3443) + node T_3536 = or(T_3535, T_3445) + node T_3537 = or(T_3536, T_3447) + node T_3538 = or(T_3537, T_3449) + node T_3539 = or(T_3538, T_3451) + node T_3540 = or(T_3539, T_3453) + node T_3541 = or(T_3540, T_3455) + node T_3542 = or(T_3541, T_3458) + node T_3543 = or(T_3542, T_3460) + node T_3544 = or(T_3543, T_3462) + node T_3545 = or(T_3544, T_3464) + node T_3546 = or(T_3545, T_3466) + node T_3547 = or(T_3546, T_3468) + node T_3548 = or(T_3547, T_3470) + node T_3549 = or(T_3548, T_3472) + node T_3550 = or(T_3549, T_3474) + node T_3551 = or(T_3550, T_3476) + node T_3552 = or(T_3551, T_3478) + node T_3553 = or(T_3552, T_3480) + node T_3554 = or(T_3553, T_3482) + node T_3555 = or(T_3554, T_3484) + node T_3556 = or(T_3555, T_3486) + node T_3557 = or(T_3556, T_3488) + node T_3558 = or(T_3557, T_3490) + node T_3559 = or(T_3558, T_3492) + node T_3560 = or(T_3559, T_3494) + node T_3561 = or(T_3560, T_3496) + node T_3562 = or(T_3561, T_3498) + node T_3563 = or(T_3562, T_3500) + node T_3564 = or(T_3563, T_3502) + node T_3565 = or(T_3564, T_3504) + node T_3566 = or(T_3565, T_3506) + node T_3567 = or(T_3566, T_3508) + node T_3568 = or(T_3567, T_3510) + node T_3569 = or(T_3568, T_3512) + node T_3570 = or(T_3569, T_3514) + wire T_3571 : UInt<64> + T_3571 := UInt<1>("h00") + T_3571 := T_3570 + rw.rdata := T_3571 + fcsr_rm := reg_frm + when fcsr_flags.valid : + node T_3573 = or(reg_fflags, fcsr_flags.bits) + reg_fflags := T_3573 + skip + when wen : + when T_3082 : + wire T_3608 : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>} + T_3608.ie := UInt<1>("h00") + T_3608.prv := UInt<1>("h00") + T_3608.ie1 := UInt<1>("h00") + T_3608.prv1 := UInt<1>("h00") + T_3608.ie2 := UInt<1>("h00") + T_3608.prv2 := UInt<1>("h00") + T_3608.ie3 := UInt<1>("h00") + T_3608.prv3 := UInt<1>("h00") + T_3608.fs := UInt<1>("h00") + T_3608.xs := UInt<1>("h00") + T_3608.mprv := UInt<1>("h00") + T_3608.vm := UInt<1>("h00") + T_3608.zero1 := UInt<1>("h00") + T_3608.sd_rv32 := UInt<1>("h00") + T_3608.zero2 := UInt<1>("h00") + T_3608.sd := UInt<1>("h00") + node T_3641 = bits(wdata, 0, 0) + T_3608.ie := T_3641 + node T_3642 = bits(wdata, 2, 1) + T_3608.prv := T_3642 + node T_3643 = bits(wdata, 3, 3) + T_3608.ie1 := T_3643 + node T_3644 = bits(wdata, 5, 4) + T_3608.prv1 := T_3644 + node T_3645 = bits(wdata, 6, 6) + T_3608.ie2 := T_3645 + node T_3646 = bits(wdata, 8, 7) + T_3608.prv2 := T_3646 + node T_3647 = bits(wdata, 9, 9) + T_3608.ie3 := T_3647 + node T_3648 = bits(wdata, 11, 10) + T_3608.prv3 := T_3648 + node T_3649 = bits(wdata, 13, 12) + T_3608.fs := T_3649 + node T_3650 = bits(wdata, 15, 14) + T_3608.xs := T_3650 + node T_3651 = bits(wdata, 16, 16) + T_3608.mprv := T_3651 + node T_3652 = bits(wdata, 21, 17) + T_3608.vm := T_3652 + node T_3653 = bits(wdata, 30, 22) + T_3608.zero1 := T_3653 + node T_3654 = bits(wdata, 31, 31) + T_3608.sd_rv32 := T_3654 + node T_3655 = bits(wdata, 62, 32) + T_3608.zero2 := T_3655 + node T_3656 = bits(wdata, 63, 63) + T_3608.sd := T_3656 + reg_mstatus.ie := T_3608.ie + reg_mstatus.ie1 := T_3608.ie1 + wire T_3661 : UInt<2>[3] + T_3661[0] := UInt<2>("h03") + T_3661[1] := UInt<1>("h00") + T_3661[2] := UInt<1>("h01") + reg_mstatus.mprv := T_3608.mprv + node T_3666 = eq(T_3661[0], T_3608.prv) + node T_3667 = eq(T_3661[1], T_3608.prv) + node T_3668 = eq(T_3661[2], T_3608.prv) + node T_3670 = or(UInt<1>("h00"), T_3666) + node T_3671 = or(T_3670, T_3667) + node T_3672 = or(T_3671, T_3668) + when T_3672 : + reg_mstatus.prv := T_3608.prv + skip + node T_3673 = eq(T_3661[0], T_3608.prv1) + node T_3674 = eq(T_3661[1], T_3608.prv1) + node T_3675 = eq(T_3661[2], T_3608.prv1) + node T_3677 = or(UInt<1>("h00"), T_3673) + node T_3678 = or(T_3677, T_3674) + node T_3679 = or(T_3678, T_3675) + when T_3679 : + reg_mstatus.prv1 := T_3608.prv1 + skip + node T_3680 = eq(T_3661[0], T_3608.prv2) + node T_3681 = eq(T_3661[1], T_3608.prv2) + node T_3682 = eq(T_3661[2], T_3608.prv2) + node T_3684 = or(UInt<1>("h00"), T_3680) + node T_3685 = or(T_3684, T_3681) + node T_3686 = or(T_3685, T_3682) + when T_3686 : + reg_mstatus.prv2 := T_3608.prv2 + skip + reg_mstatus.ie2 := T_3608.ie2 + node T_3688 = eq(T_3608.vm, UInt<1>("h00")) + when T_3688 : + reg_mstatus.vm := UInt<1>("h00") + skip + node T_3691 = eq(T_3608.vm, UInt<4>("h09")) + when T_3691 : + reg_mstatus.vm := UInt<4>("h09") + skip + reg_mstatus.fs := T_3608.fs + skip + when T_3090 : + wire T_3711 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_3711.usip := UInt<1>("h00") + T_3711.ssip := UInt<1>("h00") + T_3711.hsip := UInt<1>("h00") + T_3711.msip := UInt<1>("h00") + T_3711.utip := UInt<1>("h00") + T_3711.stip := UInt<1>("h00") + T_3711.htip := UInt<1>("h00") + T_3711.mtip := UInt<1>("h00") + node T_3728 = bits(wdata, 0, 0) + T_3711.usip := T_3728 + node T_3729 = bits(wdata, 1, 1) + T_3711.ssip := T_3729 + node T_3730 = bits(wdata, 2, 2) + T_3711.hsip := T_3730 + node T_3731 = bits(wdata, 3, 3) + T_3711.msip := T_3731 + node T_3732 = bits(wdata, 4, 4) + T_3711.utip := T_3732 + node T_3733 = bits(wdata, 5, 5) + T_3711.stip := T_3733 + node T_3734 = bits(wdata, 6, 6) + T_3711.htip := T_3734 + node T_3735 = bits(wdata, 7, 7) + T_3711.mtip := T_3735 + reg_mip.ssip := T_3711.ssip + reg_mip.stip := T_3711.stip + reg_mip.msip := T_3711.msip + skip + when T_3092 : + wire T_3754 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_3754.usip := UInt<1>("h00") + T_3754.ssip := UInt<1>("h00") + T_3754.hsip := UInt<1>("h00") + T_3754.msip := UInt<1>("h00") + T_3754.utip := UInt<1>("h00") + T_3754.stip := UInt<1>("h00") + T_3754.htip := UInt<1>("h00") + T_3754.mtip := UInt<1>("h00") + node T_3771 = bits(wdata, 0, 0) + T_3754.usip := T_3771 + node T_3772 = bits(wdata, 1, 1) + T_3754.ssip := T_3772 + node T_3773 = bits(wdata, 2, 2) + T_3754.hsip := T_3773 + node T_3774 = bits(wdata, 3, 3) + T_3754.msip := T_3774 + node T_3775 = bits(wdata, 4, 4) + T_3754.utip := T_3775 + node T_3776 = bits(wdata, 5, 5) + T_3754.stip := T_3776 + node T_3777 = bits(wdata, 6, 6) + T_3754.htip := T_3777 + node T_3778 = bits(wdata, 7, 7) + T_3754.mtip := T_3778 + reg_mie.ssip := T_3754.ssip + reg_mie.stip := T_3754.stip + reg_mie.msip := T_3754.msip + reg_mie.mtip := T_3754.mtip + skip + when T_3054 : + reg_fflags := wdata + skip + when T_3056 : + reg_frm := wdata + skip + when T_3058 : + reg_fflags := wdata + node T_3779 = shr(wdata, 5) + reg_frm := T_3779 + skip + when T_3096 : + node T_3780 = not(wdata) + node T_3782 = or(T_3780, UInt<2>("h03")) + node T_3783 = not(T_3782) + reg_mepc := T_3783 + skip + when T_3094 : + reg_mscratch := wdata + skip + when T_3100 : + node T_3785 = and(wdata, UInt<64>("h0800000000000001f")) + reg_mcause := T_3785 + skip + when T_3098 : + node T_3786 = bits(wdata, 39, 0) + reg_mbadaddr := T_3786 + skip + when T_3066 : + node T_3787 = bits(wdata, 5, 0) + T_2445 := T_3787 + node T_3788 = bits(wdata, 63, 6) + T_2452 := T_3788 + skip + when T_3102 : + reg_mtimecmp := wdata + reg_mip.mtip := UInt<1>("h00") + skip + when T_3086 : + reg_time := wdata + skip + when T_3112 : + node T_3791 = eq(reg_fromhost, UInt<1>("h00")) + node T_3793 = eq(host_pcr_req_fire, UInt<1>("h00")) + node T_3794 = or(T_3791, T_3793) + when T_3794 : + reg_fromhost := wdata + skip + skip + when T_3110 : + node T_3796 = eq(reg_tohost, UInt<1>("h00")) + node T_3797 = or(T_3796, host_pcr_req_fire) + when T_3797 : + reg_tohost := wdata + skip + skip + when T_3108 : + node T_3798 = bit(wdata, 0) + reg_stats := T_3798 + skip + when T_3114 : + wire T_3825 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} + T_3825.ie := UInt<1>("h00") + T_3825.zero1 := UInt<1>("h00") + T_3825.pie := UInt<1>("h00") + T_3825.ps := UInt<1>("h00") + T_3825.zero2 := UInt<1>("h00") + T_3825.fs := UInt<1>("h00") + T_3825.xs := UInt<1>("h00") + T_3825.mprv := UInt<1>("h00") + T_3825.zero3 := UInt<1>("h00") + T_3825.sd_rv32 := UInt<1>("h00") + T_3825.zero4 := UInt<1>("h00") + T_3825.sd := UInt<1>("h00") + node T_3850 = bits(wdata, 0, 0) + T_3825.ie := T_3850 + node T_3851 = bits(wdata, 2, 1) + T_3825.zero1 := T_3851 + node T_3852 = bits(wdata, 3, 3) + T_3825.pie := T_3852 + node T_3853 = bits(wdata, 4, 4) + T_3825.ps := T_3853 + node T_3854 = bits(wdata, 11, 5) + T_3825.zero2 := T_3854 + node T_3855 = bits(wdata, 13, 12) + T_3825.fs := T_3855 + node T_3856 = bits(wdata, 15, 14) + T_3825.xs := T_3856 + node T_3857 = bits(wdata, 16, 16) + T_3825.mprv := T_3857 + node T_3858 = bits(wdata, 30, 17) + T_3825.zero3 := T_3858 + node T_3859 = bits(wdata, 31, 31) + T_3825.sd_rv32 := T_3859 + node T_3860 = bits(wdata, 62, 32) + T_3825.zero4 := T_3860 + node T_3861 = bits(wdata, 63, 63) + T_3825.sd := T_3861 + reg_mstatus.ie := T_3825.ie + reg_mstatus.ie1 := T_3825.pie + node T_3864 = mux(T_3825.ps, UInt<1>("h01"), UInt<1>("h00")) + reg_mstatus.prv1 := T_3864 + reg_mstatus.mprv := T_3825.mprv + reg_mstatus.fs := T_3825.fs + skip + when T_3116 : + wire T_3883 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_3883.usip := UInt<1>("h00") + T_3883.ssip := UInt<1>("h00") + T_3883.hsip := UInt<1>("h00") + T_3883.msip := UInt<1>("h00") + T_3883.utip := UInt<1>("h00") + T_3883.stip := UInt<1>("h00") + T_3883.htip := UInt<1>("h00") + T_3883.mtip := UInt<1>("h00") + node T_3900 = bits(wdata, 0, 0) + T_3883.usip := T_3900 + node T_3901 = bits(wdata, 1, 1) + T_3883.ssip := T_3901 + node T_3902 = bits(wdata, 2, 2) + T_3883.hsip := T_3902 + node T_3903 = bits(wdata, 3, 3) + T_3883.msip := T_3903 + node T_3904 = bits(wdata, 4, 4) + T_3883.utip := T_3904 + node T_3905 = bits(wdata, 5, 5) + T_3883.stip := T_3905 + node T_3906 = bits(wdata, 6, 6) + T_3883.htip := T_3906 + node T_3907 = bits(wdata, 7, 7) + T_3883.mtip := T_3907 + reg_mip.ssip := T_3883.ssip + skip + when T_3118 : + wire T_3926 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_3926.usip := UInt<1>("h00") + T_3926.ssip := UInt<1>("h00") + T_3926.hsip := UInt<1>("h00") + T_3926.msip := UInt<1>("h00") + T_3926.utip := UInt<1>("h00") + T_3926.stip := UInt<1>("h00") + T_3926.htip := UInt<1>("h00") + T_3926.mtip := UInt<1>("h00") + node T_3943 = bits(wdata, 0, 0) + T_3926.usip := T_3943 + node T_3944 = bits(wdata, 1, 1) + T_3926.ssip := T_3944 + node T_3945 = bits(wdata, 2, 2) + T_3926.hsip := T_3945 + node T_3946 = bits(wdata, 3, 3) + T_3926.msip := T_3946 + node T_3947 = bits(wdata, 4, 4) + T_3926.utip := T_3947 + node T_3948 = bits(wdata, 5, 5) + T_3926.stip := T_3948 + node T_3949 = bits(wdata, 6, 6) + T_3926.htip := T_3949 + node T_3950 = bits(wdata, 7, 7) + T_3926.mtip := T_3950 + reg_mie.ssip := T_3926.ssip + reg_mie.stip := T_3926.stip + skip + when T_3120 : + reg_sscratch := wdata + skip + when T_3126 : + node T_3951 = bits(wdata, 31, 12) + node T_3953 = cat(T_3951, UInt<12>("h00")) + reg_sptbr := T_3953 + skip + when T_3130 : + node T_3954 = not(wdata) + node T_3956 = or(T_3954, UInt<2>("h03")) + node T_3957 = not(T_3956) + reg_sepc := T_3957 + skip + when T_3132 : + node T_3958 = not(wdata) + node T_3960 = or(T_3958, UInt<2>("h03")) + node T_3961 = not(T_3960) + reg_stvec := T_3961 + skip + skip + host.ipi_rep.ready := UInt<1>("h01") + when host.ipi_rep.valid : + reg_mip.msip := UInt<1>("h01") + skip + when reset : + reg_mstatus.zero1 := UInt<1>("h00") + reg_mstatus.zero2 := UInt<1>("h00") + reg_mstatus.ie := UInt<1>("h00") + reg_mstatus.prv := UInt<2>("h03") + reg_mstatus.ie1 := UInt<1>("h00") + reg_mstatus.prv1 := UInt<2>("h03") + reg_mstatus.ie2 := UInt<1>("h00") + reg_mstatus.prv2 := UInt<1>("h00") + reg_mstatus.ie3 := UInt<1>("h00") + reg_mstatus.prv3 := UInt<1>("h00") + reg_mstatus.mprv := UInt<1>("h00") + reg_mstatus.vm := UInt<1>("h00") + reg_mstatus.fs := UInt<1>("h00") + reg_mstatus.xs := UInt<1>("h00") + reg_mstatus.sd_rv32 := UInt<1>("h00") + reg_mstatus.sd := UInt<1>("h00") + skip + + module ALU : + output adder_out : UInt<64> + output out : UInt<64> + input in1 : UInt<64> + input in2 : UInt<64> + input fn : UInt<4> + input dw : UInt<1> + input clock : Clock + input reset : UInt<1> + + adder_out := UInt<1>("h00") + out := UInt<1>("h00") + node T_10 = bit(fn, 3) + node T_12 = subw(UInt<1>("h00"), in2) + node T_13 = mux(T_10, T_12, in2) + node sum = addw(in1, T_13) + node T_15 = bit(fn, 0) + node T_16 = bit(fn, 2) + node T_18 = eq(T_16, UInt<1>("h00")) + node T_20 = eq(sum, UInt<1>("h00")) + node T_21 = bit(in1, 63) + node T_22 = bit(in2, 63) + node T_23 = eq(T_21, T_22) + node T_24 = bit(sum, 63) + node T_25 = bit(fn, 1) + node T_26 = bit(in2, 63) + node T_27 = bit(in1, 63) + node T_28 = mux(T_25, T_26, T_27) + node T_29 = mux(T_23, T_24, T_28) + node T_30 = mux(T_18, T_20, T_29) + node cmp = xor(T_15, T_30) + node T_32 = bit(in2, 5) + node T_35 = and(dw, UInt<1>("h01")) + node T_36 = eq(UInt<1>("h01"), T_35) + node T_37 = and(T_32, T_36) + node T_38 = bits(in2, 4, 0) + node shamt = cat(T_37, T_38) + node T_40 = bit(fn, 3) + node T_41 = bit(in1, 31) + node T_43 = subw(UInt<32>("h00"), T_41) + node shin_hi_32 = mux(T_40, T_43, UInt<32>("h00")) + node T_48 = and(dw, UInt<1>("h01")) + node T_49 = eq(UInt<1>("h01"), T_48) + node T_50 = bits(in1, 63, 32) + node shin_hi = mux(T_49, T_50, shin_hi_32) + node T_52 = bits(in1, 31, 0) + node shin_r = cat(shin_hi, T_52) + node T_54 = eq(fn, UInt<3>("h05")) + node T_55 = eq(fn, UInt<4>("h0b")) + node T_56 = or(T_54, T_55) + node T_59 = shl(UInt<32>("h0ffffffff"), 32) + node T_60 = xor(UInt<64>("h0ffffffffffffffff"), T_59) + node T_61 = shr(shin_r, 32) + node T_62 = and(T_61, T_60) + node T_63 = bits(shin_r, 31, 0) + node T_64 = shl(T_63, 32) + node T_65 = not(T_60) + node T_66 = and(T_64, T_65) + node T_67 = or(T_62, T_66) + node T_68 = bits(T_60, 47, 0) + node T_69 = shl(T_68, 16) + node T_70 = xor(T_60, T_69) + node T_71 = shr(T_67, 16) + node T_72 = and(T_71, T_70) + node T_73 = bits(T_67, 47, 0) + node T_74 = shl(T_73, 16) + node T_75 = not(T_70) + node T_76 = and(T_74, T_75) + node T_77 = or(T_72, T_76) + node T_78 = bits(T_70, 55, 0) + node T_79 = shl(T_78, 8) + node T_80 = xor(T_70, T_79) + node T_81 = shr(T_77, 8) + node T_82 = and(T_81, T_80) + node T_83 = bits(T_77, 55, 0) + node T_84 = shl(T_83, 8) + node T_85 = not(T_80) + node T_86 = and(T_84, T_85) + node T_87 = or(T_82, T_86) + node T_88 = bits(T_80, 59, 0) + node T_89 = shl(T_88, 4) + node T_90 = xor(T_80, T_89) + node T_91 = shr(T_87, 4) + node T_92 = and(T_91, T_90) + node T_93 = bits(T_87, 59, 0) + node T_94 = shl(T_93, 4) + node T_95 = not(T_90) + node T_96 = and(T_94, T_95) + node T_97 = or(T_92, T_96) + node T_98 = bits(T_90, 61, 0) + node T_99 = shl(T_98, 2) + node T_100 = xor(T_90, T_99) + node T_101 = shr(T_97, 2) + node T_102 = and(T_101, T_100) + node T_103 = bits(T_97, 61, 0) + node T_104 = shl(T_103, 2) + node T_105 = not(T_100) + node T_106 = and(T_104, T_105) + node T_107 = or(T_102, T_106) + node T_108 = bits(T_100, 62, 0) + node T_109 = shl(T_108, 1) + node T_110 = xor(T_100, T_109) + node T_111 = shr(T_107, 1) + node T_112 = and(T_111, T_110) + node T_113 = bits(T_107, 62, 0) + node T_114 = shl(T_113, 1) + node T_115 = not(T_110) + node T_116 = and(T_114, T_115) + node T_117 = or(T_112, T_116) + node shin = mux(T_56, shin_r, T_117) + node T_119 = bit(fn, 3) + node T_120 = bit(shin, 63) + node T_121 = and(T_119, T_120) + node T_122 = cat(T_121, shin) + node T_123 = asSInt(T_122) + node T_124 = dshr(T_123, shamt) + node shout_r = bits(T_124, 63, 0) + node T_128 = shl(UInt<32>("h0ffffffff"), 32) + node T_129 = xor(UInt<64>("h0ffffffffffffffff"), T_128) + node T_130 = shr(shout_r, 32) + node T_131 = and(T_130, T_129) + node T_132 = bits(shout_r, 31, 0) + node T_133 = shl(T_132, 32) + node T_134 = not(T_129) + node T_135 = and(T_133, T_134) + node T_136 = or(T_131, T_135) + node T_137 = bits(T_129, 47, 0) + node T_138 = shl(T_137, 16) + node T_139 = xor(T_129, T_138) + node T_140 = shr(T_136, 16) + node T_141 = and(T_140, T_139) + node T_142 = bits(T_136, 47, 0) + node T_143 = shl(T_142, 16) + node T_144 = not(T_139) + node T_145 = and(T_143, T_144) + node T_146 = or(T_141, T_145) + node T_147 = bits(T_139, 55, 0) + node T_148 = shl(T_147, 8) + node T_149 = xor(T_139, T_148) + node T_150 = shr(T_146, 8) + node T_151 = and(T_150, T_149) + node T_152 = bits(T_146, 55, 0) + node T_153 = shl(T_152, 8) + node T_154 = not(T_149) + node T_155 = and(T_153, T_154) + node T_156 = or(T_151, T_155) + node T_157 = bits(T_149, 59, 0) + node T_158 = shl(T_157, 4) + node T_159 = xor(T_149, T_158) + node T_160 = shr(T_156, 4) + node T_161 = and(T_160, T_159) + node T_162 = bits(T_156, 59, 0) + node T_163 = shl(T_162, 4) + node T_164 = not(T_159) + node T_165 = and(T_163, T_164) + node T_166 = or(T_161, T_165) + node T_167 = bits(T_159, 61, 0) + node T_168 = shl(T_167, 2) + node T_169 = xor(T_159, T_168) + node T_170 = shr(T_166, 2) + node T_171 = and(T_170, T_169) + node T_172 = bits(T_166, 61, 0) + node T_173 = shl(T_172, 2) + node T_174 = not(T_169) + node T_175 = and(T_173, T_174) + node T_176 = or(T_171, T_175) + node T_177 = bits(T_169, 62, 0) + node T_178 = shl(T_177, 1) + node T_179 = xor(T_169, T_178) + node T_180 = shr(T_176, 1) + node T_181 = and(T_180, T_179) + node T_182 = bits(T_176, 62, 0) + node T_183 = shl(T_182, 1) + node T_184 = not(T_179) + node T_185 = and(T_183, T_184) + node shout_l = or(T_181, T_185) + node T_187 = eq(fn, UInt<1>("h00")) + node T_188 = eq(fn, UInt<4>("h0a")) + node T_189 = or(T_187, T_188) + node T_190 = eq(fn, UInt<3>("h05")) + node T_191 = eq(fn, UInt<4>("h0b")) + node T_192 = or(T_190, T_191) + node T_193 = eq(fn, UInt<1>("h01")) + node T_194 = eq(fn, UInt<3>("h07")) + node T_195 = and(in1, in2) + node T_196 = eq(fn, UInt<3>("h06")) + node T_197 = or(in1, in2) + node T_198 = eq(fn, UInt<3>("h04")) + node T_199 = xor(in1, in2) + node T_200 = shl(cmp, 0) + node T_201 = mux(T_198, T_199, T_200) + node T_202 = mux(T_196, T_197, T_201) + node T_203 = mux(T_194, T_195, T_202) + node T_204 = mux(T_193, shout_l, T_203) + node T_205 = mux(T_192, shout_r, T_204) + node out64 = mux(T_189, sum, T_205) + node T_209 = and(dw, UInt<1>("h01")) + node T_210 = eq(UInt<1>("h01"), T_209) + node T_211 = bits(out64, 63, 32) + node T_212 = bit(out64, 31) + node T_214 = subw(UInt<32>("h00"), T_212) + node out_hi = mux(T_210, T_211, T_214) + node T_216 = bits(out64, 31, 0) + node T_217 = cat(out_hi, T_216) + out := T_217 + adder_out := sum + + module MulDiv : + output resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}} + input kill : UInt<1> + input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}} + input clock : Clock + input reset : UInt<1> + + resp.bits.tag := UInt<1>("h00") + resp.bits.data := UInt<1>("h00") + resp.valid := UInt<1>("h00") + req.ready := UInt<1>("h00") + reg state : UInt<?>, clock, reset + onreset state := UInt<1>("h00") + reg req_1 : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clock, reset + reg count : UInt<7>, clock, reset + reg neg_out : UInt<1>, clock, reset + reg isMul : UInt<1>, clock, reset + reg isHi : UInt<1>, clock, reset + reg divisor : UInt<65>, clock, reset + reg remainder : UInt<130>, clock, reset + node T_81 = and(req.bits.fn, UInt<4>("h04")) + node T_83 = eq(T_81, UInt<4>("h00")) + node T_85 = and(req.bits.fn, UInt<4>("h08")) + node T_87 = eq(T_85, UInt<4>("h08")) + node T_89 = or(UInt<1>("h00"), T_83) + node T_90 = or(T_89, T_87) + node T_92 = and(req.bits.fn, UInt<4>("h05")) + node T_94 = eq(T_92, UInt<4>("h01")) + node T_96 = and(req.bits.fn, UInt<4>("h02")) + node T_98 = eq(T_96, UInt<4>("h02")) + node T_100 = or(UInt<1>("h00"), T_94) + node T_101 = or(T_100, T_98) + node T_102 = or(T_101, T_87) + node T_104 = and(req.bits.fn, UInt<4>("h09")) + node T_106 = eq(T_104, UInt<4>("h00")) + node T_108 = and(req.bits.fn, UInt<4>("h03")) + node T_110 = eq(T_108, UInt<4>("h00")) + node T_112 = or(UInt<1>("h00"), T_106) + node T_113 = or(T_112, T_83) + node T_114 = or(T_113, T_110) + node T_116 = or(UInt<1>("h00"), T_106) + node T_117 = or(T_116, T_83) + node cmdMul = bit(T_90, 0) + node cmdHi = bit(T_102, 0) + node lhsSigned = bit(T_114, 0) + node rhsSigned = bit(T_117, 0) + node T_124 = and(req.bits.dw, UInt<1>("h01")) + node T_125 = eq(UInt<1>("h01"), T_124) + node T_126 = bit(req.bits.in1, 63) + node T_127 = bit(req.bits.in1, 31) + node T_128 = mux(T_125, T_126, T_127) + node lhs_sign = and(lhsSigned, T_128) + node T_132 = and(req.bits.dw, UInt<1>("h01")) + node T_133 = eq(UInt<1>("h01"), T_132) + node T_134 = bits(req.bits.in1, 63, 32) + node T_136 = subw(UInt<32>("h00"), lhs_sign) + node T_137 = mux(T_133, T_134, T_136) + node T_138 = bits(req.bits.in1, 31, 0) + node lhs_in = cat(T_137, T_138) + node T_142 = and(req.bits.dw, UInt<1>("h01")) + node T_143 = eq(UInt<1>("h01"), T_142) + node T_144 = bit(req.bits.in2, 63) + node T_145 = bit(req.bits.in2, 31) + node T_146 = mux(T_143, T_144, T_145) + node rhs_sign = and(rhsSigned, T_146) + node T_150 = and(req.bits.dw, UInt<1>("h01")) + node T_151 = eq(UInt<1>("h01"), T_150) + node T_152 = bits(req.bits.in2, 63, 32) + node T_154 = subw(UInt<32>("h00"), rhs_sign) + node T_155 = mux(T_151, T_152, T_154) + node T_156 = bits(req.bits.in2, 31, 0) + node rhs_in = cat(T_155, T_156) + node T_158 = bits(remainder, 128, 64) + node T_159 = bits(divisor, 64, 0) + node subtractor = subw(T_158, T_159) + node less = bit(subtractor, 64) + node T_162 = bits(remainder, 63, 0) + node negated_remainder = subw(UInt<1>("h00"), T_162) + node T_165 = eq(state, UInt<1>("h01")) + when T_165 : + node T_166 = bit(remainder, 63) + node T_167 = or(T_166, isMul) + when T_167 : + remainder := negated_remainder + skip + node T_168 = bit(divisor, 63) + node T_169 = or(T_168, isMul) + when T_169 : + divisor := subtractor + skip + state := UInt<2>("h02") + skip + node T_170 = eq(state, UInt<3>("h04")) + when T_170 : + remainder := negated_remainder + state := UInt<3>("h05") + skip + node T_171 = eq(state, UInt<2>("h03")) + when T_171 : + node T_172 = bits(remainder, 128, 65) + remainder := T_172 + node T_173 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) + state := T_173 + skip + node T_174 = eq(state, UInt<2>("h02")) + node T_175 = and(T_174, isMul) + when T_175 : + node T_176 = bits(remainder, 129, 65) + node T_177 = bits(remainder, 63, 0) + node T_178 = cat(T_176, T_177) + node T_179 = bits(T_178, 63, 0) + node T_180 = bits(T_178, 128, 64) + node T_181 = asSInt(T_180) + node T_182 = asSInt(divisor) + node T_183 = bits(T_179, 7, 0) + node T_184 = mul(T_182, T_183) + node T_185 = addw(T_184, T_181) + node T_186 = bits(T_179, 63, 8) + node T_187 = asUInt(T_185) + node T_188 = cat(T_187, T_186) + node T_191 = mul(count, UInt<4>("h08")) + node T_192 = bits(T_191, 5, 0) + node T_193 = dshr(asSInt(UInt<65>("h010000000000000000")), T_192) + node T_194 = bits(T_193, 63, 0) + node T_197 = neq(count, UInt<3>("h07")) + node T_198 = and(UInt<1>("h01"), T_197) + node T_200 = neq(count, UInt<1>("h00")) + node T_201 = and(T_198, T_200) + node T_203 = eq(isHi, UInt<1>("h00")) + node T_204 = and(T_201, T_203) + node T_205 = not(T_194) + node T_206 = and(T_179, T_205) + node T_208 = eq(T_206, UInt<1>("h00")) + node T_209 = and(T_204, T_208) + node T_212 = mul(count, UInt<4>("h08")) + node T_213 = subw(UInt<7>("h040"), T_212) + node T_214 = bits(T_213, 5, 0) + node T_215 = dshr(T_178, T_214) + node T_216 = bits(T_188, 128, 64) + node T_217 = mux(T_209, T_215, T_188) + node T_218 = bits(T_217, 63, 0) + node T_219 = cat(T_216, T_218) + node T_220 = shr(T_219, 64) + node T_222 = bits(T_219, 63, 0) + node T_223 = cat(UInt<1>("h00"), T_222) + node T_224 = cat(T_220, T_223) + remainder := T_224 + node T_226 = addw(count, UInt<1>("h01")) + count := T_226 + node T_228 = eq(count, UInt<3>("h07")) + node T_229 = or(T_209, T_228) + when T_229 : + node T_230 = mux(isHi, UInt<2>("h03"), UInt<3>("h05")) + state := T_230 + skip + skip + node T_231 = eq(state, UInt<2>("h02")) + node T_233 = eq(isMul, UInt<1>("h00")) + node T_234 = and(T_231, T_233) + when T_234 : + node T_236 = eq(count, UInt<7>("h040")) + when T_236 : + node T_237 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) + node T_238 = mux(isHi, UInt<2>("h03"), T_237) + state := T_238 + skip + node T_240 = addw(count, UInt<1>("h01")) + count := T_240 + node T_241 = bits(remainder, 127, 64) + node T_242 = bits(subtractor, 63, 0) + node T_243 = mux(less, T_241, T_242) + node T_244 = bits(remainder, 63, 0) + node T_246 = eq(less, UInt<1>("h00")) + node T_247 = cat(T_244, T_246) + node T_248 = cat(T_243, T_247) + remainder := T_248 + node T_249 = bits(divisor, 63, 0) + node T_250 = bit(T_249, 63) + node T_252 = bit(T_249, 62) + node T_254 = bit(T_249, 61) + node T_256 = bit(T_249, 60) + node T_258 = bit(T_249, 59) + node T_260 = bit(T_249, 58) + node T_262 = bit(T_249, 57) + node T_264 = bit(T_249, 56) + node T_266 = bit(T_249, 55) + node T_268 = bit(T_249, 54) + node T_270 = bit(T_249, 53) + node T_272 = bit(T_249, 52) + node T_274 = bit(T_249, 51) + node T_276 = bit(T_249, 50) + node T_278 = bit(T_249, 49) + node T_280 = bit(T_249, 48) + node T_282 = bit(T_249, 47) + node T_284 = bit(T_249, 46) + node T_286 = bit(T_249, 45) + node T_288 = bit(T_249, 44) + node T_290 = bit(T_249, 43) + node T_292 = bit(T_249, 42) + node T_294 = bit(T_249, 41) + node T_296 = bit(T_249, 40) + node T_298 = bit(T_249, 39) + node T_300 = bit(T_249, 38) + node T_302 = bit(T_249, 37) + node T_304 = bit(T_249, 36) + node T_306 = bit(T_249, 35) + node T_308 = bit(T_249, 34) + node T_310 = bit(T_249, 33) + node T_312 = bit(T_249, 32) + node T_314 = bit(T_249, 31) + node T_316 = bit(T_249, 30) + node T_318 = bit(T_249, 29) + node T_320 = bit(T_249, 28) + node T_322 = bit(T_249, 27) + node T_324 = bit(T_249, 26) + node T_326 = bit(T_249, 25) + node T_328 = bit(T_249, 24) + node T_330 = bit(T_249, 23) + node T_332 = bit(T_249, 22) + node T_334 = bit(T_249, 21) + node T_336 = bit(T_249, 20) + node T_338 = bit(T_249, 19) + node T_340 = bit(T_249, 18) + node T_342 = bit(T_249, 17) + node T_344 = bit(T_249, 16) + node T_346 = bit(T_249, 15) + node T_348 = bit(T_249, 14) + node T_350 = bit(T_249, 13) + node T_352 = bit(T_249, 12) + node T_354 = bit(T_249, 11) + node T_356 = bit(T_249, 10) + node T_358 = bit(T_249, 9) + node T_360 = bit(T_249, 8) + node T_362 = bit(T_249, 7) + node T_364 = bit(T_249, 6) + node T_366 = bit(T_249, 5) + node T_368 = bit(T_249, 4) + node T_370 = bit(T_249, 3) + node T_372 = bit(T_249, 2) + node T_374 = bit(T_249, 1) + node T_375 = shl(T_374, 0) + node T_376 = mux(T_372, UInt<2>("h02"), T_375) + node T_377 = mux(T_370, UInt<2>("h03"), T_376) + node T_378 = mux(T_368, UInt<3>("h04"), T_377) + node T_379 = mux(T_366, UInt<3>("h05"), T_378) + node T_380 = mux(T_364, UInt<3>("h06"), T_379) + node T_381 = mux(T_362, UInt<3>("h07"), T_380) + node T_382 = mux(T_360, UInt<4>("h08"), T_381) + node T_383 = mux(T_358, UInt<4>("h09"), T_382) + node T_384 = mux(T_356, UInt<4>("h0a"), T_383) + node T_385 = mux(T_354, UInt<4>("h0b"), T_384) + node T_386 = mux(T_352, UInt<4>("h0c"), T_385) + node T_387 = mux(T_350, UInt<4>("h0d"), T_386) + node T_388 = mux(T_348, UInt<4>("h0e"), T_387) + node T_389 = mux(T_346, UInt<4>("h0f"), T_388) + node T_390 = mux(T_344, UInt<5>("h010"), T_389) + node T_391 = mux(T_342, UInt<5>("h011"), T_390) + node T_392 = mux(T_340, UInt<5>("h012"), T_391) + node T_393 = mux(T_338, UInt<5>("h013"), T_392) + node T_394 = mux(T_336, UInt<5>("h014"), T_393) + node T_395 = mux(T_334, UInt<5>("h015"), T_394) + node T_396 = mux(T_332, UInt<5>("h016"), T_395) + node T_397 = mux(T_330, UInt<5>("h017"), T_396) + node T_398 = mux(T_328, UInt<5>("h018"), T_397) + node T_399 = mux(T_326, UInt<5>("h019"), T_398) + node T_400 = mux(T_324, UInt<5>("h01a"), T_399) + node T_401 = mux(T_322, UInt<5>("h01b"), T_400) + node T_402 = mux(T_320, UInt<5>("h01c"), T_401) + node T_403 = mux(T_318, UInt<5>("h01d"), T_402) + node T_404 = mux(T_316, UInt<5>("h01e"), T_403) + node T_405 = mux(T_314, UInt<5>("h01f"), T_404) + node T_406 = mux(T_312, UInt<6>("h020"), T_405) + node T_407 = mux(T_310, UInt<6>("h021"), T_406) + node T_408 = mux(T_308, UInt<6>("h022"), T_407) + node T_409 = mux(T_306, UInt<6>("h023"), T_408) + node T_410 = mux(T_304, UInt<6>("h024"), T_409) + node T_411 = mux(T_302, UInt<6>("h025"), T_410) + node T_412 = mux(T_300, UInt<6>("h026"), T_411) + node T_413 = mux(T_298, UInt<6>("h027"), T_412) + node T_414 = mux(T_296, UInt<6>("h028"), T_413) + node T_415 = mux(T_294, UInt<6>("h029"), T_414) + node T_416 = mux(T_292, UInt<6>("h02a"), T_415) + node T_417 = mux(T_290, UInt<6>("h02b"), T_416) + node T_418 = mux(T_288, UInt<6>("h02c"), T_417) + node T_419 = mux(T_286, UInt<6>("h02d"), T_418) + node T_420 = mux(T_284, UInt<6>("h02e"), T_419) + node T_421 = mux(T_282, UInt<6>("h02f"), T_420) + node T_422 = mux(T_280, UInt<6>("h030"), T_421) + node T_423 = mux(T_278, UInt<6>("h031"), T_422) + node T_424 = mux(T_276, UInt<6>("h032"), T_423) + node T_425 = mux(T_274, UInt<6>("h033"), T_424) + node T_426 = mux(T_272, UInt<6>("h034"), T_425) + node T_427 = mux(T_270, UInt<6>("h035"), T_426) + node T_428 = mux(T_268, UInt<6>("h036"), T_427) + node T_429 = mux(T_266, UInt<6>("h037"), T_428) + node T_430 = mux(T_264, UInt<6>("h038"), T_429) + node T_431 = mux(T_262, UInt<6>("h039"), T_430) + node T_432 = mux(T_260, UInt<6>("h03a"), T_431) + node T_433 = mux(T_258, UInt<6>("h03b"), T_432) + node T_434 = mux(T_256, UInt<6>("h03c"), T_433) + node T_435 = mux(T_254, UInt<6>("h03d"), T_434) + node T_436 = mux(T_252, UInt<6>("h03e"), T_435) + node T_437 = mux(T_250, UInt<6>("h03f"), T_436) + node T_438 = bits(remainder, 63, 0) + node T_439 = bit(T_438, 63) + node T_441 = bit(T_438, 62) + node T_443 = bit(T_438, 61) + node T_445 = bit(T_438, 60) + node T_447 = bit(T_438, 59) + node T_449 = bit(T_438, 58) + node T_451 = bit(T_438, 57) + node T_453 = bit(T_438, 56) + node T_455 = bit(T_438, 55) + node T_457 = bit(T_438, 54) + node T_459 = bit(T_438, 53) + node T_461 = bit(T_438, 52) + node T_463 = bit(T_438, 51) + node T_465 = bit(T_438, 50) + node T_467 = bit(T_438, 49) + node T_469 = bit(T_438, 48) + node T_471 = bit(T_438, 47) + node T_473 = bit(T_438, 46) + node T_475 = bit(T_438, 45) + node T_477 = bit(T_438, 44) + node T_479 = bit(T_438, 43) + node T_481 = bit(T_438, 42) + node T_483 = bit(T_438, 41) + node T_485 = bit(T_438, 40) + node T_487 = bit(T_438, 39) + node T_489 = bit(T_438, 38) + node T_491 = bit(T_438, 37) + node T_493 = bit(T_438, 36) + node T_495 = bit(T_438, 35) + node T_497 = bit(T_438, 34) + node T_499 = bit(T_438, 33) + node T_501 = bit(T_438, 32) + node T_503 = bit(T_438, 31) + node T_505 = bit(T_438, 30) + node T_507 = bit(T_438, 29) + node T_509 = bit(T_438, 28) + node T_511 = bit(T_438, 27) + node T_513 = bit(T_438, 26) + node T_515 = bit(T_438, 25) + node T_517 = bit(T_438, 24) + node T_519 = bit(T_438, 23) + node T_521 = bit(T_438, 22) + node T_523 = bit(T_438, 21) + node T_525 = bit(T_438, 20) + node T_527 = bit(T_438, 19) + node T_529 = bit(T_438, 18) + node T_531 = bit(T_438, 17) + node T_533 = bit(T_438, 16) + node T_535 = bit(T_438, 15) + node T_537 = bit(T_438, 14) + node T_539 = bit(T_438, 13) + node T_541 = bit(T_438, 12) + node T_543 = bit(T_438, 11) + node T_545 = bit(T_438, 10) + node T_547 = bit(T_438, 9) + node T_549 = bit(T_438, 8) + node T_551 = bit(T_438, 7) + node T_553 = bit(T_438, 6) + node T_555 = bit(T_438, 5) + node T_557 = bit(T_438, 4) + node T_559 = bit(T_438, 3) + node T_561 = bit(T_438, 2) + node T_563 = bit(T_438, 1) + node T_564 = shl(T_563, 0) + node T_565 = mux(T_561, UInt<2>("h02"), T_564) + node T_566 = mux(T_559, UInt<2>("h03"), T_565) + node T_567 = mux(T_557, UInt<3>("h04"), T_566) + node T_568 = mux(T_555, UInt<3>("h05"), T_567) + node T_569 = mux(T_553, UInt<3>("h06"), T_568) + node T_570 = mux(T_551, UInt<3>("h07"), T_569) + node T_571 = mux(T_549, UInt<4>("h08"), T_570) + node T_572 = mux(T_547, UInt<4>("h09"), T_571) + node T_573 = mux(T_545, UInt<4>("h0a"), T_572) + node T_574 = mux(T_543, UInt<4>("h0b"), T_573) + node T_575 = mux(T_541, UInt<4>("h0c"), T_574) + node T_576 = mux(T_539, UInt<4>("h0d"), T_575) + node T_577 = mux(T_537, UInt<4>("h0e"), T_576) + node T_578 = mux(T_535, UInt<4>("h0f"), T_577) + node T_579 = mux(T_533, UInt<5>("h010"), T_578) + node T_580 = mux(T_531, UInt<5>("h011"), T_579) + node T_581 = mux(T_529, UInt<5>("h012"), T_580) + node T_582 = mux(T_527, UInt<5>("h013"), T_581) + node T_583 = mux(T_525, UInt<5>("h014"), T_582) + node T_584 = mux(T_523, UInt<5>("h015"), T_583) + node T_585 = mux(T_521, UInt<5>("h016"), T_584) + node T_586 = mux(T_519, UInt<5>("h017"), T_585) + node T_587 = mux(T_517, UInt<5>("h018"), T_586) + node T_588 = mux(T_515, UInt<5>("h019"), T_587) + node T_589 = mux(T_513, UInt<5>("h01a"), T_588) + node T_590 = mux(T_511, UInt<5>("h01b"), T_589) + node T_591 = mux(T_509, UInt<5>("h01c"), T_590) + node T_592 = mux(T_507, UInt<5>("h01d"), T_591) + node T_593 = mux(T_505, UInt<5>("h01e"), T_592) + node T_594 = mux(T_503, UInt<5>("h01f"), T_593) + node T_595 = mux(T_501, UInt<6>("h020"), T_594) + node T_596 = mux(T_499, UInt<6>("h021"), T_595) + node T_597 = mux(T_497, UInt<6>("h022"), T_596) + node T_598 = mux(T_495, UInt<6>("h023"), T_597) + node T_599 = mux(T_493, UInt<6>("h024"), T_598) + node T_600 = mux(T_491, UInt<6>("h025"), T_599) + node T_601 = mux(T_489, UInt<6>("h026"), T_600) + node T_602 = mux(T_487, UInt<6>("h027"), T_601) + node T_603 = mux(T_485, UInt<6>("h028"), T_602) + node T_604 = mux(T_483, UInt<6>("h029"), T_603) + node T_605 = mux(T_481, UInt<6>("h02a"), T_604) + node T_606 = mux(T_479, UInt<6>("h02b"), T_605) + node T_607 = mux(T_477, UInt<6>("h02c"), T_606) + node T_608 = mux(T_475, UInt<6>("h02d"), T_607) + node T_609 = mux(T_473, UInt<6>("h02e"), T_608) + node T_610 = mux(T_471, UInt<6>("h02f"), T_609) + node T_611 = mux(T_469, UInt<6>("h030"), T_610) + node T_612 = mux(T_467, UInt<6>("h031"), T_611) + node T_613 = mux(T_465, UInt<6>("h032"), T_612) + node T_614 = mux(T_463, UInt<6>("h033"), T_613) + node T_615 = mux(T_461, UInt<6>("h034"), T_614) + node T_616 = mux(T_459, UInt<6>("h035"), T_615) + node T_617 = mux(T_457, UInt<6>("h036"), T_616) + node T_618 = mux(T_455, UInt<6>("h037"), T_617) + node T_619 = mux(T_453, UInt<6>("h038"), T_618) + node T_620 = mux(T_451, UInt<6>("h039"), T_619) + node T_621 = mux(T_449, UInt<6>("h03a"), T_620) + node T_622 = mux(T_447, UInt<6>("h03b"), T_621) + node T_623 = mux(T_445, UInt<6>("h03c"), T_622) + node T_624 = mux(T_443, UInt<6>("h03d"), T_623) + node T_625 = mux(T_441, UInt<6>("h03e"), T_624) + node T_626 = mux(T_439, UInt<6>("h03f"), T_625) + node T_628 = addw(UInt<6>("h03f"), T_437) + node T_629 = subw(T_628, T_626) + node T_630 = gt(T_437, T_626) + node T_632 = eq(count, UInt<1>("h00")) + node T_633 = and(T_632, less) + node T_635 = gt(T_629, UInt<1>("h00")) + node T_636 = or(T_635, T_630) + node T_637 = and(T_633, T_636) + node T_639 = and(UInt<1>("h01"), T_637) + when T_639 : + node T_641 = bits(T_629, 5, 0) + node T_642 = mux(T_630, UInt<6>("h03f"), T_641) + node T_643 = bits(remainder, 63, 0) + node T_644 = dshl(T_643, T_642) + remainder := T_644 + count := T_642 + skip + node T_646 = eq(count, UInt<1>("h00")) + node T_648 = eq(less, UInt<1>("h00")) + node T_649 = and(T_646, T_648) + node T_651 = eq(isHi, UInt<1>("h00")) + node T_652 = and(T_649, T_651) + when T_652 : + neg_out := UInt<1>("h00") + skip + skip + node T_654 = and(resp.ready, resp.valid) + node T_655 = or(T_654, kill) + when T_655 : + state := UInt<1>("h00") + skip + node T_656 = and(req.ready, req.valid) + when T_656 : + node T_658 = eq(cmdMul, UInt<1>("h00")) + node T_659 = and(rhs_sign, T_658) + node T_660 = or(lhs_sign, T_659) + node T_661 = mux(T_660, UInt<1>("h01"), UInt<2>("h02")) + state := T_661 + isMul := cmdMul + isHi := cmdHi + count := UInt<1>("h00") + node T_664 = eq(cmdMul, UInt<1>("h00")) + node T_665 = neq(lhs_sign, rhs_sign) + node T_666 = mux(cmdHi, lhs_sign, T_665) + node T_667 = and(T_664, T_666) + neg_out := T_667 + node T_668 = cat(rhs_sign, rhs_in) + divisor := T_668 + remainder := lhs_in + req_1 <> req.bits + skip + resp.bits <> req_1 + node T_671 = and(req_1.dw, UInt<1>("h01")) + node T_672 = eq(UInt<1>("h00"), T_671) + node T_673 = bit(remainder, 31) + node T_675 = subw(UInt<32>("h00"), T_673) + node T_676 = bits(remainder, 31, 0) + node T_677 = cat(T_675, T_676) + node T_678 = bits(remainder, 63, 0) + node T_679 = mux(T_672, T_677, T_678) + resp.bits.data := T_679 + node T_680 = eq(state, UInt<3>("h05")) + resp.valid := T_680 + node T_681 = eq(state, UInt<1>("h00")) + req.ready := T_681 + + module Rocket : + input rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst_1 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem_1 : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, imem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, dmem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, flip exception : UInt<1>} + input fpu : {flip inst_1 : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>} + input ptw : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}} + output dmem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>} + output imem : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>} + output host : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>} + input clock : Clock + input reset : UInt<1> + + rocc.exception := UInt<1>("h00") + rocc.pptw.invalidate := UInt<1>("h00") + rocc.pptw.status.ie := UInt<1>("h00") + rocc.pptw.status.prv := UInt<1>("h00") + rocc.pptw.status.ie1 := UInt<1>("h00") + rocc.pptw.status.prv1 := UInt<1>("h00") + rocc.pptw.status.ie2 := UInt<1>("h00") + rocc.pptw.status.prv2 := UInt<1>("h00") + rocc.pptw.status.ie3 := UInt<1>("h00") + rocc.pptw.status.prv3 := UInt<1>("h00") + rocc.pptw.status.fs := UInt<1>("h00") + rocc.pptw.status.xs := UInt<1>("h00") + rocc.pptw.status.mprv := UInt<1>("h00") + rocc.pptw.status.vm := UInt<1>("h00") + rocc.pptw.status.zero1 := UInt<1>("h00") + rocc.pptw.status.sd_rv32 := UInt<1>("h00") + rocc.pptw.status.zero2 := UInt<1>("h00") + rocc.pptw.status.sd := UInt<1>("h00") + rocc.pptw.resp.bits.pte.v := UInt<1>("h00") + rocc.pptw.resp.bits.pte.typ := UInt<1>("h00") + rocc.pptw.resp.bits.pte.r := UInt<1>("h00") + rocc.pptw.resp.bits.pte.d := UInt<1>("h00") + rocc.pptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") + rocc.pptw.resp.bits.pte.ppn := UInt<1>("h00") + rocc.pptw.resp.bits.error := UInt<1>("h00") + rocc.pptw.resp.valid := UInt<1>("h00") + rocc.pptw.req.ready := UInt<1>("h00") + rocc.dptw.invalidate := UInt<1>("h00") + rocc.dptw.status.ie := UInt<1>("h00") + rocc.dptw.status.prv := UInt<1>("h00") + rocc.dptw.status.ie1 := UInt<1>("h00") + rocc.dptw.status.prv1 := UInt<1>("h00") + rocc.dptw.status.ie2 := UInt<1>("h00") + rocc.dptw.status.prv2 := UInt<1>("h00") + rocc.dptw.status.ie3 := UInt<1>("h00") + rocc.dptw.status.prv3 := UInt<1>("h00") + rocc.dptw.status.fs := UInt<1>("h00") + rocc.dptw.status.xs := UInt<1>("h00") + rocc.dptw.status.mprv := UInt<1>("h00") + rocc.dptw.status.vm := UInt<1>("h00") + rocc.dptw.status.zero1 := UInt<1>("h00") + rocc.dptw.status.sd_rv32 := UInt<1>("h00") + rocc.dptw.status.zero2 := UInt<1>("h00") + rocc.dptw.status.sd := UInt<1>("h00") + rocc.dptw.resp.bits.pte.v := UInt<1>("h00") + rocc.dptw.resp.bits.pte.typ := UInt<1>("h00") + rocc.dptw.resp.bits.pte.r := UInt<1>("h00") + rocc.dptw.resp.bits.pte.d := UInt<1>("h00") + rocc.dptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") + rocc.dptw.resp.bits.pte.ppn := UInt<1>("h00") + rocc.dptw.resp.bits.error := UInt<1>("h00") + rocc.dptw.resp.valid := UInt<1>("h00") + rocc.dptw.req.ready := UInt<1>("h00") + rocc.iptw.invalidate := UInt<1>("h00") + rocc.iptw.status.ie := UInt<1>("h00") + rocc.iptw.status.prv := UInt<1>("h00") + rocc.iptw.status.ie1 := UInt<1>("h00") + rocc.iptw.status.prv1 := UInt<1>("h00") + rocc.iptw.status.ie2 := UInt<1>("h00") + rocc.iptw.status.prv2 := UInt<1>("h00") + rocc.iptw.status.ie3 := UInt<1>("h00") + rocc.iptw.status.prv3 := UInt<1>("h00") + rocc.iptw.status.fs := UInt<1>("h00") + rocc.iptw.status.xs := UInt<1>("h00") + rocc.iptw.status.mprv := UInt<1>("h00") + rocc.iptw.status.vm := UInt<1>("h00") + rocc.iptw.status.zero1 := UInt<1>("h00") + rocc.iptw.status.sd_rv32 := UInt<1>("h00") + rocc.iptw.status.zero2 := UInt<1>("h00") + rocc.iptw.status.sd := UInt<1>("h00") + rocc.iptw.resp.bits.pte.v := UInt<1>("h00") + rocc.iptw.resp.bits.pte.typ := UInt<1>("h00") + rocc.iptw.resp.bits.pte.r := UInt<1>("h00") + rocc.iptw.resp.bits.pte.d := UInt<1>("h00") + rocc.iptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") + rocc.iptw.resp.bits.pte.ppn := UInt<1>("h00") + rocc.iptw.resp.bits.error := UInt<1>("h00") + rocc.iptw.resp.valid := UInt<1>("h00") + rocc.iptw.req.ready := UInt<1>("h00") + rocc.dmem.grant.bits.g_type := UInt<1>("h00") + rocc.dmem.grant.bits.is_builtin_type := UInt<1>("h00") + rocc.dmem.grant.bits.manager_xact_id := UInt<1>("h00") + rocc.dmem.grant.bits.client_xact_id := UInt<1>("h00") + rocc.dmem.grant.bits.data := UInt<1>("h00") + rocc.dmem.grant.bits.addr_beat := UInt<1>("h00") + rocc.dmem.grant.valid := UInt<1>("h00") + rocc.dmem.acquire.ready := UInt<1>("h00") + rocc.imem.grant.bits.g_type := UInt<1>("h00") + rocc.imem.grant.bits.is_builtin_type := UInt<1>("h00") + rocc.imem.grant.bits.manager_xact_id := UInt<1>("h00") + rocc.imem.grant.bits.client_xact_id := UInt<1>("h00") + rocc.imem.grant.bits.data := UInt<1>("h00") + rocc.imem.grant.bits.addr_beat := UInt<1>("h00") + rocc.imem.grant.valid := UInt<1>("h00") + rocc.imem.acquire.ready := UInt<1>("h00") + rocc.s := UInt<1>("h00") + rocc.mem_1.ordered := UInt<1>("h00") + rocc.mem_1.xcpt.pf.st := UInt<1>("h00") + rocc.mem_1.xcpt.pf.ld := UInt<1>("h00") + rocc.mem_1.xcpt.ma.st := UInt<1>("h00") + rocc.mem_1.xcpt.ma.ld := UInt<1>("h00") + rocc.mem_1.replay_next.bits := UInt<1>("h00") + rocc.mem_1.replay_next.valid := UInt<1>("h00") + rocc.mem_1.resp.bits.store_data := UInt<1>("h00") + rocc.mem_1.resp.bits.data_subword := UInt<1>("h00") + rocc.mem_1.resp.bits.has_data := UInt<1>("h00") + rocc.mem_1.resp.bits.replay := UInt<1>("h00") + rocc.mem_1.resp.bits.nack := UInt<1>("h00") + rocc.mem_1.resp.bits.data := UInt<1>("h00") + rocc.mem_1.resp.bits.typ := UInt<1>("h00") + rocc.mem_1.resp.bits.cmd := UInt<1>("h00") + rocc.mem_1.resp.bits.tag := UInt<1>("h00") + rocc.mem_1.resp.bits.addr := UInt<1>("h00") + rocc.mem_1.resp.valid := UInt<1>("h00") + rocc.mem_1.req.ready := UInt<1>("h00") + rocc.resp.ready := UInt<1>("h00") + rocc.cmd.bits.rs2 := UInt<1>("h00") + rocc.cmd.bits.rs1 := UInt<1>("h00") + rocc.cmd.bits.inst_1.opcode := UInt<1>("h00") + rocc.cmd.bits.inst_1.rd := UInt<1>("h00") + rocc.cmd.bits.inst_1.xs2 := UInt<1>("h00") + rocc.cmd.bits.inst_1.xs1 := UInt<1>("h00") + rocc.cmd.bits.inst_1.xd := UInt<1>("h00") + rocc.cmd.bits.inst_1.rs1 := UInt<1>("h00") + rocc.cmd.bits.inst_1.rs2 := UInt<1>("h00") + rocc.cmd.bits.inst_1.funct := UInt<1>("h00") + rocc.cmd.valid := UInt<1>("h00") + fpu.killm := UInt<1>("h00") + fpu.killx := UInt<1>("h00") + fpu.valid := UInt<1>("h00") + fpu.dmem_resp_data := UInt<1>("h00") + fpu.dmem_resp_tag := UInt<1>("h00") + fpu.dmem_resp_type := UInt<1>("h00") + fpu.dmem_resp_val := UInt<1>("h00") + fpu.fcsr_rm := UInt<1>("h00") + fpu.fromint_data := UInt<1>("h00") + fpu.inst_1 := UInt<1>("h00") + ptw.status.ie := UInt<1>("h00") + ptw.status.prv := UInt<1>("h00") + ptw.status.ie1 := UInt<1>("h00") + ptw.status.prv1 := UInt<1>("h00") + ptw.status.ie2 := UInt<1>("h00") + ptw.status.prv2 := UInt<1>("h00") + ptw.status.ie3 := UInt<1>("h00") + ptw.status.prv3 := UInt<1>("h00") + ptw.status.fs := UInt<1>("h00") + ptw.status.xs := UInt<1>("h00") + ptw.status.mprv := UInt<1>("h00") + ptw.status.vm := UInt<1>("h00") + ptw.status.zero1 := UInt<1>("h00") + ptw.status.sd_rv32 := UInt<1>("h00") + ptw.status.zero2 := UInt<1>("h00") + ptw.status.sd := UInt<1>("h00") + ptw.invalidate := UInt<1>("h00") + ptw.ptbr := UInt<1>("h00") + dmem.invalidate_lr := UInt<1>("h00") + dmem.req.bits.data := UInt<1>("h00") + dmem.req.bits.phys := UInt<1>("h00") + dmem.req.bits.kill := UInt<1>("h00") + dmem.req.bits.typ := UInt<1>("h00") + dmem.req.bits.cmd := UInt<1>("h00") + dmem.req.bits.tag := UInt<1>("h00") + dmem.req.bits.addr := UInt<1>("h00") + dmem.req.valid := UInt<1>("h00") + imem.invalidate := UInt<1>("h00") + imem.ras_update.bits.prediction.bits.bht.value := UInt<1>("h00") + imem.ras_update.bits.prediction.bits.bht.history := UInt<1>("h00") + imem.ras_update.bits.prediction.bits.entry := UInt<1>("h00") + imem.ras_update.bits.prediction.bits.target := UInt<1>("h00") + imem.ras_update.bits.prediction.bits.bridx := UInt<1>("h00") + imem.ras_update.bits.prediction.bits.mask := UInt<1>("h00") + imem.ras_update.bits.prediction.bits.taken := UInt<1>("h00") + imem.ras_update.bits.prediction.valid := UInt<1>("h00") + imem.ras_update.bits.returnAddr := UInt<1>("h00") + imem.ras_update.bits.isReturn := UInt<1>("h00") + imem.ras_update.bits.isCall := UInt<1>("h00") + imem.ras_update.valid := UInt<1>("h00") + imem.bht_update.bits.mispredict := UInt<1>("h00") + imem.bht_update.bits.taken := UInt<1>("h00") + imem.bht_update.bits.pc := UInt<1>("h00") + imem.bht_update.bits.prediction.bits.bht.value := UInt<1>("h00") + imem.bht_update.bits.prediction.bits.bht.history := UInt<1>("h00") + imem.bht_update.bits.prediction.bits.entry := UInt<1>("h00") + imem.bht_update.bits.prediction.bits.target := UInt<1>("h00") + imem.bht_update.bits.prediction.bits.bridx := UInt<1>("h00") + imem.bht_update.bits.prediction.bits.mask := UInt<1>("h00") + imem.bht_update.bits.prediction.bits.taken := UInt<1>("h00") + imem.bht_update.bits.prediction.valid := UInt<1>("h00") + imem.bht_update.valid := UInt<1>("h00") + imem.btb_update.bits.br_pc := UInt<1>("h00") + imem.btb_update.bits.isReturn := UInt<1>("h00") + imem.btb_update.bits.isJump := UInt<1>("h00") + imem.btb_update.bits.taken := UInt<1>("h00") + imem.btb_update.bits.target := UInt<1>("h00") + imem.btb_update.bits.pc := UInt<1>("h00") + imem.btb_update.bits.prediction.bits.bht.value := UInt<1>("h00") + imem.btb_update.bits.prediction.bits.bht.history := UInt<1>("h00") + imem.btb_update.bits.prediction.bits.entry := UInt<1>("h00") + imem.btb_update.bits.prediction.bits.target := UInt<1>("h00") + imem.btb_update.bits.prediction.bits.bridx := UInt<1>("h00") + imem.btb_update.bits.prediction.bits.mask := UInt<1>("h00") + imem.btb_update.bits.prediction.bits.taken := UInt<1>("h00") + imem.btb_update.bits.prediction.valid := UInt<1>("h00") + imem.btb_update.valid := UInt<1>("h00") + imem.resp.ready := UInt<1>("h00") + imem.req.bits.pc := UInt<1>("h00") + imem.req.valid := UInt<1>("h00") + host.debug_stats_pcr := UInt<1>("h00") + host.ipi_rep.ready := UInt<1>("h00") + host.ipi_req.bits := UInt<1>("h00") + host.ipi_req.valid := UInt<1>("h00") + host.pcr_rep.bits := UInt<1>("h00") + host.pcr_rep.valid := UInt<1>("h00") + host.pcr_req.ready := UInt<1>("h00") + reg ex_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem_1 : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clock, reset + reg mem_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem_1 : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clock, reset + reg wb_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem_1 : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clock, reset + reg ex_reg_xcpt_interrupt : UInt<1>, clock, reset + reg ex_reg_valid : UInt<1>, clock, reset + reg ex_reg_btb_hit : UInt<1>, clock, reset + reg ex_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock, reset + reg ex_reg_xcpt : UInt<1>, clock, reset + reg ex_reg_flush_pipe : UInt<1>, clock, reset + reg ex_reg_load_use : UInt<1>, clock, reset + reg ex_reg_cause : UInt<?>, clock, reset + reg ex_reg_pc : UInt<?>, clock, reset + reg ex_reg_inst : UInt<?>, clock, reset + reg mem_reg_xcpt_interrupt : UInt<1>, clock, reset + reg mem_reg_valid : UInt<1>, clock, reset + reg mem_reg_btb_hit : UInt<1>, clock, reset + reg mem_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock, reset + reg mem_reg_xcpt : UInt<1>, clock, reset + reg mem_reg_replay : UInt<1>, clock, reset + reg mem_reg_flush_pipe : UInt<1>, clock, reset + reg mem_reg_cause : UInt<?>, clock, reset + reg mem_reg_slow_bypass : UInt<1>, clock, reset + reg mem_reg_pc : UInt<?>, clock, reset + reg mem_reg_inst : UInt<?>, clock, reset + reg mem_reg_wdata : UInt<?>, clock, reset + reg mem_reg_rs2 : UInt<?>, clock, reset + wire take_pc_mem : UInt<1> + take_pc_mem := UInt<1>("h00") + reg wb_reg_valid : UInt<1>, clock, reset + reg wb_reg_xcpt : UInt<1>, clock, reset + reg wb_reg_replay : UInt<1>, clock, reset + reg wb_reg_cause : UInt<?>, clock, reset + reg wb_reg_rocc_pending : UInt<1>, clock, reset + onreset wb_reg_rocc_pending := UInt<1>("h00") + reg wb_reg_pc : UInt<?>, clock, reset + reg wb_reg_inst : UInt<?>, clock, reset + reg wb_reg_wdata : UInt<?>, clock, reset + reg wb_reg_rs2 : UInt<?>, clock, reset + wire take_pc_wb : UInt<1> + take_pc_wb := UInt<1>("h00") + node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) + wire id_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem_1 : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>} + id_ctrl.amo := UInt<1>("h00") + id_ctrl.fence := UInt<1>("h00") + id_ctrl.fence_i := UInt<1>("h00") + id_ctrl.csr := UInt<1>("h00") + id_ctrl.wxd := UInt<1>("h00") + id_ctrl.div := UInt<1>("h00") + id_ctrl.wfd := UInt<1>("h00") + id_ctrl.rfs3 := UInt<1>("h00") + id_ctrl.rfs2 := UInt<1>("h00") + id_ctrl.rfs1 := UInt<1>("h00") + id_ctrl.mem_type := UInt<1>("h00") + id_ctrl.mem_cmd := UInt<1>("h00") + id_ctrl.mem_1 := UInt<1>("h00") + id_ctrl.alu_fn := UInt<1>("h00") + id_ctrl.alu_dw := UInt<1>("h00") + id_ctrl.sel_imm := UInt<1>("h00") + id_ctrl.sel_alu1 := UInt<1>("h00") + id_ctrl.sel_alu2 := UInt<1>("h00") + id_ctrl.rxs1 := UInt<1>("h00") + id_ctrl.rxs2 := UInt<1>("h00") + id_ctrl.jalr := UInt<1>("h00") + id_ctrl.jal := UInt<1>("h00") + id_ctrl.branch := UInt<1>("h00") + id_ctrl.rocc := UInt<1>("h00") + id_ctrl.fp := UInt<1>("h00") + id_ctrl.legal := UInt<1>("h00") + node T_3272 = and(imem.resp.bits.data[0], UInt<32>("h0207f")) + node T_3274 = eq(T_3272, UInt<32>("h03")) + node T_3276 = and(imem.resp.bits.data[0], UInt<32>("h0106f")) + node T_3278 = eq(T_3276, UInt<32>("h03")) + node T_3280 = and(imem.resp.bits.data[0], UInt<32>("h0607f")) + node T_3282 = eq(T_3280, UInt<32>("h0f")) + node T_3284 = and(imem.resp.bits.data[0], UInt<32>("h07077")) + node T_3286 = eq(T_3284, UInt<32>("h013")) + node T_3288 = and(imem.resp.bits.data[0], UInt<32>("h05f")) + node T_3290 = eq(T_3288, UInt<32>("h017")) + node T_3292 = and(imem.resp.bits.data[0], UInt<32>("h0fc00007f")) + node T_3294 = eq(T_3292, UInt<32>("h033")) + node T_3296 = and(imem.resp.bits.data[0], UInt<32>("h0be007077")) + node T_3298 = eq(T_3296, UInt<32>("h033")) + node T_3300 = and(imem.resp.bits.data[0], UInt<32>("h04000073")) + node T_3302 = eq(T_3300, UInt<32>("h043")) + node T_3304 = and(imem.resp.bits.data[0], UInt<32>("h0e400007f")) + node T_3306 = eq(T_3304, UInt<32>("h053")) + node T_3308 = and(imem.resp.bits.data[0], UInt<32>("h0707b")) + node T_3310 = eq(T_3308, UInt<32>("h063")) + node T_3312 = and(imem.resp.bits.data[0], UInt<32>("h07f")) + node T_3314 = eq(T_3312, UInt<32>("h06f")) + node T_3316 = and(imem.resp.bits.data[0], UInt<32>("h0ffefffff")) + node T_3318 = eq(T_3316, UInt<32>("h073")) + node T_3320 = and(imem.resp.bits.data[0], UInt<32>("h0fc00305f")) + node T_3322 = eq(T_3320, UInt<32>("h01013")) + node T_3324 = and(imem.resp.bits.data[0], UInt<32>("h0fe00305f")) + node T_3326 = eq(T_3324, UInt<32>("h0101b")) + node T_3328 = and(imem.resp.bits.data[0], UInt<32>("h0605b")) + node T_3330 = eq(T_3328, UInt<32>("h02003")) + node T_3332 = and(imem.resp.bits.data[0], UInt<32>("h0207f")) + node T_3334 = eq(T_3332, UInt<32>("h02013")) + node T_3336 = and(imem.resp.bits.data[0], UInt<32>("h01800607f")) + node T_3338 = eq(T_3336, UInt<32>("h0202f")) + node T_3340 = and(imem.resp.bits.data[0], UInt<32>("h0207f")) + node T_3342 = eq(T_3340, UInt<32>("h02073")) + node T_3344 = and(imem.resp.bits.data[0], UInt<32>("h0bc00707f")) + node T_3346 = eq(T_3344, UInt<32>("h05013")) + node T_3348 = and(imem.resp.bits.data[0], UInt<32>("h0be00705f")) + node T_3350 = eq(T_3348, UInt<32>("h0501b")) + node T_3352 = and(imem.resp.bits.data[0], UInt<32>("h0be007077")) + node T_3354 = eq(T_3352, UInt<32>("h05033")) + node T_3356 = and(imem.resp.bits.data[0], UInt<32>("h0fe004077")) + node T_3358 = eq(T_3356, UInt<32>("h02004033")) + node T_3360 = and(imem.resp.bits.data[0], UInt<32>("h0e800607f")) + node T_3362 = eq(T_3360, UInt<32>("h0800202f")) + node T_3364 = and(imem.resp.bits.data[0], UInt<32>("h0ffdfffff")) + node T_3366 = eq(T_3364, UInt<32>("h010000073")) + node T_3368 = and(imem.resp.bits.data[0], UInt<32>("h0f9f0607f")) + node T_3370 = eq(T_3368, UInt<32>("h01000202f")) + node T_3372 = and(imem.resp.bits.data[0], UInt<32>("h0fff07fff")) + node T_3374 = eq(T_3372, UInt<32>("h010100073")) + node T_3376 = and(imem.resp.bits.data[0], UInt<32>("h0f400607f")) + node T_3378 = eq(T_3376, UInt<32>("h020000053")) + node T_3380 = and(imem.resp.bits.data[0], UInt<32>("h07c00607f")) + node T_3382 = eq(T_3380, UInt<32>("h020000053")) + node T_3384 = and(imem.resp.bits.data[0], UInt<32>("h07c00507f")) + node T_3386 = eq(T_3384, UInt<32>("h020000053")) + node T_3388 = eq(imem.resp.bits.data[0], UInt<32>("h030500073")) + node T_3390 = and(imem.resp.bits.data[0], UInt<32>("h07ff0007f")) + node T_3392 = eq(T_3390, UInt<32>("h040100053")) + node T_3394 = and(imem.resp.bits.data[0], UInt<32>("h07ff0007f")) + node T_3396 = eq(T_3394, UInt<32>("h042000053")) + node T_3398 = and(imem.resp.bits.data[0], UInt<32>("h0fdf0007f")) + node T_3400 = eq(T_3398, UInt<32>("h058000053")) + node T_3402 = and(imem.resp.bits.data[0], UInt<32>("h0edc0007f")) + node T_3404 = eq(T_3402, UInt<32>("h0c0000053")) + node T_3406 = and(imem.resp.bits.data[0], UInt<32>("h0fdf0607f")) + node T_3408 = eq(T_3406, UInt<32>("h0e0000053")) + node T_3410 = and(imem.resp.bits.data[0], UInt<32>("h0edf0707f")) + node T_3412 = eq(T_3410, UInt<32>("h0e0000053")) + node T_3414 = and(imem.resp.bits.data[0], UInt<32>("h0603f")) + node T_3416 = eq(T_3414, UInt<32>("h023")) + node T_3418 = and(imem.resp.bits.data[0], UInt<32>("h0306f")) + node T_3420 = eq(T_3418, UInt<32>("h01063")) + node T_3422 = and(imem.resp.bits.data[0], UInt<32>("h0407f")) + node T_3424 = eq(T_3422, UInt<32>("h04063")) + node T_3426 = and(imem.resp.bits.data[0], UInt<32>("h0fc007077")) + node T_3428 = eq(T_3426, UInt<32>("h033")) + node T_3430 = or(UInt<1>("h00"), T_3274) + node T_3431 = or(T_3430, T_3278) + node T_3432 = or(T_3431, T_3282) + node T_3433 = or(T_3432, T_3286) + node T_3434 = or(T_3433, T_3290) + node T_3435 = or(T_3434, T_3294) + node T_3436 = or(T_3435, T_3298) + node T_3437 = or(T_3436, T_3302) + node T_3438 = or(T_3437, T_3306) + node T_3439 = or(T_3438, T_3310) + node T_3440 = or(T_3439, T_3314) + node T_3441 = or(T_3440, T_3318) + node T_3442 = or(T_3441, T_3322) + node T_3443 = or(T_3442, T_3326) + node T_3444 = or(T_3443, T_3330) + node T_3445 = or(T_3444, T_3334) + node T_3446 = or(T_3445, T_3338) + node T_3447 = or(T_3446, T_3342) + node T_3448 = or(T_3447, T_3346) + node T_3449 = or(T_3448, T_3350) + node T_3450 = or(T_3449, T_3354) + node T_3451 = or(T_3450, T_3358) + node T_3452 = or(T_3451, T_3362) + node T_3453 = or(T_3452, T_3366) + node T_3454 = or(T_3453, T_3370) + node T_3455 = or(T_3454, T_3374) + node T_3456 = or(T_3455, T_3378) + node T_3457 = or(T_3456, T_3382) + node T_3458 = or(T_3457, T_3386) + node T_3459 = or(T_3458, T_3388) + node T_3460 = or(T_3459, T_3392) + node T_3461 = or(T_3460, T_3396) + node T_3462 = or(T_3461, T_3400) + node T_3463 = or(T_3462, T_3404) + node T_3464 = or(T_3463, T_3408) + node T_3465 = or(T_3464, T_3412) + node T_3466 = or(T_3465, T_3416) + node T_3467 = or(T_3466, T_3420) + node T_3468 = or(T_3467, T_3424) + node T_3469 = or(T_3468, T_3428) + node T_3471 = and(imem.resp.bits.data[0], UInt<32>("h05c")) + node T_3473 = eq(T_3471, UInt<32>("h04")) + node T_3475 = and(imem.resp.bits.data[0], UInt<32>("h060")) + node T_3477 = eq(T_3475, UInt<32>("h040")) + node T_3479 = or(UInt<1>("h00"), T_3473) + node T_3480 = or(T_3479, T_3477) + node T_3483 = and(imem.resp.bits.data[0], UInt<32>("h074")) + node T_3485 = eq(T_3483, UInt<32>("h060")) + node T_3487 = or(UInt<1>("h00"), T_3485) + node T_3489 = and(imem.resp.bits.data[0], UInt<32>("h068")) + node T_3491 = eq(T_3489, UInt<32>("h068")) + node T_3493 = or(UInt<1>("h00"), T_3491) + node T_3495 = and(imem.resp.bits.data[0], UInt<32>("h0203c")) + node T_3497 = eq(T_3495, UInt<32>("h024")) + node T_3499 = or(UInt<1>("h00"), T_3497) + node T_3501 = and(imem.resp.bits.data[0], UInt<32>("h064")) + node T_3503 = eq(T_3501, UInt<32>("h020")) + node T_3505 = and(imem.resp.bits.data[0], UInt<32>("h034")) + node T_3507 = eq(T_3505, UInt<32>("h020")) + node T_3509 = and(imem.resp.bits.data[0], UInt<32>("h02048")) + node T_3511 = eq(T_3509, UInt<32>("h02008")) + node T_3513 = or(UInt<1>("h00"), T_3503) + node T_3514 = or(T_3513, T_3507) + node T_3515 = or(T_3514, T_3511) + node T_3517 = and(imem.resp.bits.data[0], UInt<32>("h044")) + node T_3519 = eq(T_3517, UInt<32>("h00")) + node T_3521 = and(imem.resp.bits.data[0], UInt<32>("h04024")) + node T_3523 = eq(T_3521, UInt<32>("h020")) + node T_3525 = and(imem.resp.bits.data[0], UInt<32>("h038")) + node T_3527 = eq(T_3525, UInt<32>("h020")) + node T_3529 = and(imem.resp.bits.data[0], UInt<32>("h02050")) + node T_3531 = eq(T_3529, UInt<32>("h02000")) + node T_3533 = and(imem.resp.bits.data[0], UInt<32>("h090000034")) + node T_3535 = eq(T_3533, UInt<32>("h090000010")) + node T_3537 = or(UInt<1>("h00"), T_3519) + node T_3538 = or(T_3537, T_3523) + node T_3539 = or(T_3538, T_3527) + node T_3540 = or(T_3539, T_3531) + node T_3541 = or(T_3540, T_3535) + node T_3543 = and(imem.resp.bits.data[0], UInt<32>("h058")) + node T_3545 = eq(T_3543, UInt<32>("h00")) + node T_3547 = and(imem.resp.bits.data[0], UInt<32>("h020")) + node T_3549 = eq(T_3547, UInt<32>("h00")) + node T_3551 = and(imem.resp.bits.data[0], UInt<32>("h0c")) + node T_3553 = eq(T_3551, UInt<32>("h04")) + node T_3555 = and(imem.resp.bits.data[0], UInt<32>("h048")) + node T_3557 = eq(T_3555, UInt<32>("h048")) + node T_3559 = and(imem.resp.bits.data[0], UInt<32>("h04050")) + node T_3561 = eq(T_3559, UInt<32>("h04050")) + node T_3563 = or(UInt<1>("h00"), T_3545) + node T_3564 = or(T_3563, T_3549) + node T_3565 = or(T_3564, T_3553) + node T_3566 = or(T_3565, T_3557) + node T_3567 = or(T_3566, T_3561) + node T_3569 = and(imem.resp.bits.data[0], UInt<32>("h048")) + node T_3571 = eq(T_3569, UInt<32>("h00")) + node T_3573 = and(imem.resp.bits.data[0], UInt<32>("h018")) + node T_3575 = eq(T_3573, UInt<32>("h00")) + node T_3577 = and(imem.resp.bits.data[0], UInt<32>("h04008")) + node T_3579 = eq(T_3577, UInt<32>("h04000")) + node T_3581 = or(UInt<1>("h00"), T_3571) + node T_3582 = or(T_3581, T_3519) + node T_3583 = or(T_3582, T_3575) + node T_3584 = or(T_3583, T_3579) + node T_3585 = cat(T_3584, T_3567) + node T_3587 = and(imem.resp.bits.data[0], UInt<32>("h04004")) + node T_3589 = eq(T_3587, UInt<32>("h00")) + node T_3591 = and(imem.resp.bits.data[0], UInt<32>("h050")) + node T_3593 = eq(T_3591, UInt<32>("h00")) + node T_3595 = and(imem.resp.bits.data[0], UInt<32>("h024")) + node T_3597 = eq(T_3595, UInt<32>("h00")) + node T_3599 = or(UInt<1>("h00"), T_3589) + node T_3600 = or(T_3599, T_3593) + node T_3601 = or(T_3600, T_3519) + node T_3602 = or(T_3601, T_3597) + node T_3603 = or(T_3602, T_3575) + node T_3605 = and(imem.resp.bits.data[0], UInt<32>("h034")) + node T_3607 = eq(T_3605, UInt<32>("h014")) + node T_3609 = or(UInt<1>("h00"), T_3607) + node T_3610 = or(T_3609, T_3557) + node T_3611 = cat(T_3610, T_3603) + node T_3613 = and(imem.resp.bits.data[0], UInt<32>("h018")) + node T_3615 = eq(T_3613, UInt<32>("h08")) + node T_3617 = and(imem.resp.bits.data[0], UInt<32>("h044")) + node T_3619 = eq(T_3617, UInt<32>("h040")) + node T_3621 = or(UInt<1>("h00"), T_3615) + node T_3622 = or(T_3621, T_3619) + node T_3624 = and(imem.resp.bits.data[0], UInt<32>("h014")) + node T_3626 = eq(T_3624, UInt<32>("h014")) + node T_3628 = or(UInt<1>("h00"), T_3615) + node T_3629 = or(T_3628, T_3626) + node T_3631 = and(imem.resp.bits.data[0], UInt<32>("h030")) + node T_3633 = eq(T_3631, UInt<32>("h00")) + node T_3635 = and(imem.resp.bits.data[0], UInt<32>("h0201c")) + node T_3637 = eq(T_3635, UInt<32>("h04")) + node T_3639 = and(imem.resp.bits.data[0], UInt<32>("h014")) + node T_3641 = eq(T_3639, UInt<32>("h010")) + node T_3643 = or(UInt<1>("h00"), T_3633) + node T_3644 = or(T_3643, T_3637) + node T_3645 = or(T_3644, T_3641) + node T_3646 = cat(T_3629, T_3622) + node T_3647 = cat(T_3645, T_3646) + node T_3649 = and(imem.resp.bits.data[0], UInt<32>("h010")) + node T_3651 = eq(T_3649, UInt<32>("h00")) + node T_3653 = and(imem.resp.bits.data[0], UInt<32>("h08")) + node T_3655 = eq(T_3653, UInt<32>("h00")) + node T_3657 = or(UInt<1>("h00"), T_3651) + node T_3658 = or(T_3657, T_3655) + node T_3660 = and(imem.resp.bits.data[0], UInt<32>("h03054")) + node T_3662 = eq(T_3660, UInt<32>("h01010")) + node T_3664 = and(imem.resp.bits.data[0], UInt<32>("h01058")) + node T_3666 = eq(T_3664, UInt<32>("h01040")) + node T_3668 = and(imem.resp.bits.data[0], UInt<32>("h07044")) + node T_3670 = eq(T_3668, UInt<32>("h07000")) + node T_3672 = or(UInt<1>("h00"), T_3662) + node T_3673 = or(T_3672, T_3666) + node T_3674 = or(T_3673, T_3670) + node T_3676 = and(imem.resp.bits.data[0], UInt<32>("h02058")) + node T_3678 = eq(T_3676, UInt<32>("h02040")) + node T_3680 = and(imem.resp.bits.data[0], UInt<32>("h03054")) + node T_3682 = eq(T_3680, UInt<32>("h03010")) + node T_3684 = and(imem.resp.bits.data[0], UInt<32>("h06054")) + node T_3686 = eq(T_3684, UInt<32>("h06010")) + node T_3688 = and(imem.resp.bits.data[0], UInt<32>("h040003034")) + node T_3690 = eq(T_3688, UInt<32>("h040000030")) + node T_3692 = and(imem.resp.bits.data[0], UInt<32>("h040001054")) + node T_3694 = eq(T_3692, UInt<32>("h040001010")) + node T_3696 = or(UInt<1>("h00"), T_3678) + node T_3697 = or(T_3696, T_3682) + node T_3698 = or(T_3697, T_3686) + node T_3699 = or(T_3698, T_3690) + node T_3700 = or(T_3699, T_3694) + node T_3702 = and(imem.resp.bits.data[0], UInt<32>("h02054")) + node T_3704 = eq(T_3702, UInt<32>("h02010")) + node T_3706 = and(imem.resp.bits.data[0], UInt<32>("h040004054")) + node T_3708 = eq(T_3706, UInt<32>("h04010")) + node T_3710 = and(imem.resp.bits.data[0], UInt<32>("h05054")) + node T_3712 = eq(T_3710, UInt<32>("h04010")) + node T_3714 = and(imem.resp.bits.data[0], UInt<32>("h04058")) + node T_3716 = eq(T_3714, UInt<32>("h04040")) + node T_3718 = or(UInt<1>("h00"), T_3704) + node T_3719 = or(T_3718, T_3708) + node T_3720 = or(T_3719, T_3712) + node T_3721 = or(T_3720, T_3716) + node T_3723 = and(imem.resp.bits.data[0], UInt<32>("h054")) + node T_3725 = eq(T_3723, UInt<32>("h040")) + node T_3727 = and(imem.resp.bits.data[0], UInt<32>("h06054")) + node T_3729 = eq(T_3727, UInt<32>("h02010")) + node T_3731 = and(imem.resp.bits.data[0], UInt<32>("h040003054")) + node T_3733 = eq(T_3731, UInt<32>("h040001010")) + node T_3735 = or(UInt<1>("h00"), T_3725) + node T_3736 = or(T_3735, T_3729) + node T_3737 = or(T_3736, T_3690) + node T_3738 = or(T_3737, T_3733) + node T_3739 = cat(T_3700, T_3674) + node T_3740 = cat(T_3721, T_3739) + node T_3741 = cat(T_3738, T_3740) + node T_3743 = and(imem.resp.bits.data[0], UInt<32>("h0405f")) + node T_3745 = eq(T_3743, UInt<32>("h03")) + node T_3747 = and(imem.resp.bits.data[0], UInt<32>("h0107f")) + node T_3749 = eq(T_3747, UInt<32>("h03")) + node T_3751 = or(UInt<1>("h00"), T_3745) + node T_3752 = or(T_3751, T_3274) + node T_3753 = or(T_3752, T_3749) + node T_3754 = or(T_3753, T_3330) + node T_3755 = or(T_3754, T_3338) + node T_3756 = or(T_3755, T_3362) + node T_3757 = or(T_3756, T_3370) + node T_3759 = and(imem.resp.bits.data[0], UInt<32>("h028")) + node T_3761 = eq(T_3759, UInt<32>("h020")) + node T_3763 = and(imem.resp.bits.data[0], UInt<32>("h018000020")) + node T_3765 = eq(T_3763, UInt<32>("h018000020")) + node T_3767 = and(imem.resp.bits.data[0], UInt<32>("h020000020")) + node T_3769 = eq(T_3767, UInt<32>("h020000020")) + node T_3771 = or(UInt<1>("h00"), T_3761) + node T_3772 = or(T_3771, T_3765) + node T_3773 = or(T_3772, T_3769) + node T_3775 = and(imem.resp.bits.data[0], UInt<32>("h010000008")) + node T_3777 = eq(T_3775, UInt<32>("h010000008")) + node T_3779 = and(imem.resp.bits.data[0], UInt<32>("h040000008")) + node T_3781 = eq(T_3779, UInt<32>("h040000008")) + node T_3783 = or(UInt<1>("h00"), T_3777) + node T_3784 = or(T_3783, T_3781) + node T_3786 = and(imem.resp.bits.data[0], UInt<32>("h08000008")) + node T_3788 = eq(T_3786, UInt<32>("h08000008")) + node T_3790 = and(imem.resp.bits.data[0], UInt<32>("h080000008")) + node T_3792 = eq(T_3790, UInt<32>("h080000008")) + node T_3794 = or(UInt<1>("h00"), T_3788) + node T_3795 = or(T_3794, T_3777) + node T_3796 = or(T_3795, T_3792) + node T_3798 = and(imem.resp.bits.data[0], UInt<32>("h018000008")) + node T_3800 = eq(T_3798, UInt<32>("h08")) + node T_3802 = or(UInt<1>("h00"), T_3800) + node T_3804 = cat(T_3784, T_3773) + node T_3805 = cat(T_3796, T_3804) + node T_3806 = cat(T_3802, T_3805) + node T_3807 = cat(UInt<1>("h00"), T_3806) + node T_3809 = and(imem.resp.bits.data[0], UInt<32>("h01000")) + node T_3811 = eq(T_3809, UInt<32>("h01000")) + node T_3813 = or(UInt<1>("h00"), T_3811) + node T_3815 = and(imem.resp.bits.data[0], UInt<32>("h02000")) + node T_3817 = eq(T_3815, UInt<32>("h02000")) + node T_3819 = or(UInt<1>("h00"), T_3817) + node T_3821 = and(imem.resp.bits.data[0], UInt<32>("h04000")) + node T_3823 = eq(T_3821, UInt<32>("h04000")) + node T_3825 = or(UInt<1>("h00"), T_3823) + node T_3826 = cat(T_3819, T_3813) + node T_3827 = cat(T_3825, T_3826) + node T_3829 = and(imem.resp.bits.data[0], UInt<32>("h080000060")) + node T_3831 = eq(T_3829, UInt<32>("h040")) + node T_3833 = and(imem.resp.bits.data[0], UInt<32>("h010000060")) + node T_3835 = eq(T_3833, UInt<32>("h040")) + node T_3837 = and(imem.resp.bits.data[0], UInt<32>("h070")) + node T_3839 = eq(T_3837, UInt<32>("h040")) + node T_3841 = or(UInt<1>("h00"), T_3831) + node T_3842 = or(T_3841, T_3835) + node T_3843 = or(T_3842, T_3839) + node T_3845 = and(imem.resp.bits.data[0], UInt<32>("h07c")) + node T_3847 = eq(T_3845, UInt<32>("h024")) + node T_3849 = and(imem.resp.bits.data[0], UInt<32>("h040000060")) + node T_3851 = eq(T_3849, UInt<32>("h040")) + node T_3853 = and(imem.resp.bits.data[0], UInt<32>("h090000060")) + node T_3855 = eq(T_3853, UInt<32>("h010000040")) + node T_3857 = or(UInt<1>("h00"), T_3847) + node T_3858 = or(T_3857, T_3851) + node T_3859 = or(T_3858, T_3839) + node T_3860 = or(T_3859, T_3855) + node T_3862 = or(UInt<1>("h00"), T_3839) + node T_3864 = and(imem.resp.bits.data[0], UInt<32>("h03c")) + node T_3866 = eq(T_3864, UInt<32>("h04")) + node T_3868 = and(imem.resp.bits.data[0], UInt<32>("h010000060")) + node T_3870 = eq(T_3868, UInt<32>("h010000040")) + node T_3872 = or(UInt<1>("h00"), T_3866) + node T_3873 = or(T_3872, T_3831) + node T_3874 = or(T_3873, T_3839) + node T_3875 = or(T_3874, T_3870) + node T_3877 = and(imem.resp.bits.data[0], UInt<32>("h02000074")) + node T_3879 = eq(T_3877, UInt<32>("h02000030")) + node T_3881 = or(UInt<1>("h00"), T_3879) + node T_3883 = and(imem.resp.bits.data[0], UInt<32>("h064")) + node T_3885 = eq(T_3883, UInt<32>("h00")) + node T_3887 = and(imem.resp.bits.data[0], UInt<32>("h050")) + node T_3889 = eq(T_3887, UInt<32>("h010")) + node T_3891 = and(imem.resp.bits.data[0], UInt<32>("h02024")) + node T_3893 = eq(T_3891, UInt<32>("h024")) + node T_3895 = and(imem.resp.bits.data[0], UInt<32>("h028")) + node T_3897 = eq(T_3895, UInt<32>("h028")) + node T_3899 = and(imem.resp.bits.data[0], UInt<32>("h01030")) + node T_3901 = eq(T_3899, UInt<32>("h01030")) + node T_3903 = and(imem.resp.bits.data[0], UInt<32>("h02030")) + node T_3905 = eq(T_3903, UInt<32>("h02030")) + node T_3907 = and(imem.resp.bits.data[0], UInt<32>("h090000010")) + node T_3909 = eq(T_3907, UInt<32>("h080000010")) + node T_3911 = or(UInt<1>("h00"), T_3885) + node T_3912 = or(T_3911, T_3889) + node T_3913 = or(T_3912, T_3893) + node T_3914 = or(T_3913, T_3897) + node T_3915 = or(T_3914, T_3901) + node T_3916 = or(T_3915, T_3905) + node T_3917 = or(T_3916, T_3909) + node T_3919 = and(imem.resp.bits.data[0], UInt<32>("h01070")) + node T_3921 = eq(T_3919, UInt<32>("h01070")) + node T_3923 = or(UInt<1>("h00"), T_3921) + node T_3925 = and(imem.resp.bits.data[0], UInt<32>("h02070")) + node T_3927 = eq(T_3925, UInt<32>("h02070")) + node T_3929 = or(UInt<1>("h00"), T_3927) + node T_3931 = and(imem.resp.bits.data[0], UInt<32>("h03070")) + node T_3933 = eq(T_3931, UInt<32>("h070")) + node T_3935 = or(UInt<1>("h00"), T_3933) + node T_3936 = cat(T_3929, T_3923) + node T_3937 = cat(T_3935, T_3936) + node T_3939 = and(imem.resp.bits.data[0], UInt<32>("h03058")) + node T_3941 = eq(T_3939, UInt<32>("h01008")) + node T_3943 = or(UInt<1>("h00"), T_3941) + node T_3945 = and(imem.resp.bits.data[0], UInt<32>("h03058")) + node T_3947 = eq(T_3945, UInt<32>("h08")) + node T_3949 = or(UInt<1>("h00"), T_3947) + node T_3951 = and(imem.resp.bits.data[0], UInt<32>("h06048")) + node T_3953 = eq(T_3951, UInt<32>("h02008")) + node T_3955 = or(UInt<1>("h00"), T_3953) + id_ctrl.legal := T_3469 + id_ctrl.fp := T_3480 + id_ctrl.rocc := UInt<1>("h00") + id_ctrl.branch := T_3487 + id_ctrl.jal := T_3493 + id_ctrl.jalr := T_3499 + id_ctrl.rxs2 := T_3515 + id_ctrl.rxs1 := T_3541 + id_ctrl.sel_alu2 := T_3585 + id_ctrl.sel_alu1 := T_3611 + id_ctrl.sel_imm := T_3647 + id_ctrl.alu_dw := T_3658 + id_ctrl.alu_fn := T_3741 + id_ctrl.mem_1 := T_3757 + id_ctrl.mem_cmd := T_3807 + id_ctrl.mem_type := T_3827 + id_ctrl.rfs1 := T_3843 + id_ctrl.rfs2 := T_3860 + id_ctrl.rfs3 := T_3862 + id_ctrl.wfd := T_3875 + id_ctrl.div := T_3881 + id_ctrl.wxd := T_3917 + id_ctrl.csr := T_3937 + id_ctrl.fence_i := T_3943 + id_ctrl.fence := T_3949 + id_ctrl.amo := T_3955 + node id_raddr3 = bits(imem.resp.bits.data[0], 31, 27) + node id_raddr2 = bits(imem.resp.bits.data[0], 24, 20) + node id_raddr1 = bits(imem.resp.bits.data[0], 19, 15) + node id_waddr = bits(imem.resp.bits.data[0], 11, 7) + wire id_load_use : UInt<1> + id_load_use := UInt<1>("h00") + reg id_reg_fence : UInt<1>, clock, reset + onreset id_reg_fence := UInt<1>("h00") + cmem T_3967 : UInt<64>[31], clock + wire T_3969 : UInt<?> + T_3969 := UInt<1>("h00") + node T_3971 = not(id_raddr1) + infer accessor T_3972 = T_3967[T_3971] + T_3969 := T_3972 + wire T_3974 : UInt<?> + T_3974 := UInt<1>("h00") + node T_3976 = not(id_raddr2) + infer accessor T_3977 = T_3967[T_3976] + T_3974 := T_3977 + wire ctrl_killd : UInt<1> + ctrl_killd := UInt<1>("h00") + inst csr of CSRFile + csr.rocc.pptw.req.bits.fetch := UInt<1>("h00") + csr.rocc.pptw.req.bits.store := UInt<1>("h00") + csr.rocc.pptw.req.bits.prv := UInt<1>("h00") + csr.rocc.pptw.req.bits.addr := UInt<1>("h00") + csr.rocc.pptw.req.valid := UInt<1>("h00") + csr.rocc.dptw.req.bits.fetch := UInt<1>("h00") + csr.rocc.dptw.req.bits.store := UInt<1>("h00") + csr.rocc.dptw.req.bits.prv := UInt<1>("h00") + csr.rocc.dptw.req.bits.addr := UInt<1>("h00") + csr.rocc.dptw.req.valid := UInt<1>("h00") + csr.rocc.iptw.req.bits.fetch := UInt<1>("h00") + csr.rocc.iptw.req.bits.store := UInt<1>("h00") + csr.rocc.iptw.req.bits.prv := UInt<1>("h00") + csr.rocc.iptw.req.bits.addr := UInt<1>("h00") + csr.rocc.iptw.req.valid := UInt<1>("h00") + csr.rocc.dmem.grant.ready := UInt<1>("h00") + csr.rocc.dmem.acquire.bits.union := UInt<1>("h00") + csr.rocc.dmem.acquire.bits.a_type := UInt<1>("h00") + csr.rocc.dmem.acquire.bits.is_builtin_type := UInt<1>("h00") + csr.rocc.dmem.acquire.bits.data := UInt<1>("h00") + csr.rocc.dmem.acquire.bits.addr_beat := UInt<1>("h00") + csr.rocc.dmem.acquire.bits.client_xact_id := UInt<1>("h00") + csr.rocc.dmem.acquire.bits.addr_block := UInt<1>("h00") + csr.rocc.dmem.acquire.valid := UInt<1>("h00") + csr.rocc.imem.grant.ready := UInt<1>("h00") + csr.rocc.imem.acquire.bits.union := UInt<1>("h00") + csr.rocc.imem.acquire.bits.a_type := UInt<1>("h00") + csr.rocc.imem.acquire.bits.is_builtin_type := UInt<1>("h00") + csr.rocc.imem.acquire.bits.data := UInt<1>("h00") + csr.rocc.imem.acquire.bits.addr_beat := UInt<1>("h00") + csr.rocc.imem.acquire.bits.client_xact_id := UInt<1>("h00") + csr.rocc.imem.acquire.bits.addr_block := UInt<1>("h00") + csr.rocc.imem.acquire.valid := UInt<1>("h00") + csr.rocc.interrupt := UInt<1>("h00") + csr.rocc.busy := UInt<1>("h00") + csr.rocc.mem_1.invalidate_lr := UInt<1>("h00") + csr.rocc.mem_1.req.bits.data := UInt<1>("h00") + csr.rocc.mem_1.req.bits.phys := UInt<1>("h00") + csr.rocc.mem_1.req.bits.kill := UInt<1>("h00") + csr.rocc.mem_1.req.bits.typ := UInt<1>("h00") + csr.rocc.mem_1.req.bits.cmd := UInt<1>("h00") + csr.rocc.mem_1.req.bits.tag := UInt<1>("h00") + csr.rocc.mem_1.req.bits.addr := UInt<1>("h00") + csr.rocc.mem_1.req.valid := UInt<1>("h00") + csr.rocc.resp.bits.data := UInt<1>("h00") + csr.rocc.resp.bits.rd := UInt<1>("h00") + csr.rocc.resp.valid := UInt<1>("h00") + csr.rocc.cmd.ready := UInt<1>("h00") + csr.fcsr_flags.bits := UInt<1>("h00") + csr.fcsr_flags.valid := UInt<1>("h00") + csr.pc := UInt<1>("h00") + csr.cause := UInt<1>("h00") + csr.uarch_counters[0] := UInt<1>("h00") + csr.uarch_counters[1] := UInt<1>("h00") + csr.uarch_counters[2] := UInt<1>("h00") + csr.uarch_counters[3] := UInt<1>("h00") + csr.uarch_counters[4] := UInt<1>("h00") + csr.uarch_counters[5] := UInt<1>("h00") + csr.uarch_counters[6] := UInt<1>("h00") + csr.uarch_counters[7] := UInt<1>("h00") + csr.uarch_counters[8] := UInt<1>("h00") + csr.uarch_counters[9] := UInt<1>("h00") + csr.uarch_counters[10] := UInt<1>("h00") + csr.uarch_counters[11] := UInt<1>("h00") + csr.uarch_counters[12] := UInt<1>("h00") + csr.uarch_counters[13] := UInt<1>("h00") + csr.uarch_counters[14] := UInt<1>("h00") + csr.uarch_counters[15] := UInt<1>("h00") + csr.retire := UInt<1>("h00") + csr.exception := UInt<1>("h00") + csr.rw.wdata := UInt<1>("h00") + csr.rw.cmd := UInt<1>("h00") + csr.rw.addr := UInt<1>("h00") + csr.host.ipi_rep.bits := UInt<1>("h00") + csr.host.ipi_rep.valid := UInt<1>("h00") + csr.host.ipi_req.ready := UInt<1>("h00") + csr.host.pcr_rep.ready := UInt<1>("h00") + csr.host.pcr_req.bits.data := UInt<1>("h00") + csr.host.pcr_req.bits.addr := UInt<1>("h00") + csr.host.pcr_req.bits.rw := UInt<1>("h00") + csr.host.pcr_req.valid := UInt<1>("h00") + csr.host.id := UInt<1>("h00") + csr.host.reset := UInt<1>("h00") + csr.reset := UInt<1>("h00") + csr.clock := clock + csr.reset := reset + node id_csr_en = neq(id_ctrl.csr, UInt<3>("h00")) + node id_system_insn = eq(id_ctrl.csr, UInt<3>("h04")) + node T_4067 = eq(id_ctrl.csr, UInt<3>("h02")) + node T_4068 = eq(id_ctrl.csr, UInt<3>("h03")) + node T_4069 = or(T_4067, T_4068) + node T_4071 = eq(id_raddr1, UInt<1>("h00")) + node id_csr_ren = and(T_4069, T_4071) + node id_csr = mux(id_csr_ren, UInt<3>("h05"), id_ctrl.csr) + node id_csr_addr = bits(imem.resp.bits.data[0], 31, 20) + node T_4076 = eq(id_csr_ren, UInt<1>("h00")) + node T_4077 = and(id_csr_en, T_4076) + node T_4135 = and(id_csr_addr, UInt<12>("h08c4")) + node T_4137 = eq(T_4135, UInt<12>("h040")) + node T_4139 = or(UInt<1>("h00"), T_4137) + node T_4140 = bit(T_4139, 0) + node T_4142 = eq(T_4140, UInt<1>("h00")) + node T_4143 = and(T_4077, T_4142) + node id_csr_flush = or(id_system_insn, T_4143) + node T_4146 = eq(id_ctrl.legal, UInt<1>("h00")) + node T_4148 = neq(csr.status.fs, UInt<1>("h00")) + node T_4150 = eq(T_4148, UInt<1>("h00")) + node T_4151 = and(id_ctrl.fp, T_4150) + node T_4152 = or(T_4146, T_4151) + node T_4154 = neq(csr.status.xs, UInt<1>("h00")) + node T_4156 = eq(T_4154, UInt<1>("h00")) + node T_4157 = and(id_ctrl.rocc, T_4156) + node id_illegal_insn = or(T_4152, T_4157) + node id_amo_aq = bit(imem.resp.bits.data[0], 26) + node id_amo_rl = bit(imem.resp.bits.data[0], 25) + node T_4161 = and(id_ctrl.amo, id_amo_rl) + node id_fence_next = or(id_ctrl.fence, T_4161) + node T_4164 = eq(dmem.ordered, UInt<1>("h00")) + node id_mem_busy = or(T_4164, dmem.req.valid) + node T_4167 = and(ex_reg_valid, ex_ctrl.rocc) + node T_4168 = or(rocc.busy, T_4167) + node T_4169 = and(mem_reg_valid, mem_ctrl.rocc) + node T_4170 = or(T_4168, T_4169) + node T_4171 = and(wb_reg_valid, wb_ctrl.rocc) + node T_4172 = or(T_4170, T_4171) + node id_rocc_busy = and(UInt<1>("h00"), T_4172) + node T_4174 = and(id_reg_fence, id_mem_busy) + node T_4175 = or(id_fence_next, T_4174) + id_reg_fence := T_4175 + node T_4176 = and(id_rocc_busy, id_ctrl.fence) + node T_4177 = and(id_ctrl.amo, id_amo_aq) + node T_4178 = or(T_4177, id_ctrl.fence_i) + node T_4179 = or(id_ctrl.mem_1, id_ctrl.rocc) + node T_4180 = and(id_reg_fence, T_4179) + node T_4181 = or(T_4178, T_4180) + node T_4182 = or(T_4181, id_csr_en) + node T_4183 = and(id_mem_busy, T_4182) + node id_do_fence = or(T_4176, T_4183) + node T_4187 = or(csr.interrupt, imem.resp.bits.xcpt_if) + node id_xcpt = or(T_4187, id_illegal_insn) + node T_4189 = mux(imem.resp.bits.xcpt_if, UInt<1>("h01"), UInt<2>("h02")) + node id_cause = mux(csr.interrupt, csr.interrupt_cause, T_4189) + node ex_waddr = bits(ex_reg_inst, 11, 7) + node mem_waddr = bits(mem_reg_inst, 11, 7) + node wb_waddr = bits(wb_reg_inst, 11, 7) + node T_4197 = and(ex_reg_valid, ex_ctrl.wxd) + node T_4198 = and(mem_reg_valid, mem_ctrl.wxd) + node T_4200 = eq(mem_ctrl.mem_1, UInt<1>("h00")) + node T_4201 = and(T_4198, T_4200) + node T_4202 = and(mem_reg_valid, mem_ctrl.wxd) + node T_4203 = eq(UInt<1>("h00"), id_raddr1) + node T_4204 = and(UInt<1>("h01"), T_4203) + node T_4205 = eq(ex_waddr, id_raddr1) + node T_4206 = and(T_4197, T_4205) + node T_4207 = eq(mem_waddr, id_raddr1) + node T_4208 = and(T_4201, T_4207) + node T_4209 = eq(mem_waddr, id_raddr1) + node T_4210 = and(T_4202, T_4209) + node T_4211 = eq(UInt<1>("h00"), id_raddr2) + node T_4212 = and(UInt<1>("h01"), T_4211) + node T_4213 = eq(ex_waddr, id_raddr2) + node T_4214 = and(T_4197, T_4213) + node T_4215 = eq(mem_waddr, id_raddr2) + node T_4216 = and(T_4201, T_4215) + node T_4217 = eq(mem_waddr, id_raddr2) + node T_4218 = and(T_4202, T_4217) + wire bypass_mux : UInt<?>[4] + bypass_mux[0] := UInt<1>("h00") + bypass_mux[1] := mem_reg_wdata + bypass_mux[2] := wb_reg_wdata + bypass_mux[3] := dmem.resp.bits.data + reg ex_reg_rs_bypass : UInt<1>[2], clock, reset + reg ex_reg_rs_lsb : UInt<?>[2], clock, reset + reg ex_reg_rs_msb : UInt<?>[2], clock, reset + infer accessor T_4262 = bypass_mux[ex_reg_rs_lsb[0]] + node T_4263 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) + node T_4264 = mux(ex_reg_rs_bypass[0], T_4262, T_4263) + infer accessor T_4265 = bypass_mux[ex_reg_rs_lsb[1]] + node T_4266 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) + node T_4267 = mux(ex_reg_rs_bypass[1], T_4265, T_4266) + node T_4268 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) + node T_4270 = bit(ex_reg_inst, 31) + node T_4271 = asSInt(T_4270) + node T_4272 = mux(T_4268, asSInt(UInt<1>("h00")), T_4271) + node T_4273 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) + node T_4274 = bits(ex_reg_inst, 30, 20) + node T_4275 = asSInt(T_4274) + node T_4276 = mux(T_4273, T_4275, T_4272) + node T_4277 = neq(ex_ctrl.sel_imm, UInt<3>("h02")) + node T_4278 = neq(ex_ctrl.sel_imm, UInt<3>("h03")) + node T_4279 = and(T_4277, T_4278) + node T_4280 = bits(ex_reg_inst, 19, 12) + node T_4281 = asSInt(T_4280) + node T_4282 = mux(T_4279, T_4272, T_4281) + node T_4283 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) + node T_4284 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) + node T_4285 = or(T_4283, T_4284) + node T_4287 = eq(ex_ctrl.sel_imm, UInt<3>("h03")) + node T_4288 = bit(ex_reg_inst, 20) + node T_4289 = asSInt(T_4288) + node T_4290 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) + node T_4291 = bit(ex_reg_inst, 7) + node T_4292 = asSInt(T_4291) + node T_4293 = mux(T_4290, T_4292, T_4272) + node T_4294 = mux(T_4287, T_4289, T_4293) + node T_4295 = mux(T_4285, asSInt(UInt<1>("h00")), T_4294) + node T_4296 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) + node T_4297 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) + node T_4298 = or(T_4296, T_4297) + node T_4300 = bits(ex_reg_inst, 30, 25) + node T_4301 = mux(T_4298, UInt<1>("h00"), T_4300) + node T_4302 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) + node T_4304 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) + node T_4305 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) + node T_4306 = or(T_4304, T_4305) + node T_4307 = bits(ex_reg_inst, 11, 8) + node T_4308 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) + node T_4309 = bits(ex_reg_inst, 19, 16) + node T_4310 = bits(ex_reg_inst, 24, 21) + node T_4311 = mux(T_4308, T_4309, T_4310) + node T_4312 = mux(T_4306, T_4307, T_4311) + node T_4313 = mux(T_4302, UInt<1>("h00"), T_4312) + node T_4314 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) + node T_4315 = bit(ex_reg_inst, 7) + node T_4316 = eq(ex_ctrl.sel_imm, UInt<3>("h04")) + node T_4317 = bit(ex_reg_inst, 20) + node T_4318 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) + node T_4319 = bit(ex_reg_inst, 15) + node T_4321 = shl(T_4319, 0) + node T_4322 = mux(T_4318, T_4321, UInt<1>("h00")) + node T_4323 = shl(T_4317, 0) + node T_4324 = mux(T_4316, T_4323, T_4322) + node T_4325 = shl(T_4315, 0) + node T_4326 = mux(T_4314, T_4325, T_4324) + node T_4327 = asUInt(T_4272) + node T_4328 = asUInt(T_4276) + node T_4329 = asUInt(T_4282) + node T_4330 = cat(T_4328, T_4329) + node T_4331 = cat(T_4327, T_4330) + node T_4332 = asUInt(T_4295) + node T_4333 = cat(T_4332, T_4301) + node T_4334 = cat(T_4313, T_4326) + node T_4335 = cat(T_4333, T_4334) + node T_4336 = cat(T_4331, T_4335) + node ex_imm = asSInt(T_4336) + node T_4339 = asSInt(T_4264) + node T_4340 = asSInt(ex_reg_pc) + node T_4341 = eq(UInt<2>("h02"), ex_ctrl.sel_alu1) + node T_4342 = mux(T_4341, T_4340, asSInt(UInt<1>("h00"))) + node T_4343 = eq(UInt<2>("h01"), ex_ctrl.sel_alu1) + node ex_op1 = mux(T_4343, T_4339, T_4342) + node T_4346 = asSInt(T_4267) + node T_4348 = eq(UInt<2>("h01"), ex_ctrl.sel_alu2) + node T_4349 = mux(T_4348, asSInt(UInt<4>("h04")), asSInt(UInt<1>("h00"))) + node T_4350 = eq(UInt<2>("h03"), ex_ctrl.sel_alu2) + node T_4351 = mux(T_4350, ex_imm, T_4349) + node T_4352 = eq(UInt<2>("h02"), ex_ctrl.sel_alu2) + node ex_op2 = mux(T_4352, T_4346, T_4351) + inst alu of ALU + alu.in1 := UInt<1>("h00") + alu.in2 := UInt<1>("h00") + alu.fn := UInt<1>("h00") + alu.dw := UInt<1>("h00") + alu.reset := UInt<1>("h00") + alu.clock := clock + alu.reset := reset + alu.dw := ex_ctrl.alu_dw + alu.fn := ex_ctrl.alu_fn + node T_4359 = asUInt(ex_op2) + alu.in2 := T_4359 + node T_4360 = asUInt(ex_op1) + alu.in1 := T_4360 + inst div of MulDiv + div.resp.ready := UInt<1>("h00") + div.kill := UInt<1>("h00") + div.req.bits.tag := UInt<1>("h00") + div.req.bits.in2 := UInt<1>("h00") + div.req.bits.in1 := UInt<1>("h00") + div.req.bits.dw := UInt<1>("h00") + div.req.bits.fn := UInt<1>("h00") + div.req.valid := UInt<1>("h00") + div.reset := UInt<1>("h00") + div.clock := clock + div.reset := reset + node T_4370 = and(ex_reg_valid, ex_ctrl.div) + div.req.valid := T_4370 + div.req.bits.dw := ex_ctrl.alu_dw + div.req.bits.fn := ex_ctrl.alu_fn + div.req.bits.in1 := T_4264 + div.req.bits.in2 := T_4267 + div.req.bits.tag := ex_waddr + node T_4372 = eq(ctrl_killd, UInt<1>("h00")) + ex_reg_valid := T_4372 + node T_4374 = eq(ctrl_killd, UInt<1>("h00")) + node T_4375 = and(T_4374, id_xcpt) + ex_reg_xcpt := T_4375 + node T_4377 = eq(take_pc_mem_wb, UInt<1>("h00")) + node T_4378 = and(csr.interrupt, T_4377) + node T_4379 = and(T_4378, imem.resp.valid) + ex_reg_xcpt_interrupt := T_4379 + when id_xcpt : + ex_reg_cause := id_cause + skip + node T_4381 = eq(ctrl_killd, UInt<1>("h00")) + when T_4381 : + ex_ctrl <> id_ctrl + ex_ctrl.csr := id_csr + ex_reg_btb_hit := imem.btb_resp.valid + when imem.btb_resp.valid : + ex_reg_btb_resp <> imem.btb_resp.bits + skip + node T_4382 = or(id_ctrl.fence_i, id_csr_flush) + ex_reg_flush_pipe := T_4382 + ex_reg_load_use := id_load_use + node T_4383 = or(T_4204, T_4206) + node T_4384 = or(T_4383, T_4208) + node T_4385 = or(T_4384, T_4210) + node T_4390 = mux(T_4208, UInt<2>("h02"), UInt<2>("h03")) + node T_4391 = mux(T_4206, UInt<1>("h01"), T_4390) + node T_4392 = mux(T_4204, UInt<1>("h00"), T_4391) + ex_reg_rs_bypass[0] := T_4385 + ex_reg_rs_lsb[0] := T_4392 + node T_4394 = eq(T_4385, UInt<1>("h00")) + node T_4395 = and(id_ctrl.rxs1, T_4394) + when T_4395 : + node T_4396 = bits(T_3969, 1, 0) + ex_reg_rs_lsb[0] := T_4396 + node T_4397 = shr(T_3969, 2) + ex_reg_rs_msb[0] := T_4397 + skip + node T_4398 = or(T_4212, T_4214) + node T_4399 = or(T_4398, T_4216) + node T_4400 = or(T_4399, T_4218) + node T_4405 = mux(T_4216, UInt<2>("h02"), UInt<2>("h03")) + node T_4406 = mux(T_4214, UInt<1>("h01"), T_4405) + node T_4407 = mux(T_4212, UInt<1>("h00"), T_4406) + ex_reg_rs_bypass[1] := T_4400 + ex_reg_rs_lsb[1] := T_4407 + node T_4409 = eq(T_4400, UInt<1>("h00")) + node T_4410 = and(id_ctrl.rxs2, T_4409) + when T_4410 : + node T_4411 = bits(T_3974, 1, 0) + ex_reg_rs_lsb[1] := T_4411 + node T_4412 = shr(T_3974, 2) + ex_reg_rs_msb[1] := T_4412 + skip + skip + node T_4414 = eq(ctrl_killd, UInt<1>("h00")) + node T_4415 = or(T_4414, csr.interrupt) + when T_4415 : + ex_reg_inst := imem.resp.bits.data[0] + ex_reg_pc := imem.resp.bits.pc + skip + node T_4417 = eq(dmem.resp.valid, UInt<1>("h00")) + node wb_dcache_miss = and(wb_ctrl.mem_1, T_4417) + node T_4420 = eq(dmem.req.ready, UInt<1>("h00")) + node T_4421 = and(ex_ctrl.mem_1, T_4420) + node T_4423 = eq(div.req.ready, UInt<1>("h00")) + node T_4424 = and(ex_ctrl.div, T_4423) + node replay_ex_structural = or(T_4421, T_4424) + node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) + node T_4427 = or(replay_ex_structural, replay_ex_load_use) + node replay_ex = and(ex_reg_valid, T_4427) + node T_4429 = or(take_pc_mem_wb, replay_ex) + node T_4431 = eq(ex_reg_valid, UInt<1>("h00")) + node ctrl_killx = or(T_4429, T_4431) + node T_4433 = eq(ex_ctrl.mem_cmd, UInt<5>("h07")) + wire T_4435 : UInt<3>[4] + T_4435[0] := UInt<3>("h00") + T_4435[1] := UInt<3>("h04") + T_4435[2] := UInt<3>("h01") + T_4435[3] := UInt<3>("h05") + node T_4441 = eq(T_4435[0], ex_ctrl.mem_type) + node T_4442 = eq(T_4435[1], ex_ctrl.mem_type) + node T_4443 = eq(T_4435[2], ex_ctrl.mem_type) + node T_4444 = eq(T_4435[3], ex_ctrl.mem_type) + node T_4446 = or(UInt<1>("h00"), T_4441) + node T_4447 = or(T_4446, T_4442) + node T_4448 = or(T_4447, T_4443) + node T_4449 = or(T_4448, T_4444) + node ex_slow_bypass = or(T_4433, T_4449) + node T_4451 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) + node T_4452 = and(ex_ctrl.fp, fpu.illegal_rm) + node ex_xcpt = or(T_4451, T_4452) + node ex_cause = mux(T_4451, ex_reg_cause, UInt<2>("h02")) + node mem_br_taken = bit(mem_reg_wdata, 0) + node T_4457 = asSInt(mem_reg_pc) + node T_4458 = and(mem_ctrl.branch, mem_br_taken) + node T_4459 = eq(UInt<3>("h01"), UInt<3>("h05")) + node T_4461 = bit(mem_reg_inst, 31) + node T_4462 = asSInt(T_4461) + node T_4463 = mux(T_4459, asSInt(UInt<1>("h00")), T_4462) + node T_4464 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_4465 = bits(mem_reg_inst, 30, 20) + node T_4466 = asSInt(T_4465) + node T_4467 = mux(T_4464, T_4466, T_4463) + node T_4468 = neq(UInt<3>("h01"), UInt<3>("h02")) + node T_4469 = neq(UInt<3>("h01"), UInt<3>("h03")) + node T_4470 = and(T_4468, T_4469) + node T_4471 = bits(mem_reg_inst, 19, 12) + node T_4472 = asSInt(T_4471) + node T_4473 = mux(T_4470, T_4463, T_4472) + node T_4474 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_4475 = eq(UInt<3>("h01"), UInt<3>("h05")) + node T_4476 = or(T_4474, T_4475) + node T_4478 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_4479 = bit(mem_reg_inst, 20) + node T_4480 = asSInt(T_4479) + node T_4481 = eq(UInt<3>("h01"), UInt<3>("h01")) + node T_4482 = bit(mem_reg_inst, 7) + node T_4483 = asSInt(T_4482) + node T_4484 = mux(T_4481, T_4483, T_4463) + node T_4485 = mux(T_4478, T_4480, T_4484) + node T_4486 = mux(T_4476, asSInt(UInt<1>("h00")), T_4485) + node T_4487 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_4488 = eq(UInt<3>("h01"), UInt<3>("h05")) + node T_4489 = or(T_4487, T_4488) + node T_4491 = bits(mem_reg_inst, 30, 25) + node T_4492 = mux(T_4489, UInt<1>("h00"), T_4491) + node T_4493 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_4495 = eq(UInt<3>("h01"), UInt<3>("h00")) + node T_4496 = eq(UInt<3>("h01"), UInt<3>("h01")) + node T_4497 = or(T_4495, T_4496) + node T_4498 = bits(mem_reg_inst, 11, 8) + node T_4499 = eq(UInt<3>("h01"), UInt<3>("h05")) + node T_4500 = bits(mem_reg_inst, 19, 16) + node T_4501 = bits(mem_reg_inst, 24, 21) + node T_4502 = mux(T_4499, T_4500, T_4501) + node T_4503 = mux(T_4497, T_4498, T_4502) + node T_4504 = mux(T_4493, UInt<1>("h00"), T_4503) + node T_4505 = eq(UInt<3>("h01"), UInt<3>("h00")) + node T_4506 = bit(mem_reg_inst, 7) + node T_4507 = eq(UInt<3>("h01"), UInt<3>("h04")) + node T_4508 = bit(mem_reg_inst, 20) + node T_4509 = eq(UInt<3>("h01"), UInt<3>("h05")) + node T_4510 = bit(mem_reg_inst, 15) + node T_4512 = shl(T_4510, 0) + node T_4513 = mux(T_4509, T_4512, UInt<1>("h00")) + node T_4514 = shl(T_4508, 0) + node T_4515 = mux(T_4507, T_4514, T_4513) + node T_4516 = shl(T_4506, 0) + node T_4517 = mux(T_4505, T_4516, T_4515) + node T_4518 = asUInt(T_4463) + node T_4519 = asUInt(T_4467) + node T_4520 = asUInt(T_4473) + node T_4521 = cat(T_4519, T_4520) + node T_4522 = cat(T_4518, T_4521) + node T_4523 = asUInt(T_4486) + node T_4524 = cat(T_4523, T_4492) + node T_4525 = cat(T_4504, T_4517) + node T_4526 = cat(T_4524, T_4525) + node T_4527 = cat(T_4522, T_4526) + node T_4528 = asSInt(T_4527) + node T_4529 = eq(UInt<3>("h03"), UInt<3>("h05")) + node T_4531 = bit(mem_reg_inst, 31) + node T_4532 = asSInt(T_4531) + node T_4533 = mux(T_4529, asSInt(UInt<1>("h00")), T_4532) + node T_4534 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_4535 = bits(mem_reg_inst, 30, 20) + node T_4536 = asSInt(T_4535) + node T_4537 = mux(T_4534, T_4536, T_4533) + node T_4538 = neq(UInt<3>("h03"), UInt<3>("h02")) + node T_4539 = neq(UInt<3>("h03"), UInt<3>("h03")) + node T_4540 = and(T_4538, T_4539) + node T_4541 = bits(mem_reg_inst, 19, 12) + node T_4542 = asSInt(T_4541) + node T_4543 = mux(T_4540, T_4533, T_4542) + node T_4544 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_4545 = eq(UInt<3>("h03"), UInt<3>("h05")) + node T_4546 = or(T_4544, T_4545) + node T_4548 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_4549 = bit(mem_reg_inst, 20) + node T_4550 = asSInt(T_4549) + node T_4551 = eq(UInt<3>("h03"), UInt<3>("h01")) + node T_4552 = bit(mem_reg_inst, 7) + node T_4553 = asSInt(T_4552) + node T_4554 = mux(T_4551, T_4553, T_4533) + node T_4555 = mux(T_4548, T_4550, T_4554) + node T_4556 = mux(T_4546, asSInt(UInt<1>("h00")), T_4555) + node T_4557 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_4558 = eq(UInt<3>("h03"), UInt<3>("h05")) + node T_4559 = or(T_4557, T_4558) + node T_4561 = bits(mem_reg_inst, 30, 25) + node T_4562 = mux(T_4559, UInt<1>("h00"), T_4561) + node T_4563 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_4565 = eq(UInt<3>("h03"), UInt<3>("h00")) + node T_4566 = eq(UInt<3>("h03"), UInt<3>("h01")) + node T_4567 = or(T_4565, T_4566) + node T_4568 = bits(mem_reg_inst, 11, 8) + node T_4569 = eq(UInt<3>("h03"), UInt<3>("h05")) + node T_4570 = bits(mem_reg_inst, 19, 16) + node T_4571 = bits(mem_reg_inst, 24, 21) + node T_4572 = mux(T_4569, T_4570, T_4571) + node T_4573 = mux(T_4567, T_4568, T_4572) + node T_4574 = mux(T_4563, UInt<1>("h00"), T_4573) + node T_4575 = eq(UInt<3>("h03"), UInt<3>("h00")) + node T_4576 = bit(mem_reg_inst, 7) + node T_4577 = eq(UInt<3>("h03"), UInt<3>("h04")) + node T_4578 = bit(mem_reg_inst, 20) + node T_4579 = eq(UInt<3>("h03"), UInt<3>("h05")) + node T_4580 = bit(mem_reg_inst, 15) + node T_4582 = shl(T_4580, 0) + node T_4583 = mux(T_4579, T_4582, UInt<1>("h00")) + node T_4584 = shl(T_4578, 0) + node T_4585 = mux(T_4577, T_4584, T_4583) + node T_4586 = shl(T_4576, 0) + node T_4587 = mux(T_4575, T_4586, T_4585) + node T_4588 = asUInt(T_4533) + node T_4589 = asUInt(T_4537) + node T_4590 = asUInt(T_4543) + node T_4591 = cat(T_4589, T_4590) + node T_4592 = cat(T_4588, T_4591) + node T_4593 = asUInt(T_4556) + node T_4594 = cat(T_4593, T_4562) + node T_4595 = cat(T_4574, T_4587) + node T_4596 = cat(T_4594, T_4595) + node T_4597 = cat(T_4592, T_4596) + node T_4598 = asSInt(T_4597) + node T_4600 = mux(mem_ctrl.jal, T_4598, asSInt(UInt<4>("h04"))) + node T_4601 = mux(T_4458, T_4528, T_4600) + node mem_br_target = addw(T_4457, T_4601) + node T_4603 = asSInt(mem_reg_wdata) + node T_4604 = mux(mem_ctrl.jalr, mem_br_target, T_4603) + node mem_int_wdata = asUInt(T_4604) + node T_4606 = shr(mem_reg_wdata, 38) + node T_4607 = bits(mem_reg_wdata, 39, 38) + node T_4609 = eq(T_4606, UInt<1>("h00")) + node T_4611 = eq(T_4606, UInt<1>("h01")) + node T_4612 = or(T_4609, T_4611) + node T_4614 = neq(T_4607, UInt<1>("h00")) + node T_4615 = asSInt(T_4606) + node T_4617 = eq(T_4615, asSInt(UInt<1>("h01"))) + node T_4618 = asSInt(T_4606) + node T_4620 = eq(T_4618, asSInt(UInt<2>("h02"))) + node T_4621 = or(T_4617, T_4620) + node T_4622 = asSInt(T_4607) + node T_4624 = eq(T_4622, asSInt(UInt<1>("h01"))) + node T_4625 = bit(T_4607, 0) + node T_4626 = mux(T_4621, T_4624, T_4625) + node T_4627 = mux(T_4612, T_4614, T_4626) + node T_4628 = bits(mem_reg_wdata, 38, 0) + node T_4629 = cat(T_4627, T_4628) + node T_4630 = asSInt(T_4629) + node T_4631 = mux(mem_ctrl.jalr, T_4630, mem_br_target) + node T_4633 = and(T_4631, asSInt(UInt<2>("h02"))) + node mem_npc = asUInt(T_4633) + node T_4635 = neq(mem_npc, ex_reg_pc) + node T_4637 = eq(ex_reg_valid, UInt<1>("h00")) + node mem_wrong_npc = or(T_4635, T_4637) + node mem_npc_misaligned = bit(mem_npc, 1) + node T_4640 = and(mem_wrong_npc, mem_reg_valid) + node T_4641 = or(mem_ctrl.branch, mem_ctrl.jalr) + node T_4642 = or(T_4641, mem_ctrl.jal) + node mem_misprediction = and(T_4640, T_4642) + node T_4644 = or(mem_misprediction, mem_reg_flush_pipe) + node want_take_pc_mem = and(mem_reg_valid, T_4644) + node T_4647 = eq(mem_npc_misaligned, UInt<1>("h00")) + node T_4648 = and(want_take_pc_mem, T_4647) + take_pc_mem := T_4648 + node T_4650 = eq(ctrl_killx, UInt<1>("h00")) + mem_reg_valid := T_4650 + node T_4652 = eq(take_pc_mem_wb, UInt<1>("h00")) + node T_4653 = and(T_4652, replay_ex) + mem_reg_replay := T_4653 + node T_4655 = eq(ctrl_killx, UInt<1>("h00")) + node T_4656 = and(T_4655, ex_xcpt) + mem_reg_xcpt := T_4656 + node T_4658 = eq(take_pc_mem_wb, UInt<1>("h00")) + node T_4659 = and(T_4658, ex_reg_xcpt_interrupt) + mem_reg_xcpt_interrupt := T_4659 + when ex_xcpt : + mem_reg_cause := ex_cause + skip + node T_4660 = or(ex_reg_valid, ex_reg_xcpt_interrupt) + when T_4660 : + mem_ctrl <> ex_ctrl + mem_reg_btb_hit := ex_reg_btb_hit + when ex_reg_btb_hit : + mem_reg_btb_resp <> ex_reg_btb_resp + skip + mem_reg_flush_pipe := ex_reg_flush_pipe + mem_reg_slow_bypass := ex_slow_bypass + mem_reg_inst := ex_reg_inst + mem_reg_pc := ex_reg_pc + mem_reg_wdata := alu.out + node T_4661 = or(ex_ctrl.mem_1, ex_ctrl.rocc) + node T_4662 = and(ex_ctrl.rxs2, T_4661) + when T_4662 : + mem_reg_rs2 := T_4267 + skip + skip + node T_4663 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) + node T_4664 = and(want_take_pc_mem, mem_npc_misaligned) + node T_4666 = and(mem_reg_valid, mem_ctrl.mem_1) + node T_4667 = and(T_4666, dmem.xcpt.ma.st) + node T_4669 = and(mem_reg_valid, mem_ctrl.mem_1) + node T_4670 = and(T_4669, dmem.xcpt.ma.ld) + node T_4672 = and(mem_reg_valid, mem_ctrl.mem_1) + node T_4673 = and(T_4672, dmem.xcpt.pf.st) + node T_4675 = and(mem_reg_valid, mem_ctrl.mem_1) + node T_4676 = and(T_4675, dmem.xcpt.pf.ld) + node T_4678 = or(T_4663, T_4664) + node T_4679 = or(T_4678, T_4667) + node T_4680 = or(T_4679, T_4670) + node T_4681 = or(T_4680, T_4673) + node mem_xcpt = or(T_4681, T_4676) + node T_4683 = mux(T_4673, UInt<3>("h07"), UInt<3>("h05")) + node T_4684 = mux(T_4670, UInt<3>("h04"), T_4683) + node T_4685 = mux(T_4667, UInt<3>("h06"), T_4684) + node T_4686 = mux(T_4664, UInt<1>("h00"), T_4685) + node mem_cause = mux(T_4663, mem_reg_cause, T_4686) + node T_4688 = and(mem_reg_valid, mem_ctrl.wxd) + node dcache_kill_mem = and(T_4688, dmem.replay_next.valid) + node T_4690 = and(mem_reg_valid, mem_ctrl.fp) + node fpu_kill_mem = and(T_4690, fpu.nack_mem) + node T_4692 = or(dcache_kill_mem, mem_reg_replay) + node replay_mem = or(T_4692, fpu_kill_mem) + node T_4694 = or(dcache_kill_mem, take_pc_wb) + node T_4695 = or(T_4694, mem_reg_xcpt) + node T_4697 = eq(mem_reg_valid, UInt<1>("h00")) + node killm_common = or(T_4695, T_4697) + node T_4699 = and(div.req.ready, div.req.valid) + reg T_4700 : UInt<1>, clock, reset + T_4700 := T_4699 + node T_4701 = and(killm_common, T_4700) + div.kill := T_4701 + node T_4702 = or(killm_common, mem_xcpt) + node ctrl_killm = or(T_4702, fpu_kill_mem) + node T_4705 = eq(ctrl_killm, UInt<1>("h00")) + wb_reg_valid := T_4705 + node T_4707 = eq(take_pc_wb, UInt<1>("h00")) + node T_4708 = and(replay_mem, T_4707) + wb_reg_replay := T_4708 + node T_4710 = eq(take_pc_wb, UInt<1>("h00")) + node T_4711 = and(mem_xcpt, T_4710) + wb_reg_xcpt := T_4711 + when mem_xcpt : + wb_reg_cause := mem_cause + skip + node T_4712 = or(mem_reg_valid, mem_reg_replay) + node T_4713 = or(T_4712, mem_reg_xcpt_interrupt) + when T_4713 : + wb_ctrl <> mem_ctrl + node T_4714 = and(mem_ctrl.fp, mem_ctrl.wxd) + node T_4715 = mux(T_4714, fpu.toint_data, mem_int_wdata) + wb_reg_wdata := T_4715 + when mem_ctrl.rocc : + wb_reg_rs2 := mem_reg_rs2 + skip + wb_reg_inst := mem_reg_inst + wb_reg_pc := mem_reg_pc + skip + node T_4716 = or(wb_ctrl.div, wb_dcache_miss) + node wb_set_sboard = or(T_4716, wb_ctrl.rocc) + node T_4718 = or(dmem.resp.bits.nack, wb_reg_replay) + node replay_wb_common = or(T_4718, csr.csr_replay) + node T_4720 = and(wb_reg_valid, wb_ctrl.rocc) + node T_4722 = eq(replay_wb_common, UInt<1>("h00")) + node wb_rocc_val = and(T_4720, T_4722) + node T_4724 = and(wb_reg_valid, wb_ctrl.rocc) + node T_4726 = eq(rocc.cmd.ready, UInt<1>("h00")) + node T_4727 = and(T_4724, T_4726) + node replay_wb = or(replay_wb_common, T_4727) + node wb_xcpt = or(wb_reg_xcpt, csr.csr_xcpt) + node T_4730 = or(replay_wb, wb_xcpt) + node T_4731 = or(T_4730, csr.eret) + take_pc_wb := T_4731 + when wb_rocc_val : + node T_4733 = eq(rocc.cmd.ready, UInt<1>("h00")) + wb_reg_rocc_pending := T_4733 + skip + when wb_reg_xcpt : + wb_reg_rocc_pending := UInt<1>("h00") + skip + node T_4735 = bit(dmem.resp.bits.tag, 0) + node T_4736 = bit(T_4735, 0) + node dmem_resp_xpu = eq(T_4736, UInt<1>("h00")) + node T_4739 = bit(dmem.resp.bits.tag, 0) + node dmem_resp_fpu = bit(T_4739, 0) + node dmem_resp_waddr = bits(dmem.resp.bits.tag, 5, 1) + node dmem_resp_valid = and(dmem.resp.valid, dmem.resp.bits.has_data) + node dmem_resp_replay = and(dmem.resp.bits.replay, dmem.resp.bits.has_data) + node T_4744 = and(wb_reg_valid, wb_ctrl.wxd) + node T_4746 = eq(T_4744, UInt<1>("h00")) + div.resp.ready := T_4746 + wire ll_wdata : UInt<?> + ll_wdata := div.resp.bits.data + wire ll_waddr : UInt<?> + ll_waddr := div.resp.bits.tag + node T_4749 = and(div.resp.ready, div.resp.valid) + wire ll_wen : UInt<1> + ll_wen := T_4749 + node T_4751 = and(dmem_resp_replay, dmem_resp_xpu) + when T_4751 : + div.resp.ready := UInt<1>("h00") + ll_waddr := dmem_resp_waddr + ll_wen := UInt<1>("h01") + skip + node T_4755 = eq(replay_wb, UInt<1>("h00")) + node T_4756 = and(wb_reg_valid, T_4755) + node T_4758 = eq(csr.csr_xcpt, UInt<1>("h00")) + node wb_valid = and(T_4756, T_4758) + node wb_wen = and(wb_valid, wb_ctrl.wxd) + node rf_wen = or(wb_wen, ll_wen) + node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) + node T_4763 = and(dmem_resp_valid, dmem_resp_xpu) + node T_4764 = neq(wb_ctrl.csr, UInt<3>("h00")) + node T_4765 = mux(T_4764, csr.rw.rdata, wb_reg_wdata) + node T_4766 = mux(ll_wen, ll_wdata, T_4765) + node rf_wdata = mux(T_4763, dmem.resp.bits.data_subword, T_4766) + when rf_wen : + node T_4769 = neq(rf_waddr, UInt<1>("h00")) + when T_4769 : + node T_4770 = not(rf_waddr) + infer accessor T_4771 = T_3967[T_4770] + T_4771 := rf_wdata + node T_4772 = eq(rf_waddr, id_raddr1) + when T_4772 : + T_3969 := rf_wdata + skip + node T_4773 = eq(rf_waddr, id_raddr2) + when T_4773 : + T_3974 := rf_wdata + skip + skip + skip + csr.exception := wb_reg_xcpt + csr.cause := wb_reg_cause + csr.retire := wb_valid + host <> csr.host + fpu.fcsr_rm := csr.fcsr_rm + csr.fcsr_flags <> fpu.fcsr_flags + csr.rocc <> rocc + csr.pc := wb_reg_pc + csr.uarch_counters[0] := UInt<1>("h00") + csr.uarch_counters[1] := UInt<1>("h00") + csr.uarch_counters[2] := UInt<1>("h00") + csr.uarch_counters[3] := UInt<1>("h00") + csr.uarch_counters[4] := UInt<1>("h00") + csr.uarch_counters[5] := UInt<1>("h00") + csr.uarch_counters[6] := UInt<1>("h00") + csr.uarch_counters[7] := UInt<1>("h00") + csr.uarch_counters[8] := UInt<1>("h00") + csr.uarch_counters[9] := UInt<1>("h00") + csr.uarch_counters[10] := UInt<1>("h00") + csr.uarch_counters[11] := UInt<1>("h00") + csr.uarch_counters[12] := UInt<1>("h00") + csr.uarch_counters[13] := UInt<1>("h00") + csr.uarch_counters[14] := UInt<1>("h00") + csr.uarch_counters[15] := UInt<1>("h00") + ptw.ptbr := csr.ptbr + ptw.invalidate := csr.fatc + ptw.status <> csr.status + node T_4790 = bits(wb_reg_inst, 31, 20) + csr.rw.addr := T_4790 + node T_4791 = mux(wb_reg_valid, wb_ctrl.csr, UInt<3>("h00")) + csr.rw.cmd := T_4791 + csr.rw.wdata := wb_reg_wdata + node T_4793 = neq(id_raddr1, UInt<1>("h00")) + node T_4794 = and(id_ctrl.rxs1, T_4793) + node T_4796 = neq(id_raddr2, UInt<1>("h00")) + node T_4797 = and(id_ctrl.rxs2, T_4796) + node T_4799 = neq(id_waddr, UInt<1>("h00")) + node T_4800 = and(id_ctrl.wxd, T_4799) + reg T_4802 : UInt<32>, clock, reset + onreset T_4802 := UInt<32>("h00") + node T_4805 = dshl(UInt<1>("h01"), ll_waddr) + node T_4807 = mux(ll_wen, T_4805, UInt<1>("h00")) + node T_4808 = not(T_4807) + node T_4809 = and(T_4802, T_4808) + node T_4810 = or(UInt<1>("h00"), ll_wen) + when T_4810 : + T_4802 := T_4809 + skip + node T_4811 = dshr(T_4809, id_raddr1) + node T_4812 = bit(T_4811, 0) + node T_4813 = and(T_4794, T_4812) + node T_4814 = dshr(T_4809, id_raddr2) + node T_4815 = bit(T_4814, 0) + node T_4816 = and(T_4797, T_4815) + node T_4817 = dshr(T_4809, id_waddr) + node T_4818 = bit(T_4817, 0) + node T_4819 = and(T_4800, T_4818) + node T_4820 = or(T_4813, T_4816) + node id_sboard_hazard = or(T_4820, T_4819) + node T_4822 = and(wb_set_sboard, wb_wen) + node T_4824 = dshl(UInt<1>("h01"), wb_waddr) + node T_4826 = mux(T_4822, T_4824, UInt<1>("h00")) + node T_4827 = or(T_4809, T_4826) + node T_4828 = or(T_4810, T_4822) + when T_4828 : + T_4802 := T_4827 + skip + node T_4829 = neq(ex_ctrl.csr, UInt<3>("h00")) + node T_4830 = or(T_4829, ex_ctrl.jalr) + node T_4831 = or(T_4830, ex_ctrl.mem_1) + node T_4832 = or(T_4831, ex_ctrl.div) + node T_4833 = or(T_4832, ex_ctrl.fp) + node ex_cannot_bypass = or(T_4833, ex_ctrl.rocc) + node T_4835 = eq(id_raddr1, ex_waddr) + node T_4836 = and(T_4794, T_4835) + node T_4837 = eq(id_raddr2, ex_waddr) + node T_4838 = and(T_4797, T_4837) + node T_4839 = eq(id_waddr, ex_waddr) + node T_4840 = and(T_4800, T_4839) + node T_4841 = or(T_4836, T_4838) + node T_4842 = or(T_4841, T_4840) + node data_hazard_ex = and(ex_ctrl.wxd, T_4842) + node T_4844 = eq(id_raddr1, ex_waddr) + node T_4845 = and(fpu.dec.ren1, T_4844) + node T_4846 = eq(id_raddr2, ex_waddr) + node T_4847 = and(fpu.dec.ren2, T_4846) + node T_4848 = eq(id_raddr3, ex_waddr) + node T_4849 = and(fpu.dec.ren3, T_4848) + node T_4850 = eq(id_waddr, ex_waddr) + node T_4851 = and(fpu.dec.wen, T_4850) + node T_4852 = or(T_4845, T_4847) + node T_4853 = or(T_4852, T_4849) + node T_4854 = or(T_4853, T_4851) + node fp_data_hazard_ex = and(ex_ctrl.wfd, T_4854) + node T_4856 = and(data_hazard_ex, ex_cannot_bypass) + node T_4857 = or(T_4856, fp_data_hazard_ex) + node id_ex_hazard = and(ex_reg_valid, T_4857) + node mem_mem_cmd_bh = and(UInt<1>("h01"), mem_reg_slow_bypass) + node T_4861 = neq(mem_ctrl.csr, UInt<3>("h00")) + node T_4862 = and(mem_ctrl.mem_1, mem_mem_cmd_bh) + node T_4863 = or(T_4861, T_4862) + node T_4864 = or(T_4863, mem_ctrl.div) + node T_4865 = or(T_4864, mem_ctrl.fp) + node mem_cannot_bypass = or(T_4865, mem_ctrl.rocc) + node T_4867 = eq(id_raddr1, mem_waddr) + node T_4868 = and(T_4794, T_4867) + node T_4869 = eq(id_raddr2, mem_waddr) + node T_4870 = and(T_4797, T_4869) + node T_4871 = eq(id_waddr, mem_waddr) + node T_4872 = and(T_4800, T_4871) + node T_4873 = or(T_4868, T_4870) + node T_4874 = or(T_4873, T_4872) + node data_hazard_mem = and(mem_ctrl.wxd, T_4874) + node T_4876 = eq(id_raddr1, mem_waddr) + node T_4877 = and(fpu.dec.ren1, T_4876) + node T_4878 = eq(id_raddr2, mem_waddr) + node T_4879 = and(fpu.dec.ren2, T_4878) + node T_4880 = eq(id_raddr3, mem_waddr) + node T_4881 = and(fpu.dec.ren3, T_4880) + node T_4882 = eq(id_waddr, mem_waddr) + node T_4883 = and(fpu.dec.wen, T_4882) + node T_4884 = or(T_4877, T_4879) + node T_4885 = or(T_4884, T_4881) + node T_4886 = or(T_4885, T_4883) + node fp_data_hazard_mem = and(mem_ctrl.wfd, T_4886) + node T_4888 = and(data_hazard_mem, mem_cannot_bypass) + node T_4889 = or(T_4888, fp_data_hazard_mem) + node id_mem_hazard = and(mem_reg_valid, T_4889) + node T_4891 = and(mem_reg_valid, data_hazard_mem) + node T_4892 = and(T_4891, mem_ctrl.mem_1) + id_load_use := T_4892 + node T_4893 = eq(id_raddr1, wb_waddr) + node T_4894 = and(T_4794, T_4893) + node T_4895 = eq(id_raddr2, wb_waddr) + node T_4896 = and(T_4797, T_4895) + node T_4897 = eq(id_waddr, wb_waddr) + node T_4898 = and(T_4800, T_4897) + node T_4899 = or(T_4894, T_4896) + node T_4900 = or(T_4899, T_4898) + node data_hazard_wb = and(wb_ctrl.wxd, T_4900) + node T_4902 = eq(id_raddr1, wb_waddr) + node T_4903 = and(fpu.dec.ren1, T_4902) + node T_4904 = eq(id_raddr2, wb_waddr) + node T_4905 = and(fpu.dec.ren2, T_4904) + node T_4906 = eq(id_raddr3, wb_waddr) + node T_4907 = and(fpu.dec.ren3, T_4906) + node T_4908 = eq(id_waddr, wb_waddr) + node T_4909 = and(fpu.dec.wen, T_4908) + node T_4910 = or(T_4903, T_4905) + node T_4911 = or(T_4910, T_4907) + node T_4912 = or(T_4911, T_4909) + node fp_data_hazard_wb = and(wb_ctrl.wfd, T_4912) + node T_4914 = and(data_hazard_wb, wb_set_sboard) + node T_4915 = or(T_4914, fp_data_hazard_wb) + node id_wb_hazard = and(wb_reg_valid, T_4915) + reg T_4918 : UInt<32>, clock, reset + onreset T_4918 := UInt<32>("h00") + node T_4920 = and(wb_dcache_miss, wb_ctrl.wfd) + node T_4921 = or(T_4920, fpu.sboard_set) + node T_4922 = and(T_4921, wb_valid) + node T_4924 = dshl(UInt<1>("h01"), wb_waddr) + node T_4926 = mux(T_4922, T_4924, UInt<1>("h00")) + node T_4927 = or(T_4918, T_4926) + node T_4928 = or(UInt<1>("h00"), T_4922) + when T_4928 : + T_4918 := T_4927 + skip + node T_4929 = and(dmem_resp_replay, dmem_resp_fpu) + node T_4931 = dshl(UInt<1>("h01"), dmem_resp_waddr) + node T_4933 = mux(T_4929, T_4931, UInt<1>("h00")) + node T_4934 = not(T_4933) + node T_4935 = and(T_4927, T_4934) + node T_4936 = or(T_4928, T_4929) + when T_4936 : + T_4918 := T_4935 + skip + node T_4938 = dshl(UInt<1>("h01"), fpu.sboard_clra) + node T_4940 = mux(fpu.sboard_clr, T_4938, UInt<1>("h00")) + node T_4941 = not(T_4940) + node T_4942 = and(T_4935, T_4941) + node T_4943 = or(T_4936, fpu.sboard_clr) + when T_4943 : + T_4918 := T_4942 + skip + node T_4945 = eq(fpu.fcsr_rdy, UInt<1>("h00")) + node T_4946 = and(id_csr_en, T_4945) + node T_4947 = dshr(T_4918, id_raddr1) + node T_4948 = bit(T_4947, 0) + node T_4949 = and(fpu.dec.ren1, T_4948) + node T_4950 = dshr(T_4918, id_raddr2) + node T_4951 = bit(T_4950, 0) + node T_4952 = and(fpu.dec.ren2, T_4951) + node T_4953 = dshr(T_4918, id_raddr3) + node T_4954 = bit(T_4953, 0) + node T_4955 = and(fpu.dec.ren3, T_4954) + node T_4956 = dshr(T_4918, id_waddr) + node T_4957 = bit(T_4956, 0) + node T_4958 = and(fpu.dec.wen, T_4957) + node T_4959 = or(T_4949, T_4952) + node T_4960 = or(T_4959, T_4955) + node T_4961 = or(T_4960, T_4958) + node id_stall_fpu = or(T_4946, T_4961) + node T_4963 = or(id_ex_hazard, id_mem_hazard) + node T_4964 = or(T_4963, id_wb_hazard) + node T_4965 = or(T_4964, id_sboard_hazard) + node T_4966 = and(id_ctrl.fp, id_stall_fpu) + node T_4967 = or(T_4965, T_4966) + node T_4969 = eq(dmem.req.ready, UInt<1>("h00")) + node T_4970 = and(id_ctrl.mem_1, T_4969) + node T_4971 = or(T_4967, T_4970) + node T_4973 = and(UInt<1>("h00"), wb_reg_rocc_pending) + node T_4974 = and(T_4973, id_ctrl.rocc) + node T_4976 = eq(rocc.cmd.ready, UInt<1>("h00")) + node T_4977 = and(T_4974, T_4976) + node T_4978 = or(T_4971, T_4977) + node T_4979 = or(T_4978, id_do_fence) + node ctrl_stalld = or(T_4979, csr.csr_stall) + node T_4982 = eq(imem.resp.valid, UInt<1>("h00")) + node T_4983 = or(T_4982, take_pc_mem_wb) + node T_4984 = or(T_4983, ctrl_stalld) + node T_4985 = or(T_4984, csr.interrupt) + ctrl_killd := T_4985 + imem.req.valid := take_pc_mem_wb + node T_4986 = or(wb_xcpt, csr.eret) + node T_4987 = mux(replay_wb, wb_reg_pc, mem_npc) + node T_4988 = mux(T_4986, csr.evec, T_4987) + imem.req.bits.pc := T_4988 + node T_4989 = and(wb_reg_valid, wb_ctrl.fence_i) + imem.invalidate := T_4989 + node T_4991 = eq(ctrl_stalld, UInt<1>("h00")) + node T_4992 = or(T_4991, csr.interrupt) + imem.resp.ready := T_4992 + node T_4994 = eq(mem_npc_misaligned, UInt<1>("h00")) + node T_4995 = and(mem_reg_valid, T_4994) + node T_4996 = and(T_4995, mem_wrong_npc) + node T_4997 = and(mem_ctrl.branch, mem_br_taken) + node T_4998 = or(T_4997, mem_ctrl.jalr) + node T_4999 = or(T_4998, mem_ctrl.jal) + node T_5000 = and(T_4996, T_4999) + node T_5002 = eq(take_pc_wb, UInt<1>("h00")) + node T_5003 = and(T_5000, T_5002) + imem.btb_update.valid := T_5003 + node T_5004 = or(mem_ctrl.jal, mem_ctrl.jalr) + imem.btb_update.bits.isJump := T_5004 + node T_5005 = bits(mem_reg_inst, 19, 15) + node T_5008 = and(T_5005, UInt<5>("h019")) + node T_5009 = eq(UInt<1>("h01"), T_5008) + node T_5010 = and(mem_ctrl.jalr, T_5009) + imem.btb_update.bits.isReturn := T_5010 + imem.btb_update.bits.pc := mem_reg_pc + imem.btb_update.bits.target := imem.req.bits.pc + imem.btb_update.bits.br_pc := mem_reg_pc + imem.btb_update.bits.prediction.valid := mem_reg_btb_hit + imem.btb_update.bits.prediction.bits <> mem_reg_btb_resp + node T_5011 = and(mem_reg_valid, mem_ctrl.branch) + node T_5013 = eq(take_pc_wb, UInt<1>("h00")) + node T_5014 = and(T_5011, T_5013) + imem.bht_update.valid := T_5014 + imem.bht_update.bits.pc := mem_reg_pc + imem.bht_update.bits.taken := mem_br_taken + imem.bht_update.bits.mispredict := mem_wrong_npc + imem.bht_update.bits.prediction <> imem.btb_update.bits.prediction + node T_5015 = and(mem_reg_valid, imem.btb_update.bits.isJump) + node T_5017 = eq(mem_npc_misaligned, UInt<1>("h00")) + node T_5018 = and(T_5015, T_5017) + node T_5020 = eq(take_pc_wb, UInt<1>("h00")) + node T_5021 = and(T_5018, T_5020) + imem.ras_update.valid := T_5021 + imem.ras_update.bits.returnAddr := mem_int_wdata + node T_5022 = bit(mem_waddr, 0) + node T_5023 = and(mem_ctrl.wxd, T_5022) + imem.ras_update.bits.isCall := T_5023 + imem.ras_update.bits.isReturn := imem.btb_update.bits.isReturn + imem.ras_update.bits.prediction <> imem.btb_update.bits.prediction + node T_5025 = eq(ctrl_killd, UInt<1>("h00")) + node T_5026 = and(T_5025, id_ctrl.fp) + fpu.valid := T_5026 + fpu.killx := ctrl_killx + fpu.killm := killm_common + fpu.inst_1 := imem.resp.bits.data[0] + fpu.fromint_data := T_4264 + node T_5027 = and(dmem_resp_valid, dmem_resp_fpu) + fpu.dmem_resp_val := T_5027 + fpu.dmem_resp_data := dmem.resp.bits.data + fpu.dmem_resp_type := dmem.resp.bits.typ + fpu.dmem_resp_tag := dmem_resp_waddr + node T_5028 = and(ex_reg_valid, ex_ctrl.mem_1) + dmem.req.valid := T_5028 + node T_5029 = or(killm_common, mem_xcpt) + dmem.req.bits.kill := T_5029 + dmem.req.bits.cmd := ex_ctrl.mem_cmd + dmem.req.bits.typ := ex_ctrl.mem_type + dmem.req.bits.phys := UInt<1>("h00") + node T_5031 = shr(T_4264, 38) + node T_5032 = bits(alu.adder_out, 39, 38) + node T_5034 = eq(T_5031, UInt<1>("h00")) + node T_5036 = eq(T_5031, UInt<1>("h01")) + node T_5037 = or(T_5034, T_5036) + node T_5039 = neq(T_5032, UInt<1>("h00")) + node T_5040 = asSInt(T_5031) + node T_5042 = eq(T_5040, asSInt(UInt<1>("h01"))) + node T_5043 = asSInt(T_5031) + node T_5045 = eq(T_5043, asSInt(UInt<2>("h02"))) + node T_5046 = or(T_5042, T_5045) + node T_5047 = asSInt(T_5032) + node T_5049 = eq(T_5047, asSInt(UInt<1>("h01"))) + node T_5050 = bit(T_5032, 0) + node T_5051 = mux(T_5046, T_5049, T_5050) + node T_5052 = mux(T_5037, T_5039, T_5051) + node T_5053 = bits(alu.adder_out, 38, 0) + node T_5054 = cat(T_5052, T_5053) + dmem.req.bits.addr := T_5054 + node T_5055 = cat(ex_waddr, ex_ctrl.fp) + dmem.req.bits.tag := T_5055 + node T_5056 = mux(mem_ctrl.fp, fpu.store_data, mem_reg_rs2) + dmem.req.bits.data := T_5056 + dmem.invalidate_lr := wb_xcpt + rocc.cmd.valid := wb_rocc_val + node T_5058 = neq(csr.status.xs, UInt<1>("h00")) + node T_5059 = and(wb_xcpt, T_5058) + rocc.exception := T_5059 + node T_5061 = neq(csr.status.prv, UInt<1>("h00")) + rocc.s := T_5061 + wire T_5080 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} + T_5080.opcode := UInt<1>("h00") + T_5080.rd := UInt<1>("h00") + T_5080.xs2 := UInt<1>("h00") + T_5080.xs1 := UInt<1>("h00") + T_5080.xd := UInt<1>("h00") + T_5080.rs1 := UInt<1>("h00") + T_5080.rs2 := UInt<1>("h00") + T_5080.funct := UInt<1>("h00") + node T_5097 = bits(wb_reg_inst, 6, 0) + T_5080.opcode := T_5097 + node T_5098 = bits(wb_reg_inst, 11, 7) + T_5080.rd := T_5098 + node T_5099 = bits(wb_reg_inst, 12, 12) + T_5080.xs2 := T_5099 + node T_5100 = bits(wb_reg_inst, 13, 13) + T_5080.xs1 := T_5100 + node T_5101 = bits(wb_reg_inst, 14, 14) + T_5080.xd := T_5101 + node T_5102 = bits(wb_reg_inst, 19, 15) + T_5080.rs1 := T_5102 + node T_5103 = bits(wb_reg_inst, 24, 20) + T_5080.rs2 := T_5103 + node T_5104 = bits(wb_reg_inst, 31, 25) + T_5080.funct := T_5104 + rocc.cmd.bits.inst_1 <> T_5080 + rocc.cmd.bits.rs1 := wb_reg_wdata + rocc.cmd.bits.rs2 := wb_reg_rs2 + node T_5105 = bits(csr.time, 32, 0) + node T_5107 = mux(rf_wen, rf_waddr, UInt<1>("h00")) + node T_5108 = bits(wb_reg_inst, 19, 15) + reg T_5109 : UInt<?>, clock, reset + T_5109 := T_4264 + reg T_5110 : UInt<?>, clock, reset + T_5110 := T_5109 + node T_5111 = bits(wb_reg_inst, 24, 20) + reg T_5112 : UInt<?>, clock, reset + T_5112 := T_4267 + reg T_5113 : UInt<?>, clock, reset + T_5113 := T_5112 + + module HellaCacheArbiter : + output mem_1 : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>} + input requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}[2] + input clock : Clock + input reset : UInt<1> + + mem_1.invalidate_lr := UInt<1>("h00") + mem_1.req.bits.data := UInt<1>("h00") + mem_1.req.bits.phys := UInt<1>("h00") + mem_1.req.bits.kill := UInt<1>("h00") + mem_1.req.bits.typ := UInt<1>("h00") + mem_1.req.bits.cmd := UInt<1>("h00") + mem_1.req.bits.tag := UInt<1>("h00") + mem_1.req.bits.addr := UInt<1>("h00") + mem_1.req.valid := UInt<1>("h00") + requestor[0].ordered := UInt<1>("h00") + requestor[0].xcpt.pf.st := UInt<1>("h00") + requestor[0].xcpt.pf.ld := UInt<1>("h00") + requestor[0].xcpt.ma.st := UInt<1>("h00") + requestor[0].xcpt.ma.ld := UInt<1>("h00") + requestor[0].replay_next.bits := UInt<1>("h00") + requestor[0].replay_next.valid := UInt<1>("h00") + requestor[0].resp.bits.store_data := UInt<1>("h00") + requestor[0].resp.bits.data_subword := UInt<1>("h00") + requestor[0].resp.bits.has_data := UInt<1>("h00") + requestor[0].resp.bits.replay := UInt<1>("h00") + requestor[0].resp.bits.nack := UInt<1>("h00") + requestor[0].resp.bits.data := UInt<1>("h00") + requestor[0].resp.bits.typ := UInt<1>("h00") + requestor[0].resp.bits.cmd := UInt<1>("h00") + requestor[0].resp.bits.tag := UInt<1>("h00") + requestor[0].resp.bits.addr := UInt<1>("h00") + requestor[0].resp.valid := UInt<1>("h00") + requestor[0].req.ready := UInt<1>("h00") + requestor[1].ordered := UInt<1>("h00") + requestor[1].xcpt.pf.st := UInt<1>("h00") + requestor[1].xcpt.pf.ld := UInt<1>("h00") + requestor[1].xcpt.ma.st := UInt<1>("h00") + requestor[1].xcpt.ma.ld := UInt<1>("h00") + requestor[1].replay_next.bits := UInt<1>("h00") + requestor[1].replay_next.valid := UInt<1>("h00") + requestor[1].resp.bits.store_data := UInt<1>("h00") + requestor[1].resp.bits.data_subword := UInt<1>("h00") + requestor[1].resp.bits.has_data := UInt<1>("h00") + requestor[1].resp.bits.replay := UInt<1>("h00") + requestor[1].resp.bits.nack := UInt<1>("h00") + requestor[1].resp.bits.data := UInt<1>("h00") + requestor[1].resp.bits.typ := UInt<1>("h00") + requestor[1].resp.bits.cmd := UInt<1>("h00") + requestor[1].resp.bits.tag := UInt<1>("h00") + requestor[1].resp.bits.addr := UInt<1>("h00") + requestor[1].resp.valid := UInt<1>("h00") + requestor[1].req.ready := UInt<1>("h00") + reg T_1238 : UInt<1>, clock, reset + T_1238 := requestor[0].req.valid + reg T_1239 : UInt<1>, clock, reset + T_1239 := requestor[1].req.valid + node T_1240 = or(requestor[0].req.valid, requestor[1].req.valid) + mem_1.req.valid := T_1240 + requestor[0].req.ready := mem_1.req.ready + node T_1242 = eq(requestor[0].req.valid, UInt<1>("h00")) + node T_1243 = and(requestor[0].req.ready, T_1242) + requestor[1].req.ready := T_1243 + mem_1.req.bits <> requestor[1].req.bits + node T_1245 = cat(requestor[1].req.bits.tag, UInt<1>("h01")) + mem_1.req.bits.tag := T_1245 + when requestor[0].req.valid : + mem_1.req.bits.cmd := requestor[0].req.bits.cmd + mem_1.req.bits.typ := requestor[0].req.bits.typ + mem_1.req.bits.addr := requestor[0].req.bits.addr + mem_1.req.bits.phys := requestor[0].req.bits.phys + node T_1247 = cat(requestor[0].req.bits.tag, UInt<1>("h00")) + mem_1.req.bits.tag := T_1247 + skip + when T_1238 : + mem_1.req.bits.kill := requestor[0].req.bits.kill + mem_1.req.bits.data := requestor[0].req.bits.data + skip + node T_1248 = bits(mem_1.resp.bits.tag, 0, 0) + node T_1250 = eq(T_1248, UInt<1>("h00")) + node T_1251 = and(mem_1.resp.valid, T_1250) + requestor[0].resp.valid := T_1251 + requestor[0].xcpt <> mem_1.xcpt + requestor[0].ordered := mem_1.ordered + requestor[0].resp.bits <> mem_1.resp.bits + node T_1252 = shr(mem_1.resp.bits.tag, 1) + requestor[0].resp.bits.tag := T_1252 + node T_1253 = and(mem_1.resp.bits.nack, T_1250) + requestor[0].resp.bits.nack := T_1253 + node T_1254 = and(mem_1.resp.bits.replay, T_1250) + requestor[0].resp.bits.replay := T_1254 + node T_1255 = bits(mem_1.replay_next.bits, 0, 0) + node T_1257 = eq(T_1255, UInt<1>("h00")) + node T_1258 = and(mem_1.replay_next.valid, T_1257) + requestor[0].replay_next.valid := T_1258 + node T_1259 = shr(mem_1.replay_next.bits, 1) + requestor[0].replay_next.bits := T_1259 + node T_1260 = bits(mem_1.resp.bits.tag, 0, 0) + node T_1262 = eq(T_1260, UInt<1>("h01")) + node T_1263 = and(mem_1.resp.valid, T_1262) + requestor[1].resp.valid := T_1263 + requestor[1].xcpt <> mem_1.xcpt + requestor[1].ordered := mem_1.ordered + requestor[1].resp.bits <> mem_1.resp.bits + node T_1264 = shr(mem_1.resp.bits.tag, 1) + requestor[1].resp.bits.tag := T_1264 + node T_1265 = and(mem_1.resp.bits.nack, T_1262) + requestor[1].resp.bits.nack := T_1265 + node T_1266 = and(mem_1.resp.bits.replay, T_1262) + requestor[1].resp.bits.replay := T_1266 + node T_1267 = bits(mem_1.replay_next.bits, 0, 0) + node T_1269 = eq(T_1267, UInt<1>("h01")) + node T_1270 = and(mem_1.replay_next.valid, T_1269) + requestor[1].replay_next.valid := T_1270 + node T_1271 = shr(mem_1.replay_next.bits, 1) + requestor[1].replay_next.bits := T_1271 + + module FPUDecoder : + output sigs : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>} + input inst_1 : UInt<32> + input clock : Clock + input reset : UInt<1> + + sigs.wflags := UInt<1>("h00") + sigs.round := UInt<1>("h00") + sigs.sqrt := UInt<1>("h00") + sigs.div := UInt<1>("h00") + sigs.fma := UInt<1>("h00") + sigs.fastpipe := UInt<1>("h00") + sigs.toint := UInt<1>("h00") + sigs.fromint := UInt<1>("h00") + sigs.single := UInt<1>("h00") + sigs.swap23 := UInt<1>("h00") + sigs.swap12 := UInt<1>("h00") + sigs.ren3 := UInt<1>("h00") + sigs.ren2 := UInt<1>("h00") + sigs.ren1 := UInt<1>("h00") + sigs.wen := UInt<1>("h00") + sigs.ldst := UInt<1>("h00") + sigs.cmd := UInt<1>("h00") + node T_42 = and(inst_1, UInt<32>("h04")) + node T_44 = eq(T_42, UInt<32>("h04")) + node T_46 = and(inst_1, UInt<32>("h08000010")) + node T_48 = eq(T_46, UInt<32>("h08000010")) + node T_50 = or(UInt<1>("h00"), T_44) + node T_51 = or(T_50, T_48) + node T_53 = and(inst_1, UInt<32>("h08")) + node T_55 = eq(T_53, UInt<32>("h08")) + node T_57 = and(inst_1, UInt<32>("h010000010")) + node T_59 = eq(T_57, UInt<32>("h010000010")) + node T_61 = or(UInt<1>("h00"), T_55) + node T_62 = or(T_61, T_59) + node T_64 = and(inst_1, UInt<32>("h040")) + node T_66 = eq(T_64, UInt<32>("h00")) + node T_68 = and(inst_1, UInt<32>("h020000000")) + node T_70 = eq(T_68, UInt<32>("h020000000")) + node T_72 = or(UInt<1>("h00"), T_66) + node T_73 = or(T_72, T_70) + node T_75 = and(inst_1, UInt<32>("h040000000")) + node T_77 = eq(T_75, UInt<32>("h040000000")) + node T_79 = or(UInt<1>("h00"), T_66) + node T_80 = or(T_79, T_77) + node T_82 = and(inst_1, UInt<32>("h010")) + node T_84 = eq(T_82, UInt<32>("h00")) + node T_86 = or(UInt<1>("h00"), T_84) + node T_87 = cat(T_62, T_51) + node T_88 = cat(T_73, T_87) + node T_89 = cat(T_80, T_88) + node T_90 = cat(T_86, T_89) + node T_92 = or(UInt<1>("h00"), T_66) + node T_94 = and(inst_1, UInt<32>("h080000020")) + node T_96 = eq(T_94, UInt<32>("h00")) + node T_98 = and(inst_1, UInt<32>("h030")) + node T_100 = eq(T_98, UInt<32>("h00")) + node T_102 = and(inst_1, UInt<32>("h010000020")) + node T_104 = eq(T_102, UInt<32>("h010000000")) + node T_106 = or(UInt<1>("h00"), T_96) + node T_107 = or(T_106, T_100) + node T_108 = or(T_107, T_104) + node T_110 = and(inst_1, UInt<32>("h080000004")) + node T_112 = eq(T_110, UInt<32>("h00")) + node T_114 = and(inst_1, UInt<32>("h010000004")) + node T_116 = eq(T_114, UInt<32>("h00")) + node T_118 = and(inst_1, UInt<32>("h050")) + node T_120 = eq(T_118, UInt<32>("h040")) + node T_122 = or(UInt<1>("h00"), T_112) + node T_123 = or(T_122, T_116) + node T_124 = or(T_123, T_120) + node T_126 = and(inst_1, UInt<32>("h040000004")) + node T_128 = eq(T_126, UInt<32>("h00")) + node T_130 = and(inst_1, UInt<32>("h020")) + node T_132 = eq(T_130, UInt<32>("h020")) + node T_134 = or(UInt<1>("h00"), T_128) + node T_135 = or(T_134, T_132) + node T_136 = or(T_135, T_120) + node T_138 = or(UInt<1>("h00"), T_120) + node T_140 = and(inst_1, UInt<32>("h050000010")) + node T_142 = eq(T_140, UInt<32>("h050000010")) + node T_144 = or(UInt<1>("h00"), T_66) + node T_145 = or(T_144, T_142) + node T_147 = and(inst_1, UInt<32>("h030000010")) + node T_149 = eq(T_147, UInt<32>("h010")) + node T_151 = or(UInt<1>("h00"), T_149) + node T_153 = and(inst_1, UInt<32>("h01040")) + node T_155 = eq(T_153, UInt<32>("h00")) + node T_157 = and(inst_1, UInt<32>("h02000040")) + node T_159 = eq(T_157, UInt<32>("h040")) + node T_161 = or(UInt<1>("h00"), T_155) + node T_162 = or(T_161, T_159) + node T_164 = and(inst_1, UInt<32>("h090000010")) + node T_166 = eq(T_164, UInt<32>("h090000010")) + node T_168 = or(UInt<1>("h00"), T_166) + node T_170 = and(inst_1, UInt<32>("h090000010")) + node T_172 = eq(T_170, UInt<32>("h080000010")) + node T_174 = or(UInt<1>("h00"), T_132) + node T_175 = or(T_174, T_172) + node T_177 = and(inst_1, UInt<32>("h0a0000010")) + node T_179 = eq(T_177, UInt<32>("h020000010")) + node T_181 = and(inst_1, UInt<32>("h0d0000010")) + node T_183 = eq(T_181, UInt<32>("h040000010")) + node T_185 = or(UInt<1>("h00"), T_179) + node T_186 = or(T_185, T_183) + node T_188 = and(inst_1, UInt<32>("h070000004")) + node T_190 = eq(T_188, UInt<32>("h00")) + node T_192 = and(inst_1, UInt<32>("h068000004")) + node T_194 = eq(T_192, UInt<32>("h00")) + node T_196 = or(UInt<1>("h00"), T_190) + node T_197 = or(T_196, T_194) + node T_198 = or(T_197, T_120) + node T_200 = and(inst_1, UInt<32>("h058000010")) + node T_202 = eq(T_200, UInt<32>("h018000010")) + node T_204 = or(UInt<1>("h00"), T_202) + node T_206 = and(inst_1, UInt<32>("h0d0000010")) + node T_208 = eq(T_206, UInt<32>("h050000010")) + node T_210 = or(UInt<1>("h00"), T_208) + node T_212 = and(inst_1, UInt<32>("h020000004")) + node T_214 = eq(T_212, UInt<32>("h00")) + node T_216 = and(inst_1, UInt<32>("h040002000")) + node T_218 = eq(T_216, UInt<32>("h040000000")) + node T_220 = or(UInt<1>("h00"), T_214) + node T_221 = or(T_220, T_120) + node T_222 = or(T_221, T_218) + node T_224 = and(inst_1, UInt<32>("h08002000")) + node T_226 = eq(T_224, UInt<32>("h08000000")) + node T_228 = and(inst_1, UInt<32>("h0c0000004")) + node T_230 = eq(T_228, UInt<32>("h080000000")) + node T_232 = or(UInt<1>("h00"), T_214) + node T_233 = or(T_232, T_120) + node T_234 = or(T_233, T_226) + node T_235 = or(T_234, T_230) + sigs.cmd := T_90 + sigs.ldst := T_92 + sigs.wen := T_108 + sigs.ren1 := T_124 + sigs.ren2 := T_136 + sigs.ren3 := T_138 + sigs.swap12 := T_145 + sigs.swap23 := T_151 + sigs.single := T_162 + sigs.fromint := T_168 + sigs.toint := T_175 + sigs.fastpipe := T_186 + sigs.fma := T_198 + sigs.div := T_204 + sigs.sqrt := T_210 + sigs.round := T_222 + sigs.wflags := T_235 + + module mulAddSubRecodedFloatN : + output exceptionFlags : UInt<5> + output out : UInt<33> + input roundingMode : UInt<2> + input c : UInt<33> + input b : UInt<33> + input a : UInt<33> + input op : UInt<2> + input clock : Clock + input reset : UInt<1> + + exceptionFlags := UInt<1>("h00") + out := UInt<1>("h00") + node signA = bit(a, 32) + node expA = bits(a, 31, 23) + node fractA = bits(a, 22, 0) + node T_14 = bits(expA, 8, 6) + node isZeroA = eq(T_14, UInt<1>("h00")) + node T_17 = bits(expA, 8, 7) + node isSpecialA = eq(T_17, UInt<2>("h03")) + node T_20 = bit(expA, 6) + node T_22 = eq(T_20, UInt<1>("h00")) + node isInfA = and(isSpecialA, T_22) + node T_24 = bit(expA, 6) + node isNaNA = and(isSpecialA, T_24) + node T_26 = bit(fractA, 22) + node T_28 = eq(T_26, UInt<1>("h00")) + node isSigNaNA = and(isNaNA, T_28) + node T_31 = eq(isZeroA, UInt<1>("h00")) + node sigA = cat(T_31, fractA) + node signB = bit(b, 32) + node expB = bits(b, 31, 23) + node fractB = bits(b, 22, 0) + node T_36 = bits(expB, 8, 6) + node isZeroB = eq(T_36, UInt<1>("h00")) + node T_39 = bits(expB, 8, 7) + node isSpecialB = eq(T_39, UInt<2>("h03")) + node T_42 = bit(expB, 6) + node T_44 = eq(T_42, UInt<1>("h00")) + node isInfB = and(isSpecialB, T_44) + node T_46 = bit(expB, 6) + node isNaNB = and(isSpecialB, T_46) + node T_48 = bit(fractB, 22) + node T_50 = eq(T_48, UInt<1>("h00")) + node isSigNaNB = and(isNaNB, T_50) + node T_53 = eq(isZeroB, UInt<1>("h00")) + node sigB = cat(T_53, fractB) + node T_55 = bit(c, 32) + node T_56 = bit(op, 0) + node opSignC = xor(T_55, T_56) + node expC = bits(c, 31, 23) + node fractC = bits(c, 22, 0) + node T_60 = bits(expC, 8, 6) + node isZeroC = eq(T_60, UInt<1>("h00")) + node T_63 = bits(expC, 8, 7) + node isSpecialC = eq(T_63, UInt<2>("h03")) + node T_66 = bit(expC, 6) + node T_68 = eq(T_66, UInt<1>("h00")) + node isInfC = and(isSpecialC, T_68) + node T_70 = bit(expC, 6) + node isNaNC = and(isSpecialC, T_70) + node T_72 = bit(fractC, 22) + node T_74 = eq(T_72, UInt<1>("h00")) + node isSigNaNC = and(isNaNC, T_74) + node T_77 = eq(isZeroC, UInt<1>("h00")) + node sigC = cat(T_77, fractC) + node roundingMode_nearest_even = eq(roundingMode, UInt<2>("h00")) + node roundingMode_minMag = eq(roundingMode, UInt<2>("h01")) + node roundingMode_min = eq(roundingMode, UInt<2>("h02")) + node roundingMode_max = eq(roundingMode, UInt<2>("h03")) + node T_91 = xor(signA, signB) + node T_92 = bit(op, 1) + node signProd = xor(T_91, T_92) + node isZeroProd = or(isZeroA, isZeroB) + node T_95 = bit(expB, 8) + node T_97 = eq(T_95, UInt<1>("h00")) + node T_99 = subw(UInt<3>("h00"), T_97) + node T_100 = bits(expB, 7, 0) + node T_101 = cat(T_99, T_100) + node T_102 = addw(T_101, expA) + node sExpAlignedProd = addw(T_102, UInt<5>("h01b")) + node doSubMags = xor(signProd, opSignC) + node sNatCAlignDist = subw(sExpAlignedProd, expC) + node T_107 = bit(sNatCAlignDist, 10) + node CAlignDist_floor = or(isZeroProd, T_107) + node T_109 = bits(sNatCAlignDist, 9, 0) + node T_111 = eq(T_109, UInt<1>("h00")) + node CAlignDist_0 = or(CAlignDist_floor, T_111) + node T_114 = eq(isZeroC, UInt<1>("h00")) + node T_115 = bits(sNatCAlignDist, 9, 0) + node T_117 = lt(T_115, UInt<5>("h019")) + node T_118 = or(CAlignDist_floor, T_117) + node isCDominant = and(T_114, T_118) + node T_121 = bits(sNatCAlignDist, 9, 0) + node T_123 = lt(T_121, UInt<7>("h04a")) + node T_125 = mux(T_123, sNatCAlignDist, UInt<7>("h04a")) + node T_126 = mux(CAlignDist_floor, UInt<1>("h00"), T_125) + node CAlignDist = bits(T_126, 6, 0) + node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) + node T_130 = dshr(asSInt(UInt<129>("h0100000000000000000000000000000000")), CAlignDist) + node T_131 = bits(T_130, 77, 54) + node T_132 = bits(T_131, 15, 0) + node T_135 = shl(UInt<8>("h0ff"), 8) + node T_136 = xor(UInt<16>("h0ffff"), T_135) + node T_137 = shr(T_132, 8) + node T_138 = and(T_137, T_136) + node T_139 = bits(T_132, 7, 0) + node T_140 = shl(T_139, 8) + node T_141 = not(T_136) + node T_142 = and(T_140, T_141) + node T_143 = or(T_138, T_142) + node T_144 = bits(T_136, 11, 0) + node T_145 = shl(T_144, 4) + node T_146 = xor(T_136, T_145) + node T_147 = shr(T_143, 4) + node T_148 = and(T_147, T_146) + node T_149 = bits(T_143, 11, 0) + node T_150 = shl(T_149, 4) + node T_151 = not(T_146) + node T_152 = and(T_150, T_151) + node T_153 = or(T_148, T_152) + node T_154 = bits(T_146, 13, 0) + node T_155 = shl(T_154, 2) + node T_156 = xor(T_146, T_155) + node T_157 = shr(T_153, 2) + node T_158 = and(T_157, T_156) + node T_159 = bits(T_153, 13, 0) + node T_160 = shl(T_159, 2) + node T_161 = not(T_156) + node T_162 = and(T_160, T_161) + node T_163 = or(T_158, T_162) + node T_164 = bits(T_156, 14, 0) + node T_165 = shl(T_164, 1) + node T_166 = xor(T_156, T_165) + node T_167 = shr(T_163, 1) + node T_168 = and(T_167, T_166) + node T_169 = bits(T_163, 14, 0) + node T_170 = shl(T_169, 1) + node T_171 = not(T_166) + node T_172 = and(T_170, T_171) + node T_173 = or(T_168, T_172) + node T_174 = bits(T_131, 23, 16) + node T_177 = shl(UInt<4>("h0f"), 4) + node T_178 = xor(UInt<8>("h0ff"), T_177) + node T_179 = shr(T_174, 4) + node T_180 = and(T_179, T_178) + node T_181 = bits(T_174, 3, 0) + node T_182 = shl(T_181, 4) + node T_183 = not(T_178) + node T_184 = and(T_182, T_183) + node T_185 = or(T_180, T_184) + node T_186 = bits(T_178, 5, 0) + node T_187 = shl(T_186, 2) + node T_188 = xor(T_178, T_187) + node T_189 = shr(T_185, 2) + node T_190 = and(T_189, T_188) + node T_191 = bits(T_185, 5, 0) + node T_192 = shl(T_191, 2) + node T_193 = not(T_188) + node T_194 = and(T_192, T_193) + node T_195 = or(T_190, T_194) + node T_196 = bits(T_188, 6, 0) + node T_197 = shl(T_196, 1) + node T_198 = xor(T_188, T_197) + node T_199 = shr(T_195, 1) + node T_200 = and(T_199, T_198) + node T_201 = bits(T_195, 6, 0) + node T_202 = shl(T_201, 1) + node T_203 = not(T_198) + node T_204 = and(T_202, T_203) + node T_205 = or(T_200, T_204) + node CExtraMask = cat(T_173, T_205) + node T_207 = not(sigC) + node negSigC = mux(doSubMags, T_207, sigC) + node T_210 = subw(UInt<50>("h00"), doSubMags) + node T_211 = cat(negSigC, T_210) + node T_212 = cat(doSubMags, T_211) + node T_213 = asSInt(T_212) + node T_214 = dshr(T_213, CAlignDist) + node T_215 = and(sigC, CExtraMask) + node T_217 = neq(T_215, UInt<1>("h00")) + node T_218 = xor(T_217, doSubMags) + node T_219 = asUInt(T_214) + node T_220 = cat(T_219, T_218) + node alignedNegSigC = bits(T_220, 74, 0) + node T_222 = mul(sigA, sigB) + node T_223 = shl(T_222, 1) + node sigSum = addw(T_223, alignedNegSigC) + node T_226 = bits(sigSum, 50, 1) + node T_227 = xor(UInt<50>("h00"), T_226) + node T_228 = or(UInt<50>("h00"), T_226) + node T_229 = shl(T_228, 1) + node T_230 = xor(T_227, T_229) + node T_231 = bit(T_230, 49) + node T_233 = bit(T_230, 48) + node T_235 = bit(T_230, 47) + node T_237 = bit(T_230, 46) + node T_239 = bit(T_230, 45) + node T_241 = bit(T_230, 44) + node T_243 = bit(T_230, 43) + node T_245 = bit(T_230, 42) + node T_247 = bit(T_230, 41) + node T_249 = bit(T_230, 40) + node T_251 = bit(T_230, 39) + node T_253 = bit(T_230, 38) + node T_255 = bit(T_230, 37) + node T_257 = bit(T_230, 36) + node T_259 = bit(T_230, 35) + node T_261 = bit(T_230, 34) + node T_263 = bit(T_230, 33) + node T_265 = bit(T_230, 32) + node T_267 = bit(T_230, 31) + node T_269 = bit(T_230, 30) + node T_271 = bit(T_230, 29) + node T_273 = bit(T_230, 28) + node T_275 = bit(T_230, 27) + node T_277 = bit(T_230, 26) + node T_279 = bit(T_230, 25) + node T_281 = bit(T_230, 24) + node T_283 = bit(T_230, 23) + node T_285 = bit(T_230, 22) + node T_287 = bit(T_230, 21) + node T_289 = bit(T_230, 20) + node T_291 = bit(T_230, 19) + node T_293 = bit(T_230, 18) + node T_295 = bit(T_230, 17) + node T_297 = bit(T_230, 16) + node T_299 = bit(T_230, 15) + node T_301 = bit(T_230, 14) + node T_303 = bit(T_230, 13) + node T_305 = bit(T_230, 12) + node T_307 = bit(T_230, 11) + node T_309 = bit(T_230, 10) + node T_311 = bit(T_230, 9) + node T_313 = bit(T_230, 8) + node T_315 = bit(T_230, 7) + node T_317 = bit(T_230, 6) + node T_319 = bit(T_230, 5) + node T_321 = bit(T_230, 4) + node T_323 = bit(T_230, 3) + node T_325 = bit(T_230, 2) + node T_327 = bit(T_230, 1) + node T_329 = bit(T_230, 0) + node T_331 = mux(T_327, UInt<7>("h048"), UInt<7>("h049")) + node T_332 = mux(T_325, UInt<7>("h047"), T_331) + node T_333 = mux(T_323, UInt<7>("h046"), T_332) + node T_334 = mux(T_321, UInt<7>("h045"), T_333) + node T_335 = mux(T_319, UInt<7>("h044"), T_334) + node T_336 = mux(T_317, UInt<7>("h043"), T_335) + node T_337 = mux(T_315, UInt<7>("h042"), T_336) + node T_338 = mux(T_313, UInt<7>("h041"), T_337) + node T_339 = mux(T_311, UInt<7>("h040"), T_338) + node T_340 = mux(T_309, UInt<7>("h03f"), T_339) + node T_341 = mux(T_307, UInt<7>("h03e"), T_340) + node T_342 = mux(T_305, UInt<7>("h03d"), T_341) + node T_343 = mux(T_303, UInt<7>("h03c"), T_342) + node T_344 = mux(T_301, UInt<7>("h03b"), T_343) + node T_345 = mux(T_299, UInt<7>("h03a"), T_344) + node T_346 = mux(T_297, UInt<7>("h039"), T_345) + node T_347 = mux(T_295, UInt<7>("h038"), T_346) + node T_348 = mux(T_293, UInt<7>("h037"), T_347) + node T_349 = mux(T_291, UInt<7>("h036"), T_348) + node T_350 = mux(T_289, UInt<7>("h035"), T_349) + node T_351 = mux(T_287, UInt<7>("h034"), T_350) + node T_352 = mux(T_285, UInt<7>("h033"), T_351) + node T_353 = mux(T_283, UInt<7>("h032"), T_352) + node T_354 = mux(T_281, UInt<7>("h031"), T_353) + node T_355 = mux(T_279, UInt<7>("h030"), T_354) + node T_356 = mux(T_277, UInt<7>("h02f"), T_355) + node T_357 = mux(T_275, UInt<7>("h02e"), T_356) + node T_358 = mux(T_273, UInt<7>("h02d"), T_357) + node T_359 = mux(T_271, UInt<7>("h02c"), T_358) + node T_360 = mux(T_269, UInt<7>("h02b"), T_359) + node T_361 = mux(T_267, UInt<7>("h02a"), T_360) + node T_362 = mux(T_265, UInt<7>("h029"), T_361) + node T_363 = mux(T_263, UInt<7>("h028"), T_362) + node T_364 = mux(T_261, UInt<7>("h027"), T_363) + node T_365 = mux(T_259, UInt<7>("h026"), T_364) + node T_366 = mux(T_257, UInt<7>("h025"), T_365) + node T_367 = mux(T_255, UInt<7>("h024"), T_366) + node T_368 = mux(T_253, UInt<7>("h023"), T_367) + node T_369 = mux(T_251, UInt<7>("h022"), T_368) + node T_370 = mux(T_249, UInt<7>("h021"), T_369) + node T_371 = mux(T_247, UInt<7>("h020"), T_370) + node T_372 = mux(T_245, UInt<7>("h01f"), T_371) + node T_373 = mux(T_243, UInt<7>("h01e"), T_372) + node T_374 = mux(T_241, UInt<7>("h01d"), T_373) + node T_375 = mux(T_239, UInt<7>("h01c"), T_374) + node T_376 = mux(T_237, UInt<7>("h01b"), T_375) + node T_377 = mux(T_235, UInt<7>("h01a"), T_376) + node T_378 = mux(T_233, UInt<7>("h019"), T_377) + node estNormPos_dist = mux(T_231, UInt<7>("h018"), T_378) + node T_380 = bits(sigSum, 33, 18) + node T_382 = neq(T_380, UInt<1>("h00")) + node T_383 = bits(sigSum, 17, 0) + node T_385 = neq(T_383, UInt<1>("h00")) + node firstReduceSigSum = cat(T_382, T_385) + node notSigSum = not(sigSum) + node T_388 = bits(notSigSum, 33, 18) + node T_390 = neq(T_388, UInt<1>("h00")) + node T_391 = bits(notSigSum, 17, 0) + node T_393 = neq(T_391, UInt<1>("h00")) + node firstReduceNotSigSum = cat(T_390, T_393) + node T_395 = or(CAlignDist_0, doSubMags) + node T_397 = subw(CAlignDist, UInt<1>("h01")) + node T_398 = bits(T_397, 4, 0) + node CDom_estNormDist = mux(T_395, CAlignDist, T_398) + node T_400 = not(doSubMags) + node T_401 = bit(CDom_estNormDist, 4) + node T_402 = not(T_401) + node T_403 = and(T_400, T_402) + node T_404 = asSInt(T_403) + node T_405 = bits(sigSum, 74, 34) + node T_407 = neq(firstReduceSigSum, UInt<1>("h00")) + node T_408 = cat(T_405, T_407) + node T_409 = asSInt(T_408) + node T_410 = and(T_404, T_409) + node T_411 = not(doSubMags) + node T_412 = bit(CDom_estNormDist, 4) + node T_413 = and(T_411, T_412) + node T_414 = asSInt(T_413) + node T_415 = bits(sigSum, 58, 18) + node T_416 = bit(firstReduceSigSum, 0) + node T_417 = cat(T_415, T_416) + node T_418 = asSInt(T_417) + node T_419 = and(T_414, T_418) + node T_420 = or(T_410, T_419) + node T_421 = bit(CDom_estNormDist, 4) + node T_422 = not(T_421) + node T_423 = and(doSubMags, T_422) + node T_424 = asSInt(T_423) + node T_425 = bits(notSigSum, 74, 34) + node T_427 = neq(firstReduceNotSigSum, UInt<1>("h00")) + node T_428 = cat(T_425, T_427) + node T_429 = asSInt(T_428) + node T_430 = and(T_424, T_429) + node T_431 = or(T_420, T_430) + node T_432 = bit(CDom_estNormDist, 4) + node T_433 = and(doSubMags, T_432) + node T_434 = asSInt(T_433) + node T_435 = bits(notSigSum, 58, 18) + node T_436 = bit(firstReduceNotSigSum, 0) + node T_437 = cat(T_435, T_436) + node T_438 = asSInt(T_437) + node T_439 = and(T_434, T_438) + node T_440 = or(T_431, T_439) + node CDom_firstNormAbsSigSum = asUInt(T_440) + node T_442 = bits(sigSum, 50, 18) + node T_443 = bit(firstReduceNotSigSum, 0) + node T_444 = not(T_443) + node T_445 = bit(firstReduceSigSum, 0) + node T_446 = mux(doSubMags, T_444, T_445) + node T_447 = cat(T_442, T_446) + node T_448 = bits(sigSum, 42, 1) + node T_449 = bit(estNormPos_dist, 5) + node T_450 = bit(estNormPos_dist, 4) + node T_451 = bits(sigSum, 26, 1) + node T_453 = subw(UInt<16>("h00"), doSubMags) + node T_454 = cat(T_451, T_453) + node T_455 = mux(T_450, T_454, T_448) + node T_456 = bit(estNormPos_dist, 4) + node T_457 = bits(sigSum, 10, 1) + node T_459 = subw(UInt<32>("h00"), doSubMags) + node T_460 = cat(T_457, T_459) + node T_461 = mux(T_456, T_447, T_460) + node notCDom_pos_firstNormAbsSigSum = mux(T_449, T_455, T_461) + node T_463 = bits(notSigSum, 49, 18) + node T_464 = bit(firstReduceNotSigSum, 0) + node T_465 = cat(T_463, T_464) + node T_466 = bits(notSigSum, 42, 1) + node T_467 = bit(estNormPos_dist, 5) + node T_468 = bit(estNormPos_dist, 4) + node T_469 = bits(notSigSum, 27, 1) + node T_470 = shl(T_469, 16) + node T_471 = mux(T_468, T_470, T_466) + node T_472 = bit(estNormPos_dist, 4) + node T_473 = bits(notSigSum, 11, 1) + node T_474 = shl(T_473, 32) + node T_475 = mux(T_472, T_465, T_474) + node notCDom_neg_cFirstNormAbsSigSum = mux(T_467, T_471, T_475) + node notCDom_signSigSum = bit(sigSum, 51) + node T_478 = not(isZeroC) + node T_479 = and(doSubMags, T_478) + node doNegSignSum = mux(isCDominant, T_479, notCDom_signSigSum) + node T_481 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) + node estNormDist = mux(isCDominant, CDom_estNormDist, T_481) + node T_483 = mux(isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) + node T_484 = mux(isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) + node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_483, T_484) + node T_486 = not(isCDominant) + node T_487 = not(notCDom_signSigSum) + node T_488 = and(T_486, T_487) + node doIncrSig = and(T_488, doSubMags) + node estNormDist_5 = bits(estNormDist, 3, 0) + node normTo2ShiftDist = not(estNormDist_5) + node T_493 = dshr(asSInt(UInt<17>("h010000")), normTo2ShiftDist) + node T_494 = bits(T_493, 15, 1) + node T_495 = bits(T_494, 7, 0) + node T_498 = shl(UInt<4>("h0f"), 4) + node T_499 = xor(UInt<8>("h0ff"), T_498) + node T_500 = shr(T_495, 4) + node T_501 = and(T_500, T_499) + node T_502 = bits(T_495, 3, 0) + node T_503 = shl(T_502, 4) + node T_504 = not(T_499) + node T_505 = and(T_503, T_504) + node T_506 = or(T_501, T_505) + node T_507 = bits(T_499, 5, 0) + node T_508 = shl(T_507, 2) + node T_509 = xor(T_499, T_508) + node T_510 = shr(T_506, 2) + node T_511 = and(T_510, T_509) + node T_512 = bits(T_506, 5, 0) + node T_513 = shl(T_512, 2) + node T_514 = not(T_509) + node T_515 = and(T_513, T_514) + node T_516 = or(T_511, T_515) + node T_517 = bits(T_509, 6, 0) + node T_518 = shl(T_517, 1) + node T_519 = xor(T_509, T_518) + node T_520 = shr(T_516, 1) + node T_521 = and(T_520, T_519) + node T_522 = bits(T_516, 6, 0) + node T_523 = shl(T_522, 1) + node T_524 = not(T_519) + node T_525 = and(T_523, T_524) + node T_526 = or(T_521, T_525) + node T_527 = bits(T_494, 14, 8) + node T_528 = bits(T_527, 3, 0) + node T_529 = bits(T_528, 1, 0) + node T_530 = bits(T_529, 0, 0) + node T_531 = bits(T_529, 1, 1) + node T_532 = cat(T_530, T_531) + node T_533 = bits(T_528, 3, 2) + node T_534 = bits(T_533, 0, 0) + node T_535 = bits(T_533, 1, 1) + node T_536 = cat(T_534, T_535) + node T_537 = cat(T_532, T_536) + node T_538 = bits(T_527, 6, 4) + node T_539 = bits(T_538, 1, 0) + node T_540 = bits(T_539, 0, 0) + node T_541 = bits(T_539, 1, 1) + node T_542 = cat(T_540, T_541) + node T_543 = bits(T_538, 2, 2) + node T_544 = cat(T_542, T_543) + node T_545 = cat(T_537, T_544) + node T_546 = cat(T_526, T_545) + node absSigSumExtraMask = cat(T_546, UInt<1>("h01")) + node T_549 = bits(cFirstNormAbsSigSum, 42, 1) + node T_550 = dshr(T_549, normTo2ShiftDist) + node T_551 = bits(cFirstNormAbsSigSum, 15, 0) + node T_552 = not(T_551) + node T_553 = and(T_552, absSigSumExtraMask) + node T_555 = eq(T_553, UInt<1>("h00")) + node T_556 = bits(cFirstNormAbsSigSum, 15, 0) + node T_557 = and(T_556, absSigSumExtraMask) + node T_559 = neq(T_557, UInt<1>("h00")) + node T_560 = mux(doIncrSig, T_555, T_559) + node T_561 = cat(T_550, T_560) + node sigX3 = bits(T_561, 27, 0) + node T_563 = bits(sigX3, 27, 26) + node sigX3Shift1 = eq(T_563, UInt<1>("h00")) + node sExpX3 = subw(sExpSum, estNormDist) + node T_567 = bits(sigX3, 27, 25) + node isZeroY = eq(T_567, UInt<1>("h00")) + node T_570 = not(isZeroY) + node T_571 = xor(signProd, doNegSignSum) + node signY = and(T_570, T_571) + node sExpX3_13 = bits(sExpX3, 9, 0) + node T_574 = bit(sExpX3, 10) + node T_576 = subw(UInt<27>("h00"), T_574) + node T_577 = not(sExpX3_13) + node T_579 = dshr(asSInt(UInt<1025>("h010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_577) + node T_580 = bits(T_579, 131, 107) + node T_581 = bits(T_580, 15, 0) + node T_584 = shl(UInt<8>("h0ff"), 8) + node T_585 = xor(UInt<16>("h0ffff"), T_584) + node T_586 = shr(T_581, 8) + node T_587 = and(T_586, T_585) + node T_588 = bits(T_581, 7, 0) + node T_589 = shl(T_588, 8) + node T_590 = not(T_585) + node T_591 = and(T_589, T_590) + node T_592 = or(T_587, T_591) + node T_593 = bits(T_585, 11, 0) + node T_594 = shl(T_593, 4) + node T_595 = xor(T_585, T_594) + node T_596 = shr(T_592, 4) + node T_597 = and(T_596, T_595) + node T_598 = bits(T_592, 11, 0) + node T_599 = shl(T_598, 4) + node T_600 = not(T_595) + node T_601 = and(T_599, T_600) + node T_602 = or(T_597, T_601) + node T_603 = bits(T_595, 13, 0) + node T_604 = shl(T_603, 2) + node T_605 = xor(T_595, T_604) + node T_606 = shr(T_602, 2) + node T_607 = and(T_606, T_605) + node T_608 = bits(T_602, 13, 0) + node T_609 = shl(T_608, 2) + node T_610 = not(T_605) + node T_611 = and(T_609, T_610) + node T_612 = or(T_607, T_611) + node T_613 = bits(T_605, 14, 0) + node T_614 = shl(T_613, 1) + node T_615 = xor(T_605, T_614) + node T_616 = shr(T_612, 1) + node T_617 = and(T_616, T_615) + node T_618 = bits(T_612, 14, 0) + node T_619 = shl(T_618, 1) + node T_620 = not(T_615) + node T_621 = and(T_619, T_620) + node T_622 = or(T_617, T_621) + node T_623 = bits(T_580, 24, 16) + node T_624 = bits(T_623, 7, 0) + node T_627 = shl(UInt<4>("h0f"), 4) + node T_628 = xor(UInt<8>("h0ff"), T_627) + node T_629 = shr(T_624, 4) + node T_630 = and(T_629, T_628) + node T_631 = bits(T_624, 3, 0) + node T_632 = shl(T_631, 4) + node T_633 = not(T_628) + node T_634 = and(T_632, T_633) + node T_635 = or(T_630, T_634) + node T_636 = bits(T_628, 5, 0) + node T_637 = shl(T_636, 2) + node T_638 = xor(T_628, T_637) + node T_639 = shr(T_635, 2) + node T_640 = and(T_639, T_638) + node T_641 = bits(T_635, 5, 0) + node T_642 = shl(T_641, 2) + node T_643 = not(T_638) + node T_644 = and(T_642, T_643) + node T_645 = or(T_640, T_644) + node T_646 = bits(T_638, 6, 0) + node T_647 = shl(T_646, 1) + node T_648 = xor(T_638, T_647) + node T_649 = shr(T_645, 1) + node T_650 = and(T_649, T_648) + node T_651 = bits(T_645, 6, 0) + node T_652 = shl(T_651, 1) + node T_653 = not(T_648) + node T_654 = and(T_652, T_653) + node T_655 = or(T_650, T_654) + node T_656 = bits(T_623, 8, 8) + node T_657 = cat(T_655, T_656) + node T_658 = cat(T_622, T_657) + node T_659 = bit(sigX3, 26) + node T_660 = or(T_658, T_659) + node T_662 = cat(T_660, UInt<2>("h03")) + node roundMask = or(T_576, T_662) + node T_664 = shr(roundMask, 1) + node T_665 = not(T_664) + node roundPosMask = and(T_665, roundMask) + node T_667 = and(sigX3, roundPosMask) + node roundPosBit = neq(T_667, UInt<1>("h00")) + node T_670 = shr(roundMask, 1) + node T_671 = and(sigX3, T_670) + node anyRoundExtra = neq(T_671, UInt<1>("h00")) + node T_674 = not(sigX3) + node T_675 = shr(roundMask, 1) + node T_676 = and(T_674, T_675) + node allRoundExtra = eq(T_676, UInt<1>("h00")) + node anyRound = or(roundPosBit, anyRoundExtra) + node allRound = and(roundPosBit, allRoundExtra) + node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) + node T_682 = not(doIncrSig) + node T_683 = and(T_682, roundingMode_nearest_even) + node T_684 = and(T_683, roundPosBit) + node T_685 = and(T_684, anyRoundExtra) + node T_686 = not(doIncrSig) + node T_687 = and(T_686, roundDirectUp) + node T_688 = and(T_687, anyRound) + node T_689 = or(T_685, T_688) + node T_690 = and(doIncrSig, allRound) + node T_691 = or(T_689, T_690) + node T_692 = and(doIncrSig, roundingMode_nearest_even) + node T_693 = and(T_692, roundPosBit) + node T_694 = or(T_691, T_693) + node T_695 = and(doIncrSig, roundDirectUp) + node roundUp = or(T_694, T_695) + node T_697 = not(roundPosBit) + node T_698 = and(roundingMode_nearest_even, T_697) + node T_699 = and(T_698, allRoundExtra) + node T_700 = and(roundingMode_nearest_even, roundPosBit) + node T_701 = not(anyRoundExtra) + node T_702 = and(T_700, T_701) + node roundEven = mux(doIncrSig, T_699, T_702) + node T_704 = not(allRound) + node roundInexact = mux(doIncrSig, T_704, anyRound) + node T_706 = or(sigX3, roundMask) + node T_707 = shr(T_706, 2) + node T_709 = addw(T_707, UInt<1>("h01")) + node roundUp_sigY3 = bits(T_709, 25, 0) + node T_711 = not(roundUp) + node T_712 = not(roundEven) + node T_713 = and(T_711, T_712) + node T_714 = not(roundMask) + node T_715 = and(sigX3, T_714) + node T_716 = shr(T_715, 2) + node T_718 = mux(T_713, T_716, UInt<1>("h00")) + node T_720 = mux(roundUp, roundUp_sigY3, UInt<1>("h00")) + node T_721 = or(T_718, T_720) + node T_722 = shr(roundMask, 1) + node T_723 = not(T_722) + node T_724 = and(roundUp_sigY3, T_723) + node T_726 = mux(roundEven, T_724, UInt<1>("h00")) + node sigY3 = or(T_721, T_726) + node T_728 = bit(sigY3, 25) + node T_730 = addw(sExpX3, UInt<1>("h01")) + node T_732 = mux(T_728, T_730, UInt<1>("h00")) + node T_733 = bit(sigY3, 24) + node T_735 = mux(T_733, sExpX3, UInt<1>("h00")) + node T_736 = or(T_732, T_735) + node T_737 = bits(sigY3, 25, 24) + node T_739 = eq(T_737, UInt<1>("h00")) + node T_741 = subw(sExpX3, UInt<1>("h01")) + node T_743 = mux(T_739, T_741, UInt<1>("h00")) + node sExpY = or(T_736, T_743) + node expY = bits(sExpY, 8, 0) + node T_746 = bits(sigY3, 22, 0) + node T_747 = bits(sigY3, 23, 1) + node fractY = mux(sigX3Shift1, T_746, T_747) + node T_749 = bits(sExpY, 9, 7) + node overflowY = eq(T_749, UInt<2>("h03")) + node T_752 = bit(sExpY, 9) + node T_753 = bits(sExpY, 8, 0) + node T_755 = lt(T_753, UInt<7>("h06b")) + node totalUnderflowY = or(T_752, T_755) + node T_757 = bit(sExpX3, 10) + node T_760 = mux(sigX3Shift1, UInt<8>("h082"), UInt<8>("h081")) + node T_761 = leq(sExpX3_13, T_760) + node T_762 = or(T_757, T_761) + node underflowY = and(roundInexact, T_762) + node T_764 = and(roundingMode_min, signY) + node T_765 = or(roundingMode_nearest_even, T_764) + node T_766 = not(signY) + node T_767 = and(roundingMode_max, T_766) + node overflowY_roundMagUp = or(T_765, T_767) + node mulSpecial = or(isSpecialA, isSpecialB) + node addSpecial = or(mulSpecial, isSpecialC) + node notSpecial_addZeros = and(isZeroProd, isZeroC) + node T_772 = not(addSpecial) + node T_773 = not(notSpecial_addZeros) + node commonCase = and(T_772, T_773) + node T_775 = and(isInfA, isZeroB) + node T_776 = and(isZeroA, isInfB) + node T_777 = or(T_775, T_776) + node T_778 = not(isNaNA) + node T_779 = not(isNaNB) + node T_780 = and(T_778, T_779) + node T_781 = or(isInfA, isInfB) + node T_782 = and(T_780, T_781) + node T_783 = and(T_782, isInfC) + node T_784 = and(T_783, doSubMags) + node notSigNaN_invalid = or(T_777, T_784) + node T_786 = or(isSigNaNA, isSigNaNB) + node T_787 = or(T_786, isSigNaNC) + node invalid = or(T_787, notSigNaN_invalid) + node overflow = and(commonCase, overflowY) + node underflow = and(commonCase, underflowY) + node T_791 = and(commonCase, roundInexact) + node inexact = or(overflow, T_791) + node T_793 = or(notSpecial_addZeros, isZeroY) + node notSpecial_isZeroOut = or(T_793, totalUnderflowY) + node T_795 = not(overflowY_roundMagUp) + node isSatOut = and(overflow, T_795) + node T_797 = or(isInfA, isInfB) + node T_798 = or(T_797, isInfC) + node T_799 = and(overflow, overflowY_roundMagUp) + node notNaN_isInfOut = or(T_798, T_799) + node T_801 = or(isNaNA, isNaNB) + node T_802 = or(T_801, isNaNC) + node isNaNOut = or(T_802, notSigNaN_invalid) + node T_805 = eq(doSubMags, UInt<1>("h00")) + node T_806 = and(T_805, opSignC) + node T_808 = and(isNaNOut, UInt<1>("h01")) + node T_809 = or(T_806, T_808) + node T_811 = eq(isSpecialC, UInt<1>("h00")) + node T_812 = and(mulSpecial, T_811) + node T_813 = and(T_812, signProd) + node T_814 = or(T_809, T_813) + node T_816 = eq(mulSpecial, UInt<1>("h00")) + node T_817 = and(T_816, isSpecialC) + node T_818 = and(T_817, opSignC) + node T_819 = or(T_814, T_818) + node T_821 = eq(mulSpecial, UInt<1>("h00")) + node T_822 = and(T_821, notSpecial_addZeros) + node T_823 = and(T_822, doSubMags) + node T_825 = and(T_823, UInt<1>("h00")) + node T_826 = or(T_819, T_825) + node T_827 = and(commonCase, signY) + node signOut = or(T_826, T_827) + node T_831 = mux(notSpecial_isZeroOut, UInt<9>("h01c0"), UInt<9>("h00")) + node T_832 = not(T_831) + node T_833 = and(expY, T_832) + node T_836 = mux(isSatOut, UInt<8>("h080"), UInt<9>("h00")) + node T_837 = not(T_836) + node T_838 = and(T_833, T_837) + node T_841 = mux(notNaN_isInfOut, UInt<7>("h040"), UInt<9>("h00")) + node T_842 = not(T_841) + node T_843 = and(T_838, T_842) + node T_846 = mux(isSatOut, UInt<9>("h017f"), UInt<9>("h00")) + node T_847 = or(T_843, T_846) + node T_850 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<9>("h00")) + node T_851 = or(T_847, T_850) + node T_854 = mux(isNaNOut, UInt<9>("h01c0"), UInt<9>("h00")) + node expOut = or(T_851, T_854) + node T_856 = or(isNaNOut, isSatOut) + node T_858 = subw(UInt<23>("h00"), T_856) + node fractOut = or(fractY, T_858) + node T_860 = cat(expOut, fractOut) + node T_861 = cat(signOut, T_860) + out := T_861 + node T_863 = cat(invalid, UInt<1>("h00")) + node T_864 = cat(underflow, inexact) + node T_865 = cat(overflow, T_864) + node T_866 = cat(T_863, T_865) + exceptionFlags := T_866 + + module FPUFMAPipe : + output out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} + input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} + input clock : Clock + input reset : UInt<1> + + out.bits.exc := UInt<1>("h00") + out.bits.data := UInt<1>("h00") + out.valid := UInt<1>("h00") + node one = shl(UInt<1>("h01"), 31) + node T_136 = bit(in.bits.in1, 32) + node T_137 = bit(in.bits.in2, 32) + node T_138 = xor(T_136, T_137) + node zero = shl(T_138, 32) + reg valid : UInt<1>, clock, reset + valid := in.valid + reg in_1 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset + when in.valid : + in_1 <> in.bits + node T_187 = bit(in.bits.cmd, 1) + node T_188 = or(in.bits.ren3, in.bits.swap23) + node T_189 = and(T_187, T_188) + node T_190 = bit(in.bits.cmd, 0) + node T_191 = cat(T_189, T_190) + in_1.cmd := T_191 + when in.bits.swap23 : + in_1.in2 := one + skip + node T_192 = or(in.bits.ren3, in.bits.swap23) + node T_194 = eq(T_192, UInt<1>("h00")) + when T_194 : + in_1.in3 := zero + skip + skip + inst fma of mulAddSubRecodedFloatN + fma.roundingMode := UInt<1>("h00") + fma.c := UInt<1>("h00") + fma.b := UInt<1>("h00") + fma.a := UInt<1>("h00") + fma.op := UInt<1>("h00") + fma.reset := UInt<1>("h00") + fma.clock := clock + fma.reset := reset + fma.op := in_1.cmd + fma.roundingMode := in_1.rm + fma.a := in_1.in1 + fma.b := in_1.in2 + fma.c := in_1.in3 + wire res : {data : UInt<65>, exc : UInt<5>} + res.exc := UInt<1>("h00") + res.data := UInt<1>("h00") + res.data := fma.out + res.exc := fma.exceptionFlags + reg T_211 : UInt<1>, clock, reset + onreset T_211 := UInt<1>("h00") + T_211 := valid + reg T_212 : {data : UInt<65>, exc : UInt<5>}, clock, reset + when valid : + T_212 <> res + skip + wire T_223 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} + T_223.bits.exc := UInt<1>("h00") + T_223.bits.data := UInt<1>("h00") + T_223.valid := UInt<1>("h00") + T_223.valid := T_211 + T_223.bits <> T_212 + out <> T_223 + + module mulAddSubRecodedFloatN_71 : + output exceptionFlags : UInt<5> + output out : UInt<65> + input roundingMode : UInt<2> + input c : UInt<65> + input b : UInt<65> + input a : UInt<65> + input op : UInt<2> + input clock : Clock + input reset : UInt<1> + + exceptionFlags := UInt<1>("h00") + out := UInt<1>("h00") + node signA = bit(a, 64) + node expA = bits(a, 63, 52) + node fractA = bits(a, 51, 0) + node T_14 = bits(expA, 11, 9) + node isZeroA = eq(T_14, UInt<1>("h00")) + node T_17 = bits(expA, 11, 10) + node isSpecialA = eq(T_17, UInt<2>("h03")) + node T_20 = bit(expA, 9) + node T_22 = eq(T_20, UInt<1>("h00")) + node isInfA = and(isSpecialA, T_22) + node T_24 = bit(expA, 9) + node isNaNA = and(isSpecialA, T_24) + node T_26 = bit(fractA, 51) + node T_28 = eq(T_26, UInt<1>("h00")) + node isSigNaNA = and(isNaNA, T_28) + node T_31 = eq(isZeroA, UInt<1>("h00")) + node sigA = cat(T_31, fractA) + node signB = bit(b, 64) + node expB = bits(b, 63, 52) + node fractB = bits(b, 51, 0) + node T_36 = bits(expB, 11, 9) + node isZeroB = eq(T_36, UInt<1>("h00")) + node T_39 = bits(expB, 11, 10) + node isSpecialB = eq(T_39, UInt<2>("h03")) + node T_42 = bit(expB, 9) + node T_44 = eq(T_42, UInt<1>("h00")) + node isInfB = and(isSpecialB, T_44) + node T_46 = bit(expB, 9) + node isNaNB = and(isSpecialB, T_46) + node T_48 = bit(fractB, 51) + node T_50 = eq(T_48, UInt<1>("h00")) + node isSigNaNB = and(isNaNB, T_50) + node T_53 = eq(isZeroB, UInt<1>("h00")) + node sigB = cat(T_53, fractB) + node T_55 = bit(c, 64) + node T_56 = bit(op, 0) + node opSignC = xor(T_55, T_56) + node expC = bits(c, 63, 52) + node fractC = bits(c, 51, 0) + node T_60 = bits(expC, 11, 9) + node isZeroC = eq(T_60, UInt<1>("h00")) + node T_63 = bits(expC, 11, 10) + node isSpecialC = eq(T_63, UInt<2>("h03")) + node T_66 = bit(expC, 9) + node T_68 = eq(T_66, UInt<1>("h00")) + node isInfC = and(isSpecialC, T_68) + node T_70 = bit(expC, 9) + node isNaNC = and(isSpecialC, T_70) + node T_72 = bit(fractC, 51) + node T_74 = eq(T_72, UInt<1>("h00")) + node isSigNaNC = and(isNaNC, T_74) + node T_77 = eq(isZeroC, UInt<1>("h00")) + node sigC = cat(T_77, fractC) + node roundingMode_nearest_even = eq(roundingMode, UInt<2>("h00")) + node roundingMode_minMag = eq(roundingMode, UInt<2>("h01")) + node roundingMode_min = eq(roundingMode, UInt<2>("h02")) + node roundingMode_max = eq(roundingMode, UInt<2>("h03")) + node T_83 = xor(signA, signB) + node T_84 = bit(op, 1) + node signProd = xor(T_83, T_84) + node isZeroProd = or(isZeroA, isZeroB) + node T_87 = bit(expB, 11) + node T_89 = eq(T_87, UInt<1>("h00")) + node T_91 = subw(UInt<3>("h00"), T_89) + node T_92 = bits(expB, 10, 0) + node T_93 = cat(T_91, T_92) + node T_94 = addw(T_93, expA) + node sExpAlignedProd = addw(T_94, UInt<6>("h038")) + node doSubMags = xor(signProd, opSignC) + node sNatCAlignDist = subw(sExpAlignedProd, expC) + node T_99 = bit(sNatCAlignDist, 13) + node CAlignDist_floor = or(isZeroProd, T_99) + node T_101 = bits(sNatCAlignDist, 12, 0) + node T_103 = eq(T_101, UInt<1>("h00")) + node CAlignDist_0 = or(CAlignDist_floor, T_103) + node T_106 = eq(isZeroC, UInt<1>("h00")) + node T_107 = bits(sNatCAlignDist, 12, 0) + node T_109 = lt(T_107, UInt<6>("h036")) + node T_110 = or(CAlignDist_floor, T_109) + node isCDominant = and(T_106, T_110) + node T_113 = bits(sNatCAlignDist, 12, 0) + node T_115 = lt(T_113, UInt<8>("h0a1")) + node T_117 = mux(T_115, sNatCAlignDist, UInt<8>("h0a1")) + node T_118 = mux(CAlignDist_floor, UInt<1>("h00"), T_117) + node CAlignDist = bits(T_118, 7, 0) + node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) + node T_122 = dshr(asSInt(UInt<257>("h010000000000000000000000000000000000000000000000000000000000000000")), CAlignDist) + node T_123 = bits(T_122, 147, 95) + node T_124 = bits(T_123, 31, 0) + node T_127 = shl(UInt<16>("h0ffff"), 16) + node T_128 = xor(UInt<32>("h0ffffffff"), T_127) + node T_129 = shr(T_124, 16) + node T_130 = and(T_129, T_128) + node T_131 = bits(T_124, 15, 0) + node T_132 = shl(T_131, 16) + node T_133 = not(T_128) + node T_134 = and(T_132, T_133) + node T_135 = or(T_130, T_134) + node T_136 = bits(T_128, 23, 0) + node T_137 = shl(T_136, 8) + node T_138 = xor(T_128, T_137) + node T_139 = shr(T_135, 8) + node T_140 = and(T_139, T_138) + node T_141 = bits(T_135, 23, 0) + node T_142 = shl(T_141, 8) + node T_143 = not(T_138) + node T_144 = and(T_142, T_143) + node T_145 = or(T_140, T_144) + node T_146 = bits(T_138, 27, 0) + node T_147 = shl(T_146, 4) + node T_148 = xor(T_138, T_147) + node T_149 = shr(T_145, 4) + node T_150 = and(T_149, T_148) + node T_151 = bits(T_145, 27, 0) + node T_152 = shl(T_151, 4) + node T_153 = not(T_148) + node T_154 = and(T_152, T_153) + node T_155 = or(T_150, T_154) + node T_156 = bits(T_148, 29, 0) + node T_157 = shl(T_156, 2) + node T_158 = xor(T_148, T_157) + node T_159 = shr(T_155, 2) + node T_160 = and(T_159, T_158) + node T_161 = bits(T_155, 29, 0) + node T_162 = shl(T_161, 2) + node T_163 = not(T_158) + node T_164 = and(T_162, T_163) + node T_165 = or(T_160, T_164) + node T_166 = bits(T_158, 30, 0) + node T_167 = shl(T_166, 1) + node T_168 = xor(T_158, T_167) + node T_169 = shr(T_165, 1) + node T_170 = and(T_169, T_168) + node T_171 = bits(T_165, 30, 0) + node T_172 = shl(T_171, 1) + node T_173 = not(T_168) + node T_174 = and(T_172, T_173) + node T_175 = or(T_170, T_174) + node T_176 = bits(T_123, 52, 32) + node T_177 = bits(T_176, 15, 0) + node T_180 = shl(UInt<8>("h0ff"), 8) + node T_181 = xor(UInt<16>("h0ffff"), T_180) + node T_182 = shr(T_177, 8) + node T_183 = and(T_182, T_181) + node T_184 = bits(T_177, 7, 0) + node T_185 = shl(T_184, 8) + node T_186 = not(T_181) + node T_187 = and(T_185, T_186) + node T_188 = or(T_183, T_187) + node T_189 = bits(T_181, 11, 0) + node T_190 = shl(T_189, 4) + node T_191 = xor(T_181, T_190) + node T_192 = shr(T_188, 4) + node T_193 = and(T_192, T_191) + node T_194 = bits(T_188, 11, 0) + node T_195 = shl(T_194, 4) + node T_196 = not(T_191) + node T_197 = and(T_195, T_196) + node T_198 = or(T_193, T_197) + node T_199 = bits(T_191, 13, 0) + node T_200 = shl(T_199, 2) + node T_201 = xor(T_191, T_200) + node T_202 = shr(T_198, 2) + node T_203 = and(T_202, T_201) + node T_204 = bits(T_198, 13, 0) + node T_205 = shl(T_204, 2) + node T_206 = not(T_201) + node T_207 = and(T_205, T_206) + node T_208 = or(T_203, T_207) + node T_209 = bits(T_201, 14, 0) + node T_210 = shl(T_209, 1) + node T_211 = xor(T_201, T_210) + node T_212 = shr(T_208, 1) + node T_213 = and(T_212, T_211) + node T_214 = bits(T_208, 14, 0) + node T_215 = shl(T_214, 1) + node T_216 = not(T_211) + node T_217 = and(T_215, T_216) + node T_218 = or(T_213, T_217) + node T_219 = bits(T_176, 20, 16) + node T_220 = bits(T_219, 3, 0) + node T_221 = bits(T_220, 1, 0) + node T_222 = bits(T_221, 0, 0) + node T_223 = bits(T_221, 1, 1) + node T_224 = cat(T_222, T_223) + node T_225 = bits(T_220, 3, 2) + node T_226 = bits(T_225, 0, 0) + node T_227 = bits(T_225, 1, 1) + node T_228 = cat(T_226, T_227) + node T_229 = cat(T_224, T_228) + node T_230 = bits(T_219, 4, 4) + node T_231 = cat(T_229, T_230) + node T_232 = cat(T_218, T_231) + node CExtraMask = cat(T_175, T_232) + node T_234 = not(sigC) + node negSigC = mux(doSubMags, T_234, sigC) + node T_237 = subw(UInt<108>("h00"), doSubMags) + node T_238 = cat(negSigC, T_237) + node T_239 = cat(doSubMags, T_238) + node T_240 = asSInt(T_239) + node T_241 = dshr(T_240, CAlignDist) + node T_242 = and(sigC, CExtraMask) + node T_244 = neq(T_242, UInt<1>("h00")) + node T_245 = xor(T_244, doSubMags) + node T_246 = asUInt(T_241) + node T_247 = cat(T_246, T_245) + node alignedNegSigC = bits(T_247, 161, 0) + node T_249 = mul(sigA, sigB) + node T_250 = shl(T_249, 1) + node sigSum = addw(T_250, alignedNegSigC) + node T_253 = bits(sigSum, 108, 1) + node T_254 = xor(UInt<108>("h00"), T_253) + node T_255 = or(UInt<108>("h00"), T_253) + node T_256 = shl(T_255, 1) + node T_257 = xor(T_254, T_256) + node T_258 = bit(T_257, 107) + node T_260 = bit(T_257, 106) + node T_262 = bit(T_257, 105) + node T_264 = bit(T_257, 104) + node T_266 = bit(T_257, 103) + node T_268 = bit(T_257, 102) + node T_270 = bit(T_257, 101) + node T_272 = bit(T_257, 100) + node T_274 = bit(T_257, 99) + node T_276 = bit(T_257, 98) + node T_278 = bit(T_257, 97) + node T_280 = bit(T_257, 96) + node T_282 = bit(T_257, 95) + node T_284 = bit(T_257, 94) + node T_286 = bit(T_257, 93) + node T_288 = bit(T_257, 92) + node T_290 = bit(T_257, 91) + node T_292 = bit(T_257, 90) + node T_294 = bit(T_257, 89) + node T_296 = bit(T_257, 88) + node T_298 = bit(T_257, 87) + node T_300 = bit(T_257, 86) + node T_302 = bit(T_257, 85) + node T_304 = bit(T_257, 84) + node T_306 = bit(T_257, 83) + node T_308 = bit(T_257, 82) + node T_310 = bit(T_257, 81) + node T_312 = bit(T_257, 80) + node T_314 = bit(T_257, 79) + node T_316 = bit(T_257, 78) + node T_318 = bit(T_257, 77) + node T_320 = bit(T_257, 76) + node T_322 = bit(T_257, 75) + node T_324 = bit(T_257, 74) + node T_326 = bit(T_257, 73) + node T_328 = bit(T_257, 72) + node T_330 = bit(T_257, 71) + node T_332 = bit(T_257, 70) + node T_334 = bit(T_257, 69) + node T_336 = bit(T_257, 68) + node T_338 = bit(T_257, 67) + node T_340 = bit(T_257, 66) + node T_342 = bit(T_257, 65) + node T_344 = bit(T_257, 64) + node T_346 = bit(T_257, 63) + node T_348 = bit(T_257, 62) + node T_350 = bit(T_257, 61) + node T_352 = bit(T_257, 60) + node T_354 = bit(T_257, 59) + node T_356 = bit(T_257, 58) + node T_358 = bit(T_257, 57) + node T_360 = bit(T_257, 56) + node T_362 = bit(T_257, 55) + node T_364 = bit(T_257, 54) + node T_366 = bit(T_257, 53) + node T_368 = bit(T_257, 52) + node T_370 = bit(T_257, 51) + node T_372 = bit(T_257, 50) + node T_374 = bit(T_257, 49) + node T_376 = bit(T_257, 48) + node T_378 = bit(T_257, 47) + node T_380 = bit(T_257, 46) + node T_382 = bit(T_257, 45) + node T_384 = bit(T_257, 44) + node T_386 = bit(T_257, 43) + node T_388 = bit(T_257, 42) + node T_390 = bit(T_257, 41) + node T_392 = bit(T_257, 40) + node T_394 = bit(T_257, 39) + node T_396 = bit(T_257, 38) + node T_398 = bit(T_257, 37) + node T_400 = bit(T_257, 36) + node T_402 = bit(T_257, 35) + node T_404 = bit(T_257, 34) + node T_406 = bit(T_257, 33) + node T_408 = bit(T_257, 32) + node T_410 = bit(T_257, 31) + node T_412 = bit(T_257, 30) + node T_414 = bit(T_257, 29) + node T_416 = bit(T_257, 28) + node T_418 = bit(T_257, 27) + node T_420 = bit(T_257, 26) + node T_422 = bit(T_257, 25) + node T_424 = bit(T_257, 24) + node T_426 = bit(T_257, 23) + node T_428 = bit(T_257, 22) + node T_430 = bit(T_257, 21) + node T_432 = bit(T_257, 20) + node T_434 = bit(T_257, 19) + node T_436 = bit(T_257, 18) + node T_438 = bit(T_257, 17) + node T_440 = bit(T_257, 16) + node T_442 = bit(T_257, 15) + node T_444 = bit(T_257, 14) + node T_446 = bit(T_257, 13) + node T_448 = bit(T_257, 12) + node T_450 = bit(T_257, 11) + node T_452 = bit(T_257, 10) + node T_454 = bit(T_257, 9) + node T_456 = bit(T_257, 8) + node T_458 = bit(T_257, 7) + node T_460 = bit(T_257, 6) + node T_462 = bit(T_257, 5) + node T_464 = bit(T_257, 4) + node T_466 = bit(T_257, 3) + node T_468 = bit(T_257, 2) + node T_470 = bit(T_257, 1) + node T_472 = bit(T_257, 0) + node T_474 = mux(T_470, UInt<8>("h09f"), UInt<8>("h0a0")) + node T_475 = mux(T_468, UInt<8>("h09e"), T_474) + node T_476 = mux(T_466, UInt<8>("h09d"), T_475) + node T_477 = mux(T_464, UInt<8>("h09c"), T_476) + node T_478 = mux(T_462, UInt<8>("h09b"), T_477) + node T_479 = mux(T_460, UInt<8>("h09a"), T_478) + node T_480 = mux(T_458, UInt<8>("h099"), T_479) + node T_481 = mux(T_456, UInt<8>("h098"), T_480) + node T_482 = mux(T_454, UInt<8>("h097"), T_481) + node T_483 = mux(T_452, UInt<8>("h096"), T_482) + node T_484 = mux(T_450, UInt<8>("h095"), T_483) + node T_485 = mux(T_448, UInt<8>("h094"), T_484) + node T_486 = mux(T_446, UInt<8>("h093"), T_485) + node T_487 = mux(T_444, UInt<8>("h092"), T_486) + node T_488 = mux(T_442, UInt<8>("h091"), T_487) + node T_489 = mux(T_440, UInt<8>("h090"), T_488) + node T_490 = mux(T_438, UInt<8>("h08f"), T_489) + node T_491 = mux(T_436, UInt<8>("h08e"), T_490) + node T_492 = mux(T_434, UInt<8>("h08d"), T_491) + node T_493 = mux(T_432, UInt<8>("h08c"), T_492) + node T_494 = mux(T_430, UInt<8>("h08b"), T_493) + node T_495 = mux(T_428, UInt<8>("h08a"), T_494) + node T_496 = mux(T_426, UInt<8>("h089"), T_495) + node T_497 = mux(T_424, UInt<8>("h088"), T_496) + node T_498 = mux(T_422, UInt<8>("h087"), T_497) + node T_499 = mux(T_420, UInt<8>("h086"), T_498) + node T_500 = mux(T_418, UInt<8>("h085"), T_499) + node T_501 = mux(T_416, UInt<8>("h084"), T_500) + node T_502 = mux(T_414, UInt<8>("h083"), T_501) + node T_503 = mux(T_412, UInt<8>("h082"), T_502) + node T_504 = mux(T_410, UInt<8>("h081"), T_503) + node T_505 = mux(T_408, UInt<8>("h080"), T_504) + node T_506 = mux(T_406, UInt<8>("h07f"), T_505) + node T_507 = mux(T_404, UInt<8>("h07e"), T_506) + node T_508 = mux(T_402, UInt<8>("h07d"), T_507) + node T_509 = mux(T_400, UInt<8>("h07c"), T_508) + node T_510 = mux(T_398, UInt<8>("h07b"), T_509) + node T_511 = mux(T_396, UInt<8>("h07a"), T_510) + node T_512 = mux(T_394, UInt<8>("h079"), T_511) + node T_513 = mux(T_392, UInt<8>("h078"), T_512) + node T_514 = mux(T_390, UInt<8>("h077"), T_513) + node T_515 = mux(T_388, UInt<8>("h076"), T_514) + node T_516 = mux(T_386, UInt<8>("h075"), T_515) + node T_517 = mux(T_384, UInt<8>("h074"), T_516) + node T_518 = mux(T_382, UInt<8>("h073"), T_517) + node T_519 = mux(T_380, UInt<8>("h072"), T_518) + node T_520 = mux(T_378, UInt<8>("h071"), T_519) + node T_521 = mux(T_376, UInt<8>("h070"), T_520) + node T_522 = mux(T_374, UInt<8>("h06f"), T_521) + node T_523 = mux(T_372, UInt<8>("h06e"), T_522) + node T_524 = mux(T_370, UInt<8>("h06d"), T_523) + node T_525 = mux(T_368, UInt<8>("h06c"), T_524) + node T_526 = mux(T_366, UInt<8>("h06b"), T_525) + node T_527 = mux(T_364, UInt<8>("h06a"), T_526) + node T_528 = mux(T_362, UInt<8>("h069"), T_527) + node T_529 = mux(T_360, UInt<8>("h068"), T_528) + node T_530 = mux(T_358, UInt<8>("h067"), T_529) + node T_531 = mux(T_356, UInt<8>("h066"), T_530) + node T_532 = mux(T_354, UInt<8>("h065"), T_531) + node T_533 = mux(T_352, UInt<8>("h064"), T_532) + node T_534 = mux(T_350, UInt<8>("h063"), T_533) + node T_535 = mux(T_348, UInt<8>("h062"), T_534) + node T_536 = mux(T_346, UInt<8>("h061"), T_535) + node T_537 = mux(T_344, UInt<8>("h060"), T_536) + node T_538 = mux(T_342, UInt<8>("h05f"), T_537) + node T_539 = mux(T_340, UInt<8>("h05e"), T_538) + node T_540 = mux(T_338, UInt<8>("h05d"), T_539) + node T_541 = mux(T_336, UInt<8>("h05c"), T_540) + node T_542 = mux(T_334, UInt<8>("h05b"), T_541) + node T_543 = mux(T_332, UInt<8>("h05a"), T_542) + node T_544 = mux(T_330, UInt<8>("h059"), T_543) + node T_545 = mux(T_328, UInt<8>("h058"), T_544) + node T_546 = mux(T_326, UInt<8>("h057"), T_545) + node T_547 = mux(T_324, UInt<8>("h056"), T_546) + node T_548 = mux(T_322, UInt<8>("h055"), T_547) + node T_549 = mux(T_320, UInt<8>("h054"), T_548) + node T_550 = mux(T_318, UInt<8>("h053"), T_549) + node T_551 = mux(T_316, UInt<8>("h052"), T_550) + node T_552 = mux(T_314, UInt<8>("h051"), T_551) + node T_553 = mux(T_312, UInt<8>("h050"), T_552) + node T_554 = mux(T_310, UInt<8>("h04f"), T_553) + node T_555 = mux(T_308, UInt<8>("h04e"), T_554) + node T_556 = mux(T_306, UInt<8>("h04d"), T_555) + node T_557 = mux(T_304, UInt<8>("h04c"), T_556) + node T_558 = mux(T_302, UInt<8>("h04b"), T_557) + node T_559 = mux(T_300, UInt<8>("h04a"), T_558) + node T_560 = mux(T_298, UInt<8>("h049"), T_559) + node T_561 = mux(T_296, UInt<8>("h048"), T_560) + node T_562 = mux(T_294, UInt<8>("h047"), T_561) + node T_563 = mux(T_292, UInt<8>("h046"), T_562) + node T_564 = mux(T_290, UInt<8>("h045"), T_563) + node T_565 = mux(T_288, UInt<8>("h044"), T_564) + node T_566 = mux(T_286, UInt<8>("h043"), T_565) + node T_567 = mux(T_284, UInt<8>("h042"), T_566) + node T_568 = mux(T_282, UInt<8>("h041"), T_567) + node T_569 = mux(T_280, UInt<8>("h040"), T_568) + node T_570 = mux(T_278, UInt<8>("h03f"), T_569) + node T_571 = mux(T_276, UInt<8>("h03e"), T_570) + node T_572 = mux(T_274, UInt<8>("h03d"), T_571) + node T_573 = mux(T_272, UInt<8>("h03c"), T_572) + node T_574 = mux(T_270, UInt<8>("h03b"), T_573) + node T_575 = mux(T_268, UInt<8>("h03a"), T_574) + node T_576 = mux(T_266, UInt<8>("h039"), T_575) + node T_577 = mux(T_264, UInt<8>("h038"), T_576) + node T_578 = mux(T_262, UInt<8>("h037"), T_577) + node T_579 = mux(T_260, UInt<8>("h036"), T_578) + node estNormPos_dist = mux(T_258, UInt<8>("h035"), T_579) + node T_581 = bits(sigSum, 75, 44) + node T_583 = neq(T_581, UInt<1>("h00")) + node T_584 = bits(sigSum, 43, 0) + node T_586 = neq(T_584, UInt<1>("h00")) + node firstReduceSigSum = cat(T_583, T_586) + node notSigSum = not(sigSum) + node T_589 = bits(notSigSum, 75, 44) + node T_591 = neq(T_589, UInt<1>("h00")) + node T_592 = bits(notSigSum, 43, 0) + node T_594 = neq(T_592, UInt<1>("h00")) + node firstReduceNotSigSum = cat(T_591, T_594) + node T_596 = or(CAlignDist_0, doSubMags) + node T_598 = subw(CAlignDist, UInt<1>("h01")) + node T_599 = bits(T_598, 5, 0) + node CDom_estNormDist = mux(T_596, CAlignDist, T_599) + node T_601 = not(doSubMags) + node T_602 = bit(CDom_estNormDist, 5) + node T_603 = not(T_602) + node T_604 = and(T_601, T_603) + node T_605 = asSInt(T_604) + node T_606 = bits(sigSum, 161, 76) + node T_608 = neq(firstReduceSigSum, UInt<1>("h00")) + node T_609 = cat(T_606, T_608) + node T_610 = asSInt(T_609) + node T_611 = and(T_605, T_610) + node T_612 = not(doSubMags) + node T_613 = bit(CDom_estNormDist, 5) + node T_614 = and(T_612, T_613) + node T_615 = asSInt(T_614) + node T_616 = bits(sigSum, 129, 44) + node T_617 = bit(firstReduceSigSum, 0) + node T_618 = cat(T_616, T_617) + node T_619 = asSInt(T_618) + node T_620 = and(T_615, T_619) + node T_621 = or(T_611, T_620) + node T_622 = bit(CDom_estNormDist, 5) + node T_623 = not(T_622) + node T_624 = and(doSubMags, T_623) + node T_625 = asSInt(T_624) + node T_626 = bits(notSigSum, 161, 76) + node T_628 = neq(firstReduceNotSigSum, UInt<1>("h00")) + node T_629 = cat(T_626, T_628) + node T_630 = asSInt(T_629) + node T_631 = and(T_625, T_630) + node T_632 = or(T_621, T_631) + node T_633 = bit(CDom_estNormDist, 5) + node T_634 = and(doSubMags, T_633) + node T_635 = asSInt(T_634) + node T_636 = bits(notSigSum, 129, 44) + node T_637 = bit(firstReduceNotSigSum, 0) + node T_638 = cat(T_636, T_637) + node T_639 = asSInt(T_638) + node T_640 = and(T_635, T_639) + node T_641 = or(T_632, T_640) + node CDom_firstNormAbsSigSum = asUInt(T_641) + node T_643 = bits(sigSum, 108, 44) + node T_644 = bit(firstReduceNotSigSum, 0) + node T_645 = not(T_644) + node T_646 = bit(firstReduceSigSum, 0) + node T_647 = mux(doSubMags, T_645, T_646) + node T_648 = cat(T_643, T_647) + node T_649 = bits(sigSum, 97, 1) + node T_650 = bit(estNormPos_dist, 4) + node T_651 = bits(sigSum, 1, 1) + node T_653 = subw(UInt<86>("h00"), doSubMags) + node T_654 = cat(T_651, T_653) + node T_655 = mux(T_650, T_648, T_654) + node T_656 = bits(sigSum, 97, 12) + node T_657 = bits(notSigSum, 11, 1) + node T_659 = eq(T_657, UInt<1>("h00")) + node T_660 = bits(sigSum, 11, 1) + node T_662 = neq(T_660, UInt<1>("h00")) + node T_663 = mux(doSubMags, T_659, T_662) + node T_664 = cat(T_656, T_663) + node T_665 = bit(estNormPos_dist, 6) + node T_666 = bit(estNormPos_dist, 5) + node T_667 = bits(sigSum, 65, 1) + node T_669 = subw(UInt<22>("h00"), doSubMags) + node T_670 = cat(T_667, T_669) + node T_671 = mux(T_666, T_670, T_664) + node T_672 = bit(estNormPos_dist, 5) + node T_673 = bits(sigSum, 33, 1) + node T_675 = subw(UInt<54>("h00"), doSubMags) + node T_676 = cat(T_673, T_675) + node T_677 = mux(T_672, T_655, T_676) + node notCDom_pos_firstNormAbsSigSum = mux(T_665, T_671, T_677) + node T_679 = bits(notSigSum, 107, 44) + node T_680 = bit(firstReduceNotSigSum, 0) + node T_681 = cat(T_679, T_680) + node T_682 = bits(notSigSum, 97, 1) + node T_683 = bit(estNormPos_dist, 4) + node T_684 = bits(notSigSum, 2, 1) + node T_685 = shl(T_684, 86) + node T_686 = mux(T_683, T_681, T_685) + node T_687 = bits(notSigSum, 98, 12) + node T_688 = bits(notSigSum, 11, 1) + node T_690 = neq(T_688, UInt<1>("h00")) + node T_691 = cat(T_687, T_690) + node T_692 = bit(estNormPos_dist, 6) + node T_693 = bit(estNormPos_dist, 5) + node T_694 = bits(notSigSum, 66, 1) + node T_695 = shl(T_694, 22) + node T_696 = mux(T_693, T_695, T_691) + node T_697 = bit(estNormPos_dist, 5) + node T_698 = bits(notSigSum, 34, 1) + node T_699 = shl(T_698, 54) + node T_700 = mux(T_697, T_686, T_699) + node notCDom_neg_cFirstNormAbsSigSum = mux(T_692, T_696, T_700) + node notCDom_signSigSum = bit(sigSum, 109) + node T_703 = not(isZeroC) + node T_704 = and(doSubMags, T_703) + node doNegSignSum = mux(isCDominant, T_704, notCDom_signSigSum) + node T_706 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) + node estNormDist = mux(isCDominant, CDom_estNormDist, T_706) + node T_708 = mux(isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) + node T_709 = mux(isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) + node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_708, T_709) + node T_711 = not(isCDominant) + node T_712 = not(notCDom_signSigSum) + node T_713 = and(T_711, T_712) + node doIncrSig = and(T_713, doSubMags) + node estNormDist_5 = bits(estNormDist, 4, 0) + node normTo2ShiftDist = not(estNormDist_5) + node T_718 = dshr(asSInt(UInt<33>("h0100000000")), normTo2ShiftDist) + node T_719 = bits(T_718, 31, 1) + node T_720 = bits(T_719, 15, 0) + node T_723 = shl(UInt<8>("h0ff"), 8) + node T_724 = xor(UInt<16>("h0ffff"), T_723) + node T_725 = shr(T_720, 8) + node T_726 = and(T_725, T_724) + node T_727 = bits(T_720, 7, 0) + node T_728 = shl(T_727, 8) + node T_729 = not(T_724) + node T_730 = and(T_728, T_729) + node T_731 = or(T_726, T_730) + node T_732 = bits(T_724, 11, 0) + node T_733 = shl(T_732, 4) + node T_734 = xor(T_724, T_733) + node T_735 = shr(T_731, 4) + node T_736 = and(T_735, T_734) + node T_737 = bits(T_731, 11, 0) + node T_738 = shl(T_737, 4) + node T_739 = not(T_734) + node T_740 = and(T_738, T_739) + node T_741 = or(T_736, T_740) + node T_742 = bits(T_734, 13, 0) + node T_743 = shl(T_742, 2) + node T_744 = xor(T_734, T_743) + node T_745 = shr(T_741, 2) + node T_746 = and(T_745, T_744) + node T_747 = bits(T_741, 13, 0) + node T_748 = shl(T_747, 2) + node T_749 = not(T_744) + node T_750 = and(T_748, T_749) + node T_751 = or(T_746, T_750) + node T_752 = bits(T_744, 14, 0) + node T_753 = shl(T_752, 1) + node T_754 = xor(T_744, T_753) + node T_755 = shr(T_751, 1) + node T_756 = and(T_755, T_754) + node T_757 = bits(T_751, 14, 0) + node T_758 = shl(T_757, 1) + node T_759 = not(T_754) + node T_760 = and(T_758, T_759) + node T_761 = or(T_756, T_760) + node T_762 = bits(T_719, 30, 16) + node T_763 = bits(T_762, 7, 0) + node T_766 = shl(UInt<4>("h0f"), 4) + node T_767 = xor(UInt<8>("h0ff"), T_766) + node T_768 = shr(T_763, 4) + node T_769 = and(T_768, T_767) + node T_770 = bits(T_763, 3, 0) + node T_771 = shl(T_770, 4) + node T_772 = not(T_767) + node T_773 = and(T_771, T_772) + node T_774 = or(T_769, T_773) + node T_775 = bits(T_767, 5, 0) + node T_776 = shl(T_775, 2) + node T_777 = xor(T_767, T_776) + node T_778 = shr(T_774, 2) + node T_779 = and(T_778, T_777) + node T_780 = bits(T_774, 5, 0) + node T_781 = shl(T_780, 2) + node T_782 = not(T_777) + node T_783 = and(T_781, T_782) + node T_784 = or(T_779, T_783) + node T_785 = bits(T_777, 6, 0) + node T_786 = shl(T_785, 1) + node T_787 = xor(T_777, T_786) + node T_788 = shr(T_784, 1) + node T_789 = and(T_788, T_787) + node T_790 = bits(T_784, 6, 0) + node T_791 = shl(T_790, 1) + node T_792 = not(T_787) + node T_793 = and(T_791, T_792) + node T_794 = or(T_789, T_793) + node T_795 = bits(T_762, 14, 8) + node T_796 = bits(T_795, 3, 0) + node T_797 = bits(T_796, 1, 0) + node T_798 = bits(T_797, 0, 0) + node T_799 = bits(T_797, 1, 1) + node T_800 = cat(T_798, T_799) + node T_801 = bits(T_796, 3, 2) + node T_802 = bits(T_801, 0, 0) + node T_803 = bits(T_801, 1, 1) + node T_804 = cat(T_802, T_803) + node T_805 = cat(T_800, T_804) + node T_806 = bits(T_795, 6, 4) + node T_807 = bits(T_806, 1, 0) + node T_808 = bits(T_807, 0, 0) + node T_809 = bits(T_807, 1, 1) + node T_810 = cat(T_808, T_809) + node T_811 = bits(T_806, 2, 2) + node T_812 = cat(T_810, T_811) + node T_813 = cat(T_805, T_812) + node T_814 = cat(T_794, T_813) + node T_815 = cat(T_761, T_814) + node absSigSumExtraMask = cat(T_815, UInt<1>("h01")) + node T_818 = bits(cFirstNormAbsSigSum, 87, 1) + node T_819 = dshr(T_818, normTo2ShiftDist) + node T_820 = bits(cFirstNormAbsSigSum, 31, 0) + node T_821 = not(T_820) + node T_822 = and(T_821, absSigSumExtraMask) + node T_824 = eq(T_822, UInt<1>("h00")) + node T_825 = bits(cFirstNormAbsSigSum, 31, 0) + node T_826 = and(T_825, absSigSumExtraMask) + node T_828 = neq(T_826, UInt<1>("h00")) + node T_829 = mux(doIncrSig, T_824, T_828) + node T_830 = cat(T_819, T_829) + node sigX3 = bits(T_830, 56, 0) + node T_832 = bits(sigX3, 56, 55) + node sigX3Shift1 = eq(T_832, UInt<1>("h00")) + node sExpX3 = subw(sExpSum, estNormDist) + node T_836 = bits(sigX3, 56, 54) + node isZeroY = eq(T_836, UInt<1>("h00")) + node T_839 = not(isZeroY) + node T_840 = xor(signProd, doNegSignSum) + node signY = and(T_839, T_840) + node sExpX3_13 = bits(sExpX3, 12, 0) + node T_843 = bit(sExpX3, 13) + node T_845 = subw(UInt<56>("h00"), T_843) + node T_846 = not(sExpX3_13) + node T_848 = dshr(asSInt(UInt<8193>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_846) + node T_849 = bits(T_848, 1027, 974) + node T_850 = bits(T_849, 31, 0) + node T_853 = shl(UInt<16>("h0ffff"), 16) + node T_854 = xor(UInt<32>("h0ffffffff"), T_853) + node T_855 = shr(T_850, 16) + node T_856 = and(T_855, T_854) + node T_857 = bits(T_850, 15, 0) + node T_858 = shl(T_857, 16) + node T_859 = not(T_854) + node T_860 = and(T_858, T_859) + node T_861 = or(T_856, T_860) + node T_862 = bits(T_854, 23, 0) + node T_863 = shl(T_862, 8) + node T_864 = xor(T_854, T_863) + node T_865 = shr(T_861, 8) + node T_866 = and(T_865, T_864) + node T_867 = bits(T_861, 23, 0) + node T_868 = shl(T_867, 8) + node T_869 = not(T_864) + node T_870 = and(T_868, T_869) + node T_871 = or(T_866, T_870) + node T_872 = bits(T_864, 27, 0) + node T_873 = shl(T_872, 4) + node T_874 = xor(T_864, T_873) + node T_875 = shr(T_871, 4) + node T_876 = and(T_875, T_874) + node T_877 = bits(T_871, 27, 0) + node T_878 = shl(T_877, 4) + node T_879 = not(T_874) + node T_880 = and(T_878, T_879) + node T_881 = or(T_876, T_880) + node T_882 = bits(T_874, 29, 0) + node T_883 = shl(T_882, 2) + node T_884 = xor(T_874, T_883) + node T_885 = shr(T_881, 2) + node T_886 = and(T_885, T_884) + node T_887 = bits(T_881, 29, 0) + node T_888 = shl(T_887, 2) + node T_889 = not(T_884) + node T_890 = and(T_888, T_889) + node T_891 = or(T_886, T_890) + node T_892 = bits(T_884, 30, 0) + node T_893 = shl(T_892, 1) + node T_894 = xor(T_884, T_893) + node T_895 = shr(T_891, 1) + node T_896 = and(T_895, T_894) + node T_897 = bits(T_891, 30, 0) + node T_898 = shl(T_897, 1) + node T_899 = not(T_894) + node T_900 = and(T_898, T_899) + node T_901 = or(T_896, T_900) + node T_902 = bits(T_849, 53, 32) + node T_903 = bits(T_902, 15, 0) + node T_906 = shl(UInt<8>("h0ff"), 8) + node T_907 = xor(UInt<16>("h0ffff"), T_906) + node T_908 = shr(T_903, 8) + node T_909 = and(T_908, T_907) + node T_910 = bits(T_903, 7, 0) + node T_911 = shl(T_910, 8) + node T_912 = not(T_907) + node T_913 = and(T_911, T_912) + node T_914 = or(T_909, T_913) + node T_915 = bits(T_907, 11, 0) + node T_916 = shl(T_915, 4) + node T_917 = xor(T_907, T_916) + node T_918 = shr(T_914, 4) + node T_919 = and(T_918, T_917) + node T_920 = bits(T_914, 11, 0) + node T_921 = shl(T_920, 4) + node T_922 = not(T_917) + node T_923 = and(T_921, T_922) + node T_924 = or(T_919, T_923) + node T_925 = bits(T_917, 13, 0) + node T_926 = shl(T_925, 2) + node T_927 = xor(T_917, T_926) + node T_928 = shr(T_924, 2) + node T_929 = and(T_928, T_927) + node T_930 = bits(T_924, 13, 0) + node T_931 = shl(T_930, 2) + node T_932 = not(T_927) + node T_933 = and(T_931, T_932) + node T_934 = or(T_929, T_933) + node T_935 = bits(T_927, 14, 0) + node T_936 = shl(T_935, 1) + node T_937 = xor(T_927, T_936) + node T_938 = shr(T_934, 1) + node T_939 = and(T_938, T_937) + node T_940 = bits(T_934, 14, 0) + node T_941 = shl(T_940, 1) + node T_942 = not(T_937) + node T_943 = and(T_941, T_942) + node T_944 = or(T_939, T_943) + node T_945 = bits(T_902, 21, 16) + node T_946 = bits(T_945, 3, 0) + node T_947 = bits(T_946, 1, 0) + node T_948 = bits(T_947, 0, 0) + node T_949 = bits(T_947, 1, 1) + node T_950 = cat(T_948, T_949) + node T_951 = bits(T_946, 3, 2) + node T_952 = bits(T_951, 0, 0) + node T_953 = bits(T_951, 1, 1) + node T_954 = cat(T_952, T_953) + node T_955 = cat(T_950, T_954) + node T_956 = bits(T_945, 5, 4) + node T_957 = bits(T_956, 0, 0) + node T_958 = bits(T_956, 1, 1) + node T_959 = cat(T_957, T_958) + node T_960 = cat(T_955, T_959) + node T_961 = cat(T_944, T_960) + node T_962 = cat(T_901, T_961) + node T_963 = bit(sigX3, 55) + node T_964 = or(T_962, T_963) + node T_966 = cat(T_964, UInt<2>("h03")) + node roundMask = or(T_845, T_966) + node T_968 = shr(roundMask, 1) + node T_969 = not(T_968) + node roundPosMask = and(T_969, roundMask) + node T_971 = and(sigX3, roundPosMask) + node roundPosBit = neq(T_971, UInt<1>("h00")) + node T_974 = shr(roundMask, 1) + node T_975 = and(sigX3, T_974) + node anyRoundExtra = neq(T_975, UInt<1>("h00")) + node T_978 = not(sigX3) + node T_979 = shr(roundMask, 1) + node T_980 = and(T_978, T_979) + node allRoundExtra = eq(T_980, UInt<1>("h00")) + node anyRound = or(roundPosBit, anyRoundExtra) + node allRound = and(roundPosBit, allRoundExtra) + node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) + node T_986 = not(doIncrSig) + node T_987 = and(T_986, roundingMode_nearest_even) + node T_988 = and(T_987, roundPosBit) + node T_989 = and(T_988, anyRoundExtra) + node T_990 = not(doIncrSig) + node T_991 = and(T_990, roundDirectUp) + node T_992 = and(T_991, anyRound) + node T_993 = or(T_989, T_992) + node T_994 = and(doIncrSig, allRound) + node T_995 = or(T_993, T_994) + node T_996 = and(doIncrSig, roundingMode_nearest_even) + node T_997 = and(T_996, roundPosBit) + node T_998 = or(T_995, T_997) + node T_999 = and(doIncrSig, roundDirectUp) + node roundUp = or(T_998, T_999) + node T_1001 = not(roundPosBit) + node T_1002 = and(roundingMode_nearest_even, T_1001) + node T_1003 = and(T_1002, allRoundExtra) + node T_1004 = and(roundingMode_nearest_even, roundPosBit) + node T_1005 = not(anyRoundExtra) + node T_1006 = and(T_1004, T_1005) + node roundEven = mux(doIncrSig, T_1003, T_1006) + node T_1008 = not(allRound) + node roundInexact = mux(doIncrSig, T_1008, anyRound) + node T_1010 = or(sigX3, roundMask) + node T_1011 = shr(T_1010, 2) + node T_1013 = addw(T_1011, UInt<1>("h01")) + node roundUp_sigY3 = bits(T_1013, 54, 0) + node T_1015 = not(roundUp) + node T_1016 = not(roundEven) + node T_1017 = and(T_1015, T_1016) + node T_1018 = not(roundMask) + node T_1019 = and(sigX3, T_1018) + node T_1020 = shr(T_1019, 2) + node T_1022 = mux(T_1017, T_1020, UInt<1>("h00")) + node T_1024 = mux(roundUp, roundUp_sigY3, UInt<1>("h00")) + node T_1025 = or(T_1022, T_1024) + node T_1026 = shr(roundMask, 1) + node T_1027 = not(T_1026) + node T_1028 = and(roundUp_sigY3, T_1027) + node T_1030 = mux(roundEven, T_1028, UInt<1>("h00")) + node sigY3 = or(T_1025, T_1030) + node T_1032 = bit(sigY3, 54) + node T_1034 = addw(sExpX3, UInt<1>("h01")) + node T_1036 = mux(T_1032, T_1034, UInt<1>("h00")) + node T_1037 = bit(sigY3, 53) + node T_1039 = mux(T_1037, sExpX3, UInt<1>("h00")) + node T_1040 = or(T_1036, T_1039) + node T_1041 = bits(sigY3, 54, 53) + node T_1043 = eq(T_1041, UInt<1>("h00")) + node T_1045 = subw(sExpX3, UInt<1>("h01")) + node T_1047 = mux(T_1043, T_1045, UInt<1>("h00")) + node sExpY = or(T_1040, T_1047) + node expY = bits(sExpY, 11, 0) + node T_1050 = bits(sigY3, 51, 0) + node T_1051 = bits(sigY3, 52, 1) + node fractY = mux(sigX3Shift1, T_1050, T_1051) + node T_1053 = bits(sExpY, 12, 10) + node overflowY = eq(T_1053, UInt<2>("h03")) + node T_1056 = bit(sExpY, 12) + node T_1057 = bits(sExpY, 11, 0) + node T_1059 = lt(T_1057, UInt<10>("h03ce")) + node totalUnderflowY = or(T_1056, T_1059) + node T_1061 = bit(sExpX3, 13) + node T_1064 = mux(sigX3Shift1, UInt<11>("h0402"), UInt<11>("h0401")) + node T_1065 = leq(sExpX3_13, T_1064) + node T_1066 = or(T_1061, T_1065) + node underflowY = and(roundInexact, T_1066) + node T_1068 = and(roundingMode_min, signY) + node T_1069 = or(roundingMode_nearest_even, T_1068) + node T_1070 = not(signY) + node T_1071 = and(roundingMode_max, T_1070) + node overflowY_roundMagUp = or(T_1069, T_1071) + node mulSpecial = or(isSpecialA, isSpecialB) + node addSpecial = or(mulSpecial, isSpecialC) + node notSpecial_addZeros = and(isZeroProd, isZeroC) + node T_1076 = not(addSpecial) + node T_1077 = not(notSpecial_addZeros) + node commonCase = and(T_1076, T_1077) + node T_1079 = and(isInfA, isZeroB) + node T_1080 = and(isZeroA, isInfB) + node T_1081 = or(T_1079, T_1080) + node T_1082 = not(isNaNA) + node T_1083 = not(isNaNB) + node T_1084 = and(T_1082, T_1083) + node T_1085 = or(isInfA, isInfB) + node T_1086 = and(T_1084, T_1085) + node T_1087 = and(T_1086, isInfC) + node T_1088 = and(T_1087, doSubMags) + node notSigNaN_invalid = or(T_1081, T_1088) + node T_1090 = or(isSigNaNA, isSigNaNB) + node T_1091 = or(T_1090, isSigNaNC) + node invalid = or(T_1091, notSigNaN_invalid) + node overflow = and(commonCase, overflowY) + node underflow = and(commonCase, underflowY) + node T_1095 = and(commonCase, roundInexact) + node inexact = or(overflow, T_1095) + node T_1097 = or(notSpecial_addZeros, isZeroY) + node notSpecial_isZeroOut = or(T_1097, totalUnderflowY) + node T_1099 = not(overflowY_roundMagUp) + node isSatOut = and(overflow, T_1099) + node T_1101 = or(isInfA, isInfB) + node T_1102 = or(T_1101, isInfC) + node T_1103 = and(overflow, overflowY_roundMagUp) + node notNaN_isInfOut = or(T_1102, T_1103) + node T_1105 = or(isNaNA, isNaNB) + node T_1106 = or(T_1105, isNaNC) + node isNaNOut = or(T_1106, notSigNaN_invalid) + node T_1109 = eq(doSubMags, UInt<1>("h00")) + node T_1110 = and(T_1109, opSignC) + node T_1112 = and(isNaNOut, UInt<1>("h01")) + node T_1113 = or(T_1110, T_1112) + node T_1115 = eq(isSpecialC, UInt<1>("h00")) + node T_1116 = and(mulSpecial, T_1115) + node T_1117 = and(T_1116, signProd) + node T_1118 = or(T_1113, T_1117) + node T_1120 = eq(mulSpecial, UInt<1>("h00")) + node T_1121 = and(T_1120, isSpecialC) + node T_1122 = and(T_1121, opSignC) + node T_1123 = or(T_1118, T_1122) + node T_1125 = eq(mulSpecial, UInt<1>("h00")) + node T_1126 = and(T_1125, notSpecial_addZeros) + node T_1127 = and(T_1126, doSubMags) + node T_1129 = and(T_1127, UInt<1>("h00")) + node T_1130 = or(T_1123, T_1129) + node T_1131 = and(commonCase, signY) + node signOut = or(T_1130, T_1131) + node T_1135 = mux(notSpecial_isZeroOut, UInt<12>("h0e00"), UInt<12>("h00")) + node T_1136 = not(T_1135) + node T_1137 = and(expY, T_1136) + node T_1140 = mux(isSatOut, UInt<11>("h0400"), UInt<12>("h00")) + node T_1141 = not(T_1140) + node T_1142 = and(T_1137, T_1141) + node T_1145 = mux(notNaN_isInfOut, UInt<10>("h0200"), UInt<12>("h00")) + node T_1146 = not(T_1145) + node T_1147 = and(T_1142, T_1146) + node T_1150 = mux(isSatOut, UInt<12>("h0bff"), UInt<12>("h00")) + node T_1151 = or(T_1147, T_1150) + node T_1154 = mux(notNaN_isInfOut, UInt<12>("h0c00"), UInt<12>("h00")) + node T_1155 = or(T_1151, T_1154) + node T_1158 = mux(isNaNOut, UInt<12>("h0e00"), UInt<12>("h00")) + node expOut = or(T_1155, T_1158) + node T_1160 = or(isNaNOut, isSatOut) + node T_1162 = subw(UInt<52>("h00"), T_1160) + node fractOut = or(fractY, T_1162) + node T_1164 = cat(expOut, fractOut) + node T_1165 = cat(signOut, T_1164) + out := T_1165 + node T_1167 = cat(invalid, UInt<1>("h00")) + node T_1168 = cat(underflow, inexact) + node T_1169 = cat(overflow, T_1168) + node T_1170 = cat(T_1167, T_1169) + exceptionFlags := T_1170 + + module FPUFMAPipe_70 : + output out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} + input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} + input clock : Clock + input reset : UInt<1> + + out.bits.exc := UInt<1>("h00") + out.bits.data := UInt<1>("h00") + out.valid := UInt<1>("h00") + node one = shl(UInt<1>("h01"), 63) + node T_136 = bit(in.bits.in1, 64) + node T_137 = bit(in.bits.in2, 64) + node T_138 = xor(T_136, T_137) + node zero = shl(T_138, 64) + reg valid : UInt<1>, clock, reset + valid := in.valid + reg in_1 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset + when in.valid : + in_1 <> in.bits + node T_187 = bit(in.bits.cmd, 1) + node T_188 = or(in.bits.ren3, in.bits.swap23) + node T_189 = and(T_187, T_188) + node T_190 = bit(in.bits.cmd, 0) + node T_191 = cat(T_189, T_190) + in_1.cmd := T_191 + when in.bits.swap23 : + in_1.in2 := one + skip + node T_192 = or(in.bits.ren3, in.bits.swap23) + node T_194 = eq(T_192, UInt<1>("h00")) + when T_194 : + in_1.in3 := zero + skip + skip + inst fma of mulAddSubRecodedFloatN_71 + fma.roundingMode := UInt<1>("h00") + fma.c := UInt<1>("h00") + fma.b := UInt<1>("h00") + fma.a := UInt<1>("h00") + fma.op := UInt<1>("h00") + fma.reset := UInt<1>("h00") + fma.clock := clock + fma.reset := reset + fma.op := in_1.cmd + fma.roundingMode := in_1.rm + fma.a := in_1.in1 + fma.b := in_1.in2 + fma.c := in_1.in3 + wire res : {data : UInt<65>, exc : UInt<5>} + res.exc := UInt<1>("h00") + res.data := UInt<1>("h00") + res.data := fma.out + res.exc := fma.exceptionFlags + reg T_211 : UInt<1>, clock, reset + onreset T_211 := UInt<1>("h00") + T_211 := valid + reg T_212 : {data : UInt<65>, exc : UInt<5>}, clock, reset + when valid : + T_212 <> res + skip + reg T_217 : UInt<1>, clock, reset + onreset T_217 := UInt<1>("h00") + T_217 := T_211 + reg T_218 : {data : UInt<65>, exc : UInt<5>}, clock, reset + when T_211 : + T_218 <> T_212 + skip + wire T_229 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} + T_229.bits.exc := UInt<1>("h00") + T_229.bits.data := UInt<1>("h00") + T_229.valid := UInt<1>("h00") + T_229.valid := T_217 + T_229.bits <> T_218 + out <> T_229 + + module recodedFloatNCompare : + output a_lt_b_invalid : UInt<1> + output a_eq_b_invalid : UInt<1> + output a_lt_b : UInt<1> + output a_eq_b : UInt<1> + input b : UInt<65> + input a : UInt<65> + input clock : Clock + input reset : UInt<1> + + a_lt_b_invalid := UInt<1>("h00") + a_eq_b_invalid := UInt<1>("h00") + a_lt_b := UInt<1>("h00") + a_eq_b := UInt<1>("h00") + node signA = bit(a, 64) + node expA = bits(a, 63, 52) + node sigA = bits(a, 51, 0) + node codeA = bits(expA, 11, 9) + node T_15 = neq(codeA, UInt<1>("h00")) + node isZeroA = eq(T_15, UInt<1>("h00")) + node T_18 = not(codeA) + node isNaNA = eq(T_18, UInt<1>("h00")) + node T_21 = bit(sigA, 51) + node T_23 = eq(T_21, UInt<1>("h00")) + node isSignalingNaNA = and(isNaNA, T_23) + node signB = bit(b, 64) + node expB = bits(b, 63, 52) + node sigB = bits(b, 51, 0) + node codeB = bits(expB, 11, 9) + node T_30 = neq(codeB, UInt<1>("h00")) + node isZeroB = eq(T_30, UInt<1>("h00")) + node T_33 = not(codeB) + node isNaNB = eq(T_33, UInt<1>("h00")) + node T_36 = bit(sigB, 51) + node T_38 = eq(T_36, UInt<1>("h00")) + node isSignalingNaNB = and(isNaNB, T_38) + node signEqual = eq(signA, signB) + node expEqual = eq(expA, expB) + node T_42 = eq(sigA, sigB) + node magEqual = and(expEqual, T_42) + node T_44 = lt(expA, expB) + node T_45 = lt(sigA, sigB) + node T_46 = and(expEqual, T_45) + node magLess = or(T_44, T_46) + node T_48 = or(isSignalingNaNA, isSignalingNaNB) + a_eq_b_invalid := T_48 + node T_49 = or(isNaNA, isNaNB) + a_lt_b_invalid := T_49 + node T_51 = eq(isNaNA, UInt<1>("h00")) + node T_52 = and(T_51, magEqual) + node T_53 = or(isZeroA, signEqual) + node T_54 = and(T_52, T_53) + a_eq_b := T_54 + node T_56 = eq(a_lt_b_invalid, UInt<1>("h00")) + node T_58 = eq(magLess, UInt<1>("h00")) + node T_59 = and(signA, T_58) + node T_61 = eq(magEqual, UInt<1>("h00")) + node T_62 = and(T_59, T_61) + node T_63 = and(isZeroA, isZeroB) + node T_65 = eq(T_63, UInt<1>("h00")) + node T_66 = mux(signA, T_65, magLess) + node T_67 = mux(signB, T_62, T_66) + node T_68 = and(T_56, T_67) + a_lt_b := T_68 + + module FPToInt : + output out : {valid : UInt<1>, bits : {lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}} + output as_double : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} + input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} + input clock : Clock + input reset : UInt<1> + + out.bits.exc := UInt<1>("h00") + out.bits.toint := UInt<1>("h00") + out.bits.store := UInt<1>("h00") + out.bits.lt := UInt<1>("h00") + out.valid := UInt<1>("h00") + as_double.in3 := UInt<1>("h00") + as_double.in2 := UInt<1>("h00") + as_double.in1 := UInt<1>("h00") + as_double.typ := UInt<1>("h00") + as_double.rm := UInt<1>("h00") + as_double.wflags := UInt<1>("h00") + as_double.round := UInt<1>("h00") + as_double.sqrt := UInt<1>("h00") + as_double.div := UInt<1>("h00") + as_double.fma := UInt<1>("h00") + as_double.fastpipe := UInt<1>("h00") + as_double.toint := UInt<1>("h00") + as_double.fromint := UInt<1>("h00") + as_double.single := UInt<1>("h00") + as_double.swap23 := UInt<1>("h00") + as_double.swap12 := UInt<1>("h00") + as_double.ren3 := UInt<1>("h00") + as_double.ren2 := UInt<1>("h00") + as_double.ren1 := UInt<1>("h00") + as_double.wen := UInt<1>("h00") + as_double.ldst := UInt<1>("h00") + as_double.cmd := UInt<1>("h00") + reg in_1 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset + reg valid : UInt<1>, clock, reset + valid := in.valid + when in.valid : + in_1 <> in.bits + node T_234 = eq(in.bits.ldst, UInt<1>("h00")) + node T_235 = and(in.bits.single, T_234) + node T_238 = and(in.bits.cmd, UInt<4>("h0c")) + node T_239 = eq(UInt<4>("h0c"), T_238) + node T_241 = eq(T_239, UInt<1>("h00")) + node T_242 = and(T_235, T_241) + when T_242 : + node T_244 = bit(in.bits.in1, 32) + node T_245 = bits(in.bits.in1, 22, 0) + node T_246 = bits(in.bits.in1, 31, 23) + node T_247 = bits(in.bits.in1, 31, 29) + node T_248 = bits(in.bits.in1, 30, 23) + node T_249 = not(T_247) + node T_251 = eq(T_249, UInt<1>("h00")) + node T_252 = bit(T_245, 22) + node T_254 = eq(T_252, UInt<1>("h00")) + node T_255 = and(T_251, T_254) + node T_257 = lt(T_247, UInt<1>("h01")) + node T_259 = lt(T_247, UInt<3>("h04")) + node T_261 = cat(UInt<3>("h07"), T_248) + node T_263 = lt(T_247, UInt<3>("h06")) + node T_265 = cat(UInt<4>("h08"), T_248) + node T_267 = lt(T_247, UInt<3>("h07")) + node T_270 = mux(T_267, UInt<12>("h0c00"), UInt<12>("h0e00")) + node T_271 = mux(T_263, T_265, T_270) + node T_272 = mux(T_259, T_261, T_271) + node T_273 = mux(T_257, T_248, T_272) + node T_275 = subw(UInt<52>("h00"), T_251) + node T_276 = shl(T_245, 29) + node T_277 = or(T_275, T_276) + node T_278 = cat(T_273, T_277) + node T_279 = cat(T_244, T_278) + node T_280 = shl(T_255, 4) + in_1.in1 := T_279 + node T_282 = bit(in.bits.in2, 32) + node T_283 = bits(in.bits.in2, 22, 0) + node T_284 = bits(in.bits.in2, 31, 23) + node T_285 = bits(in.bits.in2, 31, 29) + node T_286 = bits(in.bits.in2, 30, 23) + node T_287 = not(T_285) + node T_289 = eq(T_287, UInt<1>("h00")) + node T_290 = bit(T_283, 22) + node T_292 = eq(T_290, UInt<1>("h00")) + node T_293 = and(T_289, T_292) + node T_295 = lt(T_285, UInt<1>("h01")) + node T_297 = lt(T_285, UInt<3>("h04")) + node T_299 = cat(UInt<3>("h07"), T_286) + node T_301 = lt(T_285, UInt<3>("h06")) + node T_303 = cat(UInt<4>("h08"), T_286) + node T_305 = lt(T_285, UInt<3>("h07")) + node T_308 = mux(T_305, UInt<12>("h0c00"), UInt<12>("h0e00")) + node T_309 = mux(T_301, T_303, T_308) + node T_310 = mux(T_297, T_299, T_309) + node T_311 = mux(T_295, T_286, T_310) + node T_313 = subw(UInt<52>("h00"), T_289) + node T_314 = shl(T_283, 29) + node T_315 = or(T_313, T_314) + node T_316 = cat(T_311, T_315) + node T_317 = cat(T_282, T_316) + node T_318 = shl(T_293, 4) + in_1.in2 := T_317 + skip + skip + node T_319 = bit(in_1.in1, 32) + node T_320 = bits(in_1.in1, 31, 23) + node T_321 = bits(in_1.in1, 22, 0) + node T_322 = bits(T_320, 6, 0) + node T_324 = lt(T_322, UInt<2>("h02")) + node T_325 = bits(T_320, 8, 6) + node T_327 = eq(T_325, UInt<1>("h01")) + node T_328 = bits(T_320, 8, 7) + node T_330 = eq(T_328, UInt<1>("h01")) + node T_331 = and(T_330, T_324) + node T_332 = or(T_327, T_331) + node T_333 = bits(T_320, 8, 7) + node T_335 = eq(T_333, UInt<1>("h01")) + node T_337 = eq(T_324, UInt<1>("h00")) + node T_338 = and(T_335, T_337) + node T_339 = bits(T_320, 8, 7) + node T_341 = eq(T_339, UInt<2>("h02")) + node T_342 = or(T_338, T_341) + node T_343 = bits(T_320, 8, 7) + node T_345 = eq(T_343, UInt<2>("h03")) + node T_346 = bit(T_320, 6) + node T_347 = and(T_345, T_346) + node T_349 = bits(T_320, 4, 0) + node T_350 = subw(UInt<2>("h02"), T_349) + node T_352 = cat(UInt<1>("h01"), T_321) + node T_353 = dshr(T_352, T_350) + node T_354 = bits(T_353, 22, 0) + node T_355 = bits(T_320, 7, 0) + node T_357 = subw(T_355, UInt<8>("h081")) + node T_359 = subw(UInt<8>("h00"), T_345) + node T_360 = mux(T_342, T_357, T_359) + node T_361 = or(T_342, T_347) + node T_363 = mux(T_332, T_354, UInt<1>("h00")) + node T_364 = mux(T_361, T_321, T_363) + node T_365 = cat(T_360, T_364) + node unrec_s = cat(T_319, T_365) + node T_367 = bit(in_1.in1, 64) + node T_368 = bits(in_1.in1, 63, 52) + node T_369 = bits(in_1.in1, 51, 0) + node T_370 = bits(T_368, 9, 0) + node T_372 = lt(T_370, UInt<2>("h02")) + node T_373 = bits(T_368, 11, 9) + node T_375 = eq(T_373, UInt<1>("h01")) + node T_376 = bits(T_368, 11, 10) + node T_378 = eq(T_376, UInt<1>("h01")) + node T_379 = and(T_378, T_372) + node T_380 = or(T_375, T_379) + node T_381 = bits(T_368, 11, 10) + node T_383 = eq(T_381, UInt<1>("h01")) + node T_385 = eq(T_372, UInt<1>("h00")) + node T_386 = and(T_383, T_385) + node T_387 = bits(T_368, 11, 10) + node T_389 = eq(T_387, UInt<2>("h02")) + node T_390 = or(T_386, T_389) + node T_391 = bits(T_368, 11, 10) + node T_393 = eq(T_391, UInt<2>("h03")) + node T_394 = bit(T_368, 9) + node T_395 = and(T_393, T_394) + node T_397 = bits(T_368, 5, 0) + node T_398 = subw(UInt<2>("h02"), T_397) + node T_400 = cat(UInt<1>("h01"), T_369) + node T_401 = dshr(T_400, T_398) + node T_402 = bits(T_401, 51, 0) + node T_403 = bits(T_368, 10, 0) + node T_405 = subw(T_403, UInt<11>("h0401")) + node T_407 = subw(UInt<11>("h00"), T_393) + node T_408 = mux(T_390, T_405, T_407) + node T_409 = or(T_390, T_395) + node T_411 = mux(T_380, T_402, UInt<1>("h00")) + node T_412 = mux(T_409, T_369, T_411) + node T_413 = cat(T_408, T_412) + node unrec_d = cat(T_367, T_413) + node T_415 = bit(unrec_s, 31) + node T_417 = subw(UInt<32>("h00"), T_415) + node T_418 = cat(T_417, unrec_s) + node unrec_out = mux(in_1.single, T_418, unrec_d) + node T_420 = bit(in_1.in1, 32) + node T_421 = bits(in_1.in1, 31, 23) + node T_422 = bits(in_1.in1, 22, 0) + node T_423 = bits(T_421, 8, 6) + node T_424 = bits(T_423, 2, 1) + node T_426 = eq(T_424, UInt<2>("h03")) + node T_427 = bits(T_421, 6, 0) + node T_429 = lt(T_427, UInt<2>("h02")) + node T_431 = eq(T_423, UInt<1>("h01")) + node T_433 = eq(T_424, UInt<1>("h01")) + node T_434 = and(T_433, T_429) + node T_435 = or(T_431, T_434) + node T_437 = eq(T_424, UInt<1>("h01")) + node T_439 = eq(T_429, UInt<1>("h00")) + node T_440 = and(T_437, T_439) + node T_442 = eq(T_424, UInt<2>("h02")) + node T_443 = or(T_440, T_442) + node T_445 = eq(T_423, UInt<1>("h00")) + node T_446 = bit(T_421, 6) + node T_448 = eq(T_446, UInt<1>("h00")) + node T_449 = and(T_426, T_448) + node T_450 = not(T_423) + node T_452 = eq(T_450, UInt<1>("h00")) + node T_453 = bit(T_422, 22) + node T_455 = eq(T_453, UInt<1>("h00")) + node T_456 = and(T_452, T_455) + node T_457 = bit(T_422, 22) + node T_458 = and(T_452, T_457) + node T_460 = eq(T_420, UInt<1>("h00")) + node T_461 = and(T_449, T_460) + node T_463 = eq(T_420, UInt<1>("h00")) + node T_464 = and(T_443, T_463) + node T_466 = eq(T_420, UInt<1>("h00")) + node T_467 = and(T_435, T_466) + node T_469 = eq(T_420, UInt<1>("h00")) + node T_470 = and(T_445, T_469) + node T_471 = and(T_445, T_420) + node T_472 = and(T_435, T_420) + node T_473 = and(T_443, T_420) + node T_474 = and(T_449, T_420) + node T_475 = cat(T_458, T_456) + node T_476 = cat(T_464, T_467) + node T_477 = cat(T_461, T_476) + node T_478 = cat(T_475, T_477) + node T_479 = cat(T_470, T_471) + node T_480 = cat(T_473, T_474) + node T_481 = cat(T_472, T_480) + node T_482 = cat(T_479, T_481) + node classify_s = cat(T_478, T_482) + node T_484 = bit(in_1.in1, 64) + node T_485 = bits(in_1.in1, 63, 52) + node T_486 = bits(in_1.in1, 51, 0) + node T_487 = bits(T_485, 11, 9) + node T_488 = bits(T_487, 2, 1) + node T_490 = eq(T_488, UInt<2>("h03")) + node T_491 = bits(T_485, 9, 0) + node T_493 = lt(T_491, UInt<2>("h02")) + node T_495 = eq(T_487, UInt<1>("h01")) + node T_497 = eq(T_488, UInt<1>("h01")) + node T_498 = and(T_497, T_493) + node T_499 = or(T_495, T_498) + node T_501 = eq(T_488, UInt<1>("h01")) + node T_503 = eq(T_493, UInt<1>("h00")) + node T_504 = and(T_501, T_503) + node T_506 = eq(T_488, UInt<2>("h02")) + node T_507 = or(T_504, T_506) + node T_509 = eq(T_487, UInt<1>("h00")) + node T_510 = bit(T_485, 9) + node T_512 = eq(T_510, UInt<1>("h00")) + node T_513 = and(T_490, T_512) + node T_514 = not(T_487) + node T_516 = eq(T_514, UInt<1>("h00")) + node T_517 = bit(T_486, 51) + node T_519 = eq(T_517, UInt<1>("h00")) + node T_520 = and(T_516, T_519) + node T_521 = bit(T_486, 51) + node T_522 = and(T_516, T_521) + node T_524 = eq(T_484, UInt<1>("h00")) + node T_525 = and(T_513, T_524) + node T_527 = eq(T_484, UInt<1>("h00")) + node T_528 = and(T_507, T_527) + node T_530 = eq(T_484, UInt<1>("h00")) + node T_531 = and(T_499, T_530) + node T_533 = eq(T_484, UInt<1>("h00")) + node T_534 = and(T_509, T_533) + node T_535 = and(T_509, T_484) + node T_536 = and(T_499, T_484) + node T_537 = and(T_507, T_484) + node T_538 = and(T_513, T_484) + node T_539 = cat(T_522, T_520) + node T_540 = cat(T_528, T_531) + node T_541 = cat(T_525, T_540) + node T_542 = cat(T_539, T_541) + node T_543 = cat(T_534, T_535) + node T_544 = cat(T_537, T_538) + node T_545 = cat(T_536, T_544) + node T_546 = cat(T_543, T_545) + node classify_d = cat(T_542, T_546) + node classify_out = mux(in_1.single, classify_s, classify_d) + inst dcmp of recodedFloatNCompare + dcmp.b := UInt<1>("h00") + dcmp.a := UInt<1>("h00") + dcmp.reset := UInt<1>("h00") + dcmp.clock := clock + dcmp.reset := reset + dcmp.a := in_1.in1 + dcmp.b := in_1.in2 + node T_552 = not(in_1.rm) + node T_553 = cat(dcmp.a_lt_b, dcmp.a_eq_b) + node T_554 = and(T_552, T_553) + node dcmp_out = neq(T_554, UInt<1>("h00")) + node T_557 = not(in_1.rm) + node T_558 = cat(dcmp.a_lt_b_invalid, dcmp.a_eq_b_invalid) + node T_559 = and(T_557, T_558) + node T_561 = neq(T_559, UInt<1>("h00")) + node dcmp_exc = shl(T_561, 4) + node T_564 = xor(in_1.typ, UInt<1>("h01")) + node T_565 = bit(in_1.in1, 64) + node T_566 = bits(in_1.in1, 63, 52) + node T_567 = bits(in_1.in1, 51, 0) + node T_568 = bits(T_566, 10, 0) + node T_569 = not(T_568) + node T_571 = eq(T_569, UInt<1>("h00")) + node T_573 = eq(T_571, UInt<1>("h00")) + node T_574 = bit(T_566, 11) + node T_576 = eq(T_574, UInt<1>("h00")) + node T_577 = bits(T_566, 11, 9) + node T_579 = eq(T_577, UInt<1>("h00")) + node T_580 = bits(T_566, 11, 10) + node T_581 = not(T_580) + node T_583 = eq(T_581, UInt<1>("h00")) + node T_585 = bits(T_566, 5, 0) + node T_586 = mux(T_576, UInt<1>("h00"), T_585) + node T_588 = eq(T_576, UInt<1>("h00")) + node T_589 = cat(T_588, T_567) + node T_590 = dshl(T_589, T_586) + node T_591 = bits(T_590, 115, 52) + node T_592 = bits(T_590, 52, 51) + node T_593 = bits(T_590, 50, 0) + node T_595 = neq(T_593, UInt<1>("h00")) + node T_596 = cat(T_592, T_595) + node T_597 = bits(T_596, 1, 0) + node T_599 = neq(T_597, UInt<1>("h00")) + node T_601 = eq(T_573, UInt<1>("h00")) + node T_602 = and(T_601, T_599) + node T_603 = bits(T_596, 2, 1) + node T_604 = not(T_603) + node T_606 = eq(T_604, UInt<1>("h00")) + node T_607 = bits(T_596, 1, 0) + node T_608 = not(T_607) + node T_610 = eq(T_608, UInt<1>("h00")) + node T_611 = or(T_606, T_610) + node T_612 = mux(T_576, T_602, T_611) + node T_614 = eq(T_579, UInt<1>("h00")) + node T_615 = mux(T_576, T_614, T_599) + node T_616 = eq(in_1.rm, UInt<2>("h00")) + node T_617 = eq(in_1.rm, UInt<2>("h02")) + node T_618 = and(T_565, T_615) + node T_619 = eq(in_1.rm, UInt<2>("h03")) + node T_621 = eq(T_565, UInt<1>("h00")) + node T_622 = and(T_621, T_615) + node T_624 = mux(T_619, T_622, UInt<1>("h00")) + node T_625 = mux(T_617, T_618, T_624) + node T_626 = mux(T_616, T_612, T_625) + node T_627 = not(T_591) + node T_628 = mux(T_565, T_627, T_591) + node T_629 = xor(T_626, T_565) + node T_631 = addw(T_628, UInt<1>("h01")) + node T_632 = mux(T_629, T_631, T_628) + node T_633 = asSInt(T_632) + node T_634 = not(T_591) + node T_636 = eq(T_634, UInt<1>("h00")) + node T_637 = and(T_626, T_636) + node T_639 = eq(T_565, UInt<1>("h00")) + node T_640 = and(T_639, T_637) + node T_642 = eq(T_565, UInt<1>("h00")) + node T_643 = or(T_642, T_626) + node T_645 = neq(T_591, UInt<1>("h00")) + node T_646 = or(T_643, T_645) + node T_647 = bits(T_566, 10, 0) + node T_648 = eq(T_564, UInt<2>("h00")) + node T_649 = and(T_565, T_626) + node T_651 = eq(T_647, UInt<5>("h01f")) + node T_653 = geq(T_647, UInt<6>("h020")) + node T_654 = mux(T_651, T_637, T_653) + node T_655 = or(T_565, T_654) + node T_656 = mux(T_576, T_649, T_655) + node T_657 = eq(T_564, UInt<2>("h01")) + node T_660 = eq(T_647, UInt<5>("h01e")) + node T_662 = eq(T_647, UInt<5>("h01f")) + node T_664 = geq(T_647, UInt<6>("h020")) + node T_665 = mux(T_662, T_646, T_664) + node T_666 = mux(T_660, T_640, T_665) + node T_667 = mux(T_576, UInt<1>("h00"), T_666) + node T_668 = eq(T_564, UInt<2>("h02")) + node T_669 = and(T_565, T_626) + node T_671 = eq(T_647, UInt<6>("h03f")) + node T_673 = geq(T_647, UInt<7>("h040")) + node T_674 = mux(T_671, T_637, T_673) + node T_675 = or(T_565, T_674) + node T_676 = mux(T_576, T_669, T_675) + node T_679 = eq(T_647, UInt<6>("h03e")) + node T_681 = eq(T_647, UInt<6>("h03f")) + node T_683 = geq(T_647, UInt<7>("h040")) + node T_684 = mux(T_681, T_646, T_683) + node T_685 = mux(T_679, T_640, T_684) + node T_686 = mux(T_576, UInt<1>("h00"), T_685) + node T_687 = mux(T_668, T_676, T_686) + node T_688 = mux(T_657, T_667, T_687) + node T_689 = mux(T_648, T_656, T_688) + node T_690 = or(T_583, T_689) + node T_691 = eq(T_564, UInt<2>("h03")) + node T_692 = and(T_691, T_565) + node T_694 = eq(T_564, UInt<2>("h01")) + node T_695 = and(T_694, T_565) + node T_697 = eq(T_564, UInt<2>("h03")) + node T_699 = eq(T_565, UInt<1>("h00")) + node T_700 = and(T_697, T_699) + node T_702 = eq(T_564, UInt<2>("h01")) + node T_704 = eq(T_565, UInt<1>("h00")) + node T_705 = and(T_702, T_704) + node T_708 = mux(T_705, asSInt(UInt<32>("h07fffffff")), asSInt(UInt<1>("h01"))) + node T_709 = mux(T_700, asSInt(UInt<64>("h07fffffffffffffff")), T_708) + node T_710 = mux(T_695, asSInt(UInt<32>("h080000000")), T_709) + node T_711 = mux(T_692, asSInt(UInt<64>("h08000000000000000")), T_710) + node T_713 = eq(T_690, UInt<1>("h00")) + node T_714 = and(T_599, T_713) + node T_715 = mux(T_690, T_711, T_633) + node T_717 = cat(UInt<3>("h00"), T_714) + node T_718 = cat(T_690, T_717) + node T_719 = bit(in_1.rm, 0) + node T_720 = mux(T_719, classify_out, unrec_out) + out.bits.toint := T_720 + out.bits.store := unrec_out + out.bits.exc := UInt<1>("h00") + node T_724 = and(in_1.cmd, UInt<4>("h0c")) + node T_725 = eq(UInt<3>("h04"), T_724) + when T_725 : + out.bits.toint := dcmp_out + out.bits.exc := dcmp_exc + skip + node T_728 = and(in_1.cmd, UInt<4>("h0c")) + node T_729 = eq(UInt<4>("h08"), T_728) + when T_729 : + node T_730 = bit(in_1.typ, 1) + node T_731 = bits(T_715, 31, 0) + node T_732 = asSInt(T_731) + node T_733 = mux(T_730, T_715, T_732) + node T_734 = asUInt(T_733) + out.bits.toint := T_734 + out.bits.exc := T_718 + skip + out.valid := valid + out.bits.lt := dcmp.a_lt_b + as_double <> in_1 + + module IntToFP : + output out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} + input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} + input clock : Clock + input reset : UInt<1> + + out.bits.exc := UInt<1>("h00") + out.bits.data := UInt<1>("h00") + out.valid := UInt<1>("h00") + reg T_136 : UInt<1>, clock, reset + onreset T_136 := UInt<1>("h00") + T_136 := in.valid + reg T_137 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset + when in.valid : + T_137 <> in.bits + skip + wire in_1 : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} + in_1.bits.in3 := UInt<1>("h00") + in_1.bits.in2 := UInt<1>("h00") + in_1.bits.in1 := UInt<1>("h00") + in_1.bits.typ := UInt<1>("h00") + in_1.bits.rm := UInt<1>("h00") + in_1.bits.wflags := UInt<1>("h00") + in_1.bits.round := UInt<1>("h00") + in_1.bits.sqrt := UInt<1>("h00") + in_1.bits.div := UInt<1>("h00") + in_1.bits.fma := UInt<1>("h00") + in_1.bits.fastpipe := UInt<1>("h00") + in_1.bits.toint := UInt<1>("h00") + in_1.bits.fromint := UInt<1>("h00") + in_1.bits.single := UInt<1>("h00") + in_1.bits.swap23 := UInt<1>("h00") + in_1.bits.swap12 := UInt<1>("h00") + in_1.bits.ren3 := UInt<1>("h00") + in_1.bits.ren2 := UInt<1>("h00") + in_1.bits.ren1 := UInt<1>("h00") + in_1.bits.wen := UInt<1>("h00") + in_1.bits.ldst := UInt<1>("h00") + in_1.bits.cmd := UInt<1>("h00") + in_1.valid := UInt<1>("h00") + in_1.valid := T_136 + in_1.bits <> T_137 + wire mux : {data : UInt<65>, exc : UInt<5>} + mux.exc := UInt<1>("h00") + mux.data := UInt<1>("h00") + mux.exc := UInt<1>("h00") + node T_288 = bit(in_1.bits.in1, 63) + node T_289 = bits(in_1.bits.in1, 62, 52) + node T_290 = bits(in_1.bits.in1, 51, 0) + node T_292 = eq(T_289, UInt<1>("h00")) + node T_294 = eq(T_290, UInt<1>("h00")) + node T_295 = and(T_292, T_294) + node T_297 = eq(T_294, UInt<1>("h00")) + node T_298 = and(T_292, T_297) + node T_299 = shl(T_290, 12) + node T_300 = bit(T_299, 63) + node T_302 = bit(T_299, 62) + node T_304 = bit(T_299, 61) + node T_306 = bit(T_299, 60) + node T_308 = bit(T_299, 59) + node T_310 = bit(T_299, 58) + node T_312 = bit(T_299, 57) + node T_314 = bit(T_299, 56) + node T_316 = bit(T_299, 55) + node T_318 = bit(T_299, 54) + node T_320 = bit(T_299, 53) + node T_322 = bit(T_299, 52) + node T_324 = bit(T_299, 51) + node T_326 = bit(T_299, 50) + node T_328 = bit(T_299, 49) + node T_330 = bit(T_299, 48) + node T_332 = bit(T_299, 47) + node T_334 = bit(T_299, 46) + node T_336 = bit(T_299, 45) + node T_338 = bit(T_299, 44) + node T_340 = bit(T_299, 43) + node T_342 = bit(T_299, 42) + node T_344 = bit(T_299, 41) + node T_346 = bit(T_299, 40) + node T_348 = bit(T_299, 39) + node T_350 = bit(T_299, 38) + node T_352 = bit(T_299, 37) + node T_354 = bit(T_299, 36) + node T_356 = bit(T_299, 35) + node T_358 = bit(T_299, 34) + node T_360 = bit(T_299, 33) + node T_362 = bit(T_299, 32) + node T_364 = bit(T_299, 31) + node T_366 = bit(T_299, 30) + node T_368 = bit(T_299, 29) + node T_370 = bit(T_299, 28) + node T_372 = bit(T_299, 27) + node T_374 = bit(T_299, 26) + node T_376 = bit(T_299, 25) + node T_378 = bit(T_299, 24) + node T_380 = bit(T_299, 23) + node T_382 = bit(T_299, 22) + node T_384 = bit(T_299, 21) + node T_386 = bit(T_299, 20) + node T_388 = bit(T_299, 19) + node T_390 = bit(T_299, 18) + node T_392 = bit(T_299, 17) + node T_394 = bit(T_299, 16) + node T_396 = bit(T_299, 15) + node T_398 = bit(T_299, 14) + node T_400 = bit(T_299, 13) + node T_402 = bit(T_299, 12) + node T_404 = bit(T_299, 11) + node T_406 = bit(T_299, 10) + node T_408 = bit(T_299, 9) + node T_410 = bit(T_299, 8) + node T_412 = bit(T_299, 7) + node T_414 = bit(T_299, 6) + node T_416 = bit(T_299, 5) + node T_418 = bit(T_299, 4) + node T_420 = bit(T_299, 3) + node T_422 = bit(T_299, 2) + node T_424 = bit(T_299, 1) + node T_425 = shl(T_424, 0) + node T_426 = mux(T_422, UInt<2>("h02"), T_425) + node T_427 = mux(T_420, UInt<2>("h03"), T_426) + node T_428 = mux(T_418, UInt<3>("h04"), T_427) + node T_429 = mux(T_416, UInt<3>("h05"), T_428) + node T_430 = mux(T_414, UInt<3>("h06"), T_429) + node T_431 = mux(T_412, UInt<3>("h07"), T_430) + node T_432 = mux(T_410, UInt<4>("h08"), T_431) + node T_433 = mux(T_408, UInt<4>("h09"), T_432) + node T_434 = mux(T_406, UInt<4>("h0a"), T_433) + node T_435 = mux(T_404, UInt<4>("h0b"), T_434) + node T_436 = mux(T_402, UInt<4>("h0c"), T_435) + node T_437 = mux(T_400, UInt<4>("h0d"), T_436) + node T_438 = mux(T_398, UInt<4>("h0e"), T_437) + node T_439 = mux(T_396, UInt<4>("h0f"), T_438) + node T_440 = mux(T_394, UInt<5>("h010"), T_439) + node T_441 = mux(T_392, UInt<5>("h011"), T_440) + node T_442 = mux(T_390, UInt<5>("h012"), T_441) + node T_443 = mux(T_388, UInt<5>("h013"), T_442) + node T_444 = mux(T_386, UInt<5>("h014"), T_443) + node T_445 = mux(T_384, UInt<5>("h015"), T_444) + node T_446 = mux(T_382, UInt<5>("h016"), T_445) + node T_447 = mux(T_380, UInt<5>("h017"), T_446) + node T_448 = mux(T_378, UInt<5>("h018"), T_447) + node T_449 = mux(T_376, UInt<5>("h019"), T_448) + node T_450 = mux(T_374, UInt<5>("h01a"), T_449) + node T_451 = mux(T_372, UInt<5>("h01b"), T_450) + node T_452 = mux(T_370, UInt<5>("h01c"), T_451) + node T_453 = mux(T_368, UInt<5>("h01d"), T_452) + node T_454 = mux(T_366, UInt<5>("h01e"), T_453) + node T_455 = mux(T_364, UInt<5>("h01f"), T_454) + node T_456 = mux(T_362, UInt<6>("h020"), T_455) + node T_457 = mux(T_360, UInt<6>("h021"), T_456) + node T_458 = mux(T_358, UInt<6>("h022"), T_457) + node T_459 = mux(T_356, UInt<6>("h023"), T_458) + node T_460 = mux(T_354, UInt<6>("h024"), T_459) + node T_461 = mux(T_352, UInt<6>("h025"), T_460) + node T_462 = mux(T_350, UInt<6>("h026"), T_461) + node T_463 = mux(T_348, UInt<6>("h027"), T_462) + node T_464 = mux(T_346, UInt<6>("h028"), T_463) + node T_465 = mux(T_344, UInt<6>("h029"), T_464) + node T_466 = mux(T_342, UInt<6>("h02a"), T_465) + node T_467 = mux(T_340, UInt<6>("h02b"), T_466) + node T_468 = mux(T_338, UInt<6>("h02c"), T_467) + node T_469 = mux(T_336, UInt<6>("h02d"), T_468) + node T_470 = mux(T_334, UInt<6>("h02e"), T_469) + node T_471 = mux(T_332, UInt<6>("h02f"), T_470) + node T_472 = mux(T_330, UInt<6>("h030"), T_471) + node T_473 = mux(T_328, UInt<6>("h031"), T_472) + node T_474 = mux(T_326, UInt<6>("h032"), T_473) + node T_475 = mux(T_324, UInt<6>("h033"), T_474) + node T_476 = mux(T_322, UInt<6>("h034"), T_475) + node T_477 = mux(T_320, UInt<6>("h035"), T_476) + node T_478 = mux(T_318, UInt<6>("h036"), T_477) + node T_479 = mux(T_316, UInt<6>("h037"), T_478) + node T_480 = mux(T_314, UInt<6>("h038"), T_479) + node T_481 = mux(T_312, UInt<6>("h039"), T_480) + node T_482 = mux(T_310, UInt<6>("h03a"), T_481) + node T_483 = mux(T_308, UInt<6>("h03b"), T_482) + node T_484 = mux(T_306, UInt<6>("h03c"), T_483) + node T_485 = mux(T_304, UInt<6>("h03d"), T_484) + node T_486 = mux(T_302, UInt<6>("h03e"), T_485) + node T_487 = mux(T_300, UInt<6>("h03f"), T_486) + node T_488 = not(T_487) + node T_489 = dshl(T_299, T_488) + node T_492 = subw(UInt<6>("h00"), UInt<1>("h01")) + node T_493 = not(T_488) + node T_494 = cat(T_492, T_493) + node T_495 = bits(T_489, 62, 11) + node T_497 = mux(T_294, UInt<1>("h00"), T_494) + node T_498 = mux(T_292, T_497, T_289) + node T_503 = mux(T_298, UInt<2>("h02"), UInt<1>("h01")) + node T_504 = or(UInt<11>("h0400"), T_503) + node T_505 = mux(T_295, UInt<1>("h00"), T_504) + node T_506 = addw(T_498, T_505) + node T_507 = bits(T_506, 11, 10) + node T_508 = not(T_507) + node T_510 = eq(T_508, UInt<1>("h00")) + node T_512 = eq(T_294, UInt<1>("h00")) + node T_513 = and(T_510, T_512) + node T_514 = shl(T_513, 9) + node T_515 = or(T_506, T_514) + node T_516 = mux(T_292, T_495, T_290) + node T_517 = cat(T_515, T_516) + node T_518 = cat(T_288, T_517) + mux.data := T_518 + when in_1.bits.single : + node T_520 = bit(in_1.bits.in1, 31) + node T_521 = bits(in_1.bits.in1, 30, 23) + node T_522 = bits(in_1.bits.in1, 22, 0) + node T_524 = eq(T_521, UInt<1>("h00")) + node T_526 = eq(T_522, UInt<1>("h00")) + node T_527 = and(T_524, T_526) + node T_529 = eq(T_526, UInt<1>("h00")) + node T_530 = and(T_524, T_529) + node T_531 = shl(T_522, 9) + node T_532 = bit(T_531, 31) + node T_534 = bit(T_531, 30) + node T_536 = bit(T_531, 29) + node T_538 = bit(T_531, 28) + node T_540 = bit(T_531, 27) + node T_542 = bit(T_531, 26) + node T_544 = bit(T_531, 25) + node T_546 = bit(T_531, 24) + node T_548 = bit(T_531, 23) + node T_550 = bit(T_531, 22) + node T_552 = bit(T_531, 21) + node T_554 = bit(T_531, 20) + node T_556 = bit(T_531, 19) + node T_558 = bit(T_531, 18) + node T_560 = bit(T_531, 17) + node T_562 = bit(T_531, 16) + node T_564 = bit(T_531, 15) + node T_566 = bit(T_531, 14) + node T_568 = bit(T_531, 13) + node T_570 = bit(T_531, 12) + node T_572 = bit(T_531, 11) + node T_574 = bit(T_531, 10) + node T_576 = bit(T_531, 9) + node T_578 = bit(T_531, 8) + node T_580 = bit(T_531, 7) + node T_582 = bit(T_531, 6) + node T_584 = bit(T_531, 5) + node T_586 = bit(T_531, 4) + node T_588 = bit(T_531, 3) + node T_590 = bit(T_531, 2) + node T_592 = bit(T_531, 1) + node T_593 = shl(T_592, 0) + node T_594 = mux(T_590, UInt<2>("h02"), T_593) + node T_595 = mux(T_588, UInt<2>("h03"), T_594) + node T_596 = mux(T_586, UInt<3>("h04"), T_595) + node T_597 = mux(T_584, UInt<3>("h05"), T_596) + node T_598 = mux(T_582, UInt<3>("h06"), T_597) + node T_599 = mux(T_580, UInt<3>("h07"), T_598) + node T_600 = mux(T_578, UInt<4>("h08"), T_599) + node T_601 = mux(T_576, UInt<4>("h09"), T_600) + node T_602 = mux(T_574, UInt<4>("h0a"), T_601) + node T_603 = mux(T_572, UInt<4>("h0b"), T_602) + node T_604 = mux(T_570, UInt<4>("h0c"), T_603) + node T_605 = mux(T_568, UInt<4>("h0d"), T_604) + node T_606 = mux(T_566, UInt<4>("h0e"), T_605) + node T_607 = mux(T_564, UInt<4>("h0f"), T_606) + node T_608 = mux(T_562, UInt<5>("h010"), T_607) + node T_609 = mux(T_560, UInt<5>("h011"), T_608) + node T_610 = mux(T_558, UInt<5>("h012"), T_609) + node T_611 = mux(T_556, UInt<5>("h013"), T_610) + node T_612 = mux(T_554, UInt<5>("h014"), T_611) + node T_613 = mux(T_552, UInt<5>("h015"), T_612) + node T_614 = mux(T_550, UInt<5>("h016"), T_613) + node T_615 = mux(T_548, UInt<5>("h017"), T_614) + node T_616 = mux(T_546, UInt<5>("h018"), T_615) + node T_617 = mux(T_544, UInt<5>("h019"), T_616) + node T_618 = mux(T_542, UInt<5>("h01a"), T_617) + node T_619 = mux(T_540, UInt<5>("h01b"), T_618) + node T_620 = mux(T_538, UInt<5>("h01c"), T_619) + node T_621 = mux(T_536, UInt<5>("h01d"), T_620) + node T_622 = mux(T_534, UInt<5>("h01e"), T_621) + node T_623 = mux(T_532, UInt<5>("h01f"), T_622) + node T_624 = not(T_623) + node T_625 = dshl(T_531, T_624) + node T_628 = subw(UInt<4>("h00"), UInt<1>("h01")) + node T_629 = not(T_624) + node T_630 = cat(T_628, T_629) + node T_631 = bits(T_625, 30, 8) + node T_633 = mux(T_526, UInt<1>("h00"), T_630) + node T_634 = mux(T_524, T_633, T_521) + node T_639 = mux(T_530, UInt<2>("h02"), UInt<1>("h01")) + node T_640 = or(UInt<8>("h080"), T_639) + node T_641 = mux(T_527, UInt<1>("h00"), T_640) + node T_642 = addw(T_634, T_641) + node T_643 = bits(T_642, 8, 7) + node T_644 = not(T_643) + node T_646 = eq(T_644, UInt<1>("h00")) + node T_648 = eq(T_526, UInt<1>("h00")) + node T_649 = and(T_646, T_648) + node T_650 = shl(T_649, 6) + node T_651 = or(T_642, T_650) + node T_652 = mux(T_524, T_631, T_522) + node T_653 = cat(T_651, T_652) + node T_654 = cat(T_520, T_653) + node T_655 = asUInt(asSInt(UInt<32>("h0ffffffff"))) + node T_656 = cat(T_655, T_654) + mux.data := T_656 + skip + node T_659 = and(in_1.bits.cmd, UInt<3>("h04")) + node T_660 = eq(UInt<1>("h00"), T_659) + when T_660 : + when in_1.bits.single : + node T_661 = bits(in_1.bits.in1, 63, 0) + node T_663 = xor(in_1.bits.typ, UInt<1>("h01")) + node T_664 = eq(T_663, UInt<2>("h01")) + node T_665 = bit(T_661, 31) + node T_666 = eq(T_663, UInt<2>("h03")) + node T_667 = bit(T_661, 63) + node T_669 = mux(T_666, T_667, UInt<1>("h00")) + node T_670 = mux(T_664, T_665, T_669) + node T_672 = subw(UInt<1>("h00"), T_661) + node T_673 = mux(T_670, T_672, T_661) + node T_674 = eq(T_663, UInt<2>("h03")) + node T_675 = eq(T_663, UInt<2>("h02")) + node T_676 = or(T_674, T_675) + node T_677 = bits(T_673, 31, 0) + node T_678 = mux(T_676, T_673, T_677) + node T_679 = bit(T_678, 63) + node T_681 = bit(T_678, 62) + node T_683 = bit(T_678, 61) + node T_685 = bit(T_678, 60) + node T_687 = bit(T_678, 59) + node T_689 = bit(T_678, 58) + node T_691 = bit(T_678, 57) + node T_693 = bit(T_678, 56) + node T_695 = bit(T_678, 55) + node T_697 = bit(T_678, 54) + node T_699 = bit(T_678, 53) + node T_701 = bit(T_678, 52) + node T_703 = bit(T_678, 51) + node T_705 = bit(T_678, 50) + node T_707 = bit(T_678, 49) + node T_709 = bit(T_678, 48) + node T_711 = bit(T_678, 47) + node T_713 = bit(T_678, 46) + node T_715 = bit(T_678, 45) + node T_717 = bit(T_678, 44) + node T_719 = bit(T_678, 43) + node T_721 = bit(T_678, 42) + node T_723 = bit(T_678, 41) + node T_725 = bit(T_678, 40) + node T_727 = bit(T_678, 39) + node T_729 = bit(T_678, 38) + node T_731 = bit(T_678, 37) + node T_733 = bit(T_678, 36) + node T_735 = bit(T_678, 35) + node T_737 = bit(T_678, 34) + node T_739 = bit(T_678, 33) + node T_741 = bit(T_678, 32) + node T_743 = bit(T_678, 31) + node T_745 = bit(T_678, 30) + node T_747 = bit(T_678, 29) + node T_749 = bit(T_678, 28) + node T_751 = bit(T_678, 27) + node T_753 = bit(T_678, 26) + node T_755 = bit(T_678, 25) + node T_757 = bit(T_678, 24) + node T_759 = bit(T_678, 23) + node T_761 = bit(T_678, 22) + node T_763 = bit(T_678, 21) + node T_765 = bit(T_678, 20) + node T_767 = bit(T_678, 19) + node T_769 = bit(T_678, 18) + node T_771 = bit(T_678, 17) + node T_773 = bit(T_678, 16) + node T_775 = bit(T_678, 15) + node T_777 = bit(T_678, 14) + node T_779 = bit(T_678, 13) + node T_781 = bit(T_678, 12) + node T_783 = bit(T_678, 11) + node T_785 = bit(T_678, 10) + node T_787 = bit(T_678, 9) + node T_789 = bit(T_678, 8) + node T_791 = bit(T_678, 7) + node T_793 = bit(T_678, 6) + node T_795 = bit(T_678, 5) + node T_797 = bit(T_678, 4) + node T_799 = bit(T_678, 3) + node T_801 = bit(T_678, 2) + node T_803 = bit(T_678, 1) + node T_804 = shl(T_803, 0) + node T_805 = mux(T_801, UInt<2>("h02"), T_804) + node T_806 = mux(T_799, UInt<2>("h03"), T_805) + node T_807 = mux(T_797, UInt<3>("h04"), T_806) + node T_808 = mux(T_795, UInt<3>("h05"), T_807) + node T_809 = mux(T_793, UInt<3>("h06"), T_808) + node T_810 = mux(T_791, UInt<3>("h07"), T_809) + node T_811 = mux(T_789, UInt<4>("h08"), T_810) + node T_812 = mux(T_787, UInt<4>("h09"), T_811) + node T_813 = mux(T_785, UInt<4>("h0a"), T_812) + node T_814 = mux(T_783, UInt<4>("h0b"), T_813) + node T_815 = mux(T_781, UInt<4>("h0c"), T_814) + node T_816 = mux(T_779, UInt<4>("h0d"), T_815) + node T_817 = mux(T_777, UInt<4>("h0e"), T_816) + node T_818 = mux(T_775, UInt<4>("h0f"), T_817) + node T_819 = mux(T_773, UInt<5>("h010"), T_818) + node T_820 = mux(T_771, UInt<5>("h011"), T_819) + node T_821 = mux(T_769, UInt<5>("h012"), T_820) + node T_822 = mux(T_767, UInt<5>("h013"), T_821) + node T_823 = mux(T_765, UInt<5>("h014"), T_822) + node T_824 = mux(T_763, UInt<5>("h015"), T_823) + node T_825 = mux(T_761, UInt<5>("h016"), T_824) + node T_826 = mux(T_759, UInt<5>("h017"), T_825) + node T_827 = mux(T_757, UInt<5>("h018"), T_826) + node T_828 = mux(T_755, UInt<5>("h019"), T_827) + node T_829 = mux(T_753, UInt<5>("h01a"), T_828) + node T_830 = mux(T_751, UInt<5>("h01b"), T_829) + node T_831 = mux(T_749, UInt<5>("h01c"), T_830) + node T_832 = mux(T_747, UInt<5>("h01d"), T_831) + node T_833 = mux(T_745, UInt<5>("h01e"), T_832) + node T_834 = mux(T_743, UInt<5>("h01f"), T_833) + node T_835 = mux(T_741, UInt<6>("h020"), T_834) + node T_836 = mux(T_739, UInt<6>("h021"), T_835) + node T_837 = mux(T_737, UInt<6>("h022"), T_836) + node T_838 = mux(T_735, UInt<6>("h023"), T_837) + node T_839 = mux(T_733, UInt<6>("h024"), T_838) + node T_840 = mux(T_731, UInt<6>("h025"), T_839) + node T_841 = mux(T_729, UInt<6>("h026"), T_840) + node T_842 = mux(T_727, UInt<6>("h027"), T_841) + node T_843 = mux(T_725, UInt<6>("h028"), T_842) + node T_844 = mux(T_723, UInt<6>("h029"), T_843) + node T_845 = mux(T_721, UInt<6>("h02a"), T_844) + node T_846 = mux(T_719, UInt<6>("h02b"), T_845) + node T_847 = mux(T_717, UInt<6>("h02c"), T_846) + node T_848 = mux(T_715, UInt<6>("h02d"), T_847) + node T_849 = mux(T_713, UInt<6>("h02e"), T_848) + node T_850 = mux(T_711, UInt<6>("h02f"), T_849) + node T_851 = mux(T_709, UInt<6>("h030"), T_850) + node T_852 = mux(T_707, UInt<6>("h031"), T_851) + node T_853 = mux(T_705, UInt<6>("h032"), T_852) + node T_854 = mux(T_703, UInt<6>("h033"), T_853) + node T_855 = mux(T_701, UInt<6>("h034"), T_854) + node T_856 = mux(T_699, UInt<6>("h035"), T_855) + node T_857 = mux(T_697, UInt<6>("h036"), T_856) + node T_858 = mux(T_695, UInt<6>("h037"), T_857) + node T_859 = mux(T_693, UInt<6>("h038"), T_858) + node T_860 = mux(T_691, UInt<6>("h039"), T_859) + node T_861 = mux(T_689, UInt<6>("h03a"), T_860) + node T_862 = mux(T_687, UInt<6>("h03b"), T_861) + node T_863 = mux(T_685, UInt<6>("h03c"), T_862) + node T_864 = mux(T_683, UInt<6>("h03d"), T_863) + node T_865 = mux(T_681, UInt<6>("h03e"), T_864) + node T_866 = mux(T_679, UInt<6>("h03f"), T_865) + node T_867 = not(T_866) + node T_868 = dshl(T_678, T_867) + node T_870 = bits(T_868, 40, 39) + node T_871 = bits(T_868, 38, 0) + node T_873 = neq(T_871, UInt<1>("h00")) + node T_874 = cat(T_870, T_873) + node T_875 = bits(T_874, 1, 0) + node T_877 = neq(T_875, UInt<1>("h00")) + node T_878 = eq(in_1.bits.rm, UInt<2>("h00")) + node T_879 = bits(T_874, 2, 1) + node T_880 = not(T_879) + node T_882 = eq(T_880, UInt<1>("h00")) + node T_883 = bits(T_874, 1, 0) + node T_884 = not(T_883) + node T_886 = eq(T_884, UInt<1>("h00")) + node T_887 = or(T_882, T_886) + node T_888 = eq(in_1.bits.rm, UInt<2>("h02")) + node T_889 = and(T_670, T_877) + node T_890 = eq(in_1.bits.rm, UInt<2>("h03")) + node T_892 = eq(T_670, UInt<1>("h00")) + node T_893 = and(T_892, T_877) + node T_895 = mux(T_890, T_893, UInt<1>("h00")) + node T_896 = mux(T_888, T_889, T_895) + node T_897 = mux(T_878, T_887, T_896) + node T_898 = bits(T_868, 63, 40) + node T_900 = cat(UInt<1>("h00"), T_898) + node T_902 = addw(T_900, UInt<1>("h01")) + node T_903 = mux(T_897, T_902, T_900) + node T_906 = not(T_867) + node T_908 = cat(UInt<1>("h00"), T_906) + node T_910 = cat(UInt<1>("h00"), T_908) + node T_911 = bit(T_903, 24) + node T_912 = addw(T_910, T_911) + node T_913 = bit(T_868, 63) + node T_915 = bits(T_912, 7, 0) + node T_916 = mux(UInt<1>("h00"), UInt<8>("h080"), T_915) + node T_917 = cat(T_913, T_916) + node T_918 = or(UInt<1>("h00"), UInt<1>("h00")) + node T_919 = or(T_877, T_918) + node T_920 = bits(T_903, 22, 0) + node T_921 = cat(T_917, T_920) + node T_922 = cat(T_670, T_921) + node T_925 = cat(UInt<2>("h00"), T_918) + node T_926 = cat(UInt<1>("h00"), T_919) + node T_927 = cat(T_925, T_926) + node T_929 = asUInt(asSInt(UInt<32>("h0ffffffff"))) + node T_930 = cat(T_929, T_922) + mux.data := T_930 + mux.exc := T_927 + skip + else : + node T_931 = bits(in_1.bits.in1, 63, 0) + node T_933 = xor(in_1.bits.typ, UInt<1>("h01")) + node T_934 = eq(T_933, UInt<2>("h01")) + node T_935 = bit(T_931, 31) + node T_936 = eq(T_933, UInt<2>("h03")) + node T_937 = bit(T_931, 63) + node T_939 = mux(T_936, T_937, UInt<1>("h00")) + node T_940 = mux(T_934, T_935, T_939) + node T_942 = subw(UInt<1>("h00"), T_931) + node T_943 = mux(T_940, T_942, T_931) + node T_944 = eq(T_933, UInt<2>("h03")) + node T_945 = eq(T_933, UInt<2>("h02")) + node T_946 = or(T_944, T_945) + node T_947 = bits(T_943, 31, 0) + node T_948 = mux(T_946, T_943, T_947) + node T_949 = bit(T_948, 63) + node T_951 = bit(T_948, 62) + node T_953 = bit(T_948, 61) + node T_955 = bit(T_948, 60) + node T_957 = bit(T_948, 59) + node T_959 = bit(T_948, 58) + node T_961 = bit(T_948, 57) + node T_963 = bit(T_948, 56) + node T_965 = bit(T_948, 55) + node T_967 = bit(T_948, 54) + node T_969 = bit(T_948, 53) + node T_971 = bit(T_948, 52) + node T_973 = bit(T_948, 51) + node T_975 = bit(T_948, 50) + node T_977 = bit(T_948, 49) + node T_979 = bit(T_948, 48) + node T_981 = bit(T_948, 47) + node T_983 = bit(T_948, 46) + node T_985 = bit(T_948, 45) + node T_987 = bit(T_948, 44) + node T_989 = bit(T_948, 43) + node T_991 = bit(T_948, 42) + node T_993 = bit(T_948, 41) + node T_995 = bit(T_948, 40) + node T_997 = bit(T_948, 39) + node T_999 = bit(T_948, 38) + node T_1001 = bit(T_948, 37) + node T_1003 = bit(T_948, 36) + node T_1005 = bit(T_948, 35) + node T_1007 = bit(T_948, 34) + node T_1009 = bit(T_948, 33) + node T_1011 = bit(T_948, 32) + node T_1013 = bit(T_948, 31) + node T_1015 = bit(T_948, 30) + node T_1017 = bit(T_948, 29) + node T_1019 = bit(T_948, 28) + node T_1021 = bit(T_948, 27) + node T_1023 = bit(T_948, 26) + node T_1025 = bit(T_948, 25) + node T_1027 = bit(T_948, 24) + node T_1029 = bit(T_948, 23) + node T_1031 = bit(T_948, 22) + node T_1033 = bit(T_948, 21) + node T_1035 = bit(T_948, 20) + node T_1037 = bit(T_948, 19) + node T_1039 = bit(T_948, 18) + node T_1041 = bit(T_948, 17) + node T_1043 = bit(T_948, 16) + node T_1045 = bit(T_948, 15) + node T_1047 = bit(T_948, 14) + node T_1049 = bit(T_948, 13) + node T_1051 = bit(T_948, 12) + node T_1053 = bit(T_948, 11) + node T_1055 = bit(T_948, 10) + node T_1057 = bit(T_948, 9) + node T_1059 = bit(T_948, 8) + node T_1061 = bit(T_948, 7) + node T_1063 = bit(T_948, 6) + node T_1065 = bit(T_948, 5) + node T_1067 = bit(T_948, 4) + node T_1069 = bit(T_948, 3) + node T_1071 = bit(T_948, 2) + node T_1073 = bit(T_948, 1) + node T_1074 = shl(T_1073, 0) + node T_1075 = mux(T_1071, UInt<2>("h02"), T_1074) + node T_1076 = mux(T_1069, UInt<2>("h03"), T_1075) + node T_1077 = mux(T_1067, UInt<3>("h04"), T_1076) + node T_1078 = mux(T_1065, UInt<3>("h05"), T_1077) + node T_1079 = mux(T_1063, UInt<3>("h06"), T_1078) + node T_1080 = mux(T_1061, UInt<3>("h07"), T_1079) + node T_1081 = mux(T_1059, UInt<4>("h08"), T_1080) + node T_1082 = mux(T_1057, UInt<4>("h09"), T_1081) + node T_1083 = mux(T_1055, UInt<4>("h0a"), T_1082) + node T_1084 = mux(T_1053, UInt<4>("h0b"), T_1083) + node T_1085 = mux(T_1051, UInt<4>("h0c"), T_1084) + node T_1086 = mux(T_1049, UInt<4>("h0d"), T_1085) + node T_1087 = mux(T_1047, UInt<4>("h0e"), T_1086) + node T_1088 = mux(T_1045, UInt<4>("h0f"), T_1087) + node T_1089 = mux(T_1043, UInt<5>("h010"), T_1088) + node T_1090 = mux(T_1041, UInt<5>("h011"), T_1089) + node T_1091 = mux(T_1039, UInt<5>("h012"), T_1090) + node T_1092 = mux(T_1037, UInt<5>("h013"), T_1091) + node T_1093 = mux(T_1035, UInt<5>("h014"), T_1092) + node T_1094 = mux(T_1033, UInt<5>("h015"), T_1093) + node T_1095 = mux(T_1031, UInt<5>("h016"), T_1094) + node T_1096 = mux(T_1029, UInt<5>("h017"), T_1095) + node T_1097 = mux(T_1027, UInt<5>("h018"), T_1096) + node T_1098 = mux(T_1025, UInt<5>("h019"), T_1097) + node T_1099 = mux(T_1023, UInt<5>("h01a"), T_1098) + node T_1100 = mux(T_1021, UInt<5>("h01b"), T_1099) + node T_1101 = mux(T_1019, UInt<5>("h01c"), T_1100) + node T_1102 = mux(T_1017, UInt<5>("h01d"), T_1101) + node T_1103 = mux(T_1015, UInt<5>("h01e"), T_1102) + node T_1104 = mux(T_1013, UInt<5>("h01f"), T_1103) + node T_1105 = mux(T_1011, UInt<6>("h020"), T_1104) + node T_1106 = mux(T_1009, UInt<6>("h021"), T_1105) + node T_1107 = mux(T_1007, UInt<6>("h022"), T_1106) + node T_1108 = mux(T_1005, UInt<6>("h023"), T_1107) + node T_1109 = mux(T_1003, UInt<6>("h024"), T_1108) + node T_1110 = mux(T_1001, UInt<6>("h025"), T_1109) + node T_1111 = mux(T_999, UInt<6>("h026"), T_1110) + node T_1112 = mux(T_997, UInt<6>("h027"), T_1111) + node T_1113 = mux(T_995, UInt<6>("h028"), T_1112) + node T_1114 = mux(T_993, UInt<6>("h029"), T_1113) + node T_1115 = mux(T_991, UInt<6>("h02a"), T_1114) + node T_1116 = mux(T_989, UInt<6>("h02b"), T_1115) + node T_1117 = mux(T_987, UInt<6>("h02c"), T_1116) + node T_1118 = mux(T_985, UInt<6>("h02d"), T_1117) + node T_1119 = mux(T_983, UInt<6>("h02e"), T_1118) + node T_1120 = mux(T_981, UInt<6>("h02f"), T_1119) + node T_1121 = mux(T_979, UInt<6>("h030"), T_1120) + node T_1122 = mux(T_977, UInt<6>("h031"), T_1121) + node T_1123 = mux(T_975, UInt<6>("h032"), T_1122) + node T_1124 = mux(T_973, UInt<6>("h033"), T_1123) + node T_1125 = mux(T_971, UInt<6>("h034"), T_1124) + node T_1126 = mux(T_969, UInt<6>("h035"), T_1125) + node T_1127 = mux(T_967, UInt<6>("h036"), T_1126) + node T_1128 = mux(T_965, UInt<6>("h037"), T_1127) + node T_1129 = mux(T_963, UInt<6>("h038"), T_1128) + node T_1130 = mux(T_961, UInt<6>("h039"), T_1129) + node T_1131 = mux(T_959, UInt<6>("h03a"), T_1130) + node T_1132 = mux(T_957, UInt<6>("h03b"), T_1131) + node T_1133 = mux(T_955, UInt<6>("h03c"), T_1132) + node T_1134 = mux(T_953, UInt<6>("h03d"), T_1133) + node T_1135 = mux(T_951, UInt<6>("h03e"), T_1134) + node T_1136 = mux(T_949, UInt<6>("h03f"), T_1135) + node T_1137 = not(T_1136) + node T_1138 = dshl(T_948, T_1137) + node T_1140 = bits(T_1138, 11, 10) + node T_1141 = bits(T_1138, 9, 0) + node T_1143 = neq(T_1141, UInt<1>("h00")) + node T_1144 = cat(T_1140, T_1143) + node T_1145 = bits(T_1144, 1, 0) + node T_1147 = neq(T_1145, UInt<1>("h00")) + node T_1148 = eq(in_1.bits.rm, UInt<2>("h00")) + node T_1149 = bits(T_1144, 2, 1) + node T_1150 = not(T_1149) + node T_1152 = eq(T_1150, UInt<1>("h00")) + node T_1153 = bits(T_1144, 1, 0) + node T_1154 = not(T_1153) + node T_1156 = eq(T_1154, UInt<1>("h00")) + node T_1157 = or(T_1152, T_1156) + node T_1158 = eq(in_1.bits.rm, UInt<2>("h02")) + node T_1159 = and(T_940, T_1147) + node T_1160 = eq(in_1.bits.rm, UInt<2>("h03")) + node T_1162 = eq(T_940, UInt<1>("h00")) + node T_1163 = and(T_1162, T_1147) + node T_1165 = mux(T_1160, T_1163, UInt<1>("h00")) + node T_1166 = mux(T_1158, T_1159, T_1165) + node T_1167 = mux(T_1148, T_1157, T_1166) + node T_1168 = bits(T_1138, 63, 11) + node T_1170 = cat(UInt<1>("h00"), T_1168) + node T_1172 = addw(T_1170, UInt<1>("h01")) + node T_1173 = mux(T_1167, T_1172, T_1170) + node T_1176 = not(T_1137) + node T_1178 = cat(UInt<4>("h00"), T_1176) + node T_1180 = cat(UInt<1>("h00"), T_1178) + node T_1181 = bit(T_1173, 53) + node T_1182 = addw(T_1180, T_1181) + node T_1183 = bit(T_1138, 63) + node T_1185 = bits(T_1182, 10, 0) + node T_1186 = mux(UInt<1>("h00"), UInt<11>("h0400"), T_1185) + node T_1187 = cat(T_1183, T_1186) + node T_1188 = or(UInt<1>("h00"), UInt<1>("h00")) + node T_1189 = or(T_1147, T_1188) + node T_1190 = bits(T_1173, 51, 0) + node T_1191 = cat(T_1187, T_1190) + node T_1192 = cat(T_940, T_1191) + node T_1195 = cat(UInt<2>("h00"), T_1188) + node T_1196 = cat(UInt<1>("h00"), T_1189) + node T_1197 = cat(T_1195, T_1196) + mux.data := T_1192 + mux.exc := T_1197 + skip + skip + reg T_1200 : UInt<1>, clock, reset + onreset T_1200 := UInt<1>("h00") + T_1200 := in_1.valid + reg T_1201 : {data : UInt<65>, exc : UInt<5>}, clock, reset + when in_1.valid : + T_1201 <> mux + skip + reg T_1206 : UInt<1>, clock, reset + onreset T_1206 := UInt<1>("h00") + T_1206 := T_1200 + reg T_1207 : {data : UInt<65>, exc : UInt<5>}, clock, reset + when T_1200 : + T_1207 <> T_1201 + skip + wire T_1218 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} + T_1218.bits.exc := UInt<1>("h00") + T_1218.bits.data := UInt<1>("h00") + T_1218.valid := UInt<1>("h00") + T_1218.valid := T_1206 + T_1218.bits <> T_1207 + out <> T_1218 + + module FPToFP : + input lt : UInt<1> + output out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} + input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} + input clock : Clock + input reset : UInt<1> + + out.bits.exc := UInt<1>("h00") + out.bits.data := UInt<1>("h00") + out.valid := UInt<1>("h00") + reg T_137 : UInt<1>, clock, reset + onreset T_137 := UInt<1>("h00") + T_137 := in.valid + reg T_138 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock, reset + when in.valid : + T_138 <> in.bits + skip + wire in_1 : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} + in_1.bits.in3 := UInt<1>("h00") + in_1.bits.in2 := UInt<1>("h00") + in_1.bits.in1 := UInt<1>("h00") + in_1.bits.typ := UInt<1>("h00") + in_1.bits.rm := UInt<1>("h00") + in_1.bits.wflags := UInt<1>("h00") + in_1.bits.round := UInt<1>("h00") + in_1.bits.sqrt := UInt<1>("h00") + in_1.bits.div := UInt<1>("h00") + in_1.bits.fma := UInt<1>("h00") + in_1.bits.fastpipe := UInt<1>("h00") + in_1.bits.toint := UInt<1>("h00") + in_1.bits.fromint := UInt<1>("h00") + in_1.bits.single := UInt<1>("h00") + in_1.bits.swap23 := UInt<1>("h00") + in_1.bits.swap12 := UInt<1>("h00") + in_1.bits.ren3 := UInt<1>("h00") + in_1.bits.ren2 := UInt<1>("h00") + in_1.bits.ren1 := UInt<1>("h00") + in_1.bits.wen := UInt<1>("h00") + in_1.bits.ldst := UInt<1>("h00") + in_1.bits.cmd := UInt<1>("h00") + in_1.valid := UInt<1>("h00") + in_1.valid := T_137 + in_1.bits <> T_138 + node T_282 = and(in_1.bits.cmd, UInt<3>("h05")) + node isSgnj = eq(UInt<3>("h04"), T_282) + node T_284 = and(in_1.bits.single, isSgnj) + node T_285 = bit(in_1.bits.rm, 1) + node T_287 = eq(T_284, UInt<1>("h00")) + node T_288 = or(T_285, T_287) + node T_289 = bit(in_1.bits.in1, 32) + node T_290 = bit(in_1.bits.rm, 0) + node T_291 = mux(T_288, T_289, T_290) + node T_292 = bit(in_1.bits.in2, 32) + node T_293 = and(T_284, T_292) + node sign_s = xor(T_291, T_293) + node T_296 = eq(in_1.bits.single, UInt<1>("h00")) + node T_297 = and(T_296, isSgnj) + node T_298 = bit(in_1.bits.rm, 1) + node T_300 = eq(T_297, UInt<1>("h00")) + node T_301 = or(T_298, T_300) + node T_302 = bit(in_1.bits.in1, 64) + node T_303 = bit(in_1.bits.rm, 0) + node T_304 = mux(T_301, T_302, T_303) + node T_305 = bit(in_1.bits.in2, 64) + node T_306 = and(T_297, T_305) + node sign_d = xor(T_304, T_306) + node T_308 = bits(in_1.bits.in1, 63, 33) + node T_309 = bits(in_1.bits.in1, 31, 0) + node T_310 = cat(sign_d, T_308) + node T_311 = cat(sign_s, T_309) + node fsgnj = cat(T_310, T_311) + node T_313 = bit(in_1.bits.in1, 32) + node T_314 = bits(in_1.bits.in1, 22, 0) + node T_315 = bits(in_1.bits.in1, 31, 23) + node T_316 = bits(in_1.bits.in1, 31, 29) + node T_317 = bits(in_1.bits.in1, 30, 23) + node T_318 = not(T_316) + node T_320 = eq(T_318, UInt<1>("h00")) + node T_321 = bit(T_314, 22) + node T_323 = eq(T_321, UInt<1>("h00")) + node T_324 = and(T_320, T_323) + node T_326 = lt(T_316, UInt<1>("h01")) + node T_328 = lt(T_316, UInt<3>("h04")) + node T_330 = cat(UInt<3>("h07"), T_317) + node T_332 = lt(T_316, UInt<3>("h06")) + node T_334 = cat(UInt<4>("h08"), T_317) + node T_336 = lt(T_316, UInt<3>("h07")) + node T_339 = mux(T_336, UInt<12>("h0c00"), UInt<12>("h0e00")) + node T_340 = mux(T_332, T_334, T_339) + node T_341 = mux(T_328, T_330, T_340) + node T_342 = mux(T_326, T_317, T_341) + node T_344 = subw(UInt<52>("h00"), T_320) + node T_345 = shl(T_314, 29) + node T_346 = or(T_344, T_345) + node T_347 = cat(T_342, T_346) + node T_348 = cat(T_313, T_347) + node T_349 = shl(T_324, 4) + node T_350 = bit(in_1.bits.in1, 64) + node T_351 = bits(in_1.bits.in1, 51, 0) + node T_352 = bits(in_1.bits.in1, 63, 52) + node T_353 = bits(in_1.bits.in1, 63, 61) + node T_354 = bits(in_1.bits.in1, 62, 52) + node T_355 = not(T_353) + node T_357 = eq(T_355, UInt<1>("h00")) + node T_358 = bit(T_351, 51) + node T_360 = eq(T_358, UInt<1>("h00")) + node T_361 = and(T_357, T_360) + node T_366 = neq(T_353, UInt<1>("h00")) + node T_368 = eq(T_366, UInt<1>("h00")) + node T_369 = bits(T_353, 2, 1) + node T_370 = not(T_369) + node T_372 = eq(T_370, UInt<1>("h00")) + node T_373 = or(T_368, T_372) + node T_374 = geq(T_352, UInt<11>("h076a")) + node T_375 = leq(T_352, UInt<11>("h0781")) + node T_376 = and(T_374, T_375) + node T_377 = lt(T_352, UInt<11>("h076a")) + node T_379 = eq(T_373, UInt<1>("h00")) + node T_380 = and(T_377, T_379) + node T_381 = gt(T_352, UInt<12>("h087f")) + node T_383 = eq(T_373, UInt<1>("h00")) + node T_384 = and(T_381, T_383) + node T_386 = addw(UInt<11>("h0781"), UInt<1>("h01")) + node T_387 = subw(T_386, T_352) + node T_389 = mux(T_376, T_387, UInt<1>("h00")) + node T_390 = bits(T_389, 4, 0) + node T_392 = bits(T_351, 51, 28) + node T_394 = cat(T_392, UInt<24>("h00")) + node T_395 = cat(UInt<1>("h01"), T_394) + node T_396 = dshr(T_395, T_390) + node T_397 = bits(T_396, 23, 0) + node T_399 = neq(T_397, UInt<1>("h00")) + node T_400 = bits(T_351, 27, 0) + node T_402 = neq(T_400, UInt<1>("h00")) + node T_403 = or(T_399, T_402) + node T_404 = bits(T_396, 25, 24) + node T_405 = cat(T_404, T_403) + node T_406 = bits(T_405, 1, 0) + node T_408 = neq(T_406, UInt<1>("h00")) + node T_410 = eq(T_373, UInt<1>("h00")) + node T_411 = and(T_408, T_410) + node T_412 = eq(in_1.bits.rm, UInt<2>("h00")) + node T_413 = bits(T_405, 1, 0) + node T_414 = not(T_413) + node T_416 = eq(T_414, UInt<1>("h00")) + node T_417 = bits(T_405, 2, 1) + node T_418 = not(T_417) + node T_420 = eq(T_418, UInt<1>("h00")) + node T_421 = or(T_416, T_420) + node T_422 = eq(in_1.bits.rm, UInt<2>("h02")) + node T_423 = and(T_350, T_411) + node T_424 = eq(in_1.bits.rm, UInt<2>("h03")) + node T_426 = eq(T_350, UInt<1>("h00")) + node T_427 = and(T_426, T_411) + node T_429 = mux(T_424, T_427, UInt<1>("h00")) + node T_430 = mux(T_422, T_423, T_429) + node T_431 = mux(T_412, T_421, T_430) + node T_433 = cat(UInt<1>("h01"), UInt<1>("h01")) + node T_434 = cat(T_433, T_433) + node T_435 = cat(T_434, T_434) + node T_436 = cat(T_435, T_435) + node T_437 = cat(T_435, T_436) + node T_438 = cat(UInt<1>("h01"), T_437) + node T_439 = dshl(T_438, T_390) + node T_440 = bits(T_439, 24, 0) + node T_442 = bits(T_351, 51, 29) + node T_443 = cat(UInt<2>("h01"), T_442) + node T_444 = not(T_440) + node T_445 = or(T_443, T_444) + node T_447 = addw(T_445, UInt<1>("h01")) + node T_448 = mux(T_431, T_447, T_445) + node T_449 = bits(T_352, 8, 0) + node T_451 = addw(T_449, UInt<9>("h0100")) + node T_452 = bit(T_448, 24) + node T_454 = addw(T_451, UInt<1>("h01")) + node T_455 = mux(T_452, T_454, T_451) + node T_456 = eq(in_1.bits.rm, UInt<2>("h02")) + node T_457 = and(T_456, T_350) + node T_458 = eq(in_1.bits.rm, UInt<2>("h03")) + node T_460 = eq(T_350, UInt<1>("h00")) + node T_461 = and(T_458, T_460) + node T_462 = or(T_457, T_461) + node T_463 = eq(in_1.bits.rm, UInt<2>("h00")) + node T_464 = or(T_462, T_463) + node T_466 = eq(T_464, UInt<1>("h00")) + node T_468 = subw(UInt<23>("h00"), T_466) + node T_471 = mux(T_464, UInt<9>("h0180"), UInt<9>("h017f")) + node T_475 = mux(T_462, UInt<7>("h06b"), UInt<1>("h00")) + node T_476 = shl(T_353, 6) + node T_477 = mux(T_380, T_475, T_455) + node T_478 = mux(T_384, T_471, T_477) + node T_479 = mux(T_373, T_476, T_478) + node T_481 = subw(UInt<23>("h00"), T_357) + node T_482 = bits(T_448, 22, 0) + node T_483 = mux(T_380, UInt<1>("h00"), T_482) + node T_484 = mux(T_384, T_468, T_483) + node T_485 = mux(T_373, T_481, T_484) + node T_486 = cat(T_479, T_485) + node T_487 = cat(T_350, T_486) + node T_488 = and(T_376, T_411) + node T_489 = or(T_380, T_488) + node T_490 = eq(T_352, UInt<12>("h087f")) + node T_491 = bit(T_448, 24) + node T_492 = and(T_490, T_491) + node T_493 = or(T_384, T_492) + node T_495 = or(T_411, T_384) + node T_496 = or(T_495, T_380) + node T_497 = cat(T_361, UInt<1>("h00")) + node T_498 = cat(T_489, T_496) + node T_499 = cat(T_493, T_498) + node T_500 = cat(T_497, T_499) + node T_501 = bits(in_1.bits.in1, 31, 29) + node T_502 = not(T_501) + node T_504 = eq(T_502, UInt<1>("h00")) + node T_505 = bits(in_1.bits.in1, 63, 61) + node T_506 = not(T_505) + node T_508 = eq(T_506, UInt<1>("h00")) + node isnan1 = mux(in_1.bits.single, T_504, T_508) + node T_510 = bits(in_1.bits.in2, 31, 29) + node T_511 = not(T_510) + node T_513 = eq(T_511, UInt<1>("h00")) + node T_514 = bits(in_1.bits.in2, 63, 61) + node T_515 = not(T_514) + node T_517 = eq(T_515, UInt<1>("h00")) + node isnan2 = mux(in_1.bits.single, T_513, T_517) + node T_519 = bit(in_1.bits.in1, 22) + node T_520 = bit(in_1.bits.in1, 51) + node T_521 = mux(in_1.bits.single, T_519, T_520) + node T_522 = not(T_521) + node issnan1 = and(isnan1, T_522) + node T_524 = bit(in_1.bits.in2, 22) + node T_525 = bit(in_1.bits.in2, 51) + node T_526 = mux(in_1.bits.single, T_524, T_525) + node T_527 = not(T_526) + node issnan2 = and(isnan2, T_527) + node T_529 = or(issnan1, issnan2) + node minmax_exc = cat(T_529, UInt<4>("h00")) + node isMax = bit(in_1.bits.rm, 0) + node T_533 = neq(isMax, lt) + node T_535 = eq(isnan1, UInt<1>("h00")) + node T_536 = and(T_533, T_535) + node isLHS = or(isnan2, T_536) + wire mux : {data : UInt<65>, exc : UInt<5>} + mux.exc := UInt<1>("h00") + mux.data := UInt<1>("h00") + mux.exc := minmax_exc + mux.data := in_1.bits.in2 + when isSgnj : + mux.exc := UInt<1>("h00") + skip + node T_547 = or(isSgnj, isLHS) + when T_547 : + mux.data := fsgnj + skip + node T_550 = and(in_1.bits.cmd, UInt<3>("h04")) + node T_551 = eq(UInt<1>("h00"), T_550) + when T_551 : + when in_1.bits.single : + node T_553 = asUInt(asSInt(UInt<32>("h0ffffffff"))) + node T_554 = cat(T_553, T_487) + mux.data := T_554 + mux.exc := T_500 + skip + else : + mux.data := T_348 + mux.exc := T_349 + skip + skip + reg T_557 : UInt<1>, clock, reset + onreset T_557 := UInt<1>("h00") + T_557 := in_1.valid + reg T_558 : {data : UInt<65>, exc : UInt<5>}, clock, reset + when in_1.valid : + T_558 <> mux + skip + wire T_569 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} + T_569.bits.exc := UInt<1>("h00") + T_569.bits.data := UInt<1>("h00") + T_569.valid := UInt<1>("h00") + T_569.valid := T_557 + T_569.bits <> T_558 + out <> T_569 + + module divSqrtRecodedFloat64_mulAddZ31 : + input mulAddResult_3 : UInt<105> + output mulAddC_2 : UInt<105> + output mulAddB_0 : UInt<54> + output latchMulAddB_0 : UInt<1> + output mulAddA_0 : UInt<54> + output latchMulAddA_0 : UInt<1> + output usingMulAdd : UInt<4> + output exceptionFlags : UInt<5> + output out : UInt<65> + output outValid_sqrt : UInt<1> + output outValid_div : UInt<1> + input roundingMode : UInt<2> + input b : UInt<65> + input a : UInt<65> + input sqrtOp : UInt<1> + input inValid : UInt<1> + output inReady_sqrt : UInt<1> + output inReady_div : UInt<1> + input clock : Clock + input reset : UInt<1> + + mulAddC_2 := UInt<1>("h00") + mulAddB_0 := UInt<1>("h00") + latchMulAddB_0 := UInt<1>("h00") + mulAddA_0 := UInt<1>("h00") + latchMulAddA_0 := UInt<1>("h00") + usingMulAdd := UInt<1>("h00") + exceptionFlags := UInt<1>("h00") + out := UInt<1>("h00") + outValid_sqrt := UInt<1>("h00") + outValid_div := UInt<1>("h00") + inReady_sqrt := UInt<1>("h00") + inReady_div := UInt<1>("h00") + reg valid_PA : UInt<1>, clock, reset + onreset valid_PA := UInt<1>("h00") + reg sqrtOp_PA : UInt<1>, clock, reset + reg sign_PA : UInt<1>, clock, reset + reg specialCodeB_PA : UInt<3>, clock, reset + reg fractB_51_PA : UInt<1>, clock, reset + reg roundingMode_PA : UInt<2>, clock, reset + reg specialCodeA_PA : UInt<3>, clock, reset + reg fractA_51_PA : UInt<1>, clock, reset + reg exp_PA : UInt<14>, clock, reset + reg fractB_other_PA : UInt<51>, clock, reset + reg fractA_other_PA : UInt<51>, clock, reset + reg valid_PB : UInt<1>, clock, reset + onreset valid_PB := UInt<1>("h00") + reg sqrtOp_PB : UInt<1>, clock, reset + reg sign_PB : UInt<1>, clock, reset + reg specialCodeA_PB : UInt<3>, clock, reset + reg fractA_51_PB : UInt<1>, clock, reset + reg specialCodeB_PB : UInt<3>, clock, reset + reg fractB_51_PB : UInt<1>, clock, reset + reg roundingMode_PB : UInt<2>, clock, reset + reg exp_PB : UInt<14>, clock, reset + reg fractA_0_PB : UInt<1>, clock, reset + reg fractB_other_PB : UInt<51>, clock, reset + reg valid_PC : UInt<1>, clock, reset + onreset valid_PC := UInt<1>("h00") + reg sqrtOp_PC : UInt<1>, clock, reset + reg sign_PC : UInt<1>, clock, reset + reg specialCodeA_PC : UInt<3>, clock, reset + reg fractA_51_PC : UInt<1>, clock, reset + reg specialCodeB_PC : UInt<3>, clock, reset + reg fractB_51_PC : UInt<1>, clock, reset + reg roundingMode_PC : UInt<2>, clock, reset + reg exp_PC : UInt<14>, clock, reset + reg fractA_0_PC : UInt<1>, clock, reset + reg fractB_other_PC : UInt<51>, clock, reset + reg cycleNum_A : UInt<3>, clock, reset + onreset cycleNum_A := UInt<3>("h00") + reg cycleNum_B : UInt<4>, clock, reset + onreset cycleNum_B := UInt<4>("h00") + reg cycleNum_C : UInt<3>, clock, reset + onreset cycleNum_C := UInt<3>("h00") + reg cycleNum_E : UInt<3>, clock, reset + onreset cycleNum_E := UInt<3>("h00") + reg fractR0_A : UInt<9>, clock, reset + reg hiSqrR0_A_sqrt : UInt<10>, clock, reset + reg partNegSigma0_A : UInt<21>, clock, reset + reg nextMulAdd9A_A : UInt<9>, clock, reset + reg nextMulAdd9B_A : UInt<9>, clock, reset + reg ER1_B_sqrt : UInt<17>, clock, reset + reg ESqrR1_B_sqrt : UInt<32>, clock, reset + reg sigX1_B : UInt<58>, clock, reset + reg sqrSigma1_C : UInt<33>, clock, reset + reg sigXN_C : UInt<58>, clock, reset + reg u_C_sqrt : UInt<31>, clock, reset + reg E_E_div : UInt<1>, clock, reset + reg sigT_E : UInt<53>, clock, reset + reg extraT_E : UInt<1>, clock, reset + reg isNegRemT_E : UInt<1>, clock, reset + reg trueEqX_E1 : UInt<1>, clock, reset + wire ready_PA : UInt<1> + ready_PA := UInt<1>("h00") + wire ready_PB : UInt<1> + ready_PB := UInt<1>("h00") + wire ready_PC : UInt<1> + ready_PC := UInt<1>("h00") + wire leaving_PA : UInt<1> + leaving_PA := UInt<1>("h00") + wire leaving_PB : UInt<1> + leaving_PB := UInt<1>("h00") + wire leaving_PC : UInt<1> + leaving_PC := UInt<1>("h00") + wire cyc_B10_sqrt : UInt<1> + cyc_B10_sqrt := UInt<1>("h00") + wire cyc_B9_sqrt : UInt<1> + cyc_B9_sqrt := UInt<1>("h00") + wire cyc_B8_sqrt : UInt<1> + cyc_B8_sqrt := UInt<1>("h00") + wire cyc_B7_sqrt : UInt<1> + cyc_B7_sqrt := UInt<1>("h00") + wire cyc_B6 : UInt<1> + cyc_B6 := UInt<1>("h00") + wire cyc_B5 : UInt<1> + cyc_B5 := UInt<1>("h00") + wire cyc_B4 : UInt<1> + cyc_B4 := UInt<1>("h00") + wire cyc_B3 : UInt<1> + cyc_B3 := UInt<1>("h00") + wire cyc_B2 : UInt<1> + cyc_B2 := UInt<1>("h00") + wire cyc_B1 : UInt<1> + cyc_B1 := UInt<1>("h00") + wire cyc_B6_div : UInt<1> + cyc_B6_div := UInt<1>("h00") + wire cyc_B5_div : UInt<1> + cyc_B5_div := UInt<1>("h00") + wire cyc_B4_div : UInt<1> + cyc_B4_div := UInt<1>("h00") + wire cyc_B3_div : UInt<1> + cyc_B3_div := UInt<1>("h00") + wire cyc_B2_div : UInt<1> + cyc_B2_div := UInt<1>("h00") + wire cyc_B1_div : UInt<1> + cyc_B1_div := UInt<1>("h00") + wire cyc_B6_sqrt : UInt<1> + cyc_B6_sqrt := UInt<1>("h00") + wire cyc_B5_sqrt : UInt<1> + cyc_B5_sqrt := UInt<1>("h00") + wire cyc_B4_sqrt : UInt<1> + cyc_B4_sqrt := UInt<1>("h00") + wire cyc_B3_sqrt : UInt<1> + cyc_B3_sqrt := UInt<1>("h00") + wire cyc_B2_sqrt : UInt<1> + cyc_B2_sqrt := UInt<1>("h00") + wire cyc_B1_sqrt : UInt<1> + cyc_B1_sqrt := UInt<1>("h00") + wire cyc_C5 : UInt<1> + cyc_C5 := UInt<1>("h00") + wire cyc_C4 : UInt<1> + cyc_C4 := UInt<1>("h00") + wire valid_normalCase_leaving_PB : UInt<1> + valid_normalCase_leaving_PB := UInt<1>("h00") + wire cyc_C2 : UInt<1> + cyc_C2 := UInt<1>("h00") + wire cyc_C1 : UInt<1> + cyc_C1 := UInt<1>("h00") + wire cyc_E4 : UInt<1> + cyc_E4 := UInt<1>("h00") + wire cyc_E3 : UInt<1> + cyc_E3 := UInt<1>("h00") + wire cyc_E2 : UInt<1> + cyc_E2 := UInt<1>("h00") + wire cyc_E1 : UInt<1> + cyc_E1 := UInt<1>("h00") + wire zSigma1_B4 : UInt<?> + zSigma1_B4 := UInt<1>("h00") + wire sigXNU_B3_CX : UInt<?> + sigXNU_B3_CX := UInt<1>("h00") + wire zComplSigT_C1_sqrt : UInt<?> + zComplSigT_C1_sqrt := UInt<1>("h00") + wire zComplSigT_C1 : UInt<?> + zComplSigT_C1 := UInt<1>("h00") + node T_250 = not(cyc_B6_sqrt) + node T_251 = and(ready_PA, T_250) + node T_252 = not(cyc_B5_sqrt) + node T_253 = and(T_251, T_252) + node T_254 = not(cyc_B4_sqrt) + node T_255 = and(T_253, T_254) + node T_256 = not(cyc_B3) + node T_257 = and(T_255, T_256) + node T_258 = not(cyc_B2) + node T_259 = and(T_257, T_258) + node T_260 = not(cyc_B1_sqrt) + node T_261 = and(T_259, T_260) + node T_262 = not(cyc_C5) + node T_263 = and(T_261, T_262) + node T_264 = not(cyc_C4) + node T_265 = and(T_263, T_264) + inReady_div := T_265 + node T_266 = not(cyc_B6_sqrt) + node T_267 = and(ready_PA, T_266) + node T_268 = not(cyc_B5_sqrt) + node T_269 = and(T_267, T_268) + node T_270 = not(cyc_B4_sqrt) + node T_271 = and(T_269, T_270) + node T_272 = not(cyc_B2_div) + node T_273 = and(T_271, T_272) + node T_274 = not(cyc_B1_sqrt) + node T_275 = and(T_273, T_274) + inReady_sqrt := T_275 + node T_276 = and(inReady_div, inValid) + node T_277 = not(sqrtOp) + node cyc_S_div = and(T_276, T_277) + node T_279 = and(inReady_sqrt, inValid) + node cyc_S_sqrt = and(T_279, sqrtOp) + node cyc_S = or(cyc_S_div, cyc_S_sqrt) + node signA_S = bit(a, 64) + node expA_S = bits(a, 63, 52) + node fractA_S = bits(a, 51, 0) + node specialCodeA_S = bits(expA_S, 11, 9) + node isZeroA_S = eq(specialCodeA_S, UInt<3>("h00")) + node T_288 = bits(specialCodeA_S, 2, 1) + node isSpecialA_S = eq(T_288, UInt<2>("h03")) + node signB_S = bit(b, 64) + node expB_S = bits(b, 63, 52) + node fractB_S = bits(b, 51, 0) + node specialCodeB_S = bits(expB_S, 11, 9) + node isZeroB_S = eq(specialCodeB_S, UInt<3>("h00")) + node T_297 = bits(specialCodeB_S, 2, 1) + node isSpecialB_S = eq(T_297, UInt<2>("h03")) + node T_300 = xor(signA_S, signB_S) + node sign_S = mux(sqrtOp, signB_S, T_300) + node T_302 = not(isSpecialA_S) + node T_303 = not(isSpecialB_S) + node T_304 = and(T_302, T_303) + node T_305 = not(isZeroA_S) + node T_306 = and(T_304, T_305) + node T_307 = not(isZeroB_S) + node normalCase_S_div = and(T_306, T_307) + node T_309 = not(isSpecialB_S) + node T_310 = not(isZeroB_S) + node T_311 = and(T_309, T_310) + node T_312 = not(signB_S) + node normalCase_S_sqrt = and(T_311, T_312) + node normalCase_S = mux(sqrtOp, normalCase_S_sqrt, normalCase_S_div) + node entering_PA_normalCase_div = and(cyc_S_div, normalCase_S_div) + node entering_PA_normalCase_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt) + node entering_PA_normalCase = or(entering_PA_normalCase_div, entering_PA_normalCase_sqrt) + node T_318 = not(ready_PB) + node T_319 = or(valid_PA, T_318) + node T_320 = and(cyc_S, T_319) + node entering_PA = or(entering_PA_normalCase, T_320) + node T_322 = not(normalCase_S) + node T_323 = and(cyc_S, T_322) + node T_324 = not(valid_PA) + node T_325 = and(T_323, T_324) + node T_326 = not(valid_PB) + node T_327 = not(ready_PC) + node T_328 = and(T_326, T_327) + node T_329 = or(leaving_PB, T_328) + node entering_PB_S = and(T_325, T_329) + node T_331 = not(normalCase_S) + node T_332 = and(cyc_S, T_331) + node T_333 = not(valid_PA) + node T_334 = and(T_332, T_333) + node T_335 = not(valid_PB) + node T_336 = and(T_334, T_335) + node entering_PC_S = and(T_336, ready_PC) + node T_338 = or(entering_PA, leaving_PA) + when T_338 : + valid_PA := entering_PA + skip + when entering_PA : + sqrtOp_PA := sqrtOp + sign_PA := sign_S + specialCodeB_PA := specialCodeB_S + node T_339 = bit(fractB_S, 51) + fractB_51_PA := T_339 + roundingMode_PA := roundingMode + skip + node T_340 = not(sqrtOp) + node T_341 = and(entering_PA, T_340) + when T_341 : + specialCodeA_PA := specialCodeA_S + node T_342 = bit(fractA_S, 51) + fractA_51_PA := T_342 + skip + when entering_PA_normalCase : + node T_343 = bit(expB_S, 11) + node T_345 = subw(UInt<3>("h00"), T_343) + node T_346 = bits(expB_S, 10, 0) + node T_347 = not(T_346) + node T_348 = cat(T_345, T_347) + node T_349 = addw(expA_S, T_348) + node T_350 = mux(sqrtOp, expB_S, T_349) + exp_PA := T_350 + node T_351 = bits(fractB_S, 50, 0) + fractB_other_PA := T_351 + skip + when entering_PA_normalCase_div : + node T_352 = bits(fractA_S, 50, 0) + fractA_other_PA := T_352 + skip + node isZeroA_PA = eq(specialCodeA_PA, UInt<3>("h00")) + node T_355 = bits(specialCodeA_PA, 2, 1) + node isSpecialA_PA = eq(T_355, UInt<2>("h03")) + node T_359 = cat(fractA_51_PA, fractA_other_PA) + node sigA_PA = cat(UInt<1>("h01"), T_359) + node isZeroB_PA = eq(specialCodeB_PA, UInt<3>("h00")) + node T_363 = bits(specialCodeB_PA, 2, 1) + node isSpecialB_PA = eq(T_363, UInt<2>("h03")) + node T_367 = cat(fractB_51_PA, fractB_other_PA) + node sigB_PA = cat(UInt<1>("h01"), T_367) + node T_369 = not(isSpecialB_PA) + node T_370 = not(isZeroB_PA) + node T_371 = and(T_369, T_370) + node T_372 = not(sign_PA) + node T_373 = and(T_371, T_372) + node T_374 = not(isSpecialA_PA) + node T_375 = not(isSpecialB_PA) + node T_376 = and(T_374, T_375) + node T_377 = not(isZeroA_PA) + node T_378 = and(T_376, T_377) + node T_379 = not(isZeroB_PA) + node T_380 = and(T_378, T_379) + node normalCase_PA = mux(sqrtOp_PA, T_373, T_380) + node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt) + node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB) + node T_384 = and(valid_PA, valid_leaving_PA) + leaving_PA := T_384 + node T_385 = not(valid_PA) + node T_386 = or(T_385, valid_leaving_PA) + ready_PA := T_386 + node T_387 = and(valid_PA, normalCase_PA) + node entering_PB_normalCase = and(T_387, valid_normalCase_leaving_PA) + node entering_PB = or(entering_PB_S, leaving_PA) + node T_390 = or(entering_PB, leaving_PB) + when T_390 : + valid_PB := entering_PB + skip + when entering_PB : + node T_391 = mux(valid_PA, sqrtOp_PA, sqrtOp) + sqrtOp_PB := T_391 + node T_392 = mux(valid_PA, sign_PA, sign_S) + sign_PB := T_392 + node T_393 = mux(valid_PA, specialCodeA_PA, specialCodeA_S) + specialCodeA_PB := T_393 + node T_394 = bit(fractA_S, 51) + node T_395 = mux(valid_PA, fractA_51_PA, T_394) + fractA_51_PB := T_395 + node T_396 = mux(valid_PA, specialCodeB_PA, specialCodeB_S) + specialCodeB_PB := T_396 + node T_397 = bit(fractB_S, 51) + node T_398 = mux(valid_PA, fractB_51_PA, T_397) + fractB_51_PB := T_398 + node T_399 = mux(valid_PA, roundingMode_PA, roundingMode) + roundingMode_PB := T_399 + skip + when entering_PB_normalCase : + exp_PB := exp_PA + node T_400 = bit(fractA_other_PA, 0) + fractA_0_PB := T_400 + fractB_other_PB := fractB_other_PA + skip + node isZeroA_PB = eq(specialCodeA_PB, UInt<3>("h00")) + node T_403 = bits(specialCodeA_PB, 2, 1) + node isSpecialA_PB = eq(T_403, UInt<2>("h03")) + node isZeroB_PB = eq(specialCodeB_PB, UInt<3>("h00")) + node T_408 = bits(specialCodeB_PB, 2, 1) + node isSpecialB_PB = eq(T_408, UInt<2>("h03")) + node T_411 = not(isSpecialB_PB) + node T_412 = not(isZeroB_PB) + node T_413 = and(T_411, T_412) + node T_414 = not(sign_PB) + node T_415 = and(T_413, T_414) + node T_416 = not(isSpecialA_PB) + node T_417 = not(isSpecialB_PB) + node T_418 = and(T_416, T_417) + node T_419 = not(isZeroA_PB) + node T_420 = and(T_418, T_419) + node T_421 = not(isZeroB_PB) + node T_422 = and(T_420, T_421) + node normalCase_PB = mux(sqrtOp_PB, T_415, T_422) + node valid_leaving_PB = mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC) + node T_425 = and(valid_PB, valid_leaving_PB) + leaving_PB := T_425 + node T_426 = not(valid_PB) + node T_427 = or(T_426, valid_leaving_PB) + ready_PB := T_427 + node T_428 = and(valid_PB, normalCase_PB) + node entering_PC_normalCase = and(T_428, valid_normalCase_leaving_PB) + node entering_PC = or(entering_PC_S, leaving_PB) + node T_431 = or(entering_PC, leaving_PC) + when T_431 : + valid_PC := entering_PC + skip + when entering_PC : + node T_432 = mux(valid_PB, sqrtOp_PB, sqrtOp) + sqrtOp_PC := T_432 + node T_433 = mux(valid_PB, sign_PB, sign_S) + sign_PC := T_433 + node T_434 = mux(valid_PB, specialCodeA_PB, specialCodeA_S) + specialCodeA_PC := T_434 + node T_435 = bit(fractA_S, 51) + node T_436 = mux(valid_PB, fractA_51_PB, T_435) + fractA_51_PC := T_436 + node T_437 = mux(valid_PB, specialCodeB_PB, specialCodeB_S) + specialCodeB_PC := T_437 + node T_438 = bit(fractB_S, 51) + node T_439 = mux(valid_PB, fractB_51_PB, T_438) + fractB_51_PC := T_439 + node T_440 = mux(valid_PB, roundingMode_PB, roundingMode) + roundingMode_PC := T_440 + skip + when entering_PC_normalCase : + exp_PC := exp_PB + fractA_0_PC := fractA_0_PB + fractB_other_PC := fractB_other_PB + skip + node isZeroA_PC = eq(specialCodeA_PC, UInt<3>("h00")) + node T_443 = bits(specialCodeA_PC, 2, 1) + node isSpecialA_PC = eq(T_443, UInt<2>("h03")) + node T_446 = bit(specialCodeA_PC, 0) + node T_447 = not(T_446) + node isInfA_PC = and(isSpecialA_PC, T_447) + node T_449 = bit(specialCodeA_PC, 0) + node isNaNA_PC = and(isSpecialA_PC, T_449) + node T_451 = not(fractA_51_PC) + node isSigNaNA_PC = and(isNaNA_PC, T_451) + node isZeroB_PC = eq(specialCodeB_PC, UInt<3>("h00")) + node T_455 = bits(specialCodeB_PC, 2, 1) + node isSpecialB_PC = eq(T_455, UInt<2>("h03")) + node T_458 = bit(specialCodeB_PC, 0) + node T_459 = not(T_458) + node isInfB_PC = and(isSpecialB_PC, T_459) + node T_461 = bit(specialCodeB_PC, 0) + node isNaNB_PC = and(isSpecialB_PC, T_461) + node T_463 = not(fractB_51_PC) + node isSigNaNB_PC = and(isNaNB_PC, T_463) + node T_466 = cat(fractB_51_PC, fractB_other_PC) + node sigB_PC = cat(UInt<1>("h01"), T_466) + node T_468 = not(isSpecialB_PC) + node T_469 = not(isZeroB_PC) + node T_470 = and(T_468, T_469) + node T_471 = not(sign_PC) + node T_472 = and(T_470, T_471) + node T_473 = not(isSpecialA_PC) + node T_474 = not(isSpecialB_PC) + node T_475 = and(T_473, T_474) + node T_476 = not(isZeroA_PC) + node T_477 = and(T_475, T_476) + node T_478 = not(isZeroB_PC) + node T_479 = and(T_477, T_478) + node normalCase_PC = mux(sqrtOp_PC, T_472, T_479) + node expP2_PC = addw(exp_PC, UInt<2>("h02")) + node T_483 = bit(exp_PC, 0) + node T_484 = bits(expP2_PC, 13, 1) + node T_486 = cat(T_484, UInt<1>("h00")) + node T_487 = bits(exp_PC, 13, 1) + node T_489 = cat(T_487, UInt<1>("h01")) + node expP1_PC = mux(T_483, T_486, T_489) + node roundingMode_near_even_PC = eq(roundingMode_PC, UInt<2>("h00")) + node roundingMode_minMag_PC = eq(roundingMode_PC, UInt<2>("h01")) + node roundingMode_min_PC = eq(roundingMode_PC, UInt<2>("h02")) + node roundingMode_max_PC = eq(roundingMode_PC, UInt<2>("h03")) + node roundMagUp_PC = mux(sign_PC, roundingMode_min_PC, roundingMode_max_PC) + node overflowY_roundMagUp_PC = or(roundingMode_near_even_PC, roundMagUp_PC) + node T_497 = not(roundMagUp_PC) + node T_498 = not(roundingMode_near_even_PC) + node roundMagDown_PC = and(T_497, T_498) + node T_500 = not(normalCase_PC) + node valid_leaving_PC = or(T_500, cyc_E1) + node T_502 = and(valid_PC, valid_leaving_PC) + leaving_PC := T_502 + node T_503 = not(valid_PC) + node T_504 = or(T_503, valid_leaving_PC) + ready_PC := T_504 + node T_505 = not(sqrtOp_PC) + node T_506 = and(leaving_PC, T_505) + outValid_div := T_506 + node T_507 = and(leaving_PC, sqrtOp_PC) + outValid_sqrt := T_507 + node T_509 = neq(cycleNum_A, UInt<1>("h00")) + node T_510 = or(entering_PA_normalCase, T_509) + when T_510 : + node T_513 = mux(entering_PA_normalCase_div, UInt<2>("h03"), UInt<1>("h00")) + node T_516 = mux(entering_PA_normalCase_sqrt, UInt<3>("h06"), UInt<1>("h00")) + node T_517 = or(T_513, T_516) + node T_518 = not(entering_PA_normalCase) + node T_520 = subw(cycleNum_A, UInt<1>("h01")) + node T_522 = mux(T_518, T_520, UInt<1>("h00")) + node T_523 = or(T_517, T_522) + cycleNum_A := T_523 + skip + node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>("h06")) + node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>("h05")) + node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>("h04")) + node cyc_A4 = or(cyc_A4_sqrt, entering_PA_normalCase_div) + node cyc_A3 = eq(cycleNum_A, UInt<2>("h03")) + node cyc_A2 = eq(cycleNum_A, UInt<2>("h02")) + node cyc_A1 = eq(cycleNum_A, UInt<1>("h01")) + node T_537 = not(sqrtOp_PA) + node cyc_A3_div = and(cyc_A3, T_537) + node T_539 = not(sqrtOp_PA) + node cyc_A2_div = and(cyc_A2, T_539) + node T_541 = not(sqrtOp_PA) + node cyc_A1_div = and(cyc_A1, T_541) + node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA) + node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA) + node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA) + node T_547 = neq(cycleNum_B, UInt<1>("h00")) + node T_548 = or(cyc_A1, T_547) + when T_548 : + node T_551 = mux(sqrtOp_PA, UInt<4>("h0a"), UInt<3>("h06")) + node T_553 = subw(cycleNum_B, UInt<1>("h01")) + node T_554 = mux(cyc_A1, T_551, T_553) + cycleNum_B := T_554 + skip + node T_556 = eq(cycleNum_B, UInt<4>("h0a")) + cyc_B10_sqrt := T_556 + node T_558 = eq(cycleNum_B, UInt<4>("h09")) + cyc_B9_sqrt := T_558 + node T_560 = eq(cycleNum_B, UInt<4>("h08")) + cyc_B8_sqrt := T_560 + node T_562 = eq(cycleNum_B, UInt<3>("h07")) + cyc_B7_sqrt := T_562 + node T_564 = eq(cycleNum_B, UInt<3>("h06")) + cyc_B6 := T_564 + node T_566 = eq(cycleNum_B, UInt<3>("h05")) + cyc_B5 := T_566 + node T_568 = eq(cycleNum_B, UInt<3>("h04")) + cyc_B4 := T_568 + node T_570 = eq(cycleNum_B, UInt<2>("h03")) + cyc_B3 := T_570 + node T_572 = eq(cycleNum_B, UInt<2>("h02")) + cyc_B2 := T_572 + node T_574 = eq(cycleNum_B, UInt<1>("h01")) + cyc_B1 := T_574 + node T_575 = and(cyc_B6, valid_PA) + node T_576 = not(sqrtOp_PA) + node T_577 = and(T_575, T_576) + cyc_B6_div := T_577 + node T_578 = and(cyc_B5, valid_PA) + node T_579 = not(sqrtOp_PA) + node T_580 = and(T_578, T_579) + cyc_B5_div := T_580 + node T_581 = and(cyc_B4, valid_PA) + node T_582 = not(sqrtOp_PA) + node T_583 = and(T_581, T_582) + cyc_B4_div := T_583 + node T_584 = not(sqrtOp_PB) + node T_585 = and(cyc_B3, T_584) + cyc_B3_div := T_585 + node T_586 = not(sqrtOp_PB) + node T_587 = and(cyc_B2, T_586) + cyc_B2_div := T_587 + node T_588 = not(sqrtOp_PB) + node T_589 = and(cyc_B1, T_588) + cyc_B1_div := T_589 + node T_590 = and(cyc_B6, valid_PB) + node T_591 = and(T_590, sqrtOp_PB) + cyc_B6_sqrt := T_591 + node T_592 = and(cyc_B5, valid_PB) + node T_593 = and(T_592, sqrtOp_PB) + cyc_B5_sqrt := T_593 + node T_594 = and(cyc_B4, valid_PB) + node T_595 = and(T_594, sqrtOp_PB) + cyc_B4_sqrt := T_595 + node T_596 = and(cyc_B3, sqrtOp_PB) + cyc_B3_sqrt := T_596 + node T_597 = and(cyc_B2, sqrtOp_PB) + cyc_B2_sqrt := T_597 + node T_598 = and(cyc_B1, sqrtOp_PB) + cyc_B1_sqrt := T_598 + node T_600 = neq(cycleNum_C, UInt<1>("h00")) + node T_601 = or(cyc_B1, T_600) + when T_601 : + node T_604 = mux(sqrtOp_PB, UInt<3>("h06"), UInt<3>("h05")) + node T_606 = subw(cycleNum_C, UInt<1>("h01")) + node T_607 = mux(cyc_B1, T_604, T_606) + cycleNum_C := T_607 + skip + node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>("h06")) + node T_611 = eq(cycleNum_C, UInt<3>("h05")) + cyc_C5 := T_611 + node T_613 = eq(cycleNum_C, UInt<3>("h04")) + cyc_C4 := T_613 + node T_615 = eq(cycleNum_C, UInt<2>("h03")) + valid_normalCase_leaving_PB := T_615 + node T_617 = eq(cycleNum_C, UInt<2>("h02")) + cyc_C2 := T_617 + node T_619 = eq(cycleNum_C, UInt<1>("h01")) + cyc_C1 := T_619 + node T_620 = not(sqrtOp_PB) + node cyc_C5_div = and(cyc_C5, T_620) + node T_622 = not(sqrtOp_PB) + node cyc_C4_div = and(cyc_C4, T_622) + node T_624 = not(sqrtOp_PB) + node cyc_C3_div = and(valid_normalCase_leaving_PB, T_624) + node T_626 = not(sqrtOp_PC) + node cyc_C2_div = and(cyc_C2, T_626) + node T_628 = not(sqrtOp_PC) + node cyc_C1_div = and(cyc_C1, T_628) + node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB) + node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB) + node cyc_C3_sqrt = and(valid_normalCase_leaving_PB, sqrtOp_PB) + node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC) + node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC) + node T_636 = neq(cycleNum_E, UInt<1>("h00")) + node T_637 = or(cyc_C1, T_636) + when T_637 : + node T_640 = subw(cycleNum_E, UInt<1>("h01")) + node T_641 = mux(cyc_C1, UInt<3>("h04"), T_640) + cycleNum_E := T_641 + skip + node T_643 = eq(cycleNum_E, UInt<3>("h04")) + cyc_E4 := T_643 + node T_645 = eq(cycleNum_E, UInt<2>("h03")) + cyc_E3 := T_645 + node T_647 = eq(cycleNum_E, UInt<2>("h02")) + cyc_E2 := T_647 + node T_649 = eq(cycleNum_E, UInt<1>("h01")) + cyc_E1 := T_649 + node T_650 = not(sqrtOp_PC) + node cyc_E4_div = and(cyc_E4, T_650) + node T_652 = not(sqrtOp_PC) + node cyc_E3_div = and(cyc_E3, T_652) + node T_654 = not(sqrtOp_PC) + node cyc_E2_div = and(cyc_E2, T_654) + node T_656 = not(sqrtOp_PC) + node cyc_E1_div = and(cyc_E1, T_656) + node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC) + node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC) + node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC) + node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC) + node zFractB_A4_div = mux(entering_PA_normalCase_div, fractB_S, UInt<1>("h00")) + node T_664 = bits(fractB_S, 51, 49) + node T_666 = eq(T_664, UInt<1>("h00")) + node zLinPiece_0_A4_div = and(entering_PA_normalCase_div, T_666) + node T_668 = bits(fractB_S, 51, 49) + node T_670 = eq(T_668, UInt<1>("h01")) + node zLinPiece_1_A4_div = and(entering_PA_normalCase_div, T_670) + node T_672 = bits(fractB_S, 51, 49) + node T_674 = eq(T_672, UInt<2>("h02")) + node zLinPiece_2_A4_div = and(entering_PA_normalCase_div, T_674) + node T_676 = bits(fractB_S, 51, 49) + node T_678 = eq(T_676, UInt<2>("h03")) + node zLinPiece_3_A4_div = and(entering_PA_normalCase_div, T_678) + node T_680 = bits(fractB_S, 51, 49) + node T_682 = eq(T_680, UInt<3>("h04")) + node zLinPiece_4_A4_div = and(entering_PA_normalCase_div, T_682) + node T_684 = bits(fractB_S, 51, 49) + node T_686 = eq(T_684, UInt<3>("h05")) + node zLinPiece_5_A4_div = and(entering_PA_normalCase_div, T_686) + node T_688 = bits(fractB_S, 51, 49) + node T_690 = eq(T_688, UInt<3>("h06")) + node zLinPiece_6_A4_div = and(entering_PA_normalCase_div, T_690) + node T_692 = bits(fractB_S, 51, 49) + node T_694 = eq(T_692, UInt<3>("h07")) + node zLinPiece_7_A4_div = and(entering_PA_normalCase_div, T_694) + node T_698 = mux(zLinPiece_0_A4_div, UInt<9>("h01c7"), UInt<1>("h00")) + node T_701 = mux(zLinPiece_1_A4_div, UInt<9>("h016c"), UInt<1>("h00")) + node T_702 = or(T_698, T_701) + node T_705 = mux(zLinPiece_2_A4_div, UInt<9>("h012a"), UInt<1>("h00")) + node T_706 = or(T_702, T_705) + node T_709 = mux(zLinPiece_3_A4_div, UInt<9>("h0f8"), UInt<1>("h00")) + node T_710 = or(T_706, T_709) + node T_713 = mux(zLinPiece_4_A4_div, UInt<9>("h0d2"), UInt<1>("h00")) + node T_714 = or(T_710, T_713) + node T_717 = mux(zLinPiece_5_A4_div, UInt<9>("h0b4"), UInt<1>("h00")) + node T_718 = or(T_714, T_717) + node T_721 = mux(zLinPiece_6_A4_div, UInt<9>("h09c"), UInt<1>("h00")) + node T_722 = or(T_718, T_721) + node T_725 = mux(zLinPiece_7_A4_div, UInt<9>("h089"), UInt<1>("h00")) + node zK1_A4_div = or(T_722, T_725) + node T_728 = not(UInt<12>("h0fe3")) + node T_730 = mux(zLinPiece_0_A4_div, T_728, UInt<1>("h00")) + node T_732 = not(UInt<12>("h0c5d")) + node T_734 = mux(zLinPiece_1_A4_div, T_732, UInt<1>("h00")) + node T_735 = or(T_730, T_734) + node T_737 = not(UInt<12>("h098a")) + node T_739 = mux(zLinPiece_2_A4_div, T_737, UInt<1>("h00")) + node T_740 = or(T_735, T_739) + node T_742 = not(UInt<12>("h0739")) + node T_744 = mux(zLinPiece_3_A4_div, T_742, UInt<1>("h00")) + node T_745 = or(T_740, T_744) + node T_747 = not(UInt<12>("h054b")) + node T_749 = mux(zLinPiece_4_A4_div, T_747, UInt<1>("h00")) + node T_750 = or(T_745, T_749) + node T_752 = not(UInt<12>("h03a9")) + node T_754 = mux(zLinPiece_5_A4_div, T_752, UInt<1>("h00")) + node T_755 = or(T_750, T_754) + node T_757 = not(UInt<12>("h0242")) + node T_759 = mux(zLinPiece_6_A4_div, T_757, UInt<1>("h00")) + node T_760 = or(T_755, T_759) + node T_762 = not(UInt<12>("h010b")) + node T_764 = mux(zLinPiece_7_A4_div, T_762, UInt<1>("h00")) + node zComplFractK0_A4_div = or(T_760, T_764) + node zFractB_A7_sqrt = mux(entering_PA_normalCase_sqrt, fractB_S, UInt<1>("h00")) + node T_768 = bit(expB_S, 0) + node T_769 = not(T_768) + node T_770 = and(entering_PA_normalCase_sqrt, T_769) + node T_771 = bit(fractB_S, 51) + node T_772 = not(T_771) + node zQuadPiece_0_A7_sqrt = and(T_770, T_772) + node T_774 = bit(expB_S, 0) + node T_775 = not(T_774) + node T_776 = and(entering_PA_normalCase_sqrt, T_775) + node T_777 = bit(fractB_S, 51) + node zQuadPiece_1_A7_sqrt = and(T_776, T_777) + node T_779 = bit(expB_S, 0) + node T_780 = and(entering_PA_normalCase_sqrt, T_779) + node T_781 = bit(fractB_S, 51) + node T_782 = not(T_781) + node zQuadPiece_2_A7_sqrt = and(T_780, T_782) + node T_784 = bit(expB_S, 0) + node T_785 = and(entering_PA_normalCase_sqrt, T_784) + node T_786 = bit(fractB_S, 51) + node zQuadPiece_3_A7_sqrt = and(T_785, T_786) + node T_790 = mux(zQuadPiece_0_A7_sqrt, UInt<9>("h01c8"), UInt<1>("h00")) + node T_793 = mux(zQuadPiece_1_A7_sqrt, UInt<9>("h0c1"), UInt<1>("h00")) + node T_794 = or(T_790, T_793) + node T_797 = mux(zQuadPiece_2_A7_sqrt, UInt<9>("h0143"), UInt<1>("h00")) + node T_798 = or(T_794, T_797) + node T_801 = mux(zQuadPiece_3_A7_sqrt, UInt<9>("h089"), UInt<1>("h00")) + node zK2_A7_sqrt = or(T_798, T_801) + node T_804 = not(UInt<10>("h03d0")) + node T_806 = mux(zQuadPiece_0_A7_sqrt, T_804, UInt<1>("h00")) + node T_808 = not(UInt<10>("h0220")) + node T_810 = mux(zQuadPiece_1_A7_sqrt, T_808, UInt<1>("h00")) + node T_811 = or(T_806, T_810) + node T_813 = not(UInt<10>("h02b2")) + node T_815 = mux(zQuadPiece_2_A7_sqrt, T_813, UInt<1>("h00")) + node T_816 = or(T_811, T_815) + node T_818 = not(UInt<10>("h0181")) + node T_820 = mux(zQuadPiece_3_A7_sqrt, T_818, UInt<1>("h00")) + node zComplK1_A7_sqrt = or(T_816, T_820) + node T_822 = bit(exp_PA, 0) + node T_823 = not(T_822) + node T_824 = and(cyc_A6_sqrt, T_823) + node T_825 = bit(sigB_PA, 51) + node T_826 = not(T_825) + node zQuadPiece_0_A6_sqrt = and(T_824, T_826) + node T_828 = bit(exp_PA, 0) + node T_829 = not(T_828) + node T_830 = and(cyc_A6_sqrt, T_829) + node T_831 = bit(sigB_PA, 51) + node zQuadPiece_1_A6_sqrt = and(T_830, T_831) + node T_833 = bit(exp_PA, 0) + node T_834 = and(cyc_A6_sqrt, T_833) + node T_835 = bit(sigB_PA, 51) + node T_836 = not(T_835) + node zQuadPiece_2_A6_sqrt = and(T_834, T_836) + node T_838 = bit(exp_PA, 0) + node T_839 = and(cyc_A6_sqrt, T_838) + node T_840 = bit(sigB_PA, 51) + node zQuadPiece_3_A6_sqrt = and(T_839, T_840) + node T_843 = not(UInt<13>("h01fe5")) + node T_845 = mux(zQuadPiece_0_A6_sqrt, T_843, UInt<1>("h00")) + node T_847 = not(UInt<13>("h01435")) + node T_849 = mux(zQuadPiece_1_A6_sqrt, T_847, UInt<1>("h00")) + node T_850 = or(T_845, T_849) + node T_852 = not(UInt<13>("h0d2c")) + node T_854 = mux(zQuadPiece_2_A6_sqrt, T_852, UInt<1>("h00")) + node T_855 = or(T_850, T_854) + node T_857 = not(UInt<13>("h04e8")) + node T_859 = mux(zQuadPiece_3_A6_sqrt, T_857, UInt<1>("h00")) + node zComplFractK0_A6_sqrt = or(T_855, T_859) + node T_861 = bits(zFractB_A4_div, 48, 40) + node T_862 = or(T_861, zK2_A7_sqrt) + node T_863 = not(cyc_S) + node T_865 = mux(T_863, nextMulAdd9A_A, UInt<1>("h00")) + node mulAdd9A_A = or(T_862, T_865) + node T_867 = bits(zFractB_A7_sqrt, 50, 42) + node T_868 = or(zK1_A4_div, T_867) + node T_869 = not(cyc_S) + node T_871 = mux(T_869, nextMulAdd9B_A, UInt<1>("h00")) + node mulAdd9B_A = or(T_868, T_871) + node T_873 = shl(zComplK1_A7_sqrt, 10) + node T_875 = subw(UInt<6>("h00"), cyc_A6_sqrt) + node T_876 = cat(zComplFractK0_A6_sqrt, T_875) + node T_877 = cat(cyc_A6_sqrt, T_876) + node T_878 = or(T_873, T_877) + node T_880 = subw(UInt<8>("h00"), entering_PA_normalCase_div) + node T_881 = cat(zComplFractK0_A4_div, T_880) + node T_882 = cat(entering_PA_normalCase_div, T_881) + node T_883 = or(T_878, T_882) + node T_885 = shl(fractR0_A, 10) + node T_886 = addw(UInt<20>("h040000"), T_885) + node T_888 = mux(cyc_A5_sqrt, T_886, UInt<1>("h00")) + node T_889 = or(T_883, T_888) + node T_890 = bit(hiSqrR0_A_sqrt, 9) + node T_891 = not(T_890) + node T_892 = and(cyc_A4_sqrt, T_891) + node T_895 = mux(T_892, UInt<11>("h0400"), UInt<1>("h00")) + node T_896 = or(T_889, T_895) + node T_897 = bit(hiSqrR0_A_sqrt, 9) + node T_898 = and(cyc_A4_sqrt, T_897) + node T_899 = or(T_898, cyc_A3_div) + node T_900 = bits(sigB_PA, 46, 26) + node T_902 = addw(T_900, UInt<11>("h0400")) + node T_904 = mux(T_899, T_902, UInt<1>("h00")) + node T_905 = or(T_896, T_904) + node T_906 = or(cyc_A3_sqrt, cyc_A2) + node T_908 = mux(T_906, partNegSigma0_A, UInt<1>("h00")) + node T_909 = or(T_905, T_908) + node T_910 = shl(fractR0_A, 16) + node T_912 = mux(cyc_A1_sqrt, T_910, UInt<1>("h00")) + node T_913 = or(T_909, T_912) + node T_914 = shl(fractR0_A, 15) + node T_916 = mux(cyc_A1_div, T_914, UInt<1>("h00")) + node mulAdd9C_A = or(T_913, T_916) + node T_918 = mul(mulAdd9A_A, mulAdd9B_A) + node T_920 = bits(mulAdd9C_A, 17, 0) + node T_921 = cat(UInt<1>("h00"), T_920) + node loMulAdd9Out_A = addw(T_918, T_921) + node T_923 = bit(loMulAdd9Out_A, 18) + node T_924 = bits(mulAdd9C_A, 24, 18) + node T_926 = addw(T_924, UInt<1>("h01")) + node T_927 = bits(mulAdd9C_A, 24, 18) + node T_928 = mux(T_923, T_926, T_927) + node T_929 = bits(loMulAdd9Out_A, 17, 0) + node mulAdd9Out_A = cat(T_928, T_929) + node T_931 = bit(mulAdd9Out_A, 19) + node T_932 = and(cyc_A6_sqrt, T_931) + node T_933 = not(mulAdd9Out_A) + node T_934 = shr(T_933, 10) + node T_936 = mux(T_932, T_934, UInt<1>("h00")) + node zFractR0_A6_sqrt = bits(T_936, 8, 0) + node T_938 = bit(exp_PA, 0) + node T_939 = shl(mulAdd9Out_A, 1) + node sqrR0_A5_sqrt = mux(T_938, T_939, mulAdd9Out_A) + node T_941 = bit(mulAdd9Out_A, 20) + node T_942 = and(entering_PA_normalCase_div, T_941) + node T_943 = not(mulAdd9Out_A) + node T_944 = shr(T_943, 11) + node T_946 = mux(T_942, T_944, UInt<1>("h00")) + node zFractR0_A4_div = bits(T_946, 8, 0) + node T_948 = bit(mulAdd9Out_A, 11) + node T_949 = and(cyc_A2, T_948) + node T_950 = not(mulAdd9Out_A) + node T_951 = shr(T_950, 2) + node T_953 = mux(T_949, T_951, UInt<1>("h00")) + node zSigma0_A2 = bits(T_953, 8, 0) + node T_955 = shr(mulAdd9Out_A, 10) + node T_956 = shr(mulAdd9Out_A, 9) + node T_957 = mux(sqrtOp_PA, T_955, T_956) + node fractR1_A1 = bits(T_957, 14, 0) + node r1_A1 = cat(UInt<1>("h01"), fractR1_A1) + node T_961 = bit(exp_PA, 0) + node T_962 = shl(r1_A1, 1) + node ER1_A1_sqrt = mux(T_961, T_962, r1_A1) + node T_964 = or(cyc_A6_sqrt, entering_PA_normalCase_div) + when T_964 : + node T_965 = or(zFractR0_A6_sqrt, zFractR0_A4_div) + fractR0_A := T_965 + skip + when cyc_A5_sqrt : + node T_966 = shr(sqrR0_A5_sqrt, 10) + hiSqrR0_A_sqrt := T_966 + skip + node T_967 = or(cyc_A4_sqrt, cyc_A3) + when T_967 : + node T_968 = shr(mulAdd9Out_A, 9) + node T_969 = mux(cyc_A4_sqrt, mulAdd9Out_A, T_968) + node T_970 = bits(T_969, 20, 0) + partNegSigma0_A := T_970 + skip + node T_971 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) + node T_972 = or(T_971, cyc_A5_sqrt) + node T_973 = or(T_972, cyc_A4) + node T_974 = or(T_973, cyc_A3) + node T_975 = or(T_974, cyc_A2) + when T_975 : + node T_976 = not(mulAdd9Out_A) + node T_977 = shr(T_976, 11) + node T_979 = mux(entering_PA_normalCase_sqrt, T_977, UInt<1>("h00")) + node T_980 = or(T_979, zFractR0_A6_sqrt) + node T_981 = bits(sigB_PA, 43, 35) + node T_983 = mux(cyc_A4_sqrt, T_981, UInt<1>("h00")) + node T_984 = or(T_980, T_983) + node T_985 = bits(zFractB_A4_div, 43, 35) + node T_986 = or(T_984, T_985) + node T_987 = or(cyc_A5_sqrt, cyc_A3) + node T_988 = bits(sigB_PA, 52, 44) + node T_990 = mux(T_987, T_988, UInt<1>("h00")) + node T_991 = or(T_986, T_990) + node T_992 = or(T_991, zSigma0_A2) + nextMulAdd9A_A := T_992 + skip + node T_993 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) + node T_994 = or(T_993, cyc_A5_sqrt) + node T_995 = or(T_994, cyc_A4) + node T_996 = or(T_995, cyc_A2) + when T_996 : + node T_997 = bits(zFractB_A7_sqrt, 50, 42) + node T_998 = or(T_997, zFractR0_A6_sqrt) + node T_999 = bits(sqrR0_A5_sqrt, 9, 1) + node T_1001 = mux(cyc_A5_sqrt, T_999, UInt<1>("h00")) + node T_1002 = or(T_998, T_1001) + node T_1003 = or(T_1002, zFractR0_A4_div) + node T_1004 = bits(hiSqrR0_A_sqrt, 8, 0) + node T_1006 = mux(cyc_A4_sqrt, T_1004, UInt<1>("h00")) + node T_1007 = or(T_1003, T_1006) + node T_1009 = bits(fractR0_A, 8, 1) + node T_1010 = cat(UInt<1>("h01"), T_1009) + node T_1012 = mux(cyc_A2, T_1010, UInt<1>("h00")) + node T_1013 = or(T_1007, T_1012) + nextMulAdd9B_A := T_1013 + skip + when cyc_A1_sqrt : + ER1_B_sqrt := ER1_A1_sqrt + skip + node T_1014 = or(cyc_A1, cyc_B7_sqrt) + node T_1015 = or(T_1014, cyc_B6_div) + node T_1016 = or(T_1015, cyc_B4) + node T_1017 = or(T_1016, cyc_B3) + node T_1018 = or(T_1017, cyc_C6_sqrt) + node T_1019 = or(T_1018, cyc_C4) + node T_1020 = or(T_1019, cyc_C1) + latchMulAddA_0 := T_1020 + node T_1021 = shl(ER1_A1_sqrt, 36) + node T_1023 = mux(cyc_A1_sqrt, T_1021, UInt<1>("h00")) + node T_1024 = or(cyc_B7_sqrt, cyc_A1_div) + node T_1026 = mux(T_1024, sigB_PA, UInt<1>("h00")) + node T_1027 = or(T_1023, T_1026) + node T_1029 = mux(cyc_B6_div, sigA_PA, UInt<1>("h00")) + node T_1030 = or(T_1027, T_1029) + node T_1031 = bits(zSigma1_B4, 45, 12) + node T_1032 = or(T_1030, T_1031) + node T_1033 = or(cyc_B3, cyc_C6_sqrt) + node T_1034 = bits(sigXNU_B3_CX, 57, 12) + node T_1036 = mux(T_1033, T_1034, UInt<1>("h00")) + node T_1037 = or(T_1032, T_1036) + node T_1038 = bits(sigXN_C, 57, 25) + node T_1039 = shl(T_1038, 13) + node T_1041 = mux(cyc_C4_div, T_1039, UInt<1>("h00")) + node T_1042 = or(T_1037, T_1041) + node T_1043 = shl(u_C_sqrt, 15) + node T_1045 = mux(cyc_C4_sqrt, T_1043, UInt<1>("h00")) + node T_1046 = or(T_1042, T_1045) + node T_1048 = mux(cyc_C1_div, sigB_PC, UInt<1>("h00")) + node T_1049 = or(T_1046, T_1048) + node T_1050 = or(T_1049, zComplSigT_C1_sqrt) + mulAddA_0 := T_1050 + node T_1051 = or(cyc_A1, cyc_B7_sqrt) + node T_1052 = or(T_1051, cyc_B6_sqrt) + node T_1053 = or(T_1052, cyc_B4) + node T_1054 = or(T_1053, cyc_C6_sqrt) + node T_1055 = or(T_1054, cyc_C4) + node T_1056 = or(T_1055, cyc_C1) + latchMulAddB_0 := T_1056 + node T_1057 = shl(r1_A1, 36) + node T_1059 = mux(cyc_A1, T_1057, UInt<1>("h00")) + node T_1060 = shl(ESqrR1_B_sqrt, 19) + node T_1062 = mux(cyc_B7_sqrt, T_1060, UInt<1>("h00")) + node T_1063 = or(T_1059, T_1062) + node T_1064 = shl(ER1_B_sqrt, 36) + node T_1066 = mux(cyc_B6_sqrt, T_1064, UInt<1>("h00")) + node T_1067 = or(T_1063, T_1066) + node T_1068 = or(T_1067, zSigma1_B4) + node T_1069 = bits(sqrSigma1_C, 30, 1) + node T_1071 = mux(cyc_C6_sqrt, T_1069, UInt<1>("h00")) + node T_1072 = or(T_1068, T_1071) + node T_1074 = mux(cyc_C4, sqrSigma1_C, UInt<1>("h00")) + node T_1075 = or(T_1072, T_1074) + node T_1076 = or(T_1075, zComplSigT_C1) + mulAddB_0 := T_1076 + node T_1077 = or(cyc_A4, cyc_A3_div) + node T_1078 = or(T_1077, cyc_A1_div) + node T_1079 = or(T_1078, cyc_B10_sqrt) + node T_1080 = or(T_1079, cyc_B9_sqrt) + node T_1081 = or(T_1080, cyc_B7_sqrt) + node T_1082 = or(T_1081, cyc_B6) + node T_1083 = or(T_1082, cyc_B5_sqrt) + node T_1084 = or(T_1083, cyc_B3_sqrt) + node T_1085 = or(T_1084, cyc_B2_div) + node T_1086 = or(T_1085, cyc_B1_sqrt) + node T_1087 = or(T_1086, cyc_C4) + node T_1088 = or(cyc_A3, cyc_A2_div) + node T_1089 = or(T_1088, cyc_B9_sqrt) + node T_1090 = or(T_1089, cyc_B8_sqrt) + node T_1091 = or(T_1090, cyc_B6) + node T_1092 = or(T_1091, cyc_B5) + node T_1093 = or(T_1092, cyc_B4_sqrt) + node T_1094 = or(T_1093, cyc_B2_sqrt) + node T_1095 = or(T_1094, cyc_B1_div) + node T_1096 = or(T_1095, cyc_C6_sqrt) + node T_1097 = or(T_1096, valid_normalCase_leaving_PB) + node T_1098 = or(cyc_A2, cyc_A1_div) + node T_1099 = or(T_1098, cyc_B8_sqrt) + node T_1100 = or(T_1099, cyc_B7_sqrt) + node T_1101 = or(T_1100, cyc_B5) + node T_1102 = or(T_1101, cyc_B4) + node T_1103 = or(T_1102, cyc_B3_sqrt) + node T_1104 = or(T_1103, cyc_B1_sqrt) + node T_1105 = or(T_1104, cyc_C5) + node T_1106 = or(T_1105, cyc_C2) + node T_1107 = or(latchMulAddA_0, cyc_B6) + node T_1108 = or(T_1107, cyc_B2_sqrt) + node T_1109 = cat(T_1087, T_1097) + node T_1110 = cat(T_1106, T_1108) + node T_1111 = cat(T_1109, T_1110) + usingMulAdd := T_1111 + node T_1112 = shl(sigX1_B, 47) + node T_1114 = mux(cyc_B1, T_1112, UInt<1>("h00")) + node T_1115 = shl(sigX1_B, 46) + node T_1117 = mux(cyc_C6_sqrt, T_1115, UInt<1>("h00")) + node T_1118 = or(T_1114, T_1117) + node T_1119 = or(cyc_C4_sqrt, cyc_C2) + node T_1120 = shl(sigXN_C, 47) + node T_1122 = mux(T_1119, T_1120, UInt<1>("h00")) + node T_1123 = or(T_1118, T_1122) + node T_1124 = not(E_E_div) + node T_1125 = and(cyc_E3_div, T_1124) + node T_1126 = shl(fractA_0_PC, 53) + node T_1128 = mux(T_1125, T_1126, UInt<1>("h00")) + node T_1129 = or(T_1123, T_1128) + node T_1130 = bit(exp_PC, 0) + node T_1131 = bit(sigB_PC, 0) + node T_1133 = cat(T_1131, UInt<1>("h00")) + node T_1134 = bit(sigB_PC, 1) + node T_1135 = bit(sigB_PC, 0) + node T_1136 = xor(T_1134, T_1135) + node T_1137 = bit(sigB_PC, 0) + node T_1138 = cat(T_1136, T_1137) + node T_1139 = mux(T_1130, T_1133, T_1138) + node T_1140 = not(extraT_E) + node T_1142 = cat(T_1140, UInt<1>("h00")) + node T_1143 = xor(T_1139, T_1142) + node T_1144 = shl(T_1143, 54) + node T_1146 = mux(cyc_E3_sqrt, T_1144, UInt<1>("h00")) + node T_1147 = or(T_1129, T_1146) + mulAddC_2 := T_1147 + node ESqrR1_B8_sqrt = bits(mulAddResult_3, 103, 72) + node T_1149 = bits(mulAddResult_3, 90, 45) + node T_1150 = not(T_1149) + node T_1152 = mux(cyc_B4, T_1150, UInt<1>("h00")) + zSigma1_B4 := T_1152 + node sqrSigma1_B1 = bits(mulAddResult_3, 79, 47) + node T_1154 = bits(mulAddResult_3, 104, 47) + sigXNU_B3_CX := T_1154 + node T_1155 = bit(mulAddResult_3, 104) + node E_C1_div = not(T_1155) + node T_1157 = not(E_C1_div) + node T_1158 = and(cyc_C1_div, T_1157) + node T_1159 = or(T_1158, cyc_C1_sqrt) + node T_1160 = bits(mulAddResult_3, 104, 51) + node T_1161 = not(T_1160) + node T_1163 = mux(T_1159, T_1161, UInt<1>("h00")) + node T_1164 = and(cyc_C1_div, E_C1_div) + node T_1166 = bits(mulAddResult_3, 102, 50) + node T_1167 = not(T_1166) + node T_1168 = cat(UInt<1>("h00"), T_1167) + node T_1170 = mux(T_1164, T_1168, UInt<1>("h00")) + node T_1171 = or(T_1163, T_1170) + zComplSigT_C1 := T_1171 + node T_1172 = bits(mulAddResult_3, 104, 51) + node T_1173 = not(T_1172) + node T_1175 = mux(cyc_C1_sqrt, T_1173, UInt<1>("h00")) + zComplSigT_C1_sqrt := T_1175 + node sigT_C1 = not(zComplSigT_C1) + node remT_E2 = bits(mulAddResult_3, 55, 0) + when cyc_B8_sqrt : + ESqrR1_B_sqrt := ESqrR1_B8_sqrt + skip + when cyc_B3 : + sigX1_B := sigXNU_B3_CX + skip + when cyc_B1 : + sqrSigma1_C := sqrSigma1_B1 + skip + node T_1178 = or(cyc_C6_sqrt, cyc_C5_div) + node T_1179 = or(T_1178, cyc_C3_sqrt) + when T_1179 : + sigXN_C := sigXNU_B3_CX + skip + when cyc_C5_sqrt : + node T_1180 = bits(sigXNU_B3_CX, 56, 26) + u_C_sqrt := T_1180 + skip + when cyc_C1 : + E_E_div := E_C1_div + node T_1181 = bits(sigT_C1, 53, 1) + sigT_E := T_1181 + node T_1182 = bit(sigT_C1, 0) + extraT_E := T_1182 + skip + when cyc_E2 : + node T_1183 = bit(remT_E2, 55) + node T_1184 = bit(remT_E2, 53) + node T_1185 = mux(sqrtOp_PC, T_1183, T_1184) + isNegRemT_E := T_1185 + node T_1186 = bits(remT_E2, 53, 0) + node T_1188 = eq(T_1186, UInt<1>("h00")) + node T_1189 = not(sqrtOp_PC) + node T_1190 = bits(remT_E2, 55, 54) + node T_1192 = eq(T_1190, UInt<1>("h00")) + node T_1193 = or(T_1189, T_1192) + node T_1194 = and(T_1188, T_1193) + trueEqX_E1 := T_1194 + skip + node T_1195 = not(sqrtOp_PC) + node T_1196 = and(T_1195, E_E_div) + node T_1198 = mux(T_1196, exp_PC, UInt<1>("h00")) + node T_1199 = not(sqrtOp_PC) + node T_1200 = not(E_E_div) + node T_1201 = and(T_1199, T_1200) + node T_1203 = mux(T_1201, expP1_PC, UInt<1>("h00")) + node T_1204 = or(T_1198, T_1203) + node T_1205 = shr(exp_PC, 1) + node T_1207 = addw(T_1205, UInt<12>("h0400")) + node T_1209 = mux(sqrtOp_PC, T_1207, UInt<1>("h00")) + node sExpX_E = or(T_1204, T_1209) + node posExpX_E = bits(sExpX_E, 12, 0) + node T_1212 = bits(posExpX_E, 12, 6) + node posExpX_0001111_E = eq(T_1212, UInt<7>("h0f")) + node T_1215 = bit(posExpX_E, 5) + node T_1216 = not(T_1215) + node posExpX_00011110_E = and(posExpX_0001111_E, T_1216) + node T_1218 = bit(posExpX_E, 4) + node T_1219 = not(T_1218) + node posExpX_000111100_E = and(posExpX_00011110_E, T_1219) + node T_1221 = bits(sExpX_E, 2, 0) + node exp3X_lt_001_E = lt(T_1221, UInt<3>("h01")) + node T_1224 = bits(sExpX_E, 2, 0) + node exp3X_lt_010_E = lt(T_1224, UInt<3>("h02")) + node T_1227 = bits(sExpX_E, 2, 0) + node exp3X_lt_011_E = lt(T_1227, UInt<3>("h03")) + node T_1230 = bits(sExpX_E, 2, 0) + node exp3X_lt_100_E = lt(T_1230, UInt<3>("h04")) + node T_1233 = bits(sExpX_E, 2, 0) + node exp3X_lt_101_E = lt(T_1233, UInt<3>("h05")) + node T_1236 = bits(sExpX_E, 2, 0) + node exp3X_lt_110_E = lt(T_1236, UInt<3>("h06")) + node T_1239 = bits(sExpX_E, 2, 0) + node exp3X_lt_111_E = lt(T_1239, UInt<3>("h07")) + node T_1242 = bits(sExpX_E, 4, 3) + node exp5X_lt_01000_E = eq(T_1242, UInt<2>("h00")) + node T_1245 = bits(sExpX_E, 4, 3) + node exp5X_01_E = eq(T_1245, UInt<2>("h01")) + node T_1248 = bits(sExpX_E, 4, 3) + node exp5X_10_E = eq(T_1248, UInt<2>("h02")) + node exp5X_lt_00001_E = and(exp5X_lt_01000_E, exp3X_lt_001_E) + node exp5X_lt_00010_E = and(exp5X_lt_01000_E, exp3X_lt_010_E) + node exp5X_lt_00011_E = and(exp5X_lt_01000_E, exp3X_lt_011_E) + node exp5X_lt_00100_E = and(exp5X_lt_01000_E, exp3X_lt_100_E) + node exp5X_lt_00101_E = and(exp5X_lt_01000_E, exp3X_lt_101_E) + node exp5X_lt_00110_E = and(exp5X_lt_01000_E, exp3X_lt_110_E) + node exp5X_lt_00111_E = and(exp5X_lt_01000_E, exp3X_lt_111_E) + node T_1258 = and(exp5X_01_E, exp3X_lt_001_E) + node exp5X_lt_01001_E = or(exp5X_lt_01000_E, T_1258) + node T_1260 = and(exp5X_01_E, exp3X_lt_010_E) + node exp5X_lt_01010_E = or(exp5X_lt_01000_E, T_1260) + node T_1262 = and(exp5X_01_E, exp3X_lt_011_E) + node exp5X_lt_01011_E = or(exp5X_lt_01000_E, T_1262) + node T_1264 = and(exp5X_01_E, exp3X_lt_100_E) + node exp5X_lt_01100_E = or(exp5X_lt_01000_E, T_1264) + node T_1266 = and(exp5X_01_E, exp3X_lt_101_E) + node exp5X_lt_01101_E = or(exp5X_lt_01000_E, T_1266) + node T_1268 = and(exp5X_01_E, exp3X_lt_110_E) + node exp5X_lt_01110_E = or(exp5X_lt_01000_E, T_1268) + node T_1270 = and(exp5X_01_E, exp3X_lt_111_E) + node exp5X_lt_01111_E = or(exp5X_lt_01000_E, T_1270) + node T_1272 = bit(sExpX_E, 4) + node exp5X_lt_10000_E = not(T_1272) + node T_1274 = bit(sExpX_E, 4) + node T_1275 = not(T_1274) + node T_1276 = and(exp5X_10_E, exp3X_lt_001_E) + node exp5X_lt_10001_E = or(T_1275, T_1276) + node T_1278 = bit(sExpX_E, 4) + node T_1279 = not(T_1278) + node T_1280 = and(exp5X_10_E, exp3X_lt_010_E) + node exp5X_lt_10010_E = or(T_1279, T_1280) + node T_1282 = bit(sExpX_E, 4) + node T_1283 = not(T_1282) + node T_1284 = and(exp5X_10_E, exp3X_lt_011_E) + node exp5X_lt_10011_E = or(T_1283, T_1284) + node T_1286 = bit(sExpX_E, 4) + node T_1287 = not(T_1286) + node T_1288 = and(exp5X_10_E, exp3X_lt_100_E) + node exp5X_lt_10100_E = or(T_1287, T_1288) + node T_1290 = bit(sExpX_E, 4) + node T_1291 = not(T_1290) + node T_1292 = and(exp5X_10_E, exp3X_lt_101_E) + node exp5X_lt_10101_E = or(T_1291, T_1292) + node T_1294 = bit(sExpX_E, 4) + node T_1295 = not(T_1294) + node T_1296 = and(exp5X_10_E, exp3X_lt_110_E) + node exp5X_lt_10110_E = or(T_1295, T_1296) + node T_1298 = bit(sExpX_E, 4) + node T_1299 = not(T_1298) + node T_1300 = and(exp5X_10_E, exp3X_lt_111_E) + node exp5X_lt_10111_E = or(T_1299, T_1300) + node T_1302 = bits(sExpX_E, 4, 3) + node exp5X_lt_11000_E = neq(T_1302, UInt<2>("h03")) + node exp5X_lt_11001_E = or(exp5X_lt_11000_E, exp3X_lt_001_E) + node exp5X_lt_11010_E = or(exp5X_lt_11000_E, exp3X_lt_010_E) + node exp5X_lt_11011_E = or(exp5X_lt_11000_E, exp3X_lt_011_E) + node exp5X_lt_11100_E = or(exp5X_lt_11000_E, exp3X_lt_100_E) + node exp5X_lt_11101_E = or(exp5X_lt_11000_E, exp3X_lt_101_E) + node exp5X_lt_11110_E = or(exp5X_lt_11000_E, exp3X_lt_110_E) + node exp5X_lt_11111_E = or(exp5X_lt_11000_E, exp3X_lt_111_E) + node T_1312 = bits(sExpX_E, 3, 0) + node T_1314 = lt(T_1312, UInt<4>("h0e")) + node T_1315 = and(posExpX_000111100_E, T_1314) + node T_1316 = bits(sExpX_E, 3, 0) + node T_1318 = lt(T_1316, UInt<4>("h0f")) + node T_1319 = and(posExpX_000111100_E, T_1318) + node T_1320 = and(posExpX_00011110_E, exp5X_lt_10001_E) + node T_1321 = and(posExpX_00011110_E, exp5X_lt_10010_E) + node T_1322 = and(posExpX_00011110_E, exp5X_lt_10011_E) + node T_1323 = and(posExpX_00011110_E, exp5X_lt_10100_E) + node T_1324 = and(posExpX_00011110_E, exp5X_lt_10101_E) + node T_1325 = and(posExpX_00011110_E, exp5X_lt_10110_E) + node T_1326 = and(posExpX_00011110_E, exp5X_lt_10111_E) + node T_1327 = and(posExpX_00011110_E, exp5X_lt_11000_E) + node T_1328 = and(posExpX_00011110_E, exp5X_lt_11001_E) + node T_1329 = and(posExpX_00011110_E, exp5X_lt_11010_E) + node T_1330 = and(posExpX_00011110_E, exp5X_lt_11011_E) + node T_1331 = and(posExpX_00011110_E, exp5X_lt_11100_E) + node T_1332 = and(posExpX_00011110_E, exp5X_lt_11101_E) + node T_1333 = and(posExpX_00011110_E, exp5X_lt_11110_E) + node T_1334 = and(posExpX_00011110_E, exp5X_lt_11111_E) + node T_1335 = bit(sExpX_E, 5) + node T_1336 = not(T_1335) + node T_1337 = or(T_1336, exp5X_lt_00001_E) + node T_1338 = and(posExpX_0001111_E, T_1337) + node T_1339 = bit(sExpX_E, 5) + node T_1340 = not(T_1339) + node T_1341 = or(T_1340, exp5X_lt_00010_E) + node T_1342 = and(posExpX_0001111_E, T_1341) + node T_1343 = bit(sExpX_E, 5) + node T_1344 = not(T_1343) + node T_1345 = or(T_1344, exp5X_lt_00011_E) + node T_1346 = and(posExpX_0001111_E, T_1345) + node T_1347 = bit(sExpX_E, 5) + node T_1348 = not(T_1347) + node T_1349 = or(T_1348, exp5X_lt_00100_E) + node T_1350 = and(posExpX_0001111_E, T_1349) + node T_1351 = bit(sExpX_E, 5) + node T_1352 = not(T_1351) + node T_1353 = or(T_1352, exp5X_lt_00101_E) + node T_1354 = and(posExpX_0001111_E, T_1353) + node T_1355 = bit(sExpX_E, 5) + node T_1356 = not(T_1355) + node T_1357 = or(T_1356, exp5X_lt_00110_E) + node T_1358 = and(posExpX_0001111_E, T_1357) + node T_1359 = bit(sExpX_E, 5) + node T_1360 = not(T_1359) + node T_1361 = or(T_1360, exp5X_lt_00111_E) + node T_1362 = and(posExpX_0001111_E, T_1361) + node T_1363 = bit(sExpX_E, 5) + node T_1364 = not(T_1363) + node T_1365 = or(T_1364, exp5X_lt_01000_E) + node T_1366 = and(posExpX_0001111_E, T_1365) + node T_1367 = bit(sExpX_E, 5) + node T_1368 = not(T_1367) + node T_1369 = or(T_1368, exp5X_lt_01001_E) + node T_1370 = and(posExpX_0001111_E, T_1369) + node T_1371 = bit(sExpX_E, 5) + node T_1372 = not(T_1371) + node T_1373 = or(T_1372, exp5X_lt_01010_E) + node T_1374 = and(posExpX_0001111_E, T_1373) + node T_1375 = bit(sExpX_E, 5) + node T_1376 = not(T_1375) + node T_1377 = or(T_1376, exp5X_lt_01011_E) + node T_1378 = and(posExpX_0001111_E, T_1377) + node T_1379 = bit(sExpX_E, 5) + node T_1380 = not(T_1379) + node T_1381 = or(T_1380, exp5X_lt_01100_E) + node T_1382 = and(posExpX_0001111_E, T_1381) + node T_1383 = bit(sExpX_E, 5) + node T_1384 = not(T_1383) + node T_1385 = or(T_1384, exp5X_lt_01101_E) + node T_1386 = and(posExpX_0001111_E, T_1385) + node T_1387 = bit(sExpX_E, 5) + node T_1388 = not(T_1387) + node T_1389 = or(T_1388, exp5X_lt_01110_E) + node T_1390 = and(posExpX_0001111_E, T_1389) + node T_1391 = bit(sExpX_E, 5) + node T_1392 = not(T_1391) + node T_1393 = or(T_1392, exp5X_lt_01111_E) + node T_1394 = and(posExpX_0001111_E, T_1393) + node T_1395 = bit(sExpX_E, 5) + node T_1396 = not(T_1395) + node T_1397 = or(T_1396, exp5X_lt_10000_E) + node T_1398 = and(posExpX_0001111_E, T_1397) + node T_1399 = bit(sExpX_E, 5) + node T_1400 = not(T_1399) + node T_1401 = or(T_1400, exp5X_lt_10001_E) + node T_1402 = and(posExpX_0001111_E, T_1401) + node T_1403 = bit(sExpX_E, 5) + node T_1404 = not(T_1403) + node T_1405 = or(T_1404, exp5X_lt_10010_E) + node T_1406 = and(posExpX_0001111_E, T_1405) + node T_1407 = bit(sExpX_E, 5) + node T_1408 = not(T_1407) + node T_1409 = or(T_1408, exp5X_lt_10011_E) + node T_1410 = and(posExpX_0001111_E, T_1409) + node T_1411 = bit(sExpX_E, 5) + node T_1412 = not(T_1411) + node T_1413 = or(T_1412, exp5X_lt_10100_E) + node T_1414 = and(posExpX_0001111_E, T_1413) + node T_1415 = bit(sExpX_E, 5) + node T_1416 = not(T_1415) + node T_1417 = or(T_1416, exp5X_lt_10101_E) + node T_1418 = and(posExpX_0001111_E, T_1417) + node T_1419 = bit(sExpX_E, 5) + node T_1420 = not(T_1419) + node T_1421 = or(T_1420, exp5X_lt_10110_E) + node T_1422 = and(posExpX_0001111_E, T_1421) + node T_1423 = bit(sExpX_E, 5) + node T_1424 = not(T_1423) + node T_1425 = or(T_1424, exp5X_lt_10111_E) + node T_1426 = and(posExpX_0001111_E, T_1425) + node T_1427 = bit(sExpX_E, 5) + node T_1428 = not(T_1427) + node T_1429 = or(T_1428, exp5X_lt_11000_E) + node T_1430 = and(posExpX_0001111_E, T_1429) + node T_1431 = bit(sExpX_E, 5) + node T_1432 = not(T_1431) + node T_1433 = or(T_1432, exp5X_lt_11001_E) + node T_1434 = and(posExpX_0001111_E, T_1433) + node T_1435 = bit(sExpX_E, 5) + node T_1436 = not(T_1435) + node T_1437 = or(T_1436, exp5X_lt_11010_E) + node T_1438 = and(posExpX_0001111_E, T_1437) + node T_1439 = bit(sExpX_E, 5) + node T_1440 = not(T_1439) + node T_1441 = or(T_1440, exp5X_lt_11011_E) + node T_1442 = and(posExpX_0001111_E, T_1441) + node T_1443 = bit(sExpX_E, 5) + node T_1444 = not(T_1443) + node T_1445 = or(T_1444, exp5X_lt_11100_E) + node T_1446 = and(posExpX_0001111_E, T_1445) + node T_1447 = bit(sExpX_E, 5) + node T_1448 = not(T_1447) + node T_1449 = or(T_1448, exp5X_lt_11101_E) + node T_1450 = and(posExpX_0001111_E, T_1449) + node T_1451 = bit(sExpX_E, 5) + node T_1452 = not(T_1451) + node T_1453 = or(T_1452, exp5X_lt_11110_E) + node T_1454 = and(posExpX_0001111_E, T_1453) + node T_1455 = bit(sExpX_E, 5) + node T_1456 = not(T_1455) + node T_1457 = or(T_1456, exp5X_lt_11111_E) + node T_1458 = and(posExpX_0001111_E, T_1457) + node T_1460 = lt(posExpX_E, UInt<13>("h0401")) + node T_1462 = lt(posExpX_E, UInt<13>("h0402")) + node T_1463 = cat(T_1319, posExpX_000111100_E) + node T_1464 = cat(T_1315, T_1463) + node T_1465 = cat(T_1321, T_1322) + node T_1466 = cat(T_1320, T_1465) + node T_1467 = cat(T_1464, T_1466) + node T_1468 = cat(T_1324, T_1325) + node T_1469 = cat(T_1323, T_1468) + node T_1470 = cat(T_1326, T_1327) + node T_1471 = cat(T_1328, T_1329) + node T_1472 = cat(T_1470, T_1471) + node T_1473 = cat(T_1469, T_1472) + node T_1474 = cat(T_1467, T_1473) + node T_1475 = cat(T_1331, T_1332) + node T_1476 = cat(T_1330, T_1475) + node T_1477 = cat(T_1334, posExpX_00011110_E) + node T_1478 = cat(T_1333, T_1477) + node T_1479 = cat(T_1476, T_1478) + node T_1480 = cat(T_1342, T_1346) + node T_1481 = cat(T_1338, T_1480) + node T_1482 = cat(T_1350, T_1354) + node T_1483 = cat(T_1358, T_1362) + node T_1484 = cat(T_1482, T_1483) + node T_1485 = cat(T_1481, T_1484) + node T_1486 = cat(T_1479, T_1485) + node T_1487 = cat(T_1474, T_1486) + node T_1488 = cat(T_1370, T_1374) + node T_1489 = cat(T_1366, T_1488) + node T_1490 = cat(T_1382, T_1386) + node T_1491 = cat(T_1378, T_1490) + node T_1492 = cat(T_1489, T_1491) + node T_1493 = cat(T_1394, T_1398) + node T_1494 = cat(T_1390, T_1493) + node T_1495 = cat(T_1402, T_1406) + node T_1496 = cat(T_1410, T_1414) + node T_1497 = cat(T_1495, T_1496) + node T_1498 = cat(T_1494, T_1497) + node T_1499 = cat(T_1492, T_1498) + node T_1500 = cat(T_1422, T_1426) + node T_1501 = cat(T_1418, T_1500) + node T_1502 = cat(T_1430, T_1434) + node T_1503 = cat(T_1438, T_1442) + node T_1504 = cat(T_1502, T_1503) + node T_1505 = cat(T_1501, T_1504) + node T_1506 = cat(T_1450, T_1454) + node T_1507 = cat(T_1446, T_1506) + node T_1508 = cat(T_1458, posExpX_0001111_E) + node T_1509 = cat(T_1460, T_1462) + node T_1510 = cat(T_1508, T_1509) + node T_1511 = cat(T_1507, T_1510) + node T_1512 = cat(T_1505, T_1511) + node T_1513 = cat(T_1499, T_1512) + node roundMask_E = cat(T_1487, T_1513) + node T_1516 = cat(UInt<1>("h00"), roundMask_E) + node T_1517 = not(T_1516) + node T_1519 = cat(roundMask_E, UInt<1>("h01")) + node incrPosMask_E = and(T_1517, T_1519) + node T_1521 = shr(incrPosMask_E, 1) + node T_1522 = and(sigT_E, T_1521) + node hiRoundPosBitT_E = neq(T_1522, UInt<1>("h00")) + node T_1525 = shr(roundMask_E, 1) + node T_1526 = and(sigT_E, T_1525) + node all0sHiRoundExtraT_E = eq(T_1526, UInt<1>("h00")) + node T_1529 = not(sigT_E) + node T_1530 = shr(roundMask_E, 1) + node T_1531 = and(T_1529, T_1530) + node all1sHiRoundExtraT_E = eq(T_1531, UInt<1>("h00")) + node T_1534 = bit(roundMask_E, 0) + node T_1535 = not(T_1534) + node T_1536 = or(T_1535, hiRoundPosBitT_E) + node all1sHiRoundT_E = and(T_1536, all1sHiRoundExtraT_E) + node T_1539 = addw(UInt<54>("h00"), sigT_E) + node sigAdjT_E = addw(T_1539, roundMagUp_PC) + node T_1542 = not(roundMask_E) + node T_1543 = cat(UInt<1>("h01"), T_1542) + node sigY0_E = and(sigAdjT_E, T_1543) + node T_1546 = cat(UInt<1>("h00"), roundMask_E) + node T_1547 = or(sigAdjT_E, T_1546) + node sigY1_E = addw(T_1547, UInt<1>("h01")) + node T_1550 = not(isNegRemT_E) + node T_1551 = not(trueEqX_E1) + node T_1552 = and(T_1550, T_1551) + node trueLtX_E1 = mux(sqrtOp_PC, T_1552, isNegRemT_E) + node T_1554 = bit(roundMask_E, 0) + node T_1555 = not(trueLtX_E1) + node T_1556 = and(T_1554, T_1555) + node T_1557 = and(T_1556, all1sHiRoundExtraT_E) + node T_1558 = and(T_1557, extraT_E) + node hiRoundPosBit_E1 = xor(hiRoundPosBitT_E, T_1558) + node T_1560 = not(trueEqX_E1) + node T_1561 = not(extraT_E) + node T_1562 = or(T_1560, T_1561) + node T_1563 = not(all1sHiRoundExtraT_E) + node anyRoundExtra_E1 = or(T_1562, T_1563) + node T_1565 = and(roundingMode_near_even_PC, hiRoundPosBit_E1) + node T_1566 = not(anyRoundExtra_E1) + node T_1567 = and(T_1565, T_1566) + node roundEvenMask_E1 = mux(T_1567, incrPosMask_E, UInt<1>("h00")) + node T_1570 = and(roundMagDown_PC, extraT_E) + node T_1571 = not(trueLtX_E1) + node T_1572 = and(T_1570, T_1571) + node T_1573 = and(T_1572, all1sHiRoundT_E) + node T_1574 = not(trueLtX_E1) + node T_1575 = and(extraT_E, T_1574) + node T_1576 = not(trueEqX_E1) + node T_1577 = and(T_1575, T_1576) + node T_1578 = not(all1sHiRoundT_E) + node T_1579 = or(T_1577, T_1578) + node T_1580 = and(roundMagUp_PC, T_1579) + node T_1581 = or(T_1573, T_1580) + node T_1582 = not(trueLtX_E1) + node T_1583 = or(extraT_E, T_1582) + node T_1584 = bit(roundMask_E, 0) + node T_1585 = not(T_1584) + node T_1586 = and(T_1583, T_1585) + node T_1587 = or(hiRoundPosBitT_E, T_1586) + node T_1588 = not(trueLtX_E1) + node T_1589 = and(extraT_E, T_1588) + node T_1590 = and(T_1589, all1sHiRoundExtraT_E) + node T_1591 = or(T_1587, T_1590) + node T_1592 = and(roundingMode_near_even_PC, T_1591) + node T_1593 = or(T_1581, T_1592) + node T_1594 = mux(T_1593, sigY1_E, sigY0_E) + node T_1595 = not(roundEvenMask_E1) + node sigY_E1 = and(T_1594, T_1595) + node fractY_E1 = bits(sigY_E1, 51, 0) + node inexactY_E1 = or(hiRoundPosBit_E1, anyRoundExtra_E1) + node T_1599 = bit(sigY_E1, 53) + node T_1600 = not(T_1599) + node T_1602 = mux(T_1600, sExpX_E, UInt<1>("h00")) + node T_1603 = bit(sigY_E1, 53) + node T_1604 = not(sqrtOp_PC) + node T_1605 = and(T_1603, T_1604) + node T_1606 = and(T_1605, E_E_div) + node T_1608 = mux(T_1606, expP1_PC, UInt<1>("h00")) + node T_1609 = or(T_1602, T_1608) + node T_1610 = bit(sigY_E1, 53) + node T_1611 = not(sqrtOp_PC) + node T_1612 = and(T_1610, T_1611) + node T_1613 = not(E_E_div) + node T_1614 = and(T_1612, T_1613) + node T_1616 = mux(T_1614, expP2_PC, UInt<1>("h00")) + node T_1617 = or(T_1609, T_1616) + node T_1618 = bit(sigY_E1, 53) + node T_1619 = and(T_1618, sqrtOp_PC) + node T_1620 = shr(expP2_PC, 1) + node T_1622 = addw(T_1620, UInt<12>("h0400")) + node T_1624 = mux(T_1619, T_1622, UInt<1>("h00")) + node sExpY_E1 = or(T_1617, T_1624) + node expY_E1 = bits(sExpY_E1, 11, 0) + node T_1627 = bit(sExpY_E1, 13) + node T_1628 = not(T_1627) + node T_1630 = bits(sExpY_E1, 12, 10) + node T_1631 = leq(UInt<3>("h03"), T_1630) + node overflowY_E1 = and(T_1628, T_1631) + node T_1633 = bit(sExpY_E1, 13) + node T_1634 = bits(sExpY_E1, 12, 0) + node T_1636 = lt(T_1634, UInt<13>("h03ce")) + node totalUnderflowY_E1 = or(T_1633, T_1636) + node T_1639 = leq(posExpX_E, UInt<13>("h0401")) + node T_1640 = and(T_1639, inexactY_E1) + node underflowY_E1 = or(totalUnderflowY_E1, T_1640) + node T_1642 = not(isNaNB_PC) + node T_1643 = not(isZeroB_PC) + node T_1644 = and(T_1642, T_1643) + node T_1645 = and(T_1644, sign_PC) + node T_1646 = and(isZeroA_PC, isZeroB_PC) + node T_1647 = and(isInfA_PC, isInfB_PC) + node T_1648 = or(T_1646, T_1647) + node notSigNaN_invalid_PC = mux(sqrtOp_PC, T_1645, T_1648) + node T_1650 = not(sqrtOp_PC) + node T_1651 = and(T_1650, isSigNaNA_PC) + node T_1652 = or(T_1651, isSigNaNB_PC) + node invalid_PC = or(T_1652, notSigNaN_invalid_PC) + node T_1654 = not(sqrtOp_PC) + node T_1655 = not(isSpecialA_PC) + node T_1656 = and(T_1654, T_1655) + node T_1657 = not(isZeroA_PC) + node T_1658 = and(T_1656, T_1657) + node infinity_PC = and(T_1658, isZeroB_PC) + node overflow_E1 = and(normalCase_PC, overflowY_E1) + node underflow_E1 = and(normalCase_PC, underflowY_E1) + node T_1662 = or(overflow_E1, underflow_E1) + node T_1663 = and(normalCase_PC, inexactY_E1) + node inexact_E1 = or(T_1662, T_1663) + node T_1665 = or(isZeroA_PC, isInfB_PC) + node T_1666 = not(roundMagUp_PC) + node T_1667 = and(totalUnderflowY_E1, T_1666) + node T_1668 = or(T_1665, T_1667) + node notSpecial_isZeroOut_E1 = mux(sqrtOp_PC, isZeroB_PC, T_1668) + node T_1670 = and(normalCase_PC, totalUnderflowY_E1) + node pegMinFiniteMagOut_E1 = and(T_1670, roundMagUp_PC) + node T_1672 = not(overflowY_roundMagUp_PC) + node pegMaxFiniteMagOut_E1 = and(overflow_E1, T_1672) + node T_1674 = or(isInfA_PC, isZeroB_PC) + node T_1675 = and(overflow_E1, overflowY_roundMagUp_PC) + node T_1676 = or(T_1674, T_1675) + node notNaN_isInfOut_E1 = mux(sqrtOp_PC, isInfB_PC, T_1676) + node T_1678 = not(sqrtOp_PC) + node T_1679 = and(T_1678, isNaNA_PC) + node T_1680 = or(T_1679, isNaNB_PC) + node isNaNOut_PC = or(T_1680, notSigNaN_invalid_PC) + node T_1682 = and(isZeroB_PC, sign_PC) + node T_1683 = mux(sqrtOp_PC, T_1682, sign_PC) + node signOut_PC = or(isNaNOut_PC, T_1683) + node T_1686 = not(UInt<12>("h01ff")) + node T_1688 = mux(notSpecial_isZeroOut_E1, T_1686, UInt<1>("h00")) + node T_1689 = not(T_1688) + node T_1690 = and(expY_E1, T_1689) + node T_1692 = not(UInt<12>("h03ce")) + node T_1694 = mux(pegMinFiniteMagOut_E1, T_1692, UInt<1>("h00")) + node T_1695 = not(T_1694) + node T_1696 = and(T_1690, T_1695) + node T_1698 = not(UInt<12>("h0bff")) + node T_1700 = mux(pegMaxFiniteMagOut_E1, T_1698, UInt<1>("h00")) + node T_1701 = not(T_1700) + node T_1702 = and(T_1696, T_1701) + node T_1704 = not(UInt<12>("h0dff")) + node T_1706 = mux(notNaN_isInfOut_E1, T_1704, UInt<1>("h00")) + node T_1707 = not(T_1706) + node T_1708 = and(T_1702, T_1707) + node T_1711 = mux(pegMinFiniteMagOut_E1, UInt<12>("h03ce"), UInt<1>("h00")) + node T_1712 = or(T_1708, T_1711) + node T_1715 = mux(pegMaxFiniteMagOut_E1, UInt<12>("h0bff"), UInt<1>("h00")) + node T_1716 = or(T_1712, T_1715) + node T_1719 = mux(notNaN_isInfOut_E1, UInt<12>("h0c00"), UInt<1>("h00")) + node T_1720 = or(T_1716, T_1719) + node T_1723 = mux(isNaNOut_PC, UInt<12>("h0e00"), UInt<1>("h00")) + node expOut_E1 = or(T_1720, T_1723) + node T_1725 = and(totalUnderflowY_E1, roundMagUp_PC) + node T_1727 = mux(T_1725, UInt<1>("h00"), fractY_E1) + node T_1728 = or(isNaNOut_PC, pegMaxFiniteMagOut_E1) + node T_1731 = mux(T_1728, UInt<52>("h0fffffffffffff"), UInt<1>("h00")) + node fractOut_E1 = or(T_1727, T_1731) + node T_1733 = cat(expOut_E1, fractOut_E1) + node T_1734 = cat(signOut_PC, T_1733) + out := T_1734 + node T_1735 = cat(invalid_PC, infinity_PC) + node T_1736 = cat(underflow_E1, inexact_E1) + node T_1737 = cat(overflow_E1, T_1736) + node T_1738 = cat(T_1735, T_1737) + exceptionFlags := T_1738 + + module mul54 : + output result_s3 : UInt<105> + input c_s2 : UInt<105> + input b_s0 : UInt<54> + input latch_b_s0 : UInt<1> + input a_s0 : UInt<54> + input latch_a_s0 : UInt<1> + input val_s0 : UInt<1> + input clock : Clock + input reset : UInt<1> + + result_s3 := UInt<1>("h00") + reg val_s1 : UInt<1>, clock, reset + reg val_s2 : UInt<1>, clock, reset + reg reg_a_s1 : UInt<54>, clock, reset + reg reg_b_s1 : UInt<54>, clock, reset + reg reg_a_s2 : UInt<54>, clock, reset + reg reg_b_s2 : UInt<54>, clock, reset + reg reg_result_s3 : UInt<105>, clock, reset + val_s1 := val_s0 + val_s2 := val_s1 + when val_s0 : + when latch_a_s0 : + reg_a_s1 := a_s0 + skip + when latch_b_s0 : + reg_b_s1 := b_s0 + skip + skip + when val_s1 : + reg_a_s2 := reg_a_s1 + reg_b_s2 := reg_b_s1 + skip + when val_s2 : + node T_24 = mul(reg_a_s2, reg_b_s2) + node T_25 = addw(T_24, c_s2) + reg_result_s3 := T_25 + skip + result_s3 := reg_result_s3 + + module divSqrtRecodedFloat64 : + output exceptionFlags : UInt<5> + output out : UInt<65> + output outValid_sqrt : UInt<1> + output outValid_div : UInt<1> + input roundingMode : UInt<2> + input b : UInt<65> + input a : UInt<65> + input sqrtOp : UInt<1> + input inValid : UInt<1> + output inReady_sqrt : UInt<1> + output inReady_div : UInt<1> + input clock : Clock + input reset : UInt<1> + + exceptionFlags := UInt<1>("h00") + out := UInt<1>("h00") + outValid_sqrt := UInt<1>("h00") + outValid_div := UInt<1>("h00") + inReady_sqrt := UInt<1>("h00") + inReady_div := UInt<1>("h00") + inst ds of divSqrtRecodedFloat64_mulAddZ31 + ds.mulAddResult_3 := UInt<1>("h00") + ds.roundingMode := UInt<1>("h00") + ds.b := UInt<1>("h00") + ds.a := UInt<1>("h00") + ds.sqrtOp := UInt<1>("h00") + ds.inValid := UInt<1>("h00") + ds.reset := UInt<1>("h00") + ds.clock := clock + ds.reset := reset + inReady_div := ds.inReady_div + inReady_sqrt := ds.inReady_sqrt + ds.inValid := inValid + ds.sqrtOp := sqrtOp + ds.a := a + ds.b := b + ds.roundingMode := roundingMode + outValid_div := ds.outValid_div + outValid_sqrt := ds.outValid_sqrt + out := ds.out + exceptionFlags := ds.exceptionFlags + inst mul of mul54 + mul.c_s2 := UInt<1>("h00") + mul.b_s0 := UInt<1>("h00") + mul.latch_b_s0 := UInt<1>("h00") + mul.a_s0 := UInt<1>("h00") + mul.latch_a_s0 := UInt<1>("h00") + mul.val_s0 := UInt<1>("h00") + mul.reset := UInt<1>("h00") + mul.clock := clock + mul.reset := reset + node T_28 = bit(ds.usingMulAdd, 0) + mul.val_s0 := T_28 + mul.latch_a_s0 := ds.latchMulAddA_0 + mul.a_s0 := ds.mulAddA_0 + mul.latch_b_s0 := ds.latchMulAddB_0 + mul.b_s0 := ds.mulAddB_0 + mul.c_s2 := ds.mulAddC_2 + ds.mulAddResult_3 := mul.result_s3 + + module FPU : + output sboard_clra : UInt<5> + output sboard_clr : UInt<1> + output sboard_set : UInt<1> + output dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>} + input killm : UInt<1> + input killx : UInt<1> + output illegal_rm : UInt<1> + output nack_mem : UInt<1> + output fcsr_rdy : UInt<1> + input valid : UInt<1> + input dmem_resp_data : UInt<64> + input dmem_resp_tag : UInt<5> + input dmem_resp_type : UInt<3> + input dmem_resp_val : UInt<1> + output toint_data : UInt<64> + output store_data : UInt<64> + output fcsr_flags : {valid : UInt<1>, bits : UInt<5>} + input fcsr_rm : UInt<3> + input fromint_data : UInt<64> + input inst_1 : UInt<32> + input clock : Clock + input reset : UInt<1> + + sboard_clra := UInt<1>("h00") + sboard_clr := UInt<1>("h00") + sboard_set := UInt<1>("h00") + dec.wflags := UInt<1>("h00") + dec.round := UInt<1>("h00") + dec.sqrt := UInt<1>("h00") + dec.div := UInt<1>("h00") + dec.fma := UInt<1>("h00") + dec.fastpipe := UInt<1>("h00") + dec.toint := UInt<1>("h00") + dec.fromint := UInt<1>("h00") + dec.single := UInt<1>("h00") + dec.swap23 := UInt<1>("h00") + dec.swap12 := UInt<1>("h00") + dec.ren3 := UInt<1>("h00") + dec.ren2 := UInt<1>("h00") + dec.ren1 := UInt<1>("h00") + dec.wen := UInt<1>("h00") + dec.ldst := UInt<1>("h00") + dec.cmd := UInt<1>("h00") + illegal_rm := UInt<1>("h00") + nack_mem := UInt<1>("h00") + fcsr_rdy := UInt<1>("h00") + toint_data := UInt<1>("h00") + store_data := UInt<1>("h00") + fcsr_flags.bits := UInt<1>("h00") + fcsr_flags.valid := UInt<1>("h00") + reg ex_reg_valid : UInt<1>, clock, reset + onreset ex_reg_valid := UInt<1>("h00") + ex_reg_valid := valid + reg ex_reg_inst : UInt<32>, clock, reset + when valid : + ex_reg_inst := inst_1 + skip + node T_69 = eq(killx, UInt<1>("h00")) + node T_70 = and(ex_reg_valid, T_69) + reg mem_reg_valid : UInt<1>, clock, reset + onreset mem_reg_valid := UInt<1>("h00") + mem_reg_valid := T_70 + reg mem_reg_inst : UInt<32>, clock, reset + when ex_reg_valid : + mem_reg_inst := ex_reg_inst + skip + node killm_2 = or(killm, nack_mem) + node T_76 = eq(killm_2, UInt<1>("h00")) + node T_77 = and(mem_reg_valid, T_76) + reg wb_reg_valid : UInt<1>, clock, reset + onreset wb_reg_valid := UInt<1>("h00") + wb_reg_valid := T_77 + inst fp_decoder of FPUDecoder + fp_decoder.inst_1 := UInt<1>("h00") + fp_decoder.reset := UInt<1>("h00") + fp_decoder.clock := clock + fp_decoder.reset := reset + fp_decoder.inst_1 := inst_1 + reg ex_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clock, reset + when valid : + ex_ctrl <> fp_decoder.sigs + skip + reg mem_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clock, reset + when ex_reg_valid : + mem_ctrl <> ex_ctrl + skip + reg wb_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clock, reset + when mem_reg_valid : + wb_ctrl <> mem_ctrl + skip + reg load_wb : UInt<1>, clock, reset + load_wb := dmem_resp_val + node T_137 = eq(dmem_resp_type, UInt<3>("h02")) + node T_138 = eq(dmem_resp_type, UInt<3>("h06")) + node T_139 = or(T_137, T_138) + reg load_wb_single : UInt<1>, clock, reset + when dmem_resp_val : + load_wb_single := T_139 + skip + reg load_wb_data : UInt<64>, clock, reset + when dmem_resp_val : + load_wb_data := dmem_resp_data + skip + reg load_wb_tag : UInt<5>, clock, reset + when dmem_resp_val : + load_wb_tag := dmem_resp_tag + skip + node T_143 = bit(load_wb_data, 31) + node T_144 = bits(load_wb_data, 30, 23) + node T_145 = bits(load_wb_data, 22, 0) + node T_147 = eq(T_144, UInt<1>("h00")) + node T_149 = eq(T_145, UInt<1>("h00")) + node T_150 = and(T_147, T_149) + node T_152 = eq(T_149, UInt<1>("h00")) + node T_153 = and(T_147, T_152) + node T_154 = shl(T_145, 9) + node T_155 = bit(T_154, 31) + node T_157 = bit(T_154, 30) + node T_159 = bit(T_154, 29) + node T_161 = bit(T_154, 28) + node T_163 = bit(T_154, 27) + node T_165 = bit(T_154, 26) + node T_167 = bit(T_154, 25) + node T_169 = bit(T_154, 24) + node T_171 = bit(T_154, 23) + node T_173 = bit(T_154, 22) + node T_175 = bit(T_154, 21) + node T_177 = bit(T_154, 20) + node T_179 = bit(T_154, 19) + node T_181 = bit(T_154, 18) + node T_183 = bit(T_154, 17) + node T_185 = bit(T_154, 16) + node T_187 = bit(T_154, 15) + node T_189 = bit(T_154, 14) + node T_191 = bit(T_154, 13) + node T_193 = bit(T_154, 12) + node T_195 = bit(T_154, 11) + node T_197 = bit(T_154, 10) + node T_199 = bit(T_154, 9) + node T_201 = bit(T_154, 8) + node T_203 = bit(T_154, 7) + node T_205 = bit(T_154, 6) + node T_207 = bit(T_154, 5) + node T_209 = bit(T_154, 4) + node T_211 = bit(T_154, 3) + node T_213 = bit(T_154, 2) + node T_215 = bit(T_154, 1) + node T_216 = shl(T_215, 0) + node T_217 = mux(T_213, UInt<2>("h02"), T_216) + node T_218 = mux(T_211, UInt<2>("h03"), T_217) + node T_219 = mux(T_209, UInt<3>("h04"), T_218) + node T_220 = mux(T_207, UInt<3>("h05"), T_219) + node T_221 = mux(T_205, UInt<3>("h06"), T_220) + node T_222 = mux(T_203, UInt<3>("h07"), T_221) + node T_223 = mux(T_201, UInt<4>("h08"), T_222) + node T_224 = mux(T_199, UInt<4>("h09"), T_223) + node T_225 = mux(T_197, UInt<4>("h0a"), T_224) + node T_226 = mux(T_195, UInt<4>("h0b"), T_225) + node T_227 = mux(T_193, UInt<4>("h0c"), T_226) + node T_228 = mux(T_191, UInt<4>("h0d"), T_227) + node T_229 = mux(T_189, UInt<4>("h0e"), T_228) + node T_230 = mux(T_187, UInt<4>("h0f"), T_229) + node T_231 = mux(T_185, UInt<5>("h010"), T_230) + node T_232 = mux(T_183, UInt<5>("h011"), T_231) + node T_233 = mux(T_181, UInt<5>("h012"), T_232) + node T_234 = mux(T_179, UInt<5>("h013"), T_233) + node T_235 = mux(T_177, UInt<5>("h014"), T_234) + node T_236 = mux(T_175, UInt<5>("h015"), T_235) + node T_237 = mux(T_173, UInt<5>("h016"), T_236) + node T_238 = mux(T_171, UInt<5>("h017"), T_237) + node T_239 = mux(T_169, UInt<5>("h018"), T_238) + node T_240 = mux(T_167, UInt<5>("h019"), T_239) + node T_241 = mux(T_165, UInt<5>("h01a"), T_240) + node T_242 = mux(T_163, UInt<5>("h01b"), T_241) + node T_243 = mux(T_161, UInt<5>("h01c"), T_242) + node T_244 = mux(T_159, UInt<5>("h01d"), T_243) + node T_245 = mux(T_157, UInt<5>("h01e"), T_244) + node T_246 = mux(T_155, UInt<5>("h01f"), T_245) + node T_247 = not(T_246) + node T_248 = dshl(T_154, T_247) + node T_251 = subw(UInt<4>("h00"), UInt<1>("h01")) + node T_252 = not(T_247) + node T_253 = cat(T_251, T_252) + node T_254 = bits(T_248, 30, 8) + node T_256 = mux(T_149, UInt<1>("h00"), T_253) + node T_257 = mux(T_147, T_256, T_144) + node T_262 = mux(T_153, UInt<2>("h02"), UInt<1>("h01")) + node T_263 = or(UInt<8>("h080"), T_262) + node T_264 = mux(T_150, UInt<1>("h00"), T_263) + node T_265 = addw(T_257, T_264) + node T_266 = bits(T_265, 8, 7) + node T_267 = not(T_266) + node T_269 = eq(T_267, UInt<1>("h00")) + node T_271 = eq(T_149, UInt<1>("h00")) + node T_272 = and(T_269, T_271) + node T_273 = shl(T_272, 6) + node T_274 = or(T_265, T_273) + node T_275 = mux(T_147, T_254, T_145) + node T_276 = cat(T_274, T_275) + node rec_s = cat(T_143, T_276) + node T_278 = bit(load_wb_data, 63) + node T_279 = bits(load_wb_data, 62, 52) + node T_280 = bits(load_wb_data, 51, 0) + node T_282 = eq(T_279, UInt<1>("h00")) + node T_284 = eq(T_280, UInt<1>("h00")) + node T_285 = and(T_282, T_284) + node T_287 = eq(T_284, UInt<1>("h00")) + node T_288 = and(T_282, T_287) + node T_289 = shl(T_280, 12) + node T_290 = bit(T_289, 63) + node T_292 = bit(T_289, 62) + node T_294 = bit(T_289, 61) + node T_296 = bit(T_289, 60) + node T_298 = bit(T_289, 59) + node T_300 = bit(T_289, 58) + node T_302 = bit(T_289, 57) + node T_304 = bit(T_289, 56) + node T_306 = bit(T_289, 55) + node T_308 = bit(T_289, 54) + node T_310 = bit(T_289, 53) + node T_312 = bit(T_289, 52) + node T_314 = bit(T_289, 51) + node T_316 = bit(T_289, 50) + node T_318 = bit(T_289, 49) + node T_320 = bit(T_289, 48) + node T_322 = bit(T_289, 47) + node T_324 = bit(T_289, 46) + node T_326 = bit(T_289, 45) + node T_328 = bit(T_289, 44) + node T_330 = bit(T_289, 43) + node T_332 = bit(T_289, 42) + node T_334 = bit(T_289, 41) + node T_336 = bit(T_289, 40) + node T_338 = bit(T_289, 39) + node T_340 = bit(T_289, 38) + node T_342 = bit(T_289, 37) + node T_344 = bit(T_289, 36) + node T_346 = bit(T_289, 35) + node T_348 = bit(T_289, 34) + node T_350 = bit(T_289, 33) + node T_352 = bit(T_289, 32) + node T_354 = bit(T_289, 31) + node T_356 = bit(T_289, 30) + node T_358 = bit(T_289, 29) + node T_360 = bit(T_289, 28) + node T_362 = bit(T_289, 27) + node T_364 = bit(T_289, 26) + node T_366 = bit(T_289, 25) + node T_368 = bit(T_289, 24) + node T_370 = bit(T_289, 23) + node T_372 = bit(T_289, 22) + node T_374 = bit(T_289, 21) + node T_376 = bit(T_289, 20) + node T_378 = bit(T_289, 19) + node T_380 = bit(T_289, 18) + node T_382 = bit(T_289, 17) + node T_384 = bit(T_289, 16) + node T_386 = bit(T_289, 15) + node T_388 = bit(T_289, 14) + node T_390 = bit(T_289, 13) + node T_392 = bit(T_289, 12) + node T_394 = bit(T_289, 11) + node T_396 = bit(T_289, 10) + node T_398 = bit(T_289, 9) + node T_400 = bit(T_289, 8) + node T_402 = bit(T_289, 7) + node T_404 = bit(T_289, 6) + node T_406 = bit(T_289, 5) + node T_408 = bit(T_289, 4) + node T_410 = bit(T_289, 3) + node T_412 = bit(T_289, 2) + node T_414 = bit(T_289, 1) + node T_415 = shl(T_414, 0) + node T_416 = mux(T_412, UInt<2>("h02"), T_415) + node T_417 = mux(T_410, UInt<2>("h03"), T_416) + node T_418 = mux(T_408, UInt<3>("h04"), T_417) + node T_419 = mux(T_406, UInt<3>("h05"), T_418) + node T_420 = mux(T_404, UInt<3>("h06"), T_419) + node T_421 = mux(T_402, UInt<3>("h07"), T_420) + node T_422 = mux(T_400, UInt<4>("h08"), T_421) + node T_423 = mux(T_398, UInt<4>("h09"), T_422) + node T_424 = mux(T_396, UInt<4>("h0a"), T_423) + node T_425 = mux(T_394, UInt<4>("h0b"), T_424) + node T_426 = mux(T_392, UInt<4>("h0c"), T_425) + node T_427 = mux(T_390, UInt<4>("h0d"), T_426) + node T_428 = mux(T_388, UInt<4>("h0e"), T_427) + node T_429 = mux(T_386, UInt<4>("h0f"), T_428) + node T_430 = mux(T_384, UInt<5>("h010"), T_429) + node T_431 = mux(T_382, UInt<5>("h011"), T_430) + node T_432 = mux(T_380, UInt<5>("h012"), T_431) + node T_433 = mux(T_378, UInt<5>("h013"), T_432) + node T_434 = mux(T_376, UInt<5>("h014"), T_433) + node T_435 = mux(T_374, UInt<5>("h015"), T_434) + node T_436 = mux(T_372, UInt<5>("h016"), T_435) + node T_437 = mux(T_370, UInt<5>("h017"), T_436) + node T_438 = mux(T_368, UInt<5>("h018"), T_437) + node T_439 = mux(T_366, UInt<5>("h019"), T_438) + node T_440 = mux(T_364, UInt<5>("h01a"), T_439) + node T_441 = mux(T_362, UInt<5>("h01b"), T_440) + node T_442 = mux(T_360, UInt<5>("h01c"), T_441) + node T_443 = mux(T_358, UInt<5>("h01d"), T_442) + node T_444 = mux(T_356, UInt<5>("h01e"), T_443) + node T_445 = mux(T_354, UInt<5>("h01f"), T_444) + node T_446 = mux(T_352, UInt<6>("h020"), T_445) + node T_447 = mux(T_350, UInt<6>("h021"), T_446) + node T_448 = mux(T_348, UInt<6>("h022"), T_447) + node T_449 = mux(T_346, UInt<6>("h023"), T_448) + node T_450 = mux(T_344, UInt<6>("h024"), T_449) + node T_451 = mux(T_342, UInt<6>("h025"), T_450) + node T_452 = mux(T_340, UInt<6>("h026"), T_451) + node T_453 = mux(T_338, UInt<6>("h027"), T_452) + node T_454 = mux(T_336, UInt<6>("h028"), T_453) + node T_455 = mux(T_334, UInt<6>("h029"), T_454) + node T_456 = mux(T_332, UInt<6>("h02a"), T_455) + node T_457 = mux(T_330, UInt<6>("h02b"), T_456) + node T_458 = mux(T_328, UInt<6>("h02c"), T_457) + node T_459 = mux(T_326, UInt<6>("h02d"), T_458) + node T_460 = mux(T_324, UInt<6>("h02e"), T_459) + node T_461 = mux(T_322, UInt<6>("h02f"), T_460) + node T_462 = mux(T_320, UInt<6>("h030"), T_461) + node T_463 = mux(T_318, UInt<6>("h031"), T_462) + node T_464 = mux(T_316, UInt<6>("h032"), T_463) + node T_465 = mux(T_314, UInt<6>("h033"), T_464) + node T_466 = mux(T_312, UInt<6>("h034"), T_465) + node T_467 = mux(T_310, UInt<6>("h035"), T_466) + node T_468 = mux(T_308, UInt<6>("h036"), T_467) + node T_469 = mux(T_306, UInt<6>("h037"), T_468) + node T_470 = mux(T_304, UInt<6>("h038"), T_469) + node T_471 = mux(T_302, UInt<6>("h039"), T_470) + node T_472 = mux(T_300, UInt<6>("h03a"), T_471) + node T_473 = mux(T_298, UInt<6>("h03b"), T_472) + node T_474 = mux(T_296, UInt<6>("h03c"), T_473) + node T_475 = mux(T_294, UInt<6>("h03d"), T_474) + node T_476 = mux(T_292, UInt<6>("h03e"), T_475) + node T_477 = mux(T_290, UInt<6>("h03f"), T_476) + node T_478 = not(T_477) + node T_479 = dshl(T_289, T_478) + node T_482 = subw(UInt<6>("h00"), UInt<1>("h01")) + node T_483 = not(T_478) + node T_484 = cat(T_482, T_483) + node T_485 = bits(T_479, 62, 11) + node T_487 = mux(T_284, UInt<1>("h00"), T_484) + node T_488 = mux(T_282, T_487, T_279) + node T_493 = mux(T_288, UInt<2>("h02"), UInt<1>("h01")) + node T_494 = or(UInt<11>("h0400"), T_493) + node T_495 = mux(T_285, UInt<1>("h00"), T_494) + node T_496 = addw(T_488, T_495) + node T_497 = bits(T_496, 11, 10) + node T_498 = not(T_497) + node T_500 = eq(T_498, UInt<1>("h00")) + node T_502 = eq(T_284, UInt<1>("h00")) + node T_503 = and(T_500, T_502) + node T_504 = shl(T_503, 9) + node T_505 = or(T_496, T_504) + node T_506 = mux(T_282, T_485, T_280) + node T_507 = cat(T_505, T_506) + node rec_d = cat(T_278, T_507) + node T_510 = asUInt(asSInt(UInt<32>("h0ffffffff"))) + node T_511 = cat(T_510, rec_s) + node load_wb_data_recoded = mux(load_wb_single, T_511, rec_d) + cmem regfile : UInt<65>[32], clock + when load_wb : + infer accessor T_516 = regfile[load_wb_tag] + T_516 := load_wb_data_recoded + skip + reg ex_ra1 : UInt<?>, clock, reset + reg ex_ra2 : UInt<?>, clock, reset + reg ex_ra3 : UInt<?>, clock, reset + when valid : + when fp_decoder.sigs.ren1 : + node T_524 = eq(fp_decoder.sigs.swap12, UInt<1>("h00")) + when T_524 : + node T_525 = bits(inst_1, 19, 15) + ex_ra1 := T_525 + skip + when fp_decoder.sigs.swap12 : + node T_526 = bits(inst_1, 19, 15) + ex_ra2 := T_526 + skip + skip + when fp_decoder.sigs.ren2 : + when fp_decoder.sigs.swap12 : + node T_527 = bits(inst_1, 24, 20) + ex_ra1 := T_527 + skip + when fp_decoder.sigs.swap23 : + node T_528 = bits(inst_1, 24, 20) + ex_ra3 := T_528 + skip + node T_530 = eq(fp_decoder.sigs.swap12, UInt<1>("h00")) + node T_532 = eq(fp_decoder.sigs.swap23, UInt<1>("h00")) + node T_533 = and(T_530, T_532) + when T_533 : + node T_534 = bits(inst_1, 24, 20) + ex_ra2 := T_534 + skip + skip + when fp_decoder.sigs.ren3 : + node T_535 = bits(inst_1, 31, 27) + ex_ra3 := T_535 + skip + skip + infer accessor ex_rs1 = regfile[ex_ra1] + infer accessor ex_rs2 = regfile[ex_ra2] + infer accessor ex_rs3 = regfile[ex_ra3] + node T_539 = bits(ex_reg_inst, 14, 12) + node T_541 = eq(T_539, UInt<3>("h07")) + node T_542 = bits(ex_reg_inst, 14, 12) + node ex_rm = mux(T_541, fcsr_rm, T_542) + wire req : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} + req.in3 := UInt<1>("h00") + req.in2 := UInt<1>("h00") + req.in1 := UInt<1>("h00") + req.typ := UInt<1>("h00") + req.rm := UInt<1>("h00") + req.wflags := UInt<1>("h00") + req.round := UInt<1>("h00") + req.sqrt := UInt<1>("h00") + req.div := UInt<1>("h00") + req.fma := UInt<1>("h00") + req.fastpipe := UInt<1>("h00") + req.toint := UInt<1>("h00") + req.fromint := UInt<1>("h00") + req.single := UInt<1>("h00") + req.swap23 := UInt<1>("h00") + req.swap12 := UInt<1>("h00") + req.ren3 := UInt<1>("h00") + req.ren2 := UInt<1>("h00") + req.ren1 := UInt<1>("h00") + req.wen := UInt<1>("h00") + req.ldst := UInt<1>("h00") + req.cmd := UInt<1>("h00") + req <> ex_ctrl + req.rm := ex_rm + req.in1 := ex_rs1 + req.in2 := ex_rs2 + req.in3 := ex_rs3 + node T_612 = bits(ex_reg_inst, 21, 20) + req.typ := T_612 + inst sfma of FPUFMAPipe + sfma.in.bits.in3 := UInt<1>("h00") + sfma.in.bits.in2 := UInt<1>("h00") + sfma.in.bits.in1 := UInt<1>("h00") + sfma.in.bits.typ := UInt<1>("h00") + sfma.in.bits.rm := UInt<1>("h00") + sfma.in.bits.wflags := UInt<1>("h00") + sfma.in.bits.round := UInt<1>("h00") + sfma.in.bits.sqrt := UInt<1>("h00") + sfma.in.bits.div := UInt<1>("h00") + sfma.in.bits.fma := UInt<1>("h00") + sfma.in.bits.fastpipe := UInt<1>("h00") + sfma.in.bits.toint := UInt<1>("h00") + sfma.in.bits.fromint := UInt<1>("h00") + sfma.in.bits.single := UInt<1>("h00") + sfma.in.bits.swap23 := UInt<1>("h00") + sfma.in.bits.swap12 := UInt<1>("h00") + sfma.in.bits.ren3 := UInt<1>("h00") + sfma.in.bits.ren2 := UInt<1>("h00") + sfma.in.bits.ren1 := UInt<1>("h00") + sfma.in.bits.wen := UInt<1>("h00") + sfma.in.bits.ldst := UInt<1>("h00") + sfma.in.bits.cmd := UInt<1>("h00") + sfma.in.valid := UInt<1>("h00") + sfma.reset := UInt<1>("h00") + sfma.clock := clock + sfma.reset := reset + node T_637 = and(ex_reg_valid, ex_ctrl.fma) + node T_638 = and(T_637, ex_ctrl.single) + sfma.in.valid := T_638 + sfma.in.bits <> req + inst dfma of FPUFMAPipe_70 + dfma.in.bits.in3 := UInt<1>("h00") + dfma.in.bits.in2 := UInt<1>("h00") + dfma.in.bits.in1 := UInt<1>("h00") + dfma.in.bits.typ := UInt<1>("h00") + dfma.in.bits.rm := UInt<1>("h00") + dfma.in.bits.wflags := UInt<1>("h00") + dfma.in.bits.round := UInt<1>("h00") + dfma.in.bits.sqrt := UInt<1>("h00") + dfma.in.bits.div := UInt<1>("h00") + dfma.in.bits.fma := UInt<1>("h00") + dfma.in.bits.fastpipe := UInt<1>("h00") + dfma.in.bits.toint := UInt<1>("h00") + dfma.in.bits.fromint := UInt<1>("h00") + dfma.in.bits.single := UInt<1>("h00") + dfma.in.bits.swap23 := UInt<1>("h00") + dfma.in.bits.swap12 := UInt<1>("h00") + dfma.in.bits.ren3 := UInt<1>("h00") + dfma.in.bits.ren2 := UInt<1>("h00") + dfma.in.bits.ren1 := UInt<1>("h00") + dfma.in.bits.wen := UInt<1>("h00") + dfma.in.bits.ldst := UInt<1>("h00") + dfma.in.bits.cmd := UInt<1>("h00") + dfma.in.valid := UInt<1>("h00") + dfma.reset := UInt<1>("h00") + dfma.clock := clock + dfma.reset := reset + node T_663 = and(ex_reg_valid, ex_ctrl.fma) + node T_665 = eq(ex_ctrl.single, UInt<1>("h00")) + node T_666 = and(T_663, T_665) + dfma.in.valid := T_666 + dfma.in.bits <> req + inst fpiu of FPToInt + fpiu.in.bits.in3 := UInt<1>("h00") + fpiu.in.bits.in2 := UInt<1>("h00") + fpiu.in.bits.in1 := UInt<1>("h00") + fpiu.in.bits.typ := UInt<1>("h00") + fpiu.in.bits.rm := UInt<1>("h00") + fpiu.in.bits.wflags := UInt<1>("h00") + fpiu.in.bits.round := UInt<1>("h00") + fpiu.in.bits.sqrt := UInt<1>("h00") + fpiu.in.bits.div := UInt<1>("h00") + fpiu.in.bits.fma := UInt<1>("h00") + fpiu.in.bits.fastpipe := UInt<1>("h00") + fpiu.in.bits.toint := UInt<1>("h00") + fpiu.in.bits.fromint := UInt<1>("h00") + fpiu.in.bits.single := UInt<1>("h00") + fpiu.in.bits.swap23 := UInt<1>("h00") + fpiu.in.bits.swap12 := UInt<1>("h00") + fpiu.in.bits.ren3 := UInt<1>("h00") + fpiu.in.bits.ren2 := UInt<1>("h00") + fpiu.in.bits.ren1 := UInt<1>("h00") + fpiu.in.bits.wen := UInt<1>("h00") + fpiu.in.bits.ldst := UInt<1>("h00") + fpiu.in.bits.cmd := UInt<1>("h00") + fpiu.in.valid := UInt<1>("h00") + fpiu.reset := UInt<1>("h00") + fpiu.clock := clock + fpiu.reset := reset + node T_691 = or(ex_ctrl.toint, ex_ctrl.div) + node T_692 = or(T_691, ex_ctrl.sqrt) + node T_695 = and(ex_ctrl.cmd, UInt<4>("h0d")) + node T_696 = eq(UInt<3>("h05"), T_695) + node T_697 = or(T_692, T_696) + node T_698 = and(ex_reg_valid, T_697) + fpiu.in.valid := T_698 + fpiu.in.bits <> req + store_data := fpiu.out.bits.store + toint_data := fpiu.out.bits.toint + inst ifpu of IntToFP + ifpu.in.bits.in3 := UInt<1>("h00") + ifpu.in.bits.in2 := UInt<1>("h00") + ifpu.in.bits.in1 := UInt<1>("h00") + ifpu.in.bits.typ := UInt<1>("h00") + ifpu.in.bits.rm := UInt<1>("h00") + ifpu.in.bits.wflags := UInt<1>("h00") + ifpu.in.bits.round := UInt<1>("h00") + ifpu.in.bits.sqrt := UInt<1>("h00") + ifpu.in.bits.div := UInt<1>("h00") + ifpu.in.bits.fma := UInt<1>("h00") + ifpu.in.bits.fastpipe := UInt<1>("h00") + ifpu.in.bits.toint := UInt<1>("h00") + ifpu.in.bits.fromint := UInt<1>("h00") + ifpu.in.bits.single := UInt<1>("h00") + ifpu.in.bits.swap23 := UInt<1>("h00") + ifpu.in.bits.swap12 := UInt<1>("h00") + ifpu.in.bits.ren3 := UInt<1>("h00") + ifpu.in.bits.ren2 := UInt<1>("h00") + ifpu.in.bits.ren1 := UInt<1>("h00") + ifpu.in.bits.wen := UInt<1>("h00") + ifpu.in.bits.ldst := UInt<1>("h00") + ifpu.in.bits.cmd := UInt<1>("h00") + ifpu.in.valid := UInt<1>("h00") + ifpu.reset := UInt<1>("h00") + ifpu.clock := clock + ifpu.reset := reset + node T_723 = and(ex_reg_valid, ex_ctrl.fromint) + ifpu.in.valid := T_723 + ifpu.in.bits <> req + ifpu.in.bits.in1 := fromint_data + inst fpmu of FPToFP + fpmu.lt := UInt<1>("h00") + fpmu.in.bits.in3 := UInt<1>("h00") + fpmu.in.bits.in2 := UInt<1>("h00") + fpmu.in.bits.in1 := UInt<1>("h00") + fpmu.in.bits.typ := UInt<1>("h00") + fpmu.in.bits.rm := UInt<1>("h00") + fpmu.in.bits.wflags := UInt<1>("h00") + fpmu.in.bits.round := UInt<1>("h00") + fpmu.in.bits.sqrt := UInt<1>("h00") + fpmu.in.bits.div := UInt<1>("h00") + fpmu.in.bits.fma := UInt<1>("h00") + fpmu.in.bits.fastpipe := UInt<1>("h00") + fpmu.in.bits.toint := UInt<1>("h00") + fpmu.in.bits.fromint := UInt<1>("h00") + fpmu.in.bits.single := UInt<1>("h00") + fpmu.in.bits.swap23 := UInt<1>("h00") + fpmu.in.bits.swap12 := UInt<1>("h00") + fpmu.in.bits.ren3 := UInt<1>("h00") + fpmu.in.bits.ren2 := UInt<1>("h00") + fpmu.in.bits.ren1 := UInt<1>("h00") + fpmu.in.bits.wen := UInt<1>("h00") + fpmu.in.bits.ldst := UInt<1>("h00") + fpmu.in.bits.cmd := UInt<1>("h00") + fpmu.in.valid := UInt<1>("h00") + fpmu.reset := UInt<1>("h00") + fpmu.clock := clock + fpmu.reset := reset + node T_749 = and(ex_reg_valid, ex_ctrl.fastpipe) + fpmu.in.valid := T_749 + fpmu.in.bits <> req + fpmu.lt := fpiu.out.bits.lt + reg divSqrt_wen : UInt<1>, clock, reset + divSqrt_wen := UInt<1>("h00") + wire divSqrt_inReady : UInt<1> + divSqrt_inReady := UInt<1>("h00") + reg divSqrt_waddr : UInt<?>, clock, reset + wire divSqrt_wdata : UInt<?> + divSqrt_wdata := UInt<1>("h00") + wire divSqrt_flags : UInt<?> + divSqrt_flags := UInt<1>("h00") + reg divSqrt_in_flight : UInt<1>, clock, reset + onreset divSqrt_in_flight := UInt<1>("h00") + node T_765 = asUInt(asSInt(UInt<32>("h0ffffffff"))) + node T_766 = cat(T_765, sfma.out.bits.data) + node T_769 = mux(mem_ctrl.fastpipe, UInt<1>("h01"), UInt<1>("h00")) + node T_772 = mux(mem_ctrl.fromint, UInt<2>("h02"), UInt<1>("h00")) + node T_773 = and(mem_ctrl.fma, mem_ctrl.single) + node T_776 = mux(T_773, UInt<1>("h01"), UInt<1>("h00")) + node T_778 = eq(mem_ctrl.single, UInt<1>("h00")) + node T_779 = and(mem_ctrl.fma, T_778) + node T_782 = mux(T_779, UInt<2>("h02"), UInt<1>("h00")) + node T_783 = or(T_769, T_772) + node T_784 = or(T_783, T_776) + node memLatencyMask = or(T_784, T_782) + reg wen : UInt<2>, clock, reset + onreset wen := UInt<2>("h00") + reg winfo : UInt<?>[2], clock, reset + node T_800 = or(mem_ctrl.fma, mem_ctrl.fastpipe) + node T_801 = or(T_800, mem_ctrl.fromint) + node mem_wen = and(mem_reg_valid, T_801) + node T_805 = mux(ex_ctrl.fastpipe, UInt<2>("h02"), UInt<1>("h00")) + node T_808 = mux(ex_ctrl.fromint, UInt<3>("h04"), UInt<1>("h00")) + node T_809 = and(ex_ctrl.fma, ex_ctrl.single) + node T_812 = mux(T_809, UInt<2>("h02"), UInt<1>("h00")) + node T_814 = eq(ex_ctrl.single, UInt<1>("h00")) + node T_815 = and(ex_ctrl.fma, T_814) + node T_818 = mux(T_815, UInt<3>("h04"), UInt<1>("h00")) + node T_819 = or(T_805, T_808) + node T_820 = or(T_819, T_812) + node T_821 = or(T_820, T_818) + node T_822 = and(memLatencyMask, T_821) + node T_824 = neq(T_822, UInt<1>("h00")) + node T_825 = and(mem_wen, T_824) + node T_828 = mux(ex_ctrl.fastpipe, UInt<3>("h04"), UInt<1>("h00")) + node T_831 = mux(ex_ctrl.fromint, UInt<4>("h08"), UInt<1>("h00")) + node T_832 = and(ex_ctrl.fma, ex_ctrl.single) + node T_835 = mux(T_832, UInt<3>("h04"), UInt<1>("h00")) + node T_837 = eq(ex_ctrl.single, UInt<1>("h00")) + node T_838 = and(ex_ctrl.fma, T_837) + node T_841 = mux(T_838, UInt<4>("h08"), UInt<1>("h00")) + node T_842 = or(T_828, T_831) + node T_843 = or(T_842, T_835) + node T_844 = or(T_843, T_841) + node T_845 = and(wen, T_844) + node T_847 = neq(T_845, UInt<1>("h00")) + node T_848 = or(T_825, T_847) + reg write_port_busy : UInt<1>, clock, reset + when ex_reg_valid : + write_port_busy := T_848 + skip + node T_852 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) + node T_855 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) + node T_856 = and(mem_ctrl.fma, mem_ctrl.single) + node T_859 = mux(T_856, UInt<2>("h02"), UInt<1>("h00")) + node T_861 = eq(mem_ctrl.single, UInt<1>("h00")) + node T_862 = and(mem_ctrl.fma, T_861) + node T_865 = mux(T_862, UInt<2>("h03"), UInt<1>("h00")) + node T_866 = or(T_852, T_855) + node T_867 = or(T_866, T_859) + node T_868 = or(T_867, T_865) + node T_869 = bits(mem_reg_inst, 11, 7) + node mem_winfo = cat(T_868, T_869) + node T_871 = bit(wen, 1) + when T_871 : + winfo[0] := winfo[1] + skip + node T_872 = shr(wen, 1) + wen := T_872 + when mem_wen : + node T_874 = eq(killm_2, UInt<1>("h00")) + when T_874 : + node T_875 = shr(wen, 1) + node T_876 = or(T_875, memLatencyMask) + wen := T_876 + skip + node T_878 = eq(write_port_busy, UInt<1>("h00")) + node T_879 = bit(memLatencyMask, 0) + node T_880 = and(T_878, T_879) + when T_880 : + winfo[0] := mem_winfo + skip + node T_882 = eq(write_port_busy, UInt<1>("h00")) + node T_883 = bit(memLatencyMask, 1) + node T_884 = and(T_882, T_883) + when T_884 : + winfo[1] := mem_winfo + skip + skip + node T_885 = bits(winfo[0], 4, 0) + node waddr = mux(divSqrt_wen, divSqrt_waddr, T_885) + node wsrc = shr(winfo[0], 5) + wire T_889 : UInt<97>[4] + T_889[0] := fpmu.out.bits.data + T_889[1] := ifpu.out.bits.data + T_889[2] := T_766 + T_889[3] := dfma.out.bits.data + infer accessor T_895 = T_889[wsrc] + node wdata = mux(divSqrt_wen, divSqrt_wdata, T_895) + wire T_898 : UInt<5>[4] + T_898[0] := fpmu.out.bits.exc + T_898[1] := ifpu.out.bits.exc + T_898[2] := sfma.out.bits.exc + T_898[3] := dfma.out.bits.exc + infer accessor wexc = T_898[wsrc] + node T_905 = bit(wen, 0) + node T_906 = or(T_905, divSqrt_wen) + when T_906 : + infer accessor T_907 = regfile[waddr] + T_907 := wdata + skip + node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) + reg wb_toint_exc : UInt<5>, clock, reset + when mem_ctrl.toint : + wb_toint_exc := fpiu.out.bits.exc + skip + node T_910 = or(wb_toint_valid, divSqrt_wen) + node T_911 = bit(wen, 0) + node T_912 = or(T_910, T_911) + fcsr_flags.valid := T_912 + node T_914 = mux(wb_toint_valid, wb_toint_exc, UInt<1>("h00")) + node T_916 = mux(divSqrt_wen, divSqrt_flags, UInt<1>("h00")) + node T_917 = or(T_914, T_916) + node T_918 = bit(wen, 0) + node T_920 = mux(T_918, wexc, UInt<1>("h00")) + node T_921 = or(T_917, T_920) + fcsr_flags.bits := T_921 + node T_922 = or(mem_ctrl.div, mem_ctrl.sqrt) + node T_923 = and(mem_reg_valid, T_922) + node T_925 = eq(divSqrt_inReady, UInt<1>("h00")) + node T_927 = neq(wen, UInt<1>("h00")) + node T_928 = or(T_925, T_927) + node units_busy = and(T_923, T_928) + node T_930 = and(ex_reg_valid, ex_ctrl.wflags) + node T_931 = and(mem_reg_valid, mem_ctrl.wflags) + node T_932 = or(T_930, T_931) + node T_933 = and(wb_reg_valid, wb_ctrl.toint) + node T_934 = or(T_932, T_933) + node T_936 = neq(wen, UInt<1>("h00")) + node T_937 = or(T_934, T_936) + node T_938 = or(T_937, divSqrt_in_flight) + node T_940 = eq(T_938, UInt<1>("h00")) + fcsr_rdy := T_940 + node T_941 = or(units_busy, write_port_busy) + node T_942 = or(T_941, divSqrt_in_flight) + nack_mem := T_942 + dec <> fp_decoder.sigs + node T_944 = or(UInt<1>("h00"), mem_ctrl.div) + node T_945 = or(T_944, mem_ctrl.sqrt) + reg T_946 : UInt<1>, clock, reset + T_946 := T_945 + node T_947 = and(wb_reg_valid, T_946) + sboard_set := T_947 + node T_948 = bit(wen, 0) + node T_950 = and(T_948, UInt<1>("h00")) + node T_951 = or(divSqrt_wen, T_950) + sboard_clr := T_951 + sboard_clra := waddr + node T_952 = bit(ex_rm, 2) + node T_953 = and(T_952, ex_ctrl.round) + illegal_rm := T_953 + divSqrt_wdata := UInt<1>("h00") + divSqrt_flags := UInt<1>("h00") + reg T_957 : UInt<1>, clock, reset + reg T_959 : UInt<?>, clock, reset + reg T_961 : UInt<?>, clock, reset + reg T_963 : UInt<?>, clock, reset + inst T_1151 of divSqrtRecodedFloat64 + T_1151.roundingMode := UInt<1>("h00") + T_1151.b := UInt<1>("h00") + T_1151.a := UInt<1>("h00") + T_1151.sqrtOp := UInt<1>("h00") + T_1151.inValid := UInt<1>("h00") + T_1151.reset := UInt<1>("h00") + T_1151.clock := clock + T_1151.reset := reset + node T_970 = mux(T_1151.sqrtOp, T_1151.inReady_sqrt, T_1151.inReady_div) + divSqrt_inReady := T_970 + node T_971 = or(T_1151.outValid_div, T_1151.outValid_sqrt) + node T_973 = neq(wen, UInt<1>("h00")) + node T_975 = eq(T_973, UInt<1>("h00")) + node T_976 = and(mem_reg_valid, T_975) + node T_978 = eq(divSqrt_in_flight, UInt<1>("h00")) + node T_979 = and(T_976, T_978) + node T_981 = eq(killm, UInt<1>("h00")) + node T_982 = and(T_979, T_981) + node T_983 = or(mem_ctrl.div, mem_ctrl.sqrt) + node T_984 = and(T_982, T_983) + T_1151.inValid := T_984 + T_1151.sqrtOp := mem_ctrl.sqrt + T_1151.a := fpiu.as_double.in1 + T_1151.b := fpiu.as_double.in2 + T_1151.roundingMode := fpiu.as_double.rm + node T_985 = and(T_1151.inValid, divSqrt_inReady) + when T_985 : + divSqrt_in_flight := UInt<1>("h01") + T_957 := mem_ctrl.single + node T_987 = bits(mem_reg_inst, 11, 7) + divSqrt_waddr := T_987 + T_959 := T_1151.roundingMode + skip + when T_971 : + divSqrt_wen := UInt<1>("h01") + T_963 := T_1151.out + divSqrt_in_flight := UInt<1>("h00") + T_961 := T_1151.exceptionFlags + skip + node T_990 = bit(T_963, 64) + node T_991 = bits(T_963, 51, 0) + node T_992 = bits(T_963, 63, 52) + node T_993 = bits(T_963, 63, 61) + node T_994 = bits(T_963, 62, 52) + node T_995 = not(T_993) + node T_997 = eq(T_995, UInt<1>("h00")) + node T_998 = bit(T_991, 51) + node T_1000 = eq(T_998, UInt<1>("h00")) + node T_1001 = and(T_997, T_1000) + node T_1006 = neq(T_993, UInt<1>("h00")) + node T_1008 = eq(T_1006, UInt<1>("h00")) + node T_1009 = bits(T_993, 2, 1) + node T_1010 = not(T_1009) + node T_1012 = eq(T_1010, UInt<1>("h00")) + node T_1013 = or(T_1008, T_1012) + node T_1014 = geq(T_992, UInt<11>("h076a")) + node T_1015 = leq(T_992, UInt<11>("h0781")) + node T_1016 = and(T_1014, T_1015) + node T_1017 = lt(T_992, UInt<11>("h076a")) + node T_1019 = eq(T_1013, UInt<1>("h00")) + node T_1020 = and(T_1017, T_1019) + node T_1021 = gt(T_992, UInt<12>("h087f")) + node T_1023 = eq(T_1013, UInt<1>("h00")) + node T_1024 = and(T_1021, T_1023) + node T_1026 = addw(UInt<11>("h0781"), UInt<1>("h01")) + node T_1027 = subw(T_1026, T_992) + node T_1029 = mux(T_1016, T_1027, UInt<1>("h00")) + node T_1030 = bits(T_1029, 4, 0) + node T_1032 = bits(T_991, 51, 28) + node T_1034 = cat(T_1032, UInt<24>("h00")) + node T_1035 = cat(UInt<1>("h01"), T_1034) + node T_1036 = dshr(T_1035, T_1030) + node T_1037 = bits(T_1036, 23, 0) + node T_1039 = neq(T_1037, UInt<1>("h00")) + node T_1040 = bits(T_991, 27, 0) + node T_1042 = neq(T_1040, UInt<1>("h00")) + node T_1043 = or(T_1039, T_1042) + node T_1044 = bits(T_1036, 25, 24) + node T_1045 = cat(T_1044, T_1043) + node T_1046 = bits(T_1045, 1, 0) + node T_1048 = neq(T_1046, UInt<1>("h00")) + node T_1050 = eq(T_1013, UInt<1>("h00")) + node T_1051 = and(T_1048, T_1050) + node T_1052 = eq(ex_rm, UInt<2>("h00")) + node T_1053 = bits(T_1045, 1, 0) + node T_1054 = not(T_1053) + node T_1056 = eq(T_1054, UInt<1>("h00")) + node T_1057 = bits(T_1045, 2, 1) + node T_1058 = not(T_1057) + node T_1060 = eq(T_1058, UInt<1>("h00")) + node T_1061 = or(T_1056, T_1060) + node T_1062 = eq(ex_rm, UInt<2>("h02")) + node T_1063 = and(T_990, T_1051) + node T_1064 = eq(ex_rm, UInt<2>("h03")) + node T_1066 = eq(T_990, UInt<1>("h00")) + node T_1067 = and(T_1066, T_1051) + node T_1069 = mux(T_1064, T_1067, UInt<1>("h00")) + node T_1070 = mux(T_1062, T_1063, T_1069) + node T_1071 = mux(T_1052, T_1061, T_1070) + node T_1073 = cat(UInt<1>("h01"), UInt<1>("h01")) + node T_1074 = cat(T_1073, T_1073) + node T_1075 = cat(T_1074, T_1074) + node T_1076 = cat(T_1075, T_1075) + node T_1077 = cat(T_1075, T_1076) + node T_1078 = cat(UInt<1>("h01"), T_1077) + node T_1079 = dshl(T_1078, T_1030) + node T_1080 = bits(T_1079, 24, 0) + node T_1082 = bits(T_991, 51, 29) + node T_1083 = cat(UInt<2>("h01"), T_1082) + node T_1084 = not(T_1080) + node T_1085 = or(T_1083, T_1084) + node T_1087 = addw(T_1085, UInt<1>("h01")) + node T_1088 = mux(T_1071, T_1087, T_1085) + node T_1089 = bits(T_992, 8, 0) + node T_1091 = addw(T_1089, UInt<9>("h0100")) + node T_1092 = bit(T_1088, 24) + node T_1094 = addw(T_1091, UInt<1>("h01")) + node T_1095 = mux(T_1092, T_1094, T_1091) + node T_1096 = eq(ex_rm, UInt<2>("h02")) + node T_1097 = and(T_1096, T_990) + node T_1098 = eq(ex_rm, UInt<2>("h03")) + node T_1100 = eq(T_990, UInt<1>("h00")) + node T_1101 = and(T_1098, T_1100) + node T_1102 = or(T_1097, T_1101) + node T_1103 = eq(ex_rm, UInt<2>("h00")) + node T_1104 = or(T_1102, T_1103) + node T_1106 = eq(T_1104, UInt<1>("h00")) + node T_1108 = subw(UInt<23>("h00"), T_1106) + node T_1111 = mux(T_1104, UInt<9>("h0180"), UInt<9>("h017f")) + node T_1115 = mux(T_1102, UInt<7>("h06b"), UInt<1>("h00")) + node T_1116 = shl(T_993, 6) + node T_1117 = mux(T_1020, T_1115, T_1095) + node T_1118 = mux(T_1024, T_1111, T_1117) + node T_1119 = mux(T_1013, T_1116, T_1118) + node T_1121 = subw(UInt<23>("h00"), T_997) + node T_1122 = bits(T_1088, 22, 0) + node T_1123 = mux(T_1020, UInt<1>("h00"), T_1122) + node T_1124 = mux(T_1024, T_1108, T_1123) + node T_1125 = mux(T_1013, T_1121, T_1124) + node T_1126 = cat(T_1119, T_1125) + node T_1127 = cat(T_990, T_1126) + node T_1128 = and(T_1016, T_1051) + node T_1129 = or(T_1020, T_1128) + node T_1130 = eq(T_992, UInt<12>("h087f")) + node T_1131 = bit(T_1088, 24) + node T_1132 = and(T_1130, T_1131) + node T_1133 = or(T_1024, T_1132) + node T_1135 = or(T_1051, T_1024) + node T_1136 = or(T_1135, T_1020) + node T_1137 = cat(T_1001, UInt<1>("h00")) + node T_1138 = cat(T_1129, T_1136) + node T_1139 = cat(T_1133, T_1138) + node T_1140 = cat(T_1137, T_1139) + node T_1141 = mux(T_957, T_1127, T_963) + divSqrt_wdata := T_1141 + node T_1143 = mux(T_957, T_1140, UInt<1>("h00")) + node T_1144 = or(T_961, T_1143) + divSqrt_flags := T_1144 + + module RocketTile : + output host : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>} + output uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} + output cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} + input clock : Clock + input reset : UInt<1> + + host.debug_stats_pcr := UInt<1>("h00") + host.ipi_rep.ready := UInt<1>("h00") + host.ipi_req.bits := UInt<1>("h00") + host.ipi_req.valid := UInt<1>("h00") + host.pcr_rep.bits := UInt<1>("h00") + host.pcr_rep.valid := UInt<1>("h00") + host.pcr_req.ready := UInt<1>("h00") + uncached.grant.ready := UInt<1>("h00") + uncached.acquire.bits.union := UInt<1>("h00") + uncached.acquire.bits.a_type := UInt<1>("h00") + uncached.acquire.bits.is_builtin_type := UInt<1>("h00") + uncached.acquire.bits.data := UInt<1>("h00") + uncached.acquire.bits.addr_beat := UInt<1>("h00") + uncached.acquire.bits.client_xact_id := UInt<1>("h00") + uncached.acquire.bits.addr_block := UInt<1>("h00") + uncached.acquire.valid := UInt<1>("h00") + cached.release.bits.voluntary := UInt<1>("h00") + cached.release.bits.r_type := UInt<1>("h00") + cached.release.bits.data := UInt<1>("h00") + cached.release.bits.addr_beat := UInt<1>("h00") + cached.release.bits.client_xact_id := UInt<1>("h00") + cached.release.bits.addr_block := UInt<1>("h00") + cached.release.valid := UInt<1>("h00") + cached.probe.ready := UInt<1>("h00") + cached.grant.ready := UInt<1>("h00") + cached.acquire.bits.union := UInt<1>("h00") + cached.acquire.bits.a_type := UInt<1>("h00") + cached.acquire.bits.is_builtin_type := UInt<1>("h00") + cached.acquire.bits.data := UInt<1>("h00") + cached.acquire.bits.addr_beat := UInt<1>("h00") + cached.acquire.bits.client_xact_id := UInt<1>("h00") + cached.acquire.bits.addr_block := UInt<1>("h00") + cached.acquire.valid := UInt<1>("h00") + inst icache of Frontend + icache.mem_1.grant.bits.g_type := UInt<1>("h00") + icache.mem_1.grant.bits.is_builtin_type := UInt<1>("h00") + icache.mem_1.grant.bits.manager_xact_id := UInt<1>("h00") + icache.mem_1.grant.bits.client_xact_id := UInt<1>("h00") + icache.mem_1.grant.bits.data := UInt<1>("h00") + icache.mem_1.grant.bits.addr_beat := UInt<1>("h00") + icache.mem_1.grant.valid := UInt<1>("h00") + icache.mem_1.acquire.ready := UInt<1>("h00") + icache.ptw.invalidate := UInt<1>("h00") + icache.ptw.status.ie := UInt<1>("h00") + icache.ptw.status.prv := UInt<1>("h00") + icache.ptw.status.ie1 := UInt<1>("h00") + icache.ptw.status.prv1 := UInt<1>("h00") + icache.ptw.status.ie2 := UInt<1>("h00") + icache.ptw.status.prv2 := UInt<1>("h00") + icache.ptw.status.ie3 := UInt<1>("h00") + icache.ptw.status.prv3 := UInt<1>("h00") + icache.ptw.status.fs := UInt<1>("h00") + icache.ptw.status.xs := UInt<1>("h00") + icache.ptw.status.mprv := UInt<1>("h00") + icache.ptw.status.vm := UInt<1>("h00") + icache.ptw.status.zero1 := UInt<1>("h00") + icache.ptw.status.sd_rv32 := UInt<1>("h00") + icache.ptw.status.zero2 := UInt<1>("h00") + icache.ptw.status.sd := UInt<1>("h00") + icache.ptw.resp.bits.pte.v := UInt<1>("h00") + icache.ptw.resp.bits.pte.typ := UInt<1>("h00") + icache.ptw.resp.bits.pte.r := UInt<1>("h00") + icache.ptw.resp.bits.pte.d := UInt<1>("h00") + icache.ptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") + icache.ptw.resp.bits.pte.ppn := UInt<1>("h00") + icache.ptw.resp.bits.error := UInt<1>("h00") + icache.ptw.resp.valid := UInt<1>("h00") + icache.ptw.req.ready := UInt<1>("h00") + icache.cpu.invalidate := UInt<1>("h00") + icache.cpu.ras_update.bits.prediction.bits.bht.value := UInt<1>("h00") + icache.cpu.ras_update.bits.prediction.bits.bht.history := UInt<1>("h00") + icache.cpu.ras_update.bits.prediction.bits.entry := UInt<1>("h00") + icache.cpu.ras_update.bits.prediction.bits.target := UInt<1>("h00") + icache.cpu.ras_update.bits.prediction.bits.bridx := UInt<1>("h00") + icache.cpu.ras_update.bits.prediction.bits.mask := UInt<1>("h00") + icache.cpu.ras_update.bits.prediction.bits.taken := UInt<1>("h00") + icache.cpu.ras_update.bits.prediction.valid := UInt<1>("h00") + icache.cpu.ras_update.bits.returnAddr := UInt<1>("h00") + icache.cpu.ras_update.bits.isReturn := UInt<1>("h00") + icache.cpu.ras_update.bits.isCall := UInt<1>("h00") + icache.cpu.ras_update.valid := UInt<1>("h00") + icache.cpu.bht_update.bits.mispredict := UInt<1>("h00") + icache.cpu.bht_update.bits.taken := UInt<1>("h00") + icache.cpu.bht_update.bits.pc := UInt<1>("h00") + icache.cpu.bht_update.bits.prediction.bits.bht.value := UInt<1>("h00") + icache.cpu.bht_update.bits.prediction.bits.bht.history := UInt<1>("h00") + icache.cpu.bht_update.bits.prediction.bits.entry := UInt<1>("h00") + icache.cpu.bht_update.bits.prediction.bits.target := UInt<1>("h00") + icache.cpu.bht_update.bits.prediction.bits.bridx := UInt<1>("h00") + icache.cpu.bht_update.bits.prediction.bits.mask := UInt<1>("h00") + icache.cpu.bht_update.bits.prediction.bits.taken := UInt<1>("h00") + icache.cpu.bht_update.bits.prediction.valid := UInt<1>("h00") + icache.cpu.bht_update.valid := UInt<1>("h00") + icache.cpu.btb_update.bits.br_pc := UInt<1>("h00") + icache.cpu.btb_update.bits.isReturn := UInt<1>("h00") + icache.cpu.btb_update.bits.isJump := UInt<1>("h00") + icache.cpu.btb_update.bits.taken := UInt<1>("h00") + icache.cpu.btb_update.bits.target := UInt<1>("h00") + icache.cpu.btb_update.bits.pc := UInt<1>("h00") + icache.cpu.btb_update.bits.prediction.bits.bht.value := UInt<1>("h00") + icache.cpu.btb_update.bits.prediction.bits.bht.history := UInt<1>("h00") + icache.cpu.btb_update.bits.prediction.bits.entry := UInt<1>("h00") + icache.cpu.btb_update.bits.prediction.bits.target := UInt<1>("h00") + icache.cpu.btb_update.bits.prediction.bits.bridx := UInt<1>("h00") + icache.cpu.btb_update.bits.prediction.bits.mask := UInt<1>("h00") + icache.cpu.btb_update.bits.prediction.bits.taken := UInt<1>("h00") + icache.cpu.btb_update.bits.prediction.valid := UInt<1>("h00") + icache.cpu.btb_update.valid := UInt<1>("h00") + icache.cpu.resp.ready := UInt<1>("h00") + icache.cpu.req.bits.pc := UInt<1>("h00") + icache.cpu.req.valid := UInt<1>("h00") + icache.reset := UInt<1>("h00") + icache.clock := clock + icache.reset := reset + inst dcache of HellaCache + dcache.mem_1.release.ready := UInt<1>("h00") + dcache.mem_1.probe.bits.p_type := UInt<1>("h00") + dcache.mem_1.probe.bits.addr_block := UInt<1>("h00") + dcache.mem_1.probe.valid := UInt<1>("h00") + dcache.mem_1.grant.bits.g_type := UInt<1>("h00") + dcache.mem_1.grant.bits.is_builtin_type := UInt<1>("h00") + dcache.mem_1.grant.bits.manager_xact_id := UInt<1>("h00") + dcache.mem_1.grant.bits.client_xact_id := UInt<1>("h00") + dcache.mem_1.grant.bits.data := UInt<1>("h00") + dcache.mem_1.grant.bits.addr_beat := UInt<1>("h00") + dcache.mem_1.grant.valid := UInt<1>("h00") + dcache.mem_1.acquire.ready := UInt<1>("h00") + dcache.ptw.invalidate := UInt<1>("h00") + dcache.ptw.status.ie := UInt<1>("h00") + dcache.ptw.status.prv := UInt<1>("h00") + dcache.ptw.status.ie1 := UInt<1>("h00") + dcache.ptw.status.prv1 := UInt<1>("h00") + dcache.ptw.status.ie2 := UInt<1>("h00") + dcache.ptw.status.prv2 := UInt<1>("h00") + dcache.ptw.status.ie3 := UInt<1>("h00") + dcache.ptw.status.prv3 := UInt<1>("h00") + dcache.ptw.status.fs := UInt<1>("h00") + dcache.ptw.status.xs := UInt<1>("h00") + dcache.ptw.status.mprv := UInt<1>("h00") + dcache.ptw.status.vm := UInt<1>("h00") + dcache.ptw.status.zero1 := UInt<1>("h00") + dcache.ptw.status.sd_rv32 := UInt<1>("h00") + dcache.ptw.status.zero2 := UInt<1>("h00") + dcache.ptw.status.sd := UInt<1>("h00") + dcache.ptw.resp.bits.pte.v := UInt<1>("h00") + dcache.ptw.resp.bits.pte.typ := UInt<1>("h00") + dcache.ptw.resp.bits.pte.r := UInt<1>("h00") + dcache.ptw.resp.bits.pte.d := UInt<1>("h00") + dcache.ptw.resp.bits.pte.reserved_for_software := UInt<1>("h00") + dcache.ptw.resp.bits.pte.ppn := UInt<1>("h00") + dcache.ptw.resp.bits.error := UInt<1>("h00") + dcache.ptw.resp.valid := UInt<1>("h00") + dcache.ptw.req.ready := UInt<1>("h00") + dcache.cpu.invalidate_lr := UInt<1>("h00") + dcache.cpu.req.bits.data := UInt<1>("h00") + dcache.cpu.req.bits.phys := UInt<1>("h00") + dcache.cpu.req.bits.kill := UInt<1>("h00") + dcache.cpu.req.bits.typ := UInt<1>("h00") + dcache.cpu.req.bits.cmd := UInt<1>("h00") + dcache.cpu.req.bits.tag := UInt<1>("h00") + dcache.cpu.req.bits.addr := UInt<1>("h00") + dcache.cpu.req.valid := UInt<1>("h00") + dcache.reset := UInt<1>("h00") + dcache.clock := clock + dcache.reset := reset + inst ptw of PTW + ptw.dpath.status.ie := UInt<1>("h00") + ptw.dpath.status.prv := UInt<1>("h00") + ptw.dpath.status.ie1 := UInt<1>("h00") + ptw.dpath.status.prv1 := UInt<1>("h00") + ptw.dpath.status.ie2 := UInt<1>("h00") + ptw.dpath.status.prv2 := UInt<1>("h00") + ptw.dpath.status.ie3 := UInt<1>("h00") + ptw.dpath.status.prv3 := UInt<1>("h00") + ptw.dpath.status.fs := UInt<1>("h00") + ptw.dpath.status.xs := UInt<1>("h00") + ptw.dpath.status.mprv := UInt<1>("h00") + ptw.dpath.status.vm := UInt<1>("h00") + ptw.dpath.status.zero1 := UInt<1>("h00") + ptw.dpath.status.sd_rv32 := UInt<1>("h00") + ptw.dpath.status.zero2 := UInt<1>("h00") + ptw.dpath.status.sd := UInt<1>("h00") + ptw.dpath.invalidate := UInt<1>("h00") + ptw.dpath.ptbr := UInt<1>("h00") + ptw.mem_1.ordered := UInt<1>("h00") + ptw.mem_1.xcpt.pf.st := UInt<1>("h00") + ptw.mem_1.xcpt.pf.ld := UInt<1>("h00") + ptw.mem_1.xcpt.ma.st := UInt<1>("h00") + ptw.mem_1.xcpt.ma.ld := UInt<1>("h00") + ptw.mem_1.replay_next.bits := UInt<1>("h00") + ptw.mem_1.replay_next.valid := UInt<1>("h00") + ptw.mem_1.resp.bits.store_data := UInt<1>("h00") + ptw.mem_1.resp.bits.data_subword := UInt<1>("h00") + ptw.mem_1.resp.bits.has_data := UInt<1>("h00") + ptw.mem_1.resp.bits.replay := UInt<1>("h00") + ptw.mem_1.resp.bits.nack := UInt<1>("h00") + ptw.mem_1.resp.bits.data := UInt<1>("h00") + ptw.mem_1.resp.bits.typ := UInt<1>("h00") + ptw.mem_1.resp.bits.cmd := UInt<1>("h00") + ptw.mem_1.resp.bits.tag := UInt<1>("h00") + ptw.mem_1.resp.bits.addr := UInt<1>("h00") + ptw.mem_1.resp.valid := UInt<1>("h00") + ptw.mem_1.req.ready := UInt<1>("h00") + ptw.requestor[0].req.bits.fetch := UInt<1>("h00") + ptw.requestor[0].req.bits.store := UInt<1>("h00") + ptw.requestor[0].req.bits.prv := UInt<1>("h00") + ptw.requestor[0].req.bits.addr := UInt<1>("h00") + ptw.requestor[0].req.valid := UInt<1>("h00") + ptw.requestor[1].req.bits.fetch := UInt<1>("h00") + ptw.requestor[1].req.bits.store := UInt<1>("h00") + ptw.requestor[1].req.bits.prv := UInt<1>("h00") + ptw.requestor[1].req.bits.addr := UInt<1>("h00") + ptw.requestor[1].req.valid := UInt<1>("h00") + ptw.reset := UInt<1>("h00") + ptw.clock := clock + ptw.reset := reset + inst core of Rocket + core.rocc.pptw.req.bits.fetch := UInt<1>("h00") + core.rocc.pptw.req.bits.store := UInt<1>("h00") + core.rocc.pptw.req.bits.prv := UInt<1>("h00") + core.rocc.pptw.req.bits.addr := UInt<1>("h00") + core.rocc.pptw.req.valid := UInt<1>("h00") + core.rocc.dptw.req.bits.fetch := UInt<1>("h00") + core.rocc.dptw.req.bits.store := UInt<1>("h00") + core.rocc.dptw.req.bits.prv := UInt<1>("h00") + core.rocc.dptw.req.bits.addr := UInt<1>("h00") + core.rocc.dptw.req.valid := UInt<1>("h00") + core.rocc.iptw.req.bits.fetch := UInt<1>("h00") + core.rocc.iptw.req.bits.store := UInt<1>("h00") + core.rocc.iptw.req.bits.prv := UInt<1>("h00") + core.rocc.iptw.req.bits.addr := UInt<1>("h00") + core.rocc.iptw.req.valid := UInt<1>("h00") + core.rocc.dmem.grant.ready := UInt<1>("h00") + core.rocc.dmem.acquire.bits.union := UInt<1>("h00") + core.rocc.dmem.acquire.bits.a_type := UInt<1>("h00") + core.rocc.dmem.acquire.bits.is_builtin_type := UInt<1>("h00") + core.rocc.dmem.acquire.bits.data := UInt<1>("h00") + core.rocc.dmem.acquire.bits.addr_beat := UInt<1>("h00") + core.rocc.dmem.acquire.bits.client_xact_id := UInt<1>("h00") + core.rocc.dmem.acquire.bits.addr_block := UInt<1>("h00") + core.rocc.dmem.acquire.valid := UInt<1>("h00") + core.rocc.imem.grant.ready := UInt<1>("h00") + core.rocc.imem.acquire.bits.union := UInt<1>("h00") + core.rocc.imem.acquire.bits.a_type := UInt<1>("h00") + core.rocc.imem.acquire.bits.is_builtin_type := UInt<1>("h00") + core.rocc.imem.acquire.bits.data := UInt<1>("h00") + core.rocc.imem.acquire.bits.addr_beat := UInt<1>("h00") + core.rocc.imem.acquire.bits.client_xact_id := UInt<1>("h00") + core.rocc.imem.acquire.bits.addr_block := UInt<1>("h00") + core.rocc.imem.acquire.valid := UInt<1>("h00") + core.rocc.interrupt := UInt<1>("h00") + core.rocc.busy := UInt<1>("h00") + core.rocc.mem_1.invalidate_lr := UInt<1>("h00") + core.rocc.mem_1.req.bits.data := UInt<1>("h00") + core.rocc.mem_1.req.bits.phys := UInt<1>("h00") + core.rocc.mem_1.req.bits.kill := UInt<1>("h00") + core.rocc.mem_1.req.bits.typ := UInt<1>("h00") + core.rocc.mem_1.req.bits.cmd := UInt<1>("h00") + core.rocc.mem_1.req.bits.tag := UInt<1>("h00") + core.rocc.mem_1.req.bits.addr := UInt<1>("h00") + core.rocc.mem_1.req.valid := UInt<1>("h00") + core.rocc.resp.bits.data := UInt<1>("h00") + core.rocc.resp.bits.rd := UInt<1>("h00") + core.rocc.resp.valid := UInt<1>("h00") + core.rocc.cmd.ready := UInt<1>("h00") + core.fpu.sboard_clra := UInt<1>("h00") + core.fpu.sboard_clr := UInt<1>("h00") + core.fpu.sboard_set := UInt<1>("h00") + core.fpu.dec.wflags := UInt<1>("h00") + core.fpu.dec.round := UInt<1>("h00") + core.fpu.dec.sqrt := UInt<1>("h00") + core.fpu.dec.div := UInt<1>("h00") + core.fpu.dec.fma := UInt<1>("h00") + core.fpu.dec.fastpipe := UInt<1>("h00") + core.fpu.dec.toint := UInt<1>("h00") + core.fpu.dec.fromint := UInt<1>("h00") + core.fpu.dec.single := UInt<1>("h00") + core.fpu.dec.swap23 := UInt<1>("h00") + core.fpu.dec.swap12 := UInt<1>("h00") + core.fpu.dec.ren3 := UInt<1>("h00") + core.fpu.dec.ren2 := UInt<1>("h00") + core.fpu.dec.ren1 := UInt<1>("h00") + core.fpu.dec.wen := UInt<1>("h00") + core.fpu.dec.ldst := UInt<1>("h00") + core.fpu.dec.cmd := UInt<1>("h00") + core.fpu.illegal_rm := UInt<1>("h00") + core.fpu.nack_mem := UInt<1>("h00") + core.fpu.fcsr_rdy := UInt<1>("h00") + core.fpu.toint_data := UInt<1>("h00") + core.fpu.store_data := UInt<1>("h00") + core.fpu.fcsr_flags.bits := UInt<1>("h00") + core.fpu.fcsr_flags.valid := UInt<1>("h00") + core.dmem.ordered := UInt<1>("h00") + core.dmem.xcpt.pf.st := UInt<1>("h00") + core.dmem.xcpt.pf.ld := UInt<1>("h00") + core.dmem.xcpt.ma.st := UInt<1>("h00") + core.dmem.xcpt.ma.ld := UInt<1>("h00") + core.dmem.replay_next.bits := UInt<1>("h00") + core.dmem.replay_next.valid := UInt<1>("h00") + core.dmem.resp.bits.store_data := UInt<1>("h00") + core.dmem.resp.bits.data_subword := UInt<1>("h00") + core.dmem.resp.bits.has_data := UInt<1>("h00") + core.dmem.resp.bits.replay := UInt<1>("h00") + core.dmem.resp.bits.nack := UInt<1>("h00") + core.dmem.resp.bits.data := UInt<1>("h00") + core.dmem.resp.bits.typ := UInt<1>("h00") + core.dmem.resp.bits.cmd := UInt<1>("h00") + core.dmem.resp.bits.tag := UInt<1>("h00") + core.dmem.resp.bits.addr := UInt<1>("h00") + core.dmem.resp.valid := UInt<1>("h00") + core.dmem.req.ready := UInt<1>("h00") + core.imem.npc := UInt<1>("h00") + core.imem.btb_resp.bits.bht.value := UInt<1>("h00") + core.imem.btb_resp.bits.bht.history := UInt<1>("h00") + core.imem.btb_resp.bits.entry := UInt<1>("h00") + core.imem.btb_resp.bits.target := UInt<1>("h00") + core.imem.btb_resp.bits.bridx := UInt<1>("h00") + core.imem.btb_resp.bits.mask := UInt<1>("h00") + core.imem.btb_resp.bits.taken := UInt<1>("h00") + core.imem.btb_resp.valid := UInt<1>("h00") + core.imem.resp.bits.xcpt_if := UInt<1>("h00") + core.imem.resp.bits.mask := UInt<1>("h00") + core.imem.resp.bits.data[0] := UInt<1>("h00") + core.imem.resp.bits.pc := UInt<1>("h00") + core.imem.resp.valid := UInt<1>("h00") + core.host.ipi_rep.bits := UInt<1>("h00") + core.host.ipi_rep.valid := UInt<1>("h00") + core.host.ipi_req.ready := UInt<1>("h00") + core.host.pcr_rep.ready := UInt<1>("h00") + core.host.pcr_req.bits.data := UInt<1>("h00") + core.host.pcr_req.bits.addr := UInt<1>("h00") + core.host.pcr_req.bits.rw := UInt<1>("h00") + core.host.pcr_req.valid := UInt<1>("h00") + core.host.id := UInt<1>("h00") + core.host.reset := UInt<1>("h00") + core.reset := UInt<1>("h00") + core.clock := clock + core.reset := reset + dcache.cpu.invalidate_lr := core.dmem.invalidate_lr + inst dcArb of HellaCacheArbiter + dcArb.mem_1.ordered := UInt<1>("h00") + dcArb.mem_1.xcpt.pf.st := UInt<1>("h00") + dcArb.mem_1.xcpt.pf.ld := UInt<1>("h00") + dcArb.mem_1.xcpt.ma.st := UInt<1>("h00") + dcArb.mem_1.xcpt.ma.ld := UInt<1>("h00") + dcArb.mem_1.replay_next.bits := UInt<1>("h00") + dcArb.mem_1.replay_next.valid := UInt<1>("h00") + dcArb.mem_1.resp.bits.store_data := UInt<1>("h00") + dcArb.mem_1.resp.bits.data_subword := UInt<1>("h00") + dcArb.mem_1.resp.bits.has_data := UInt<1>("h00") + dcArb.mem_1.resp.bits.replay := UInt<1>("h00") + dcArb.mem_1.resp.bits.nack := UInt<1>("h00") + dcArb.mem_1.resp.bits.data := UInt<1>("h00") + dcArb.mem_1.resp.bits.typ := UInt<1>("h00") + dcArb.mem_1.resp.bits.cmd := UInt<1>("h00") + dcArb.mem_1.resp.bits.tag := UInt<1>("h00") + dcArb.mem_1.resp.bits.addr := UInt<1>("h00") + dcArb.mem_1.resp.valid := UInt<1>("h00") + dcArb.mem_1.req.ready := UInt<1>("h00") + dcArb.requestor[0].invalidate_lr := UInt<1>("h00") + dcArb.requestor[0].req.bits.data := UInt<1>("h00") + dcArb.requestor[0].req.bits.phys := UInt<1>("h00") + dcArb.requestor[0].req.bits.kill := UInt<1>("h00") + dcArb.requestor[0].req.bits.typ := UInt<1>("h00") + dcArb.requestor[0].req.bits.cmd := UInt<1>("h00") + dcArb.requestor[0].req.bits.tag := UInt<1>("h00") + dcArb.requestor[0].req.bits.addr := UInt<1>("h00") + dcArb.requestor[0].req.valid := UInt<1>("h00") + dcArb.requestor[1].invalidate_lr := UInt<1>("h00") + dcArb.requestor[1].req.bits.data := UInt<1>("h00") + dcArb.requestor[1].req.bits.phys := UInt<1>("h00") + dcArb.requestor[1].req.bits.kill := UInt<1>("h00") + dcArb.requestor[1].req.bits.typ := UInt<1>("h00") + dcArb.requestor[1].req.bits.cmd := UInt<1>("h00") + dcArb.requestor[1].req.bits.tag := UInt<1>("h00") + dcArb.requestor[1].req.bits.addr := UInt<1>("h00") + dcArb.requestor[1].req.valid := UInt<1>("h00") + dcArb.reset := UInt<1>("h00") + dcArb.clock := clock + dcArb.reset := reset + dcArb.requestor[0] <> ptw.mem_1 + dcArb.requestor[1] <> core.dmem + dcache.cpu <> dcArb.mem_1 + ptw.requestor[0] <> icache.ptw + ptw.requestor[1] <> dcache.ptw + host <> core.host + icache.cpu <> core.imem + core.ptw <> ptw.dpath + inst T_1184 of FPU + T_1184.killm := UInt<1>("h00") + T_1184.killx := UInt<1>("h00") + T_1184.valid := UInt<1>("h00") + T_1184.dmem_resp_data := UInt<1>("h00") + T_1184.dmem_resp_tag := UInt<1>("h00") + T_1184.dmem_resp_type := UInt<1>("h00") + T_1184.dmem_resp_val := UInt<1>("h00") + T_1184.fcsr_rm := UInt<1>("h00") + T_1184.fromint_data := UInt<1>("h00") + T_1184.inst_1 := UInt<1>("h00") + T_1184.reset := UInt<1>("h00") + T_1184.clock := clock + T_1184.reset := reset + core.fpu <> T_1184 + cached <> dcache.mem_1 + uncached <> icache.mem_1 + + module Queue_72 : + output count : UInt<2> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits.data := UInt<1>("h00") + deq.bits.addr := UInt<1>("h00") + deq.bits.rw := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}[2], clock + reg T_52 : UInt<1>, clock, reset + onreset T_52 := UInt<1>("h00") + reg T_54 : UInt<1>, clock, reset + onreset T_54 := UInt<1>("h00") + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(T_52, T_54) + node T_59 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_59) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_65 = and(enq.ready, enq.valid) + node T_67 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_65, T_67) + node T_69 = and(deq.ready, deq.valid) + node T_71 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_69, T_71) + when do_enq : + infer accessor T_73 = ram[T_52] + T_73 <> enq.bits + node T_78 = eq(T_52, UInt<1>("h01")) + node T_80 = and(UInt<1>("h00"), T_78) + node T_83 = addw(T_52, UInt<1>("h01")) + node T_84 = mux(T_80, UInt<1>("h00"), T_83) + T_52 := T_84 + skip + when do_deq : + node T_86 = eq(T_54, UInt<1>("h01")) + node T_88 = and(UInt<1>("h00"), T_86) + node T_91 = addw(T_54, UInt<1>("h01")) + node T_92 = mux(T_88, UInt<1>("h00"), T_91) + T_54 := T_92 + skip + node T_93 = neq(do_enq, do_deq) + when T_93 : + maybe_full := do_enq + skip + node T_95 = eq(empty, UInt<1>("h00")) + node T_97 = and(UInt<1>("h00"), enq.valid) + node T_98 = or(T_95, T_97) + deq.valid := T_98 + node T_100 = eq(full, UInt<1>("h00")) + node T_102 = and(UInt<1>("h00"), deq.ready) + node T_103 = or(T_100, T_102) + enq.ready := T_103 + infer accessor T_104 = ram[T_54] + wire T_112 : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>} + T_112 <> T_104 + when maybe_flow : + T_112 <> enq.bits + skip + deq.bits <> T_112 + node ptr_diff = subw(T_52, T_54) + node T_117 = and(maybe_full, ptr_match) + node T_118 = cat(T_117, ptr_diff) + count := T_118 + + module Queue_73 : + output count : UInt<2> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : UInt<64>[2], clock + reg T_25 : UInt<1>, clock, reset + onreset T_25 := UInt<1>("h00") + reg T_27 : UInt<1>, clock, reset + onreset T_27 := UInt<1>("h00") + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(T_25, T_27) + node T_32 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_32) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_38 = and(enq.ready, enq.valid) + node T_40 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_38, T_40) + node T_42 = and(deq.ready, deq.valid) + node T_44 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_42, T_44) + when do_enq : + infer accessor T_46 = ram[T_25] + T_46 := enq.bits + node T_48 = eq(T_25, UInt<1>("h01")) + node T_50 = and(UInt<1>("h00"), T_48) + node T_53 = addw(T_25, UInt<1>("h01")) + node T_54 = mux(T_50, UInt<1>("h00"), T_53) + T_25 := T_54 + skip + when do_deq : + node T_56 = eq(T_27, UInt<1>("h01")) + node T_58 = and(UInt<1>("h00"), T_56) + node T_61 = addw(T_27, UInt<1>("h01")) + node T_62 = mux(T_58, UInt<1>("h00"), T_61) + T_27 := T_62 + skip + node T_63 = neq(do_enq, do_deq) + when T_63 : + maybe_full := do_enq + skip + node T_65 = eq(empty, UInt<1>("h00")) + node T_67 = and(UInt<1>("h00"), enq.valid) + node T_68 = or(T_65, T_67) + deq.valid := T_68 + node T_70 = eq(full, UInt<1>("h00")) + node T_72 = and(UInt<1>("h00"), deq.ready) + node T_73 = or(T_70, T_72) + enq.ready := T_73 + infer accessor T_74 = ram[T_27] + node T_75 = mux(maybe_flow, enq.bits, T_74) + deq.bits := T_75 + node ptr_diff = subw(T_25, T_27) + node T_77 = and(maybe_full, ptr_match) + node T_78 = cat(T_77, ptr_diff) + count := T_78 + + module Queue_74 : + output count : UInt<2> + output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>} + input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>} + input clock : Clock + input reset : UInt<1> + + count := UInt<1>("h00") + deq.bits := UInt<1>("h00") + deq.valid := UInt<1>("h00") + enq.ready := UInt<1>("h00") + cmem ram : UInt<1>[2], clock + reg T_25 : UInt<1>, clock, reset + onreset T_25 := UInt<1>("h00") + reg T_27 : UInt<1>, clock, reset + onreset T_27 := UInt<1>("h00") + reg maybe_full : UInt<1>, clock, reset + onreset maybe_full := UInt<1>("h00") + node ptr_match = eq(T_25, T_27) + node T_32 = eq(maybe_full, UInt<1>("h00")) + node empty = and(ptr_match, T_32) + node full = and(ptr_match, maybe_full) + node maybe_flow = and(UInt<1>("h00"), empty) + node do_flow = and(maybe_flow, deq.ready) + node T_38 = and(enq.ready, enq.valid) + node T_40 = eq(do_flow, UInt<1>("h00")) + node do_enq = and(T_38, T_40) + node T_42 = and(deq.ready, deq.valid) + node T_44 = eq(do_flow, UInt<1>("h00")) + node do_deq = and(T_42, T_44) + when do_enq : + infer accessor T_46 = ram[T_25] + T_46 := enq.bits + node T_48 = eq(T_25, UInt<1>("h01")) + node T_50 = and(UInt<1>("h00"), T_48) + node T_53 = addw(T_25, UInt<1>("h01")) + node T_54 = mux(T_50, UInt<1>("h00"), T_53) + T_25 := T_54 + skip + when do_deq : + node T_56 = eq(T_27, UInt<1>("h01")) + node T_58 = and(UInt<1>("h00"), T_56) + node T_61 = addw(T_27, UInt<1>("h01")) + node T_62 = mux(T_58, UInt<1>("h00"), T_61) + T_27 := T_62 + skip + node T_63 = neq(do_enq, do_deq) + when T_63 : + maybe_full := do_enq + skip + node T_65 = eq(empty, UInt<1>("h00")) + node T_67 = and(UInt<1>("h00"), enq.valid) + node T_68 = or(T_65, T_67) + deq.valid := T_68 + node T_70 = eq(full, UInt<1>("h00")) + node T_72 = and(UInt<1>("h00"), deq.ready) + node T_73 = or(T_70, T_72) + enq.ready := T_73 + infer accessor T_74 = ram[T_27] + node T_75 = mux(maybe_flow, enq.bits, T_74) + deq.bits := T_75 + node ptr_diff = subw(T_25, T_27) + node T_77 = and(maybe_full, ptr_match) + node T_78 = cat(T_77, ptr_diff) + count := T_78 + + module MultiChannelTop : + output mem_1 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}}[1] + output mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>} + output host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>} + input clock : Clock + input reset : UInt<1> + + mem_1[0].resp.ready := UInt<1>("h00") + mem_1[0].req_data.bits.data := UInt<1>("h00") + mem_1[0].req_data.valid := UInt<1>("h00") + mem_1[0].req_cmd.bits.rw := UInt<1>("h00") + mem_1[0].req_cmd.bits.tag := UInt<1>("h00") + mem_1[0].req_cmd.bits.addr := UInt<1>("h00") + mem_1[0].req_cmd.valid := UInt<1>("h00") + mem_backup_ctrl.out_valid := UInt<1>("h00") + host.debug_stats_pcr := UInt<1>("h00") + host.out.bits := UInt<1>("h00") + host.out.valid := UInt<1>("h00") + host.in.ready := UInt<1>("h00") + host.clk_edge := UInt<1>("h00") + host.clk := UInt<1>("h00") + inst uncore of Uncore + uncore.mem_backup_ctrl.out_ready := UInt<1>("h00") + uncore.mem_backup_ctrl.in_valid := UInt<1>("h00") + uncore.mem_backup_ctrl.en := UInt<1>("h00") + uncore.htif[0].debug_stats_pcr := UInt<1>("h00") + uncore.htif[0].ipi_rep.ready := UInt<1>("h00") + uncore.htif[0].ipi_req.bits := UInt<1>("h00") + uncore.htif[0].ipi_req.valid := UInt<1>("h00") + uncore.htif[0].pcr_rep.bits := UInt<1>("h00") + uncore.htif[0].pcr_rep.valid := UInt<1>("h00") + uncore.htif[0].pcr_req.ready := UInt<1>("h00") + uncore.tiles_uncached[0].grant.ready := UInt<1>("h00") + uncore.tiles_uncached[0].acquire.bits.union := UInt<1>("h00") + uncore.tiles_uncached[0].acquire.bits.a_type := UInt<1>("h00") + uncore.tiles_uncached[0].acquire.bits.is_builtin_type := UInt<1>("h00") + uncore.tiles_uncached[0].acquire.bits.data := UInt<1>("h00") + uncore.tiles_uncached[0].acquire.bits.addr_beat := UInt<1>("h00") + uncore.tiles_uncached[0].acquire.bits.client_xact_id := UInt<1>("h00") + uncore.tiles_uncached[0].acquire.bits.addr_block := UInt<1>("h00") + uncore.tiles_uncached[0].acquire.valid := UInt<1>("h00") + uncore.tiles_cached[0].release.bits.voluntary := UInt<1>("h00") + uncore.tiles_cached[0].release.bits.r_type := UInt<1>("h00") + uncore.tiles_cached[0].release.bits.data := UInt<1>("h00") + uncore.tiles_cached[0].release.bits.addr_beat := UInt<1>("h00") + uncore.tiles_cached[0].release.bits.client_xact_id := UInt<1>("h00") + uncore.tiles_cached[0].release.bits.addr_block := UInt<1>("h00") + uncore.tiles_cached[0].release.valid := UInt<1>("h00") + uncore.tiles_cached[0].probe.ready := UInt<1>("h00") + uncore.tiles_cached[0].grant.ready := UInt<1>("h00") + uncore.tiles_cached[0].acquire.bits.union := UInt<1>("h00") + uncore.tiles_cached[0].acquire.bits.a_type := UInt<1>("h00") + uncore.tiles_cached[0].acquire.bits.is_builtin_type := UInt<1>("h00") + uncore.tiles_cached[0].acquire.bits.data := UInt<1>("h00") + uncore.tiles_cached[0].acquire.bits.addr_beat := UInt<1>("h00") + uncore.tiles_cached[0].acquire.bits.client_xact_id := UInt<1>("h00") + uncore.tiles_cached[0].acquire.bits.addr_block := UInt<1>("h00") + uncore.tiles_cached[0].acquire.valid := UInt<1>("h00") + uncore.mem_1[0].resp.bits.tag := UInt<1>("h00") + uncore.mem_1[0].resp.bits.data := UInt<1>("h00") + uncore.mem_1[0].resp.valid := UInt<1>("h00") + uncore.mem_1[0].req_data.ready := UInt<1>("h00") + uncore.mem_1[0].req_cmd.ready := UInt<1>("h00") + uncore.host.out.ready := UInt<1>("h00") + uncore.host.in.bits := UInt<1>("h00") + uncore.host.in.valid := UInt<1>("h00") + uncore.reset := UInt<1>("h00") + uncore.clock := clock + uncore.reset := reset + inst T_321 of RocketTile + T_321.host.ipi_rep.bits := UInt<1>("h00") + T_321.host.ipi_rep.valid := UInt<1>("h00") + T_321.host.ipi_req.ready := UInt<1>("h00") + T_321.host.pcr_rep.ready := UInt<1>("h00") + T_321.host.pcr_req.bits.data := UInt<1>("h00") + T_321.host.pcr_req.bits.addr := UInt<1>("h00") + T_321.host.pcr_req.bits.rw := UInt<1>("h00") + T_321.host.pcr_req.valid := UInt<1>("h00") + T_321.host.id := UInt<1>("h00") + T_321.host.reset := UInt<1>("h00") + T_321.uncached.grant.bits.g_type := UInt<1>("h00") + T_321.uncached.grant.bits.is_builtin_type := UInt<1>("h00") + T_321.uncached.grant.bits.manager_xact_id := UInt<1>("h00") + T_321.uncached.grant.bits.client_xact_id := UInt<1>("h00") + T_321.uncached.grant.bits.data := UInt<1>("h00") + T_321.uncached.grant.bits.addr_beat := UInt<1>("h00") + T_321.uncached.grant.valid := UInt<1>("h00") + T_321.uncached.acquire.ready := UInt<1>("h00") + T_321.cached.release.ready := UInt<1>("h00") + T_321.cached.probe.bits.p_type := UInt<1>("h00") + T_321.cached.probe.bits.addr_block := UInt<1>("h00") + T_321.cached.probe.valid := UInt<1>("h00") + T_321.cached.grant.bits.g_type := UInt<1>("h00") + T_321.cached.grant.bits.is_builtin_type := UInt<1>("h00") + T_321.cached.grant.bits.manager_xact_id := UInt<1>("h00") + T_321.cached.grant.bits.client_xact_id := UInt<1>("h00") + T_321.cached.grant.bits.data := UInt<1>("h00") + T_321.cached.grant.bits.addr_beat := UInt<1>("h00") + T_321.cached.grant.valid := UInt<1>("h00") + T_321.cached.acquire.ready := UInt<1>("h00") + T_321.reset := UInt<1>("h00") + T_321.clock := clock + T_321.reset := uncore.htif[0].reset + T_321.host.id := UInt<1>("h00") + reg T_293 : UInt<1>, clock, reset + T_293 := uncore.htif[0].reset + reg T_294 : UInt<1>, clock, reset + T_294 := T_293 + T_321.host.reset := T_294 + inst T_322 of Queue_72 + T_322.deq.ready := UInt<1>("h00") + T_322.enq.bits.data := UInt<1>("h00") + T_322.enq.bits.addr := UInt<1>("h00") + T_322.enq.bits.rw := UInt<1>("h00") + T_322.enq.valid := UInt<1>("h00") + T_322.reset := UInt<1>("h00") + T_322.clock := clock + T_322.reset := reset + T_322.enq.valid := uncore.htif[0].pcr_req.valid + T_322.enq.bits <> uncore.htif[0].pcr_req.bits + uncore.htif[0].pcr_req.ready := T_322.enq.ready + T_321.host.pcr_req <> T_322.deq + inst T_323 of Queue_73 + T_323.deq.ready := UInt<1>("h00") + T_323.enq.bits := UInt<1>("h00") + T_323.enq.valid := UInt<1>("h00") + T_323.reset := UInt<1>("h00") + T_323.clock := clock + T_323.reset := reset + T_323.enq.valid := T_321.host.pcr_rep.valid + T_323.enq.bits := T_321.host.pcr_rep.bits + T_321.host.pcr_rep.ready := T_323.enq.ready + uncore.htif[0].pcr_rep <> T_323.deq + inst T_324 of Queue_74 + T_324.deq.ready := UInt<1>("h00") + T_324.enq.bits := UInt<1>("h00") + T_324.enq.valid := UInt<1>("h00") + T_324.reset := UInt<1>("h00") + T_324.clock := clock + T_324.reset := reset + T_324.enq.valid := T_321.host.ipi_req.valid + T_324.enq.bits := T_321.host.ipi_req.bits + T_321.host.ipi_req.ready := T_324.enq.ready + uncore.htif[0].ipi_req <> T_324.deq + inst T_325 of Queue_74 + T_325.deq.ready := UInt<1>("h00") + T_325.enq.bits := UInt<1>("h00") + T_325.enq.valid := UInt<1>("h00") + T_325.reset := UInt<1>("h00") + T_325.clock := clock + T_325.reset := reset + T_325.enq.valid := uncore.htif[0].ipi_rep.valid + T_325.enq.bits := uncore.htif[0].ipi_rep.bits + uncore.htif[0].ipi_rep.ready := T_325.enq.ready + T_321.host.ipi_rep <> T_325.deq + uncore.htif[0].debug_stats_pcr := T_321.host.debug_stats_pcr + uncore.tiles_cached[0] <> T_321.cached + uncore.tiles_uncached[0] <> T_321.uncached + host <> uncore.host + mem_1 <> uncore.mem_1 + mem_backup_ctrl <> uncore.mem_backup_ctrl + + module Top : + output mem_1 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} + output mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>} + output host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>} + input clock : Clock + input reset : UInt<1> + + mem_1.resp.ready := UInt<1>("h00") + mem_1.req_data.bits.data := UInt<1>("h00") + mem_1.req_data.valid := UInt<1>("h00") + mem_1.req_cmd.bits.rw := UInt<1>("h00") + mem_1.req_cmd.bits.tag := UInt<1>("h00") + mem_1.req_cmd.bits.addr := UInt<1>("h00") + mem_1.req_cmd.valid := UInt<1>("h00") + mem_backup_ctrl.out_valid := UInt<1>("h00") + host.debug_stats_pcr := UInt<1>("h00") + host.out.bits := UInt<1>("h00") + host.out.valid := UInt<1>("h00") + host.in.ready := UInt<1>("h00") + host.clk_edge := UInt<1>("h00") + host.clk := UInt<1>("h00") + inst T_102 of MultiChannelTop + T_102.mem_1[0].resp.bits.tag := UInt<1>("h00") + T_102.mem_1[0].resp.bits.data := UInt<1>("h00") + T_102.mem_1[0].resp.valid := UInt<1>("h00") + T_102.mem_1[0].req_data.ready := UInt<1>("h00") + T_102.mem_1[0].req_cmd.ready := UInt<1>("h00") + T_102.mem_backup_ctrl.out_ready := UInt<1>("h00") + T_102.mem_backup_ctrl.in_valid := UInt<1>("h00") + T_102.mem_backup_ctrl.en := UInt<1>("h00") + T_102.host.out.ready := UInt<1>("h00") + T_102.host.in.bits := UInt<1>("h00") + T_102.host.in.valid := UInt<1>("h00") + T_102.reset := UInt<1>("h00") + T_102.clock := clock + T_102.reset := reset + inst T_103 of MemIOArbiter + T_103.outer.resp.bits.tag := UInt<1>("h00") + T_103.outer.resp.bits.data := UInt<1>("h00") + T_103.outer.resp.valid := UInt<1>("h00") + T_103.outer.req_data.ready := UInt<1>("h00") + T_103.outer.req_cmd.ready := UInt<1>("h00") + T_103.inner[0].resp.ready := UInt<1>("h00") + T_103.inner[0].req_data.bits.data := UInt<1>("h00") + T_103.inner[0].req_data.valid := UInt<1>("h00") + T_103.inner[0].req_cmd.bits.rw := UInt<1>("h00") + T_103.inner[0].req_cmd.bits.tag := UInt<1>("h00") + T_103.inner[0].req_cmd.bits.addr := UInt<1>("h00") + T_103.inner[0].req_cmd.valid := UInt<1>("h00") + T_103.reset := UInt<1>("h00") + T_103.clock := clock + T_103.reset := reset + T_103.inner <> T_102.mem_1 + mem_1 <> T_103.outer + mem_backup_ctrl <> T_102.mem_backup_ctrl + host <> T_102.host + |