Fixed final bug. All tests pass. Accessors are a go.

13 files changed, 109 insertions, 92 deletions

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index ae3a30aa..9ac427db 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1218,62 +1218,65 @@ defn equality (e1:Expression,i:Int) -> Expression :
    DoPrim(EQUIV-OP,list(e1,UIntValue(BigIntLit(i),UnknownWidth())),
           List(),UIntType(UnknownWidth()))
 
-defn expand-indexed (indexer:WRef,
-                indexed-dec:Stmt,
-                stmts:Vector<Stmt>,
-                sh:HashTable<Symbol,Int>) -> Expression :
-
-   val index = index(indexed-dec as DecFromIndexer|DecToIndexer)
-   val index-name =  firrtl-gensym(get-name(index),sh)
-   val index-ref = WRef(index-name,type(index),NodeKind(),MALE) 
-
-   val replace-name = firrtl-gensym(get-name(indexer),sh)
-   val replace-ref = WRef(replace-name,type(indexer),kind(indexer),gender(indexer)) 
-
-   add(stmts, DefWire(info(indexed-dec),name(replace-ref),type(replace-ref)))
-   add(stmts, DefNode(info(indexed-dec),index-name,index))
-   match(indexed-dec) :
-      (s:DecFromIndexer) : 
-         if (gender(replace-ref) != FEMALE) : error("Shouldn't be here")
-         for (i in 0 to false, e in exps(s)) do :
-            val eq = equality(index-ref,i)
-            add(stmts,Conditionally(info(s),eq,
-                      Connect(info(s),e,replace-ref),EmptyStmt()))
-      (s:DecToIndexer) :
-         if (gender(replace-ref) != MALE) : error("Shouldn't be here")
-         add(stmts,Connect(info(s),replace-ref,head(exps(s))))
-         ;println-all(["exps: " exps(s)])
-         for (i in 1 to false, e in tail(exps(s))) do :
-            val eq = equality(index-ref,i)
-            add(stmts,Conditionally(info(s),eq,Connect(info(s),replace-ref,e),EmptyStmt()))
-   replace-ref
 
 ;------------- Inline Accessors -------------
 
+
+
 defn inline-indexed-m (m:InModule) -> InModule :
    val sh = get-sym-hash(m,keys(v-keywords))
-   val indexed-hash = HashTable<Symbol,Stmt>(symbol-hash)
-
+   val ih = HashTable<Symbol,Stmt>(symbol-hash)
    defn inline-indexed-s (s:Stmt)  -> Stmt :
       val stmts = Vector<Stmt>()
+
+      defn expand-indexed (indexer:WRef,indexed-dec:Stmt) -> Expression :
+         val index = index(indexed-dec as DecFromIndexer|DecToIndexer)
+         val index-name =  firrtl-gensym(get-name(index),sh)
+         val index-ref = WRef(index-name,type(index),NodeKind(),MALE) 
+      
+         val replace-name = firrtl-gensym(get-name(indexer),sh)
+         val replace-ref = WRef(replace-name,type(indexer),kind(indexer),gender(indexer)) 
+      
+         add(stmts, DefWire(info(indexed-dec),name(replace-ref),type(replace-ref)))
+         add(stmts, DefNode(info(indexed-dec),index-name,index))
+         match(indexed-dec) :
+            (s:DecFromIndexer) : 
+               if (gender(replace-ref) != FEMALE) : error("Shouldn't be here")
+               for (i in 0 to false, e in exps(s)) do :
+                  val eq = equality(index-ref,i)
+                  val cond = Conditionally(info(s),eq,Connect(info(s),e,replace-ref),EmptyStmt())
+                  add(stmts,map(inline-indexed-s,cond))
+            (s:DecToIndexer) :
+               if (gender(replace-ref) != MALE) : error("Shouldn't be here")
+               val cnct = Connect(info(s),replace-ref,head(exps(s)))
+               add(stmts,map(inline-indexed-e,cnct))
+               ;println-all(["exps: " exps(s)])
+               for (i in 1 to false, e in tail(exps(s))) do :
+                  val eq = equality(index-ref,i)
+                  val cond = Conditionally(info(s),eq,Connect(info(s),replace-ref,e),EmptyStmt())
+                  add(stmts,map(inline-indexed-s,cond))
+         replace-ref
+
       defn inline-indexed-e (e:Expression) -> Expression :
          match(map(inline-indexed-e,e)) :
             (e:WRef) : 
-               if key?(indexed-hash,name(e)) : 
-                  val indexer = indexed-hash[name(e)]
-                  map(inline-indexed-e,indexer)
-                  expand-indexed(e,indexer,stmts,sh)
+               if key?(ih,name(e)) : 
+                  val indexer = ih[name(e)]
+                  expand-indexed(e,indexer)
                else : e
             (e) : e
+
       match(s) :
          (s:DecFromIndexer|DecToIndexer) : 
-            indexed-hash[name(s)] = s
+            ih[name(s)] = s
+            firrtl-gensym(name(s),sh)
             add(stmts,EmptyStmt())
          (s) : 
             val s* = map(inline-indexed-e,s)
             add(stmts,map(inline-indexed-s,s*))
-      Begin(to-list(stmts))
-            
+      if length(stmts) == 1 : stmts[0]
+      else : Begin(to-list(stmts))
+
    InModule(info(m),name(m),ports(m),inline-indexed-s(body(m)))
 
 public defn inline-indexed (c:Circuit) -> Circuit :
diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir
index 1c055b48..6f8b63e3 100644
--- a/test/passes/expand-accessors/accessor-mem.fir
+++ b/test/passes/expand-accessors/accessor-mem.fir
@@ -8,16 +8,17 @@ circuit top :
       wire i : UInt<4>
       i := UInt(1)
       infer accessor a = m[i] ;CHECK: read accessor a = m[i]
-      infer accessor b = a[i] ;CHECK: b := (a[0] a[1])[i]
-      infer accessor c = b[i] ;CHECK: c := (b[0] b[1])[i]
+      infer accessor b = a[i] ;CHECK: indexer b = (a[0] a[1])[i] : UInt<32>[2]
+      infer accessor c = b[i] ;CHECK: indexer c = (b[0] b[1])[i] : UInt<32>
       wire j : UInt<32>
       j := c
 
       infer accessor x = m[i] ;CHECK: write accessor x = m[i]
-      infer accessor y = x[i] ;CHECK: (x[0] x[1])[i] := y
+      infer accessor y = x[i] ;CHECK: indexer (x[0] x[1])[i] = y : UInt<32>[2]
       y[0] := UInt(1)
       y[1] := UInt(1)
-      infer accessor z = y[i] ;CHECK: (y[0] y[1])[i] := z
+      infer accessor z = y[i] ;CHECK: indexer (y[0] y[1])[i] = z : UInt<32>
       z := j
 
 ; CHECK: Finished Expand Accessors
+; CHECK: Done!
diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir
index c505fbaf..96a5c74c 100644
--- a/test/passes/expand-accessors/accessor-vec.fir
+++ b/test/passes/expand-accessors/accessor-vec.fir
@@ -14,19 +14,19 @@ circuit top :
       m[1][1][1] := UInt(1)
       wire i : UInt
       i := UInt(1)
-      infer accessor a = m[i] ;CHECK: a := (m[0] m[1])[i]
-      infer accessor b = a[i] ;CHECK: b := (a[0] a[1])[i]
-      infer accessor c = b[i] ;CHECK: c := (b[0] b[1])[i]
+      infer accessor a = m[i] ;CHECK: indexer a = (m[0] m[1])[i] : UInt<32>[2][2]
+      infer accessor b = a[i] ;CHECK: indexer b = (a[0] a[1])[i] : UInt<32>[2]
+      infer accessor c = b[i] ;CHECK: indexer c = (b[0] b[1])[i] : UInt<32>
       wire j : UInt
       j := c
 
-      infer accessor x = m[i] ;CHECK: (m[0] m[1])[i] := x
+      infer accessor x = m[i] ;CHECK: indexer (m[0] m[1])[i] = x : UInt<32>[2][2]
       x[0][0] := UInt(1)
       x[1][0] := UInt(1)
       x[0][1] := UInt(1)
       x[1][1] := UInt(1)
-      infer accessor y = x[i] ;CHECK: (x[0] x[1])[i] := y
-      infer accessor z = y[i] ;CHECK: (y[0] y[1])[i] := z
+      infer accessor y = x[i] ;CHECK: indexer (x[0] x[1])[i] = y : UInt<32>[2]
+      infer accessor z = y[i] ;CHECK: indexer (y[0] y[1])[i] = z : UInt<32>
       y[0] := UInt(1)
       y[1] := UInt(1)
       z := j
@@ -34,13 +34,14 @@ circuit top :
       wire p : {n : UInt<32>[2]}
       p.n[0] := UInt(1)
       p.n[1] := UInt(1)
-      infer accessor q = p.n[i] ;CHECK: (p.n[0] p.n[1])[i] := q
+      infer accessor q = p.n[i] ;CHECK: indexer (p.n[0] p.n[1])[i] = q : UInt<32>
       q := j
 
       wire r : {m : UInt<32>}[2]
       r[0].m := UInt(1)
       r[1].m := UInt(1)
-      infer accessor s = r[i] ;CHECK: s := (r[0] r[1])[i]
+      infer accessor s = r[i] ;CHECK: indexer s = (r[0] r[1])[i] : { m : UInt<32>}
       j := s.m
 
 ; CHECK: Finished Expand Accessors
+; CHECK: Done!
diff --git a/test/passes/inline-indexers/bundle-vecs.fir b/test/passes/inline-indexers/bundle-vecs.fir
index c41794e3..28826056 100644
--- a/test/passes/inline-indexers/bundle-vecs.fir
+++ b/test/passes/inline-indexers/bundle-vecs.fir
@@ -1,6 +1,6 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 
-; CHECK: Expand Indexed Connects
+; CHECK: Inline Indexers
 circuit top :
    module top :
       wire i : UInt
@@ -20,16 +20,17 @@ circuit top :
 
 
       infer accessor b = a[i]
-      ; CHECK: wire b{{[_$]+}}x : UInt<32>
-      ; CHECK: wire b{{[_$]+}}y : UInt<32>
-      ; CHECK: b{{[_$]+}}x := a{{[_$]+}}0{{[_$]+}}x
+      ; CHECK: wire b{{[_$]+}}x_1 : UInt<32>
       ; CHECK: node i_1 = i
-      ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x      
+      ; CHECK: b{{[_$]+}}x_1 := a{{[_$]+}}0{{[_$]+}}x
+      ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x_1 := a{{[_$]+}}1{{[_$]+}}x      
+      ; CHECK: wire b{{[_$]+}}y_1 : UInt<32>
       ; CHECK: node i_2 = i
-      ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y      
-      ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y      
+      ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y_1
+      ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y_1
       j := b.x
       b.y := UInt(1)
       
-; CHECK: Finished Expand Indexed Connects
+; CHECK: Finished Inline Indexers
+; CHECK: Done!
 
diff --git a/test/passes/inline-indexers/simple.fir b/test/passes/inline-indexers/simple.fir
index ca65977b..ca186e97 100644
--- a/test/passes/inline-indexers/simple.fir
+++ b/test/passes/inline-indexers/simple.fir
@@ -12,8 +12,8 @@ circuit top :
       infer accessor a = m[i] 
       o := a
 
-;CHECK: a := m$0
-;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
+;CHECK: a_1 := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1
 
 
 
diff --git a/test/passes/inline-indexers/simple2.fir b/test/passes/inline-indexers/simple2.fir
index a334b626..3b7d92af 100644
--- a/test/passes/inline-indexers/simple2.fir
+++ b/test/passes/inline-indexers/simple2.fir
@@ -14,12 +14,12 @@ circuit top :
       o1 := a
       o2 := a
 
-;CHECK: wire a : UInt<32>
-;CHECK: a := m$0
-;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
 ;CHECK: wire a_1 : UInt<32>
 ;CHECK: a_1 := m$0
-;CHECK: when eqv(i_2, UInt("h1")) : a_1 := m$1
+;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1
+;CHECK: wire a_2 : UInt<32>
+;CHECK: a_2 := m$0
+;CHECK: when eqv(i_2, UInt("h1")) : a_2 := m$1
 
 
 
diff --git a/test/passes/inline-indexers/simple3.fir b/test/passes/inline-indexers/simple3.fir
index fd8d1418..688958a0 100644
--- a/test/passes/inline-indexers/simple3.fir
+++ b/test/passes/inline-indexers/simple3.fir
@@ -11,9 +11,9 @@ circuit top :
       infer accessor a = m[i] 
       a := in
 
-;CHECK: wire a : UInt<32>
-;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a
-;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a
+;CHECK: wire a_1 : UInt<32>
+;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a_1
+;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a_1
 
 
 
diff --git a/test/passes/inline-indexers/simple4.fir b/test/passes/inline-indexers/simple4.fir
index dce8f26f..df045456 100644
--- a/test/passes/inline-indexers/simple4.fir
+++ b/test/passes/inline-indexers/simple4.fir
@@ -13,11 +13,11 @@ circuit top :
       infer accessor a = m[i] 
       a.x := in.x
 
-;CHECK: wire a$x : UInt<32>
+;CHECK: wire a$x_1 : UInt<32>
 ;CHECK: node i_1 = i
-;CHECK: when eqv(i_1, UInt("h0")) : m$0$x := a$x
-;CHECK: when eqv(i_1, UInt("h1")) : m$1$x := a$x
-;CHECK: a$x := in$x
+;CHECK: when eqv(i_1, UInt("h0")) : m$0$x := a$x_1
+;CHECK: when eqv(i_1, UInt("h1")) : m$1$x := a$x_1
+;CHECK: a$x_1 := in$x
 ;CHECK: Finished Inline Indexers
 ;CHECK: Done!
 
diff --git a/test/passes/inline-indexers/simple5.fir b/test/passes/inline-indexers/simple5.fir
index 8cd7bec1..1da83cab 100644
--- a/test/passes/inline-indexers/simple5.fir
+++ b/test/passes/inline-indexers/simple5.fir
@@ -15,7 +15,7 @@ circuit top :
          o := a
 
 ;CHECK: when i :
-;CHECK: a := m$0
-;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
+;CHECK: a_1 := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1
 ;CHECK: Finished Inline Indexers
 ;CHECK: Done!
diff --git a/test/passes/inline-indexers/simple6.fir b/test/passes/inline-indexers/simple6.fir
index 98b28611..e94efc7a 100644
--- a/test/passes/inline-indexers/simple6.fir
+++ b/test/passes/inline-indexers/simple6.fir
@@ -7,19 +7,38 @@ circuit top :
       input in : {x : UInt<32>, y : UInt<32>}
       wire m :{x : UInt<32>, y : UInt<32>}[2][2] 
       wire i : UInt
+      wire j : UInt
 
       m[0][0] := in
       m[1][0] := in
       m[0][1] := in
       m[1][1] := in
       i := UInt("h1")
+      j := UInt("h1")
 
       write accessor a = m[i] 
-      write accessor b = a[i] 
+      write accessor b = a[j] 
       b.x := value
 
-;CHECK: a := m$0
-;CHECK: when eqv(i_1, UInt("h1")) : a := m$1
+;CHECK: wire b$x_1 : UInt<32>
+;CHECK: node j_1 = j
+;CHECK: when eqv(j_1, UInt("h0")) :
+;CHECK:    wire a$0$x_1 : UInt<32>
+;CHECK:    node i_1 = i
+;CHECK:    when eqv(i_1, UInt("h0")) :
+;CHECK:       m$0$0$x := a$0$x_1         
+;CHECK:    when eqv(i_1, UInt("h1")) :
+;CHECK:       m$1$0$x := a$0$x_1         
+;CHECK:    a$0$x_1 := b$x_1      
+;CHECK: when eqv(j_1, UInt("h1")) :
+;CHECK:    wire a$1$x_1 : UInt<32>
+;CHECK:    node i_2 = i
+;CHECK:    when eqv(i_2, UInt("h0")) :
+;CHECK:       m$0$1$x := a$1$x_1         
+;CHECK:    when eqv(i_2, UInt("h1")) :
+;CHECK:       m$1$1$x := a$1$x_1         
+;CHECK:    a$1$x_1 := b$x_1      
+;CHECK: b$x_1 := value   
 
 
 
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index fd261e1e..4d55d0f6 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -14,13 +14,11 @@ circuit top :
       ; CHECK: wire a{{[_$]+}}3 : UInt<32>
 
       infer accessor b = a[i]
-      ; CHECK: wire b : UInt<32>
-      ; CHECK: b := (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i]
+      ; CHECK: indexer b = (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] : UInt<32>
       j := b
 
       infer accessor c = a[i]
-      ; CHECK: wire c : UInt<32>
-      ; CHECK: (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] := c
+      ; CHECK: indexer (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] = c : UInt<32>
       c := j
       
       cmem p : UInt<32>[4],clk
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index 17927aef..7d37e65c 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -13,17 +13,13 @@ circuit top :
       ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32>
 
       infer accessor b = a[i]
-      ; CHECK: wire b{{[_$]+}}x : UInt<32>
-      ; CHECK: wire b{{[_$]+}}y : UInt<32>
-      ; CHECK: b{{[_$]+}}x := (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i]
-      ; CHECK: (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] := b{{[_$]+}}y
+      ; CHECK: indexer b{{[_$]+}}x = (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] : UInt<32>
+      ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] = b{{[_$]+}}y : UInt<32>
       j := b
       
       infer accessor c = a[i]
-      ; CHECK: wire c{{[_$]+}}x : UInt<32>
-      ; CHECK: wire c{{[_$]+}}y : UInt<32>
-      ; CHECK: (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] := c{{[_$]+}}x
-      ; CHECK: c{{[_$]+}}y := (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i]
+      ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] = c{{[_$]+}}x : UInt<32>
+      ; CHECK: indexer c{{[_$]+}}y = (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] : UInt<32>
       c := j
 
 
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index d484a6dc..aa208b01 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -15,10 +15,8 @@ circuit top :
       ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32>
 
       infer accessor b = a[i]
-      ; CHECK: wire b{{[_$]+}}x : UInt<32>
-      ; CHECK: wire b{{[_$]+}}y : UInt<32>
-      ; CHECK: b{{[_$]+}}x := (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i]
-      ; CHECK: (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] := b{{[_$]+}}y
+      ; CHECK: indexer b{{[_$]+}}x = (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] : UInt<32>
+      ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] = b{{[_$]+}}y : UInt<32>
       j := b
 
       cmem m : { x : UInt<32>, y : UInt<32> }[2],clk