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path: root/chiselFrontend/src/main/scala/chisel3/core/Module.scala
AgeCommit message (Expand)Author
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
2017-02-08Add counter for depth of when scopeJack Koenig
2017-01-31Make Module and Bundle properly use empty namespacesJack
2017-01-27Clean names of private vals in Modulesjackkoenig
2017-01-20Add Record as new superclass of Bundle (#366)Jack Koenig
2016-12-07Support for creating chisel annotations that are consumed by firrtl (#393)Chick Markley
2016-11-21Remove deduplication from Chisel (#347)Donggyu
2016-11-18Add support for parameterized BlackBoxesjackkoenig
2016-11-14Add checks for misuse or omission of Module()Jack
2016-11-02Changed T to _T for generated names (#349)Adam Izraelevitz
2016-10-27Refactor and fix field reflection (#342)Andrew Waterman
2016-10-04Add CompileOptions implicits to all Module constructors - fix #310. (#311)Jim Lawson
2016-09-29Manual dead code elimination.Jim Lawson
2016-09-29Consolidate CompileOptions and re-enable NotStrict pending macro work.Jim Lawson
2016-09-29Massive rename of CompileOptions.Jim Lawson
2016-09-23Merge branch 'master' into gsdtJim Lawson
2016-09-21Make implicit clock name consistent (#288)Andrew Waterman
2016-08-30Merge branch 'master' into gsdtJim Lawson
2016-08-29Rename CompileOptions implicit objects.Jim Lawson
2016-08-29Pass compileOptions as an implicit Module parameter.Jim Lawson
2016-08-29Rename individual compile options.Jim Lawson
2016-08-24Per Chisel meeting.chick
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
2016-08-19Simplify autioIOWrap code in computePorts().Jim Lawson
2016-08-18Use isFirrtlFlipped() to determine port direction.Jim Lawson
2016-08-17Reduce rocket-chip elaboration errors.Jim Lawson
2016-08-16Provide public SignalID trait to be used to conjure up a signal identifier.Jim Lawson
2016-08-11Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-09Support Module name overrides with "override def desiredName"Andrew Waterman
2016-07-27Additional compatibility code.Jim Lawson
2016-07-25Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-07-20Generate better names for nodes (#190)Jack Koenig
2016-07-19Incorporate connection logic.Jim Lawson
2016-07-19Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3Jim Lawson
2016-07-18Update Chisel -> chisel3 references.Jim Lawson
2016-07-18Rename "Chisel" to "chisel3" (only git mv).Jim Lawson
2016-07-01Reflectively name Module fields declared in superclassesAndrew Waterman
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson
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