diff options
| author | Jim Lawson | 2016-10-04 11:46:13 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2016-10-04 11:46:13 -0700 |
| commit | 095fd80cc1250f5ec242fde6ccc9271665f784b2 (patch) | |
| tree | 10e491596e83b55b8c84cf4f48e4748b1fcab001 /chiselFrontend/src/main/scala/chisel3/core/Module.scala | |
| parent | db25e8180a53fb8f4912fd37b7a613e15a01564f (diff) | |
Add CompileOptions implicits to all Module constructors - fix #310. (#311)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Module.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 6fb6d036..55522b4a 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -54,9 +54,9 @@ abstract class Module( extends HasId { // _clock and _reset can be clock and reset in these 2ary constructors // once chisel2 compatibility issues are resolved - def this(_clock: Clock) = this(Option(_clock), None) - def this(_reset: Bool) = this(None, Option(_reset)) - def this(_clock: Clock, _reset: Bool) = this(Option(_clock), Option(_reset)) + def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), None)(moduleCompileOptions) + def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(None, Option(_reset))(moduleCompileOptions) + def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), Option(_reset))(moduleCompileOptions) // This function binds the iodef as a port in the hardware graph private[chisel3] def Port[T<:Data](iodef: T): iodef.type = { |
