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path: root/chiselFrontend/src/main/scala/chisel3/core/Module.scala
AgeCommit message (Expand)Author
2019-05-20Repackagecore rebase (#1078)Jim Lawson
2019-05-13RawModule with no reset should be able to use withClock method. (#1065)Chick Markley
2019-04-15Style nitpick (#1068)edwardcwang
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
2019-01-22Add Rocket Chip-style clonemodule as CloneModuleAsRecord to experimental (#943)Albert Magyar
2019-01-11Move nameRecursively into Builder so it can be used elsewhereAndrew Waterman
2018-10-25Check BaseModule.name for NullPointerExceptionSchuyler Eldridge
2018-10-25Make BaseModule.name lazySchuyler Eldridge
2018-10-03Add DataMirror.modulePorts (#901)Richard Lin
2018-09-07Put do_* methods in SourceInfoTransformMacro groupSchuyler Eldridge
2018-06-29Catch returns from within when blocks and provide an error message (#842)Jack Koenig
2018-06-20Programmatic Port Creation (#833)Jack Koenig
2018-04-22Add Module.currentModule for getting a reference to the current Module (#810)Jack Koenig
2018-02-28Refactor Annotations (#767)Jack Koenig
2018-02-08Make uncloneable IO deprecated instead of error, improve error handling (#771)Richard Lin
2018-02-07Cloning IO with compatibility 🦆 (#754)Richard Lin
2017-12-20Add compileOptions to Module.apply, use for invalidating submod ports (#747)Jack Koenig
2017-08-17Make Reset a trait (#672)Jack Koenig
2017-08-11Rename userDir->specifiedDir (#671)Richard Lin
2017-08-08Give default direction to children of Vecs in compatibility codeJack Koenig
2017-06-26Directions internals mega-refactor (#617)Richard Lin
2017-05-03Clear clock and reset scope for RawModule (#607)Richard Lin
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2017-04-02Make Module instantiations draw clock from Builder instead of parent (#568)Jack Koenig
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
2017-02-08Add counter for depth of when scopeJack Koenig
2017-01-31Make Module and Bundle properly use empty namespacesJack
2017-01-27Clean names of private vals in Modulesjackkoenig
2017-01-20Add Record as new superclass of Bundle (#366)Jack Koenig
2016-12-07Support for creating chisel annotations that are consumed by firrtl (#393)Chick Markley
2016-11-21Remove deduplication from Chisel (#347)Donggyu
2016-11-18Add support for parameterized BlackBoxesjackkoenig
2016-11-14Add checks for misuse or omission of Module()Jack
2016-11-02Changed T to _T for generated names (#349)Adam Izraelevitz
2016-10-27Refactor and fix field reflection (#342)Andrew Waterman
2016-10-04Add CompileOptions implicits to all Module constructors - fix #310. (#311)Jim Lawson
2016-09-29Manual dead code elimination.Jim Lawson
2016-09-29Consolidate CompileOptions and re-enable NotStrict pending macro work.Jim Lawson
2016-09-29Massive rename of CompileOptions.Jim Lawson
2016-09-23Merge branch 'master' into gsdtJim Lawson
2016-09-21Make implicit clock name consistent (#288)Andrew Waterman
2016-08-30Merge branch 'master' into gsdtJim Lawson
2016-08-29Rename CompileOptions implicit objects.Jim Lawson
2016-08-29Pass compileOptions as an implicit Module parameter.Jim Lawson
2016-08-29Rename individual compile options.Jim Lawson
2016-08-24Per Chisel meeting.chick
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
2016-08-19Simplify autioIOWrap code in computePorts().Jim Lawson
2016-08-18Use isFirrtlFlipped() to determine port direction.Jim Lawson
2016-08-17Reduce rocket-chip elaboration errors.Jim Lawson
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