Directions internals mega-refactor (#617)

Part 1 of mega-change in #578

Major notes:
- Input(...) and Output(...) now (effectively) recursively override their elements' directions
- Nodes given userDirection (Input, Output, Flip - what the user assigned to _that_ node) and actualDirection (Input, Output, None, but also Bidirectional and BidirectionalFlip for mostly Aggregates), because of the above (since a higher-level Input(...) can override the locally specified user direction).
- DataMirror (node reflection APIs) added to chisel3.experimental. This provides ways to query the user given direction of a node as well as the actual direction.
- checkSynthesizable replaced with requireIsHardware and requireIsChiselType and made available in chisel3.experimental.

Internal changes notes:
- toType moved into Emitter, this makes the implementation cleaner especially considering that Vec types can't be flipped in FIRRTL. This also more clearly separates Chisel frontend from FIRRTL emission.
- Direction separated from Bindings, both are now fields in Data, and all nodes are given hierarchical directions (Aggregates may be Bidirectional). The actualDirection at the Element (leaf) level should be the same as binding directions previously.
- Bindings are hierarchical, children (of a, for example, Bundle) have a ChildBinding that points to their parent. This is different than the previous scheme where Bindings only applied at the Element (leaf) level.
- Lots of small misc clean up.

Future PRs will address other parts of #578, including stricter direction checks that aren't a side-effect of this internal refactor, stricter checks and splitting of binding operations (Wire vs. WireInit), and node operations not introduced here (getType and deprecation of chiselCloneType). Since those shouldn't mess with internals, those should be much smaller.

1 files changed, 27 insertions, 1 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index b512ed75..0f081daf 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -219,8 +219,34 @@ abstract class BaseModule extends HasId {
    */
   protected def IO[T<:Data](iodef: T): iodef.type = {
     require(!_closed, "Can't add more ports after module close")
+    requireIsChiselType(iodef, "io type")
+
+    // Compatibility code: Chisel2 did not require explicit direction on nodes
+    // (unspecified treated as output, and flip on nothing was input).
+    // This sets assigns the explicit directions required by newer semantics on
+    // Bundles defined in compatibility mode.
+    // This recursively walks the tree, and assigns directions if no explicit
+    // direction given by upper-levels (override Input / Output) AND element is
+    // directly inside a compatibility Bundle determined by compile options.
+    def assignCompatDir(data: Data, insideCompat: Boolean): Unit = {
+      data match {
+        case data: Element if insideCompat => data._assignCompatibilityExplicitDirection
+        case data: Element => // Not inside a compatibility Bundle, nothing to be done
+        case data: Aggregate => data.userDirection match {
+          // Recurse into children to ensure explicit direction set somewhere
+          case UserDirection.Unspecified | UserDirection.Flip => data match {
+            case data: Record if (!data.compileOptions.dontAssumeDirectionality) =>
+              data.getElements.foreach(assignCompatDir(_, true))
+            case _ => data.getElements.foreach(assignCompatDir(_, false))
+          }
+          case UserDirection.Input | UserDirection.Output => // forced assign, nothing to do
+        }
+      }
+    }
+    assignCompatDir(iodef, false)
+
     // Bind each element of the iodef to being a Port
-    Binding.bind(iodef, PortBinder(this), "Error: iodef")
+    iodef.bind(PortBinding(this))
     _ports += iodef
     iodef
   }