Make implicit clock name consistent (#288)

In the Chisel frontend, the implicit clock is named clock, but in the
generated FIRRTL, it is named clk.  There is no reason for this
discrepancy, and yet fixing it is painful, as it will break test harnesses.
Better to take the pain now than later.

Resolves #258.

1 files changed, 1 insertions, 1 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 2426ae78..8093babc 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -94,7 +94,7 @@ extends HasId {
   private[chisel3] def addId(d: HasId) { _ids += d }
 
   private[core] def ports: Seq[(String,Data)] = Vector(
-    ("clk", clock), ("reset", reset), ("io", io)
+    ("clock", clock), ("reset", reset), ("io", io)
   )
 
   private[core] def computePorts = for((name, port) <- ports) yield {