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authorchick2016-08-24 17:09:41 -0700
committerchick2016-08-24 17:09:41 -0700
commitf5e9a6c6e55ba19a7c1f2353d0207189062db1c9 (patch)
tree75a4ec69fc1935643f8fa4689d16422db1ecfd5f /chiselFrontend/src/main/scala/chisel3/core/Module.scala
parenta177f40f1ff2482ba268a27e0af02b57713e781a (diff)
Per Chisel meeting.
signalName -> instanceName SignalId -> InstanceId Based on Stephen's comments on PR
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Module.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index eb48a14d..2426ae78 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -78,7 +78,7 @@ extends HasId {
/** Signal name (for simulation). */
- override def signalName =
+ override def instanceName =
if (_parent == None) name else _component match {
case None => getRef.name
case Some(c) => getRef fullName c