Merge branch 'master' into gsdt

1 files changed, 22 insertions, 2 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 2cfc6c6a..9f7048cd 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -31,13 +31,14 @@ object Module {
     m._commands.prepend(DefInvalid(childSourceInfo, m.io.ref)) // init module outputs
     Builder.currentModule = parent // Back to parent!
     val ports = m.computePorts
-    Builder.components += Component(m, m.name, ports, m._commands)
+    val component = Component(m, m.name, ports, m._commands)
+    m._component = Some(component)
+    Builder.components += component
     // Avoid referencing 'parent' in top module
     if(!Builder.currentModule.isEmpty) {
       pushCommand(DefInstance(sourceInfo, m, ports))
       m.setupInParent(childSourceInfo)
     }
-
     m
   }
 }
@@ -100,6 +101,25 @@ extends HasId {
   /** Legalized name of this module. */
   final val name = Builder.globalNamespace.name(desiredName)
 
+  /** FIRRTL Module name */
+  private var _modName: Option[String] = None
+  private[chisel3] def setModName(name: String) = _modName = Some(name)
+  def modName = _modName match {
+    case Some(name) => name
+    case None => throwException("modName should be called after circuit elaboration")
+  }
+
+  /** Keep component for signal names */
+  private[chisel3] var _component: Option[Component] = None
+
+
+  /** Signal name (for simulation). */
+  override def instanceName =
+    if (_parent == None) name else _component match {
+      case None => getRef.name
+      case Some(c) => getRef fullName c
+    }
+
   /** IO for this Module. At the Scala level (pre-FIRRTL transformations),
     * connections in and out of a Module may only go through `io` elements.
     */